JPWO2021033266A1 - - Google Patents

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Publication number
JPWO2021033266A1
JPWO2021033266A1 JP2021541386A JP2021541386A JPWO2021033266A1 JP WO2021033266 A1 JPWO2021033266 A1 JP WO2021033266A1 JP 2021541386 A JP2021541386 A JP 2021541386A JP 2021541386 A JP2021541386 A JP 2021541386A JP WO2021033266 A1 JPWO2021033266 A1 JP WO2021033266A1
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JP
Japan
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JP2021541386A
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Japanese (ja)
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JP7284465B2 (en
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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
JP2021541386A 2019-08-20 2019-08-20 SIGNAL LINE CONNECTION METHOD, PROGRAM, AND SEMICONDUCTOR INTEGRATED CIRCUIT Active JP7284465B2 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2019/032455 WO2021033266A1 (en) 2019-08-20 2019-08-20 Connection method for signal line, program, and semiconductor integrated circuit

Publications (2)

Publication Number Publication Date
JPWO2021033266A1 true JPWO2021033266A1 (en) 2021-02-25
JP7284465B2 JP7284465B2 (en) 2023-05-31

Family

ID=74659893

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2021541386A Active JP7284465B2 (en) 2019-08-20 2019-08-20 SIGNAL LINE CONNECTION METHOD, PROGRAM, AND SEMICONDUCTOR INTEGRATED CIRCUIT

Country Status (2)

Country Link
JP (1) JP7284465B2 (en)
WO (1) WO2021033266A1 (en)

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08204543A (en) * 1984-09-26 1996-08-09 Xilinx Inc Single chip pattern adaptable logic array
JP2004039150A (en) * 2002-07-04 2004-02-05 Nec Corp Magnetic random access memory
JP2006073010A (en) * 2004-09-02 2006-03-16 Hewlett-Packard Development Co Lp Programming of programmable resistance memory element
JP2008217844A (en) * 2007-02-28 2008-09-18 Matsushita Electric Ind Co Ltd Non-volatile semiconductor memory device
JP2012198695A (en) * 2011-03-18 2012-10-18 Fujitsu Ltd Wiring design support device, wiring design support method, and program
JP2018007167A (en) * 2016-07-07 2018-01-11 日本電気株式会社 Switch circuit and semiconductor device employing the same
JP2018037783A (en) * 2016-08-30 2018-03-08 株式会社東芝 Integrated circuit and electronic apparatus

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08204543A (en) * 1984-09-26 1996-08-09 Xilinx Inc Single chip pattern adaptable logic array
JP2004039150A (en) * 2002-07-04 2004-02-05 Nec Corp Magnetic random access memory
JP2006073010A (en) * 2004-09-02 2006-03-16 Hewlett-Packard Development Co Lp Programming of programmable resistance memory element
JP2008217844A (en) * 2007-02-28 2008-09-18 Matsushita Electric Ind Co Ltd Non-volatile semiconductor memory device
JP2012198695A (en) * 2011-03-18 2012-10-18 Fujitsu Ltd Wiring design support device, wiring design support method, and program
JP2018007167A (en) * 2016-07-07 2018-01-11 日本電気株式会社 Switch circuit and semiconductor device employing the same
JP2018037783A (en) * 2016-08-30 2018-03-08 株式会社東芝 Integrated circuit and electronic apparatus

Also Published As

Publication number Publication date
WO2021033266A1 (en) 2021-02-25
JP7284465B2 (en) 2023-05-31

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