JPWO2020243098A5 - - Google Patents

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JPWO2020243098A5
JPWO2020243098A5 JP2021569842A JP2021569842A JPWO2020243098A5 JP WO2020243098 A5 JPWO2020243098 A5 JP WO2020243098A5 JP 2021569842 A JP2021569842 A JP 2021569842A JP 2021569842 A JP2021569842 A JP 2021569842A JP WO2020243098 A5 JPWO2020243098 A5 JP WO2020243098A5
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write
cache storage
miss information
cache
write miss
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装置であって、
第１のキャッシュストレージと、
前記第１のキャッシュストレージから退出されるデータのセットを格納するように動作可能な第１の部分と書き込みミス情報を格納するように動作可能な第２の部分とを含む第２のキャッシュストレージと、
前記第１のキャッシュストレージと前記第２のキャッシュストレージとに結合されるキャッシュコントローラであって、
書き込み動作を受け取り、
前記書き込み動作が前記第１のキャッシュストレージにおけるミスに関連することを判定し、
前記第１のキャッシュストレージにおけるミスに応答して、前記書き込みデータを含む第１の書き込みミス情報のセットを前記第２のキャッシュストレージの第２の部分に格納させ、
前記書き込みデータに向けられる読み出し動作を受信し、
前記第２のキャッシュストレージの第２の部分に格納された前記書き込みデータを用いて前記読み出し動作を使用可能にし、
前記第１のキャッシュストレージに格納されるべき第２のデータのセットに応答して前記第１のキャッシュストレージから第１のデータのセットを退出させ、
前記第１のデータのセットを前記第２のキャッシュストレージの第１の部分に前記第１のデータのセットを格納する、
ように動作可能である、前記キャッシュコントローラと、
を含む、装置。 a device,
a first cache storage;
a second cache storage including a first portion operable to store a set of data evicted from the first cache storage and a second portion operable to store write miss information; ,
a cache controller coupled to the first cache storage and the second cache storage,
receive a write operation,
determining that the write operation is associated with a miss in the first cache storage;
causing a first set of write miss information containing the write data to be stored in a second portion of the second cache storage in response to a miss in the first cache storage;
receiving a read operation directed to the write data;
enabling the read operation using the write data stored in a second portion of the second cache storage;
evicting a first set of data from the first cache storage in response to a second set of data to be stored in the first cache storage;
storing the first set of data in a first portion of the second cache storage;
the cache controller operable to
apparatus , including 請求項１に記載の装置であって、
前記第１のキャッシュストレージと前記第２のキャッシュストレージと前記キャッシュコントローラとが第１のキャッシュレベルに関連し、
前記キャッシュコントローラが、
前記第２のキャッシュストレージの第２の部分の利用を閾値と比較し、
前記第２の部分の利用が前記閾値を超えることに基づいて、前記書き込みミス情報を第２のキャッシュレベルに送信させる、
ように更に動作可能である、装置。 2. The device of claim 1, wherein
wherein the first cache storage, the second cache storage and the cache controller are associated with a first cache level;
the cache controller
comparing utilization of a second portion of the second cache storage to a threshold;
causing the write miss information to be sent to a second cache level based on utilization of the second portion exceeding the threshold;
A device which is further operable to. 請求項２に記載の装置であって、
前記閾値が、インタフェースの帯域幅に対応する、装置。 3. The apparatus of claim 2, wherein
The apparatus , wherein the threshold corresponds to bandwidth of an interface. 請求項２に記載の装置であって、
前記閾値が、前記第２の部分のサイズに対応する、装置。 3. The apparatus of claim 2, wherein
The apparatus, wherein the threshold corresponds to the size of the second portion. 請求項１に記載の装置であって、
前記キャッシュコントローラが、前記第２のキャッシュストレージが前記第１の書き込みミス情報のセットに対応するメモリアドレスに対する第２の書き込みミス情報のセットを含む場合に、前記第１のキャッシュストレージから前記第２のキャッシュストレージに前記第１の書き込みミス情報のセットを提供しないように更に動作可能である、装置。 2. The device of claim 1, wherein
The cache controller outputs the second write miss information from the first cache storage when the second cache storage includes a second set of write miss information for a memory address corresponding to the first set of write miss information. , further operable to not provide the first set of write miss information to cache storage of . 請求項１に記載の装置であって、
前記第１のキャッシュストレージと前記第２のキャッシュストレージとが、中央処理装置に並列に接続される、装置。 2. The device of claim 1, wherein
The apparatus, wherein said first cache storage and said second cache storage are connected in parallel to a central processing unit. 請求項１に記載の装置であって、
前記キャッシュコントローラが、前記第１のキャッシュストレージからの前記第１の書き込みミス情報のセットの第１のメモリアドレスが前記第２の部分に格納された第２の書き込みミス情報のセットの第２のメモリアドレスと一致するときに、前記第１の書き込みミス情報のセットを前記第２の書き込みミス情報のセットとマージするように更に動作可能である、装置。 2. The device of claim 1, wherein
The cache controller generates a second of a second set of write miss information with a first memory address of the first set of write miss information from the first cache storage stored in the second portion. The apparatus is further operable to merge the first set of write miss information with the second set of write miss information when matching memory addresses. 請求項７に記載の装置であって、
前記キャッシュコントローラが、（ａ）前記第１の書き込みミス情報のセットの第１の書き込み情報を維持すること、又は、（ｂ）前記第２の書き込みミス情報のセットの第２の書き込み情報が前記第１の書き込みミス情報のセットと同じ１つ又はそれ以上のバイトに対応する場合に前記第２の書き込みミス情報のセットの第２の書き込み情報を破棄すること、の少なくとも１つによって、前記第１の書き込みミス情報のセットを前記第２の書き込みミス情報のセットとマージするように更に動作可能である、装置。 8. A device according to claim 7, wherein
The cache controller may: (a) maintain a first write information of the first set of write miss information; or (b) second write information of the second set of write miss information. discarding the second write information of the second set of write miss information if it corresponds to the same one or more bytes as the first set of write miss information. and further operable to merge one set of write miss information with said second set of write miss information. 請求項１に記載の装置であって、
前記第２の部分がバイトイネーブルレジスタを含み、
前記キャッシュコントローラが、前記書き込みミス情報に基づいて前記バイトイネーブルレジスタに値を格納するように更に動作可能である、装置。 2. The device of claim 1, wherein
the second portion includes a byte enable register;
The apparatus of claim 1, wherein the cache controller is further operable to store a value in the byte enable register based on the write miss information. 請求項９に記載の装置であって、
前記値が、書き込まれる前記書き込みミス情報の要素に対応する、装置。 10. A device according to claim 9, wherein
The apparatus, wherein the values correspond to elements of the write miss information to be written. システムであって、
メモリアドレスに対応する書き込みコマンドを出力するように動作可能である中央処理装置と、
主要キャッシュストレージであって、
前記主要キャッシュストレージに格納されるべき第２のデータのセットに応答して第１のデータのセットを出力し、
前記主要キャッシュストレージにおけるミスに関連する前記書き込みコマンドに基づいて、書き込みデータを含む書き込みミス情報のセットを出力する、
ように動作可能である、前記主要キャッシュストレージと、
前記主要キャッシュストレージから退出されるデータのセットを格納するように動作可能な第１の部分と、書き込みミス情報のセットを格納するように動作可能な第２の部分とを含む犠牲キャッシュストレージであって、
前記主要キャッシュストレージから退出される前記第１のデータのセットに基づいて前記第１の部分に前記第１のデータのセットを格納し、
前記主要キャッシュストレージにおけるミスに関連する前記書き込みコマンドに基づいて前記第２の部分に前記書き込みミス情報のセットを格納し、
前記書き込みミス情報のセットの書き込みデータに向けられる前記中央処理装置からの第２のコマンドを利用可能にする、
ように動作可能である、前記犠牲キャッシュストレージと、
を含む、システム。 a system,
a central processing unit operable to output a write command corresponding to a memory address;
primary cache storage,
outputting a first set of data in response to a second set of data to be stored in the primary cache storage;
outputting a set of write miss information including write data based on the write commands associated with misses in the primary cache storage;
the primary cache storage operable to
a victim cache storage comprising a first portion operable to store a set of data evicted from said primary cache storage and a second portion operable to store a set of write miss information ; There is
storing the first set of data in the first portion based on the first set of data evicted from the primary cache storage;
storing the set of write miss information in the second portion based on the write commands associated with misses in the primary cache storage ;
enabling a second command from the central processing unit directed to write data of the set of write miss information;
the victim cache storage operable to
system, including 請求項１１に記載のシステムであって、
前記主要キャッシュストレージと前記犠牲キャッシュストレージとが第１のキャッシュレベルに関連し、
前記犠牲キャッシュストレージが、前記犠牲キャッシュストレージの第２の部分が書き込みミス情報の閾値量より多くを有するときに、前記書き込みミス情報を第２のキャッシュレベルに出力するように更に動作可能である、システム。 12. The system of claim 11, comprising:
the primary cache storage and the victim cache storage are associated with a first cache level;
the victim cache storage is further operable to output the write miss information to a second cache level when a second portion of the victim cache storage has more than a threshold amount of write miss information; system. 請求項１２に記載のシステムであって、
前記閾値量が、前記第２のキャッシュレベルへのインタフェースの帯域幅に対応する、システム。 13. The system of claim 12, wherein
The system, wherein the threshold amount corresponds to bandwidth of an interface to the second cache level . 請求項１２に記載のシステムであって、
前記閾値量が、前記第２の部分のサイズに対応する、システム。 13. The system of claim 12, wherein
The system, wherein the threshold amount corresponds to the size of the second portion. 請求項１１に記載のシステムであって、
前記犠牲キャッシュストレージが、前記犠牲キャッシュストレージが前記中央処理装置からの前記第１の書き込みミス情報のセットと同じメモリアドレスに対応する第２の書き込みミス情報のセットを含む場合に、前記主要キャッシュストレージからの前記第１の書き込みミス情報のセットを前記第２の部分に格納しないように更に動作可能である、システム。 12. The system of claim 11, comprising:
the primary cache storage, if the victim cache storage contains a second set of write miss information corresponding to the same memory address as the first set of write miss information from the central processing unit; , further operable to not store the first set of write miss information from the second portion in the second portion. 請求項１１に記載のシステムであって、
前記主要キャッシュストレージと前記犠牲キャッシュストレージとが、前記中央処理装置に並列に接続される、システム。 12. The system of claim 11, comprising:
A system, wherein the primary cache storage and the victim cache storage are connected in parallel to the central processing unit. 請求項１１に記載のシステムであって、
コントローラであって、前記主要キャッシュストレージからの前記第１の書き込みミス情報のセットの第１のメモリアドレスが前記第２の部分に格納された第２の書き込みミス情報のセットの第２のメモリアドレスと一致するときに、前記第１の書き込みミス情報のセットを前記第２の書き込みミス情報のセットとマージするように動作可能である、前記コントローラを更に含む、システム。 12. The system of claim 11, comprising:
a controller, wherein a first memory address of the first set of write miss information from the primary cache storage is stored in the second portion and a second memory address of the second set of write miss information; , further comprising the controller operable to merge the first set of write miss information with the second set of write miss information when matching. 請求項１７に記載のシステムであって、
前記コントローラが、（ａ）前記第１の書き込みミス情報のセットの第１の書き込み情報を維持すること、又は、（ｂ）前記第２の書き込みミス情報のセットの第２の書き込み情報が前記第１の書き込みミス情報のセットと同じ１つ又はそれ以上のバイトに対応する場合に前記第２の書き込みミス情報のセットの第２の書き込み情報を破棄すること、の少なくとも１つによって、前記第１の書き込みミス情報のセットを前記第２の書き込みミス情報のセットとマージするように更に動作可能である、システム。 18. The system of claim 17, comprising:
(a ) maintaining a first write information of the first set of write miss information; or (b) second write information of the second set of write miss information is maintained in the discarding second write information of the second set of write miss information if it corresponds to the same one or more bytes as one set of write miss information. with said second set of write miss information. 方法であって、
プロセッサから書き込み動作を受け取ることと、
前記書き込み動作が第１のキャッシュレベルの第１のキャッシュストレージにおいてミスを生成することを判定することと、
前記第１のキャッシュストレージにおけるミスに応答して、前記第１のキャッシュレベルの第２のキャッシュストレージに前記書き込み動作に関連する書き込みミス情報のセットを格納することであって、前記第２のキャッシュストレージが、前記第１のキャッシュストレージから退出される第１のデータのセットを格納する第１の部分と、前記書き込みミス情報のセットを格納する第２の部分とを含む、前記書き込みミス情報のセットを格納することと、
前記プロセッサから第２の動作を受信することと、
前記第２のキャッシュストレージに格納された前記書き込みミス情報のセットを用いて前記第２の動作を使用可能にし、
前記第１のキャッシュストレージに格納されるべき第２のデータのセットに応答して、前記第２のデータのセットのための余裕をつくるために前記第１のキャッシュストレージから前記第１のデータのセットを退出させることと、
前記第２のキャッシュストレージの第１の部分に前記第１のデータのセットを格納することと、
を含む、方法。 a method,
receiving a write operation from a processor ;
determining that the write operation generates a miss in a first cache storage at a first cache level ;
storing a set of write miss information associated with the write operation in a second cache storage at the first cache level in response to a miss in the first cache storage; said write miss information, wherein storage includes a first portion storing a first set of data evicted from said first cache storage and a second portion storing said set of write miss information; storing the set ;
receiving a second action from the processor;
enabling the second operation using the set of write miss information stored in the second cache storage;
responsive to a second set of data to be stored in the first cache storage, extracting the first data from the first cache storage to make room for the second set of data; leaving the set; and
storing the first set of data in a first portion of the second cache storage;
A method, including 請求項１９に記載の方法であって、
前記第２のキャッシュストレージの第２の部分の利用を閾値と比較することと、
前記第２の部分の利用が前記閾値を超えることに基づいて前記書き込みミス情報のセットを第２のキャッシュレベルに出力することと、
を更に含む、方法。 20. The method of claim 19, wherein
comparing utilization of a second portion of the second cache storage to a threshold;
outputting the set of write miss information to a second cache level based on utilization of the second portion exceeding the threshold;
The method further comprising:
JP2021569842A 2019-05-24 2020-05-26 Method and Apparatus for Facilitating Write Miscaching in Cache Systems Pending JP2022534891A (en)

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US16/882,258 US11693790B2 (en) 2019-05-24 2020-05-22 Methods and apparatus to facilitate write miss caching in cache system
US16/882,258 2020-05-22
PCT/US2020/034560 WO2020243098A1 (en) 2019-05-24 2020-05-26 Methods and apparatus to facilitate write miss caching in cache system

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