JPWO2020236363A5

JPWO2020236363A5 -

Info

Publication number: JPWO2020236363A5
Application number: JP2021569031A
Authority: JP
Publication date: 2023-04-24

Claims

a server,
a CPU (Central Processing Unit) complex;
is an off-road card,
SoC (system on chip),
an offload card external to said SoC and comprising an FPGA (Field Programmable Gate Array) coupled to said SoC;
with
the CPU complex is configured to run one or more virtual machines (VMs);
the SoC configured to perform in software one or more first functions of a hypervisor associated with the one or more VMs;
the FPGA is configured to perform in hardware one or more second functions of the hypervisor associated with the one or more VMs;
server.

2. The server of claim 1, wherein the SoC and the FPGA are via a PCIe (Peripheral Component Interconnect Express) interface internal to the offload card and an Ethernet interface internal to the offload card. Servers that are communicatively coupled to each other via a.

3. The server of claim 2, wherein the SoC and the FPGA are communicatively coupled to each other via a JTAG (Joint Test Action Group) interface internal to the offload card.

2. The server of claim 1, wherein the offload card is inserted into the mainboard of the server via a PCIe edge connector interface.

5. The server of claim 4, wherein the SoC is communicatively coupled to a baseboard management controller (BMC) of the server through the PCIe edge connector interface.

5. The server of claim 4, wherein said FPGA is communicatively coupled to said CPU complex through said PCIe edge connector interface.

2. The server of claim 1, wherein the SoC is communicatively coupled with one or more volatile memory modules on the offload card, the one or more volatile memory modules comprising: A server acting as a working memory from which said SoC can execute said one or more first functions.

2. The server of claim 1, wherein the SoC is communicatively coupled with a flash memory module residing on the offload card, the flash memory module for the one or more first functions. A server that stores program code for

2. The server of claim 1, wherein the FPGA is communicatively coupled to one or more volatile memory modules on the offload card, the one or more volatile memory modules comprising: A server that acts as a working memory for said FPGA when performing said one or more second functions.

2. The server of claim 1, wherein the FPGA is communicatively coupled to a flash memory module residing on the offload card, the flash memory module performing one or more second functions. a server that stores at least one configuration image for configuring said FPGA in a manner such as;

11. The server of claim 10, wherein the flash memory module has a first configuration image corresponding to a normal operating configuration for the FPGA and a second configuration image corresponding to a failsafe operating configuration for the FPGA. A server that stores the configuration image of the .

12. The server of claim 11, wherein the first configuration image is applied to the FPGA by default upon power up of the offload card.

13. The server of claim 12, wherein the second configuration image is applied to the FPGA if an error occurs while applying the first configuration image.

2. The server of claim 1, wherein the FPGA communicates with a first external network interface communicatively coupled to a TOR (top of rack) network switch and a NIC (network interface card) of the server. A server including a second external network interface operably coupled thereto.

2. The server of claim 1, wherein the SoC is communicatively coupled to a BIOS (basic input/output) flash component residing on the offload card via a security chip, the security chip , a server configured to verify the integrity of firmware stored in said BIOS flash component.

2. The server of claim 1, wherein the one or more first functions comprise network control plane functions or storage control plane functions.

2. The server of claim 1, wherein the one or more second functions comprise network data plane functions or storage data plane functions.

a server,
a CPU (central processing unit) complex configured to run one or more virtual machines (VMs);
is an off-road card,
means for executing in software one or more first functions of a hypervisor associated with the one or more VMs;
means for performing in hardware one or more second functions of the hypervisor associated with the one or more VMs;
a server comprising an offload card comprising:

a method,
A Field Programmable Gate Array (FPGA) on an offload card of a server receives network packets from a NIC (Network Interface Card) of said server, said network packets interconnecting said FPGA and said NIC. received via an Ethernet interface;
the FPGA performing a hardware lookup to a flow table based on the header of the network packet;
Upon determining that no matching entry was found in the flow table for the header, the FPGA forwards the network packet to a system-on-chip (SoC) residing on the offload card; network packets are transferred via an Ethernet interface interconnecting the FPGA and the SoC;
the SoC calculating in software a next-hop destination for the network packet;
said SoC updating said flow table in software with new flow entries containing said next-hop destination.

20. The method of claim 19, wherein upon determining that a matching entry is found in the flow table,
said FPGA updating said network packet based on said matching entry;
said FPGA transmitting said network packet to an external network via said FPGA's external network interface;
The method further comprising