JPWO2020226064A1 - - Google Patents

Info

Publication number
JPWO2020226064A1
JPWO2020226064A1 JP2021518342A JP2021518342A JPWO2020226064A1 JP WO2020226064 A1 JPWO2020226064 A1 JP WO2020226064A1 JP 2021518342 A JP2021518342 A JP 2021518342A JP 2021518342 A JP2021518342 A JP 2021518342A JP WO2020226064 A1 JPWO2020226064 A1 JP WO2020226064A1
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
JP2021518342A
Other versions
JPWO2020226064A5 (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of JPWO2020226064A1 publication Critical patent/JPWO2020226064A1/ja
Publication of JPWO2020226064A5 publication Critical patent/JPWO2020226064A5/ja
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/18—Manufacturability analysis or optimisation for manufacturability
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Geometry (AREA)
  • Evolutionary Computation (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
JP2021518342A 2019-05-07 2020-04-23 Abandoned JPWO2020226064A1 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2019087455 2019-05-07
PCT/JP2020/017456 WO2020226064A1 (ja) 2019-05-07 2020-04-23 欠陥密度計算方法、欠陥密度計算プログラム、欠陥密度計算装置、熱処理制御システムおよび加工制御システム

Publications (2)

Publication Number Publication Date
JPWO2020226064A1 true JPWO2020226064A1 (ja) 2020-11-12
JPWO2020226064A5 JPWO2020226064A5 (ja) 2023-03-14

Family

ID=73051056

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2021518342A Abandoned JPWO2020226064A1 (ja) 2019-05-07 2020-04-23

Country Status (3)

Country Link
US (1) US20220189833A1 (ja)
JP (1) JPWO2020226064A1 (ja)
WO (1) WO2020226064A1 (ja)

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3446572B2 (ja) * 1997-11-11 2003-09-16 信越半導体株式会社 シリコン単結晶中の酸素析出挙動を割り出す方法、およびシリコン単結晶ウエーハ製造工程の決定方法、並びにプログラムを記録した記録媒体
JP2010083712A (ja) * 2008-09-30 2010-04-15 Sumco Corp 結晶欠陥状態予測方法、シリコンウェーハの製造方法
JP6693133B2 (ja) * 2016-01-13 2020-05-13 ソニー株式会社 成膜シミュレーション方法、プログラム、および半導体加工システム
JP6784248B2 (ja) * 2017-09-06 2020-11-11 信越半導体株式会社 点欠陥の評価方法

Also Published As

Publication number Publication date
US20220189833A1 (en) 2022-06-16
WO2020226064A1 (ja) 2020-11-12

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Legal Events

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