JPWO2020176425A5

JPWO2020176425A5 -

Info

Publication number: JPWO2020176425A5
Application number: JP2021549891A
Authority: JP
Publication date: 2023-03-06

Claims

An apparatus for catalytically influenced chemical etching, comprising:
a processing chamber containing a semiconductor wafer;
one or more actuators configured to control environmental properties of one or more locations on the semiconductor wafer ;
with
A current state of the catalytically influenced chemical etch is determined using one or more of optical metrology on the front and back sides of the semiconductor wafer.
A device characterized by:

wherein the one or more actuators are configured to control temperature;
The one or more actuators comprise one or more of thermal chucks, micromirrors and electrodes to locally heat the solution.
2. A device according to claim 1, characterized in that:

2. The apparatus of claim 1, wherein the environmental characteristics include temperature, vapor pressure, electrolysis, etchant concentration, etchant composition and lighting.

2. The apparatus of claim 1, wherein the semiconductor wafer is exposed to an etchant in a vapor state.

2. The apparatus of claim 1, wherein the semiconductor wafer is exposed to an etchant that is in a liquid state.

A method for improving the reliability of catalytically influenced chemical etching, comprising:
patterning a catalyst layer on the surface of the semiconductor material;
exposing the patterned catalyst layer to one or more of an etchant and a time-varying electric field; wherein the patterned catalyst layer and one or more of the etchant and the electric field are connected to the semiconductor; cause material etching and form nanostructures,
creating one or more layers of porosity as the etching progresses, wherein the porosity is controlled by varying one or more properties of the electric field.
A method comprising:

A method for improving the reliability of catalytically influenced chemical etching, comprising:
providing a semiconductor material;
patterning a catalyst layer on the surface of the semiconductor material, wherein the pattern comprises one or more lithographic links;
exposing the patterned catalyst layer to an etchant such that the lithographic links in the patterned catalyst layer facilitate diffusion of the etchant during etching of high aspect ratio structures;
A method comprising:

A method of patterning a catalyst for catalytically affected chemical etching, comprising:
patterning a substrate with lithographic structures, wherein a surface of said substrate is exposed in areas free of said lithographic structures;
selectively depositing a catalyst on the exposed substrate surface;
exposing the substrate and the catalyst to an etchant;
A method comprising:

9. The method of claim 8, wherein the lithographic structure is designed to form a mesh to which the catalyst is connected.

The etching solution is HF or NH, which is a chemical substance. _４4 Fluoride species containing F, H as an oxidizing agent _２2 O. _２2 , KMnO _４4 or at least two of protic, aprotic, polar and non-polar solvents including dissolved oxygen, the alcohols ethanol, isopropyl alcohol or ethylene glycol, or deionized water or dimethyl sulfoxide (DMSO) 9. The method of claim 8, characterized by:

The catalyst is Au, Pt, Pd, Ru, Ag, Cu, Ni, W, TiN, TaN, RuO _２2 , IrO _２2 or graphene.

the catalyst is selectively deposited on a silicon surface using selective atomic layer deposition;
The silicon surface includes a native oxide layer
9. The method of claim 8, wherein:

A method of patterning a catalyst for catalytically affected chemical etching, comprising:
depositing a catalyst on a substrate, wherein said catalyst is patterned with a lithographic structure, said lithographic structure being used as a mask for etching of said catalyst;
exposing the substrate and the catalyst to an etchant;
A method comprising:

A method of etching a semiconductor material, comprising:
patterning a catalyst layer on the surface of the semiconductor material, wherein the catalyst layer comprises a plurality of features;
exposing the patterned catalyst layer to an etchant, wherein the patterned catalyst layer and the etchant cause etching of the semiconductor material to form nanostructures, the material of the catalyst layer contains ruthenium
A method comprising:

A method of etching a semiconductor material, comprising:
patterning a catalyst layer on the surface of the semiconductor material, wherein the catalyst layer comprises a plurality of features;
exposing the patterned catalyst layer to an etchant, wherein the patterned catalyst layer and the etchant cause etching of the semiconductor material to form nanostructures, the material of the catalyst layer is an alloy of two or more materials
A method comprising:

The two or more materials are Au, Pt, Pd, Ru, Ag, Cu, Ni, W, TiN, TaN, RuO _２2 , IrO _２2 , C, Mo, Cr, III-V, II-VI, Ge, semiconductors including metals and semiconductor oxides, metals, and semiconductor nitrides. the method of.

A method of etching a semiconductor material, comprising:
providing a substrate having at least one layer of said semiconductor material;
patterning a catalyst layer on the surface of the semiconductor material, wherein the catalyst layer comprises a plurality of features;
exposing the patterned catalyst layer to an etchant, wherein the patterned catalyst layer and the etchant cause etching of the semiconductor material to form nanostructures;
changing the doping of at least one layer of the semiconductor material;
A method comprising:

A method for preventing substantial collapse of high aspect ratio semiconductor structures formed by catalytically influenced chemical etching, comprising:
creating a support structure by depositing material over the two or more unbroken semiconductor structures;
Exposing the support structure to an etchant to form a higher aspect ratio semiconductor structure in the material of the high aspect ratio semiconductor structure increases the critical height of the feature before collapse to increase the critical height of the high aspect ratio semiconductor structure. preventing substantial collapse of the semiconductor structure of the ratio;
A method comprising:

19. The method of claim 18, wherein the two or more undisrupted semiconductor structures are made using one or more processes of plasma etching, dry etching, chemical etching and catalytically influenced chemical etching.

19. The method of Claim 18, wherein said material has a low surface energy.