WO2022216727A1

WO2022216727A1 - Ultrahigh aspect ratio nanoporous and nanotextured microstructures with exceptionally high surface area prepared using nanopore-mediated metal-assisted chemical etching

Info

Publication number: WO2022216727A1
Application number: PCT/US2022/023511
Authority: WO
Inventors: Donald Stanley GARDNER; Anne Eugenie SAKDINAWAT
Original assignee: The Board of Trustees of the Leland Stanford Junior University Office of the General Counsel
Priority date: 2021-04-05
Filing date: 2022-04-05
Publication date: 2022-10-13

Abstract

Semiconductor structures having high aspect ratio are provided. To make such structures, a new version of metal-assisted chemical etching (MACE) has been developed, where transport of the etchants to etch locations is via substrate porosity, instead of through the metal catalyst layer (as in conventional MACE). This approach provides high aspect ratio microstructures and nanostructuring with a hierarchical architecture, with the control of etch directionality achieved through the interplay of chemical, electrical and mechanical properties. Such structures have various applications, such as energy storage, x-ray optics etc. For energy storage, high aspect ratio structures are useful for increasing energy density in electrochemical capacitors. The side walls of these high aspect ratio structures are porous, and they can be coated with surface coatings to further increase electrochemical capacitor performance.

Description

Ultrahigh Aspect Ratio

Nanoporous and Nanotextured Microstructures with Exceptionally High Surface Area

Prepared using Nanopore-Mediated Metal-Assisted

Chemical Etching

FIELD OF THE INVENTION

This invention relates to fabrication of high aspect ratio structures, for example in relation to energy storage applications using supercapacitors.

BACKGROUND

High surface area microstructures with high-aspect ratios and integrated microscale and nanoscale features with a hierarchical architecture are of interest for a wide variety of applications. The miniaturization and integration of microelectronics has been key to its success, but power sources often become the limitation in achieving the small form factor needed by miniaturized electronics, wearable electronics, and nanorobotics because energy storage components cannot be easily integrated and the progress in miniaturization has been limited.

The development of energy storage devices using semiconductor processing fabrication methods provides an alternative technique to current energy storage fabrication technology. Energy storage devices that can both rapidly capture and provide high power as well as have high energy density with high cyclic lifetimes are thin planar micro electrochemical capacitors also known as ultracapacitors or supercapacitors. The primary challenge with supercapacitors is typically their low energy density. Silicon is already the most commonly used material for the integrated circuits found in every IoT (internet of things) device; however, the efforts to integrate energy storage on a silicon die have been limited.

Accordingly, it would be an advance in the art to provide improved high aspect ratio structures, for example in connection with improved electrochemical capacitors.

SUMMARY

Semiconductor structures having high aspect ratio are provided. Here high aspect ratio means 50:1 or better for the ratio of vertical height or depth to smallest horizontal feature size. To make such structures, a new version of metal-assisted chemical etching (MACE) has been developed, where transport of the etchants to etch locations is via substrate porosity (FIG. 3B), instead of through the metal catalyst layer (FIG. 3A, as in conventional MACE). Such structures have various applications, such as energy storage, x-ray optics etc.

For energy storage, high aspect ratio structures are useful for increasing energy density in electrochemical capacitors. Electrochemical capacitors have two electrodes (high aspect ratio structures as described above) with an electrolyte separated by a porous, ion-permeable membrane and operate by accumulating charge primarily within an electrochemical double layer (EDL). The side walls of these high aspect ratio structures are porous, and they can be coated with surface coatings to further increase electrochemical capacitor performance. For x-ray, gamma ray, neutron, and particle optics and collimators, high aspect ratio structure are useful for implementing phase contrast imaging, other imaging techniques, and they can be used as an analyzer. By coating the sidewalls of these high aspect ratio structures conformally by atomic layer deposition, electroplating or electroless plating or by filling the structures with a suitable material, the performance of the optic or collimator can improve significantly.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A shows an exemplary embodiment of the invention.

FIG. IB shows area normalized Ragone plots comparing devices from this work to various thin film capacitors from the literature.

FIG. 1C shows SEM (scanning electron microscope) images of a high aspect ratio structure with porous side walls and a nanotextured surface coating.

FIGs. 2A-F show measured capacitance performance results from devices of this work.

FIG. 3A shows a prior art metal-assisted chemical etching process.

FIG. 3B shows the metal-assisted chemical etching process of this work.

FIGs. 3C-1 to 3C-6 show an exemplary fabrication sequence.

FIG. 3D shows etch rate characterization for this work.

FIGs. 3E-3H are SEM images of fabricated high aspect ratio structures. FIGs. 4A-C show some effects of different metal catalyst layer thicknesses.

FIG. 5A shows an SEM image of an exemplary post pattern .

FIG. 5B shows an SEM image of an exemplary wide-H pattern .

FIG. 5C shows current-voltage curves for various capacitors of this work.

FIGs. 5D-E are further SEM images of fabricated high aspect ratio structures.

FIG. 6 shows conformal nanotexturing using atomic layer deposition of Pt on the sidewalls of the microstructure.

DETAILED DESCRIPTION

Section A describes general principles relating to embodiments of the invention. Section B describes an experimental investigation of principles relating to embodiments of the invention.

A) General principles

An exemplary embodiment of the invention is apparatus having high aspect ratio features with porous side walls, where the apparatus includes a substrate (e.g., 302 on FIG. 3B) having a feature pattern formed in it, where an aspect ratio of feature depth to feature width in the feature pattern is 50:1 or more, and where side walls (e.g., 112 on FIG. 3B and FIG. 1A) of the feature pattern are porous. Here height and depth are regarded as equivalent for the purpose of defining aspect ratio, since the walls of trenches having depth X can be regarded as posts having height X. The apparatus also includes a patterned metal catalyst layer (e.g., 110 on FIG. 3B and FIG. 3C-6) disposed to cover a bottom plane of the feature pattern, where a thickness of the patterned metal catalyst layer is 70 nm or more. Alternatively, the thickness of the patterned metal catalyst layer can be 100 nm or more, 200 nm or more, 300 nm or more, 400 nm or more, 500 nm or more, etc.

Another exemplary embodiment of the invention is a method of making high-aspect ratio structures having porous side walls. This method includes the step of depositing a patterned metal catalyst layer on a substrate, where the patterned metal catalyst layer has a predetermined pattern of openings etched into it, and where a thickness of the patterned metal catalyst layer is 70 nm or more (e.g., as shown in the example of FIGs. 3C1-3C5). Alternatively, the thickness of the patterned metal catalyst layer can be 100 nm or more, 200 nm or more, 300 nm or more, 400 nm or more, 500 nm or more, etc. The next step (e.g., FIG. 3C-6) is performing a chemical etch that is catalyzed by the patterned metal catalyst layer such that the patterned metal catalyst layer sinks vertically into the substrate with etching beneath the metal catalyst layer enabled by etchant and etchant byproduct transport (e.g., 312 on FIG. 3B) through substrate porosity. The aspect ratio of feature depth to feature width in a finished structure is 50:1 or more. Such a chemical etch can be a liquid phase etch or a gas phase etch.

A capacitor (e.g., 100 on FIG. 1A) can include two high aspect ratio structures as described above (e.g., 102, 104 on FIG. 1A) sandwiching an insulating spacer (e.g., 106 on

FIG. 1A). Such capacitors can include an electrolyte 116 disposed in the micro-trenches of the structure.

Electrolyte 116 can be an ionic liquid. Presently preferred ionic liquid electrolytes include l-Ethyl-3-methylimidazolium tetrafluoroborate (EMIM-BF₄) and l-Ethyl-3-methylimidazolium Trifluoromethanesulfonate (EMIM- Tf). In capacitor structures having surface coating 114 of FIG. 1A, titanium nitride is a preferred surface coating because it appears to have a electrochemical reaction with the electrolyte which increases the energy storage.

Preferably, reactive ion etching of the substrate is done after photoresist patterning and prior to depositing the patterned metal catalyst layer (e.g., as shown on FIG. 3C-3.

In some cases, the method further includes deposition of a surface coating on side walls of the finished structure (e.g., 114 on FIG. 1A). Preferably such a surface coating can infiltrate the pores of the porous side walls of the structure, as schematically shown on FIG. 1A with surface coating 114 within pores 112. The surface coating may or may not fill the pores of the porous side walls and may or may not fill the trenches.

Suitable surface coating materials include, but are not limited to: platinum, ruthenium, ruthenium oxide, palladium, titanium nitride, tantalum nitride, vanadium nitride, niobium nitride, zirconium nitride, tungsten nitride, aluminum oxide, gold, nickel, titanium, chromium, iron, copper, gallium, niobium, molybdenum, ruthenium, indium, tin, hafnium oxide, tantalum, tungsten, iridium, lead, bismuth, and any mixture or alloy thereof. Suitable deposition methods include, but are not limited to: atomic layer deposition, electroplating, electroless plating, and any combination of these methods.

The substrate can be silicon, silicon carbide, germanium, GaAs or any other semiconductor. A presently preferred substrate is heavily boron-doped silicon having a resistivity of less than 0.01 ohm-cm. Exemplary metal catalyst layers include: gold on top of titanium, platinum, gold, platinum on top of titanium, palladium, silver, iron, nickel, aluminum, iridium, copper, cobalt, chromium, molybdenum, vanadium, tungsten and zirconium.

Electronic circuitry (e.g., 108 on FIG. 1A) can be disposed in the substrate. A high energy radiation diffraction element or collimator (e.g., a zone plate or the like) can include a high aspect ratio structure as described above (e.g., as shown on FIG. 3C-6). High aspect ratio structures are needed for this application because the refractive index (or equivalent for particle radiation) of all materials for high energy radiation is very close to 1. Here high energy radiation includes x-rays, gamma rays, and beams of particles (e.g., ions, neutrons, electrons, alphas etc.). The high aspect ratio structure can be placed on a flat or curved substrate to structurally conform to that surface. This can be done either through direct bonding and mounting of the remaining thin silicon substrate onto a separate curved substrate or flip bonding the high aspect ratio silicon structure onto a flexible or fixed curved substrate .

High aspect ratio structures as described above can also be used in sensor applications, e.g., by having a chemical disposed in the feature pattern to provide a functionalized sensor.

An alternative to MACE is metal assisted anodic etching (MAAE). The MAAE etching process is similar to that for MACE, with the difference being that the holes for MACE are produced by the reduction of H2O2, whereas the holes for MAAE are supplied by an external electrical power source. Accordingly, it is expected that MAAE can proceed by etchant and etchant byproduct transport through substrate porosity as described herein for MACE.

B) Experimental example Bl) Introduction

High surface area microstructures with high-aspect ratios and integrated microscale and nanoscale features with a hierarchical architecture are of interest for a wide variety of applications including energy storage devices, environmental and biological sensors, micro-electro- mechanical systems (MEMS), drug delivery structures, optoelectronics, photovoltaics, and high efficiency x-ray optics for phase imaging and diffraction gratings. The miniaturization and integration of microelectronics has been key to its success, but the power sources for these devices often become the limitation in achieving the small form factor needed by miniaturized electronics, wearable electronics, and nanorobotics because energy storage components cannot be easily integrated and the progress in miniaturization has been limited. Integrated microscale energy storage in microelectronics is a key technology for energizing autonomous microsystems capable of operating remotely over extended periods of time and are enabling technologies for "smart dust", edge computing, and the internet of things (IoT) as well as maintenance-free environmental sensors, implantable biosensors, wearable and portable personal electronics, nanorobotics, and devices using energy harvesters. Wireless sensor networks require devices to be places in remote and difficult to access areas requiring self-powered sensors for environmental and industrial monitoring, agriculture, and military applications . The development of energy storage devices using semiconductor processing fabrication methods provides an alternative technique to current energy storage fabrication technology. Integrated thin-film energy storage devices have been constructed in a 2D arrangement, but require large footprints to provide reasonable energies, so areal energy density becomes an important metric given that integrated devices are constrained by area. Optimal performance of energy storage devices and sensors requires hierarchical structures with both microchannels and nanostructures. This study examines a promising research direction for on-chip energy storage devices that can achieve better integration with miniaturized electronics using metal-assisted chemical etching (MACE). This can provide high aspect ratio microstructures and nanostructuring with a hierarchical architecture, with the control of etch directionality achieved through the interplay of chemical, electrical and mechanical properties where the nanostructures such as nanopores and conformal nanotexturing provide high surface area for large reaction surfaces, and integrated microchannels provide fast response times.

Energy storage devices that can both rapidly capture and provide high power as well as have high energy density with high cyclic lifetimes are thin planar micro electrochemical capacitors also known as ultracapacitors or supercapacitors. Electrochemical capacitors have two electrodes with an electrolyte separated by a porous, ion- permeable membrane and operate by accumulating charge primarily within an electrochemical double layer (EDL).

They have the advantage of high power density, fast charge/discharge rates, and long cycling stability and integrate well with energy scavenging technology because they can capture transient electric charge more effectively than batteries and can be cycled many tens of thousands to millions of times thereby eliminating the need of replacing batteries so they would be an excellent choice for daily frequent charging using solar energy. The primary challenge with supercapacitors is typically their low energy density, but in this study, we have developed nanoporous microstructures with conformal nanotexturing that result in significantly high surface area. Large amounts of electrical energy can be stored because of this high surface area and the nanoscopic charge separation at the electrochemical interface between the electrodes and an electrolyte. Such a technology holds significant promise toward enabling the IoT and further enhancing the utilization of sustainable energy.

Silicon is already the most commonly used material for the integrated circuits found in every IoT device; however, the efforts to integrate energy storage on a silicon die have been limited. Silicon nanostructures have already been used as battery anodes in the form of nanowires, nanotubes, nanoporous particles, and porous silicon (P-Si) films. On- chip carbon based materials have been investigated with some success, but thin films typically do not scale up linearly with the thickness of the electrode. In addition, prior studies of planar porous silicon devices had low energy densities, relatively high resistivity, small areal capacitance, and limited lifetimes. Coating or doping the silicon structures reduce the resistance, but the performance was still significantly below carbon on-chip electrochemical capacitors. A study using porous silicon coated with ALD TiN films resulted in an integrated on-chip supercapacitor that used micropores, but the areal energy density of these devices was limited by the shallow depth of the porous silicon structures and the lack of nanotexturing. Higher aspect ratio deep silicon structures have been obtained using deep reactive ion etching (DRIE); however, the process requires specialized vacuum, high frequency electronics, and ion optics and can only achieve a limited etching depth which is strongly influenced by both the aspect ratio and the density of features and the bottoms of the features are typically tapered at higher aspect ratios structures, and sidewall scalloping occurs. Microbatteries have been prepared using DRIE, but with low-aspect-ratio structures and involve lithium electrochemistry that is sensitive to moisture and have limited cyclic lifetimes because of the large volume change associated with the lithiation of Si resulting in the pulverization of the silicon .

B2) Metal-assisted chemical etching

An alternative method to obtain significantly higher aspect ratio structures is metal-assisted chemical etching (MACE) which can provide high aspect ratio microstructures and nanostructuring with a hierarchical architecture, with the control of etch directionality achieved through the interplay of chemical, electrical and mechanical properties. Optimal performance of energy storage devices require both nanopores and microchannels where the nanopores provide high specific surface area for large reaction surfaces and integrated microchannels that provide large pathways for fast response times. MACE is an anisotropic wet etching method capable of providing high aspect ratios with straight sidewalls at low cost and has been developed for fabrication of dense nanostructures in a variety of materials including Si, Ge, and GaAs. The etch occurs when the substrate is exposed to an oxidant such as hydrogen peroxide, which is reduced at the surface of a metal catalyst such as Au, Pt, Ag, or Cu, and injects holes into the substrate. These regions then undergo an oxidative etch in the presence of HF and in certain conditions, etching occurs only directly underneath the catalyst offering great spatial control.

MACE has been successfully applied for fabricating dense nanostructures, such as X-ray zone plates, nanowires, nanoholes, and nanochannels.

B3) Integrated electrochemical capacitors

In this work, integrated electrochemical capacitors compatible with silicon microelectronics were designed and fabricated using ultrahigh aspect-ratio patterned nanoporous microstructures prepared using MACE (see FIGs. 1A-C) and then either conformally coated using extended-exposure ALD TiN or nanotextured using ALD Pt. The nanotexturing process was optimized to create nanoparticles that increase the surface area achieved by functionalizing the surface of the silicon prior to deposition using an organometallic precursor such as trimethylaluminum (TMA). The extended exposure process includes stopping the flow of the pulsed precursors to allow time for the process to penetrate and conformally coat the ultra-high aspect ratio structures.

FIGs. 1A-C relate to supercapacitors prepared using nanoporous microstructures coated with conformal nanotextured films. FIG. 1A is a cross sectional diagram of an electrochemical capacitor 100 formed using two nanoporous microstructured silicon electrodes 102, 104 separated by a porous, ion-permeable membrane 106. Electronic circuitry and/or sensors 108 can be incorporated onto the silicon surface as shown. FIG. IB shows area normalized Ragone plots comparing the areal energy density versus areal power density of devices from this study with a range in depths from 84 to 164 mpi and various thin film capacitors from the literature. FIG. 1C is an SEM image that shows a full thickness cross-sectional image of a Si substrate that includes the top and bottom of the substrate (left). The hierarchical nanoporous microstructure architecture has deep trenches etched into a 625 mpi thick silicon substrate with a nanoporous morphology that is conformally nanotextured with nanoparticles. The vertical trenches are up to 537 mpi deep and 1 (jm wide with porous sidewalls that are 1 mpi thick.

This corresponds to an aspect ratio of more than 500:1 for nanoporous microstructures. Magnified images (center) show the trench structure with the patterned metal at the bottom of the trench and the nanopores. The final image (right) shows the nanotexturing from the ALD coating.

The ultrahigh aspect-ratio patterned microstructures in this study included straight vertical trench structures that are 1 mpiwide and can be up to over 500 (jm deep (aspect ratio > 500:1) (see FIG. 1C) and include nanoporous surfaces prepared using the simple, low-cost, and robust MACE fabrication processes. The nanopore-mediated MACE process is capable of etching through the complete thickness of a silicon wafer with the aspect ratios approximately an order of magnitude higher than that achieved using deep reactive ion etching (DRIE). The porous sidewalls have high specific surface areas and are readily accessible using the wide trenches making them suitable for applications such as energy storage and sensors. The microstructures provide pathways for the ionic charge carriers to move from one electrode to the other and the nanoporous structure provides high surface areas. These hierarchical nanoporous microstructures are subsequently coated with extended- exposure ALD films optimized to penetrate deep into the structures to conformally nanotexture the surfaces thereby enabling the formation of high energy density electrochemical capacitor electrodes. The ALD films also improve the mechanical integrity, conductivity, stability, and prevents degradation during the charge/discharge cycling in energy storage applications.

For an on-chip energy storage device, areal energy density becomes the most important figure of merit because it relates to the energy stored in the device in the limited planar chip area of a microchip. The areal energy density versus areal power density of the electrochemical capacitors were compared to devices from the literature using a Ragone chart in FIG. IB. The areal energy density of the current devices in this study are one to three orders of magnitude higher than other devices on silicon from the literature at areal power densities of 0.1 to 1 mW/cm² (the typical power range needed by sensors, mechanical harvesters and thermoelectric devices) and continue to be higher at 10 mW/cm² (typical power level for sensors with heating and short-range communications). The increase areal energy density is from the increased depth of the structures as well as the nanoporous microstructures and/or conformal nanotexturing from the ALD. The significant performance improvement over the prior art is in part because the thin planar devices in the literature tend to be limited by the process and materials technologies making it difficult to scale vertically.

FIGs. 2A-F show measurements of microsupercapacitors prepared using high surface area silicon nanoporous microstructures 84 mpi deep coated with extended-exposure ALD TiN. FIG. 2A shows electrochemical impedance spectra at zero charge taken during lifetime cycling between 0 to 2 volts for 10,000 cycles. FIG. 2B shows galvanostatic cycling with different charge-discharge rates. The time has been normalized using the applied current density resulting in a plot of voltage versus charge or discharge. FIG. 2C shows electrochemical impedance spectrum at different DC bias voltages. FIG. 2D shows cyclic voltammograms using two- electrode cells at different scan rates. FIG. 2E shows Coulombic efficiency during lifetime cycling between 0 to 2 volts for 10,000 cycles. FIG. 2F shows self-discharge of the cell.

The lifetime of the micro supercapacitors using the high aspect ratio nanoporous microstructures was tested using cyclic voltammetry. Devices coated with extended exposure TiN were cycled 10,000 times at 100 mV/sec with intermediate electrochemical impedance spectra (EIS) recorded from 10 mHz to 400 KHz. The spectrum in FIG. 2A shows minimal change after cycling in the cell window of 0 - 2 V for 10,000 cycles. The voltage window of the device was examined using EIS in FIG. 2C by applying various potential biases to the device while measuring the impedance using a 10 mV AC signal. Based on the impedance spectroscopy, an upper voltage limit of 2.0 V was chosen. Galvanostatic cycling with different charge/discharge rates exhibit a near triangular shape which is the ideal shape of an electrochemical double layer supercapacitor confirming that the devices operates mainly with capacitive properties. Using the 90% to 10% discharge measurement, an estimate of the capacitance is 85 mF/cm² at 0.05 mA/cm² to 33 mF/cm² at 1 mA/cm² for a micro supercapacitor prepared using high surface area silicon nanoporous microstructures 84 mpi deep coated with extended-exposure ALD TiN.

At higher rates, the device is limited by the real impedance of the devices as can be seen in the cyclic voltammetry of FIG. 2D. The real impedance can be determined by examining the EIS at the highest frequency of 400 KHz in FIG. 2A. Devices prepared with these structures can provide planar integrated on-chip energy storage in a compact form factor with minimal packaging and long lifetimes.

B4) Nanopore-mediated metal-assisted chemical etching

FIGs. 3A-H show schematic drawings of the mechanism of mass transport through a nanoporous catalyst versus nanoporous substrate, the etching and fabrication process, MACE etch rates, and cross sectional SEM images. FIG. 3A shows a nanoporous catalyst 304 allows for mass transport 306 through the catalyst 304. In contrast, on FIG. 3B a nanoporous substrate 112, 310 allows for mass transport 312 through the substrate. The latter mechanism allows the use of thicker, more mechanically rigid catalysts 110.

FIGs. 3C-1 to 3C-6 show an exemplary fabrication process flow. FIG. 3C-1 shows the result after Lift-off layer 322 and photoresist 324 are spun on the Si substrate 302. FIG. 3C-2 shows the result after the photoresist 324 is patterned using a lithographic stepper and then developed which also etches the Lift-off layer 322 forming an undercut under the photoresist 324. FIG. 3C-3 shows the result after the Si substrate 302 is briefly dry etched to a certain depth to form shallow features 326. FIG. 3C-4 shows the result after a titanium/gold (Ti/Au) layer

(5-7 nm/200-400 nm), which serves as the metal catalyst, is electron-beam evaporated to deposit metal catalyst 110.

FIG. 3C-5 shows the result after liftoff is performed.

FIG. 3C-6 shows the result after the Si is etched via MACE.

FIG. 3D shows etch rate as a function of the molar ratio p = [HF]/([HF]+[H2O2]). The highest etch rate corresponds to the molar ratio of 0.8. FIGs. 3E-3H are cross section SEM images of etched narrow-H structures. On FIG. 3E, the etch time is 60 min, and the depth is 95 pm. On FIG. 3F, the etch time is 180 min, and the depth is 245 pm. On FIG. 3G, the etch time is 270 min and the depth is 415 pm. On FIG. 3H the sample is the same as on FIG. 3G but the cross section is orthogonal to that of FIG. 3G.

In the MACE etching process, chemical etching occurs in the presence of HF when the substrate is exposed to an oxidant such as hydrogen peroxide, which is reduced at the surface of a metal catalyst. The etching solution influences the formation and morphology of the etched silicon and the relative composition of the etching solution determines the etching rate. In this work, hydrogen peroxide (H2O2) is catalytically reduced by a gold catalyst film, and a hole (h⁺) is injected from the gold into the silicon. The oxidized silicon then etches by reaction with hydrofluoric acid (HF) to form a soluble silicon hexafluoride. Modeling of the chemistry of Si dissolution in HF-H2O2 solutions suggest the maximum etch rate is related to the stoichiometry of the reaction and controlled by mass transport. The etch rate as a function of the molar ratio p = [HF]/([HF]+[H2O2]) in FIG. 3D exhibits a maximum when the molar ratio is 0.8. A mechanism with 3 holes per dissolved Si atom would result in a maximum etch rate at 0.8 and at molar ratios above 0.8, the etch rate is determined by the H2O2 concentration in HF-H2O2 solutions.

The catalyst maintains contact with the silicon by sinking into it as it is etched, so mass transport of etchant and etchant byproducts to and from the active site are required. Control of these physical pathways, through location, dimensions, or restriction, can influence the mechanical motion of catalysts.

Traditionally, very thin catalyst films, often around 10-20 nm, are used in the majority of MACE studies in the literature. In most cases, patterned features with small nanoscale lateral lengths (tens or hundreds of nm) or catalyst nanoporosity (FIG. 3A) provide the mass transport pathways required. The drawback of using thin catalysts, however, is that they are mechanically less rigid and can have a higher likelihood of deformation or breakage during a deep, large area etch or for patterns with longer features, leading to a potentially undesirable etching profile. If the catalyst thickness were increased, the catalyst would become mechanically more rigid and deform less during a deep, large area etch; however, the required mass transport of etchants and byproducts, especially for feature sizes approaching 1 or larger, would become inhibited through traditional means.

The use of nanoporous features in the substrate (FIG. 3B) created during etching for the mass transport and control of etching directionality using nanopore-mediated MACE can lead to a vertical etch profile and high anisotropy can be achieved. The ability to perform extremely deep etches in Si using thick catalysts is demonstrated in FIGs. 3E-H. Etching using highly doped silicon has been shown to form nanopores, so all etches were performed on P⁺⁺ 0.0015 Q-cm Si wafer using MACE and a 200 nm thick Au catalyst with etching times varying from 60 min to 270 min. An etch depth of 95 pm was achieved at 60 min (FIG. 3E),

245 pm at 180 min (FIG. 3F), 415 pm at 270 min (FIGs. 3G-H), and 537 pm at 300 min (FIG. 1C). The etch rate was relatively high at approximately 2 pm/min. Current etch depths were limited by the thickness of the wafer, but the relatively flat and consistent etching front suggests the possibility for even deeper etches.

Significantly thinner catalysts that are from less than 5 nm thick up to tens of nm thick have been typically used for MACE. While mass transport can occur though the nanoporosity in the catalyst, a thin catalyst has a greater likelihood of folding, deforming, or breaking during the etch process due to less structural rigidity, especially for very high aspect ratio, deep etches. This can lead to tapered structures and limitations on overall aspect ratio.

FIG. 4A shows cross-section SEM images of the etched grating (2 hour etch) along the x-axis with 200 nm, 300 nm, and 400 nm thick Au catalysts. In all cases, the Au film sinks down vertically and a uniform high-aspect ratio grating structure is formed. The magnified images of FIG. 4B illustrate the wavy-shaped porous layer at the bottom of the structure with the patterned Au film all on the same plane. FIG. 4C is a comparison of catalyst bending between 200 nm and 400 nm thick catalysts in a narrow-H structure (270 min etch). The first column identifies the cleave plane where the catalyst is observed, and angles between the white dotted lines are measured for each case. It is observed that the 200 nm thick catalyst bends to a larger degree than the 400 nm thick catalysts and that the 400 nm thick catalyst can provide a flatter etching front.

A thicker metal catalyst provides increased mechanical stiffness and stability. The effect of catalyst thicknesses (200 nm, 300 nm, and 400 nm) on substrate nanoporosity are compared using a 2 hour MACE etch on P⁺⁺ Si. In all three cases, a relatively flat etching front and a regular porous region were achieved where the characteristic wave-like pattern of the nanoporous region underneath the catalyst is attributed to the space-charge effect. The thickness of the porous region increased from 1.02 pm to 1.18 pm to 1.38 pm as the Au catalyst thickness increased from 200 nm to 300 nm to 400 nm likely due to more holes being injected.

FIGs. 4A-B illustrate two cross-sections of the MACE etched pillars with 200 nm, 300 nm, and 400 nm thick Au catalysts. FIG. 4A shows that a straight etch front can be achieved in the x-axis, and a magnified image of the bottom of the pillars in FIG. 4B illustrates the spatial distribution of the nanoporosity in each of the three cases.

Taking a closer look at the orthogonal orientation to FIGs. 4A-B, where catalyst dimensions are greater than 10 pm, there are areas of the catalyst which have a single- end-fixed geometry and others which have a two-ends-fixed geometry. The schematic on the left of FIG. 4C depicts where these occur in the pattern. To further explore the effect of catalyst thickness, the deflection angles are compared for two cases. A 270 min MACE etch is performed on P⁺⁺ 0.0015 Q-cm silicon using a 200 nm and a 400 nm thick catalyst. The angles of deflection for the single-end-fixed and the two-ends-fixed geometry were analyzed (see FIG. 4C). For the single-end-fixed geometry, the 200 nm catalyst produced an average bending of 6.9°, and the 400 nm catalyst produced an average bending of 3.1° as shown by the two white dashed lines. This corresponded to an average maximum deflection for the 200 nm catalyst at 1.1 pm, and for the 400 nm catalyst at 0.6 pm. For the two-ends-fixed geometry, the 200 nm catalyst produced an average bending of 4.1° and the 400 nm catalyst produced an average bending of 1.8°. In both geometries, the 400 nm catalyst had 1.9 times less angular deflection than that of the 200 nm catalyst, demonstrating increased stiffness and a flatter etch front with increased catalyst thickness.

B5) Methods

B5a) Pattern formation method The process begins with P-type, boron-doped <100> Si wafers that are first cleaned and annealed in an oven for dehydration at 150 °C and primed using HMDS (Hexamethyldisilazane) for adhesion promotion. A 200 nm thick lift-off layer (LOL) using an inert non-UV-sensitive polymer (Microposit LOL2000) is spin coated on the wafers and baked on a hotplate at 200°C for 5min. A 1 mpi thick photoresist (Shipley 3612) is then spin-coated on the LOL layer and baked on a hotplate at 90°C for 1 min. The wafer is patterned with an ASML PAS 5500/60 photolithographic stepper using an exposure dose of 70 pj/cm². The patterned resist is then post-baked on a hotplate at 115 °C for 1 min and developed using MF-26A developer (2% TMAH, Megaposit) for 50 sec. The developer clears the photoresist and etches the lift-off layer. The wafer is then baked on a hotplate at 115 °C for 1 min. A Si reactive ion etch is performed to remove 100-300 nm of Si, depending on the catalyst thickness. The Si reactive ion etch is not only important for ensuring that there is a clean interface, free of any organic contaminants or oxide, between the silicon and the metal catalyst, but also to help inhibit any lateral sliding of the metal catalyst in the initial stages of the etch.

The metal catalyst layer of 5-7nm Ti followed by 200-400nm Au is then electron beam evaporated onto the patterned wafer. The undercut from the lift-off layer produces a catalyst geometry free from sidewall deposition artifacts. Liftoff is performed using acetone in an ultrasonic bath, followed by developer (Microposit MF319) to fully clean resist off the surface. For the electrochemical capacitors, the Si wafer is partially precut into dies 1 cm on a side before MACE and each piece is cleaned in an UV ozone cleaner for 10 min. B5b) Preparation of nanoporous microstructures

Deep microstructures required much thicker metal catalyst films to achieve straight sidewalls and flat bottoms. Thick catalyst metal films, however, will not have the required film porosity to achieve etching, so a process that involved etching pores around the catalyst has been developed that allowed etchant and the byproducts to diffuse through substrate nanoporosity and around the metal catalyst film (see FIG. 3B). The thick gold catalysts were effectively combined with chemically-etched substrate nanoporosity that enables mass transport of both etchants and etchant byproducts. This nanoporosity is simultaneously created during a novel process variation with MACE. The combination of MACE and an increased catalyst thickness with an order of magnitude greater thickness than traditional catalysts provided greater bending stiffness and substrate nanoporosity and is shown to enable control of the etch directionality .

All samples in these experiments etched using MACE were immersed in an etchant composed of 5:1:1 hydrofluoric acid (HF, 48%) : hydrogen peroxide (H2O2, 30%) : ethanol (C2H6O) by volume at room temperature. The samples are fully immersed in the etching solution at room temperature and then quenched with an ethanol rinse. Samples are dried using either a vacuum or critical point drying.

FIGs. 5A-E are a comparison of the structures used for the electrodes of the micro supercapacitor. FIG. 5A is an SEM top view image of etched post pattern. FIG. 5B is an SEM top view image of etched wide-H pattern. FIG. 5C shows cyclic voltammetry (CV) measurements comparing the wide-H structure of a silicon nanoporous microstructure coated with extended-exposure ALD Pt for 100 cycles at 20 mV/s. Differences in the nanoporous microstructure and its depth (noted in legend) as well as electrolyte results in different CV profiles. FIG. 5D is an SEM top view image of etched H-bar pattern. FIG. 5E is an SEM side view image of etched H-bar pattern.

The design of the capacitor electrode microstructure will have an influence on the performance of the electrochemical capacitor and can be either optimized for higher energy density or higher power density. Higher energy density can be achieved by using a structure that has nanoporous posts with high surface area (see FIG. 5A).

Higher power density can be achieved with a structure having more microscale pathways for the ionic charge carriers to diffuse rapidly from one electrode to the other channels (see FIG. 5B). The post structures, on the other hand, have more nanotextured material per unit volume than the wide-H structure, so result in more capacitance than the post structures .

The devices using EMI-Tf electrolyte showed better performance with both higher energy density and higher power density as compared to the devices using EMI-BF4 electrolyte suggesting that the ionic conductivity and viscosity are better for EMI-Tf. The samples coated with ALD Pt show less ideal capacitive properties than those with ALD TiN (see FIG. 5C vs. FIG. 2D). The design and details of the electrochemical capacitor microstructure can therefore be optimized to best fit the energy needs of an application.

B5c) Conformal nanotextured surface coatings

Atomic layer deposition (ALD) of films in ultra-high aspect ratio features presents unique challenges with the ALD reactor design playing a critical role. Thermal ALD was performed using an extended-exposure process that allows for deeper penetration into the high aspect ratio structures. A Fiji F202 system and a Savannah 100 system from Cambridge Nanotech equipped with a stop valve were used which allows for extended exposures during each deposition cycle. For nanotexturing using Pt depositions, the substrate was heated to 270 °C and the trimethyl (methylcyclopentadienyl) platinum (IV) precursor used was heated from 70 °C to 85 °C.

A typical process had the Pt precursor and oxygen gas alternately pulsed for 75 cycles with the stop valve closed for 20 sec between each pulse, then pumped out for 20 sec to remove the excess precursor along with reaction byproducts. The 1 pm wide trenches aid in the coating process by enhancing precursor diffusion into the nanoporous microstructure. The Pt coatings were successfully deposited to the bottom of 215 pm deep trenches with aspect ratios of over 200:1 as can be seen in the SEM images of FIG. 6. When using 75 ALD cycles of Pt resulting in an approximate thickness of 5 nm, the coating texture was Pt nodules which increases the total surface area.

B5d) Electrochemical capacitor device preparation

Electrical double-layer capacitors (EDLCs) store charge directly in the double layer of the electrode-electrolyte interface where charge is stored between the electrode and electrolyte. Silicon electrodes prepared with nanoporous microstructures were etched to a depth of 100 to 200 pm and then coated using extended-exposure ALD and diced into square electrodes with an area of 1 cm². The patterns used were either a 10 pm post structure (see FIG. 5A) or a two- dimensional grating pattern with 4 pm by 20 pm wide-H shaped structure with 1 pm spaces on all sides (see FIG. 5B). The posts structures were designed to be 10 pm wide with the expectation that the interior would become completely porous during etching. In addition, narrow-H shaped structures were prepared having 1 mpiby 10 jjm structures for etching studies. Silicon buttresses with 0.8 pm widths were used with the H-shaped structures to help support the structures during drying and were placed in between every other pair of pillars (see FIGs. 5B, 5D, and 5E).

A conventional cell with a two-electrode configuration was used for electrochemical characterization and tested using cyclic voltammetry (CV) in a symmetrical two-terminal measurement setup. The electrodes were coated in a N2-filled glove box with ionic liquids (ILs) that contain an imidazolium-based cation that have a high chemical stability and resist moisture. CV measurements used either l-Ethyl-3-methylimidazolium tetrafluoroborate (EMIM-BF4) or l-Ethyl-3-methylimidazolium Trifluoromethanesulfonate (EMIM- Tf) ionic liquid. To improve electrolyte penetration into the microstructure, the electrodes coated with the electrolyte were placed in a vacuum to remove air trapped in the pores. Two silicon electrodes were then assembled in the glove box separated by a paper spacer (Whatman Grade 541) to create a symmetrical electrochemical capacitor as shown in FIG. 1A. The devices were placed into an MTI Corp. split test cell and electrically tested using a Biologic Science Instruments VSP (versatile potentiostat) / galvanostat .

The areal stack capacitance density can be estimated by dividing the current density by the scan rate of 20 mV/s.

The CVs for the ALD Pt coated samples all remain approximately rectangular in shape in FIG. 5C and were repeatable after 100 cycles. The curves show consistent capacitance with minimal change in the measurement from cycle to cycle. The effective series resistance of the devices is from a combination of the resistance of the electrolyte, the thin Pt film, and the resistivity of the porous regions.

The equivalent capacitance C can be estimated from a CV curve by integrating the current I as a function of voltage V as

dV where D5 is the total voltage change and — is the voltage scan rate during the CV measurement. Using Equation 1, the equivalent capacitance can be calculated as a function of scan rate for each device. The capacitance in FIG. 5C is approximately 100 mF/cm² in the relatively flat region between 0.5 V and 2 V. This region represents the majority of the energy stored in the capacitor. The areal capacitance during discharge using charge-discharge measurements was also approximately 100 mF/cm² when using a constant discharge current of 100 microamps. This calculation results in a lower, but more representative capacitance than what would be obtained by simply using the maximum current divided by the scan rate as is sometimes done in the literature.

Energy density measurements were obtained by discharging the devices using a constant power for each data point. The energy is integrated over time where

E = / V x i dt. The energy of the device can be obtained by summing the product of the voltage and current over time as

E = V_ave x i x At where V_ave is the average voltage over the time period At .

B6) Conclusion Hierarchical micro/nanostructures including high-aspect ratio structures with conformal nanotexturing and nanoscale voids have the potential for usage in a variety of applications in energy storage, sensors, optics, drug delivery, MEMS, and catalysis. Self-powered microelectronics are needed for implantable, portable, and wearable devices that can function maintenance-free for extended periods of time. Devices were fabricated with nanoporous and micron- scale structures that include conformal nanotexturing. The etching process uses substrate nanoporosity allowing for thick Au catalysts with increased bending stiffness, an order of magnitude thicker than conventional catalysts, to be utilized with MACE leading to higher etch fidelity over large areas when forming high aspect ratio structures. MACE with substrate nanoporosity and thick catalysts can form nanoporous microstructures with extremely straight vertically oriented 1 pm wide and >500 pm deep features with flat bottoms, corresponding to aspect ratios greater than 500:1. The aspect ratio of these nanoporous microstructures is nearly an order of magnitude higher than the best structures fabricated using deep reactive ion etching (DRIE). Microstructures with porous sidewalls and conformal nanotexturing provide a hierarchical architecture with high specific surface area and are readily accessible using the vertically straight 1 pm wide trenches making them suitable for energy storage.

Electrochemical capacitors were fabricated on a chip with areal energy densities up to 1 mWhr/cm², one to four orders of magnitude higher than other devices on silicon from the literature at areal power densities of a few mW/cm² (the typical power range needed for sensors, mechanical harvesters and thermoelectric devices). The increase was achieved through a combination of ultra-high aspect ratios as well as nanoporous microstructures and/or nanotexturing forming micro supercapacitors that have the potential to provide localized integrated on-chip energy storage. The microscopic design of the devices can be optimized so as to have a higher power density or a higher energy density depending on the application. The electrochemical capacitor electrodes were conformally nanotextured by coating the nanoporous microstructures using atomic layer deposition. Cyclic voltammetry showed excellent long-term cyclic stability with areal capacitance densities of approximately 100 mF/cm². Energy storage devices prepared with these structures provide planar integrated on-chip energy storage in a compact form factor with minimal packaging. This process opens the door for designing and developing a variety of ultra-high aspect ratio microstructures and conformally nanotexturing them with extended-exposure ALD films.

Claims

1. A method of making high-aspect ratio structures having porous side walls, the method comprising: depositing a patterned metal catalyst layer on a substrate, wherein the patterned metal catalyst layer has a predetermined pattern of openings in it, and wherein a thickness of the patterned metal catalyst layer is 70 nm or more; performing a chemical etch that is catalyzed by the patterned metal catalyst layer such that the patterned metal catalyst layer sinks vertically into the substrate with etching beneath the metal catalyst layer enabled by etchant and etchant byproduct transport through substrate porosity; wherein an aspect ratio of feature depth to feature width in a finished structure is 50:1 or more.

2. The method of claim 1, wherein the substrate is selected from the group consisting of: silicon, boron-doped silicon having a resistivity of less than 0.01 ohm-cm, silicon carbide, germanium, gallium nitride, and GaAs.

3. The method of claim 1, further comprising reactive ion etching of the substrate done after patterning of a photoresist and prior to depositing the patterned metal catalyst layer.

4. The method of claim 1, wherein the patterned metal catalyst layer has a composition selected from the group consisting of: gold on top of titanium, platinum, gold, platinum on top of titanium, palladium, silver, iron, nickel, aluminum, iridium, copper, cobalt, chromium, molybdenum, vanadium, tungsten and zirconium.

5. The method of claim 1, further comprising deposition of a surface coating on side walls of the finished structure with a deposition method selected from the group consisting of: atomic layer deposition, electroplating, electroless plating, filling, and any combination thereof.

6. The method of claim 5 wherein the surface coating comprises a material selected from the group consisting of: platinum, ruthenium, ruthenium oxide, palladium, titanium nitride, tantalum nitride, vanadium nitride, niobium nitride, zirconium nitride, tungsten nitride, aluminum oxide, gold, nickel, titanium, chromium, iron, copper, gallium, niobium, molybdenum, ruthenium, indium, tin, hafnium oxide, tantalum, tungsten, iridium, lead, and bismuth, and any mixture or alloy thereof.

7. The method of claim 1, further comprising fabricating electronic circuitry in the substrate.

8. Apparatus having porous side walls and high aspect ratio features, the apparatus comprising: a substrate having a feature pattern formed in it, wherein an aspect ratio of feature depth to feature width in the feature pattern is 50:1 or more, and wherein side walls of the feature pattern are porous; a patterned metal catalyst layer disposed to cover a bottom plane of the feature pattern, wherein a thickness of the patterned metal catalyst layer is 70 nm or more.

9. A capacitor comprising two apparatuses according to claim 8 sandwiching an insulating spacer.

10. The apparatus of claim 8, wherein the substrate is selected from the group consisting of: silicon, boron-doped silicon having a resistivity of less than 0.01 ohm-cm, silicon carbide, germanium, gallium nitride, and GaAs.

11. The apparatus of claim 8, wherein the patterned metal catalyst layer has a composition selected from the group consisting of: gold on top of titanium, platinum, gold, platinum on top of titanium, palladium, silver, iron, nickel, aluminum, iridium, copper, cobalt, chromium, molybdenum, vanadium, tungsten and zirconium.

12. The apparatus of claim 8, further comprising a surface coating disposed on side walls of the feature pattern.

13. The apparatus of claim 8, further comprising electronic circuitry disposed in the substrate.

14. A diffraction or collimation element for high energy radiation including the apparatus of claim 8.

15. A sensor including the apparatus of claim 8 and further comprising a chemical disposed in the feature pattern to provide a functionalized sensor.