JPWO2020156797A5 - - Google Patents

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JPWO2020156797A5
JPWO2020156797A5 JP2021534351A JP2021534351A JPWO2020156797A5 JP WO2020156797 A5 JPWO2020156797 A5 JP WO2020156797A5 JP 2021534351 A JP2021534351 A JP 2021534351A JP 2021534351 A JP2021534351 A JP 2021534351A JP WO2020156797 A5 JPWO2020156797 A5 JP WO2020156797A5
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Japan
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data
data processing
store instruction
status
buffer
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JP2021534351A
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Japanese (ja)
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JP7379491B2 (ja
JP2022518349A (ja
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Priority claimed from PCT/EP2020/050757 external-priority patent/WO2020156797A1/en
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JP2021534351A 2019-01-31 2020-01-14 入出力ストア命令をハンドリングする方法、システム、およびプログラム Active JP7379491B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
EP19154735 2019-01-31
EP19154735.5 2019-01-31
PCT/EP2020/050757 WO2020156797A1 (en) 2019-01-31 2020-01-14 Handling an input/output store instruction

Publications (3)

Publication Number Publication Date
JP2022518349A JP2022518349A (ja) 2022-03-15
JPWO2020156797A5 true JPWO2020156797A5 (enExample) 2022-06-22
JP7379491B2 JP7379491B2 (ja) 2023-11-14

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JP2021534351A Active JP7379491B2 (ja) 2019-01-31 2020-01-14 入出力ストア命令をハンドリングする方法、システム、およびプログラム

Country Status (11)

Country Link
US (2) US11074203B2 (enExample)
EP (1) EP3918467B1 (enExample)
JP (1) JP7379491B2 (enExample)
KR (1) KR102681251B1 (enExample)
CN (1) CN113366438B (enExample)
ES (1) ES3015283T3 (enExample)
HU (1) HUE070517T2 (enExample)
PL (1) PL3918467T3 (enExample)
SG (1) SG11202104428PA (enExample)
WO (1) WO2020156797A1 (enExample)
ZA (1) ZA202105522B (enExample)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3918467B1 (en) 2019-01-31 2025-02-26 International Business Machines Corporation Handling an input/output store instruction
TWI773959B (zh) 2019-01-31 2022-08-11 美商萬國商業機器公司 用於處理輸入輸出儲存指令之資料處理系統、方法及電腦程式產品
TWI767175B (zh) 2019-01-31 2022-06-11 美商萬國商業機器公司 用於處理輸入輸出儲存指令之資料處理系統、方法及電腦程式產品
CN113366457B (zh) 2019-01-31 2024-06-14 国际商业机器公司 处理输入/输出存储指令

Family Cites Families (50)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2273317B1 (enExample) * 1974-05-28 1976-10-15 Philips Electrologica
US4947316A (en) 1983-12-29 1990-08-07 International Business Machines Corporation Internal bus architecture employing a simplified rapidly executable instruction set
US5131081A (en) 1989-03-23 1992-07-14 North American Philips Corp., Signetics Div. System having a host independent input/output processor for controlling data transfer between a memory and a plurality of i/o controllers
US5317739A (en) 1992-03-30 1994-05-31 International Business Machines Corp. Method and apparatus for coupling data processing systems
US5548735A (en) * 1993-09-15 1996-08-20 International Business Machines Corporation System and method for asynchronously processing store instructions to I/O space
US5553302A (en) 1993-12-30 1996-09-03 Unisys Corporation Serial I/O channel having independent and asynchronous facilities with sequence recognition, frame recognition, and frame receiving mechanism for receiving control and user defined data
JPH07302200A (ja) * 1994-04-28 1995-11-14 Hewlett Packard Co <Hp> 順次付けロード動作および順序付け記憶動作を強制する命令を有するコンピュータのロード命令方法。
US5548788A (en) 1994-10-27 1996-08-20 Emc Corporation Disk controller having host processor controls the time for transferring data to disk drive by modifying contents of the memory to indicate data is stored in the memory
DE19631289A1 (de) * 1996-08-02 1998-02-05 Ibm Verfahren zum Testen eines Protokollumsetzers und Protokollumsetzer
US6072781A (en) 1996-10-22 2000-06-06 International Business Machines Corporation Multi-tasking adapter for parallel network applications
US6085277A (en) 1997-10-15 2000-07-04 International Business Machines Corporation Interrupt and message batching apparatus and method
US6247097B1 (en) 1999-01-22 2001-06-12 International Business Machines Corporation Aligned instruction cache handling of instruction fetches across multiple predicted branch instructions
US6189088B1 (en) 1999-02-03 2001-02-13 International Business Machines Corporation Forwarding stored dara fetched for out-of-order load/read operation to over-taken operation read-accessing same memory location
US6496277B1 (en) 1999-07-23 2002-12-17 Xerox Corporation Data flow control and storage facility for an image reproduction system
US6725348B1 (en) 1999-10-13 2004-04-20 International Business Machines Corporation Data storage device and method for reducing write misses by completing transfer to a dual-port cache before initiating a disk write of the data from the cache
US6490647B1 (en) 2000-04-04 2002-12-03 International Business Machines Corporation Flushing stale data from a PCI bus system read prefetch buffer
US6578102B1 (en) 2000-04-18 2003-06-10 International Business Machines Corporation Tracking and control of prefetch data in a PCI bus system
US7042881B1 (en) 2001-06-29 2006-05-09 Cisco Technology, Inc. Asynchronous transfer mode system and method to verify a connection
US7178019B2 (en) 2003-11-13 2007-02-13 Hewlett-Packard Development Company, L.P. Networked basic input output system read only memory
US7234004B2 (en) * 2003-12-19 2007-06-19 International Business Machines Corporation Method, apparatus and program product for low latency I/O adapter queuing in a computer system
US7200626B1 (en) 2004-01-22 2007-04-03 Unisys Corporation System and method for verification of a quiesced database copy
US7079978B2 (en) 2004-05-24 2006-07-18 International Business Machines Corporation Apparatus, system, and method for abbreviated library calibration
US7467325B2 (en) * 2005-02-10 2008-12-16 International Business Machines Corporation Processor instruction retry recovery
US7631097B2 (en) 2005-07-21 2009-12-08 National Instruments Corporation Method and apparatus for optimizing the responsiveness and throughput of a system performing packetized data transfers using a transfer count mark
US7827433B1 (en) 2007-05-16 2010-11-02 Altera Corporation Time-multiplexed routing for reducing pipelining registers
US7870351B2 (en) 2007-11-15 2011-01-11 Micron Technology, Inc. System, apparatus, and method for modifying the order of memory accesses
US7941627B2 (en) 2008-02-01 2011-05-10 International Business Machines Corporation Specialized memory move barrier operations
US7991981B2 (en) 2008-02-01 2011-08-02 International Business Machines Corporation Completion of asynchronous memory move in the presence of a barrier operation
US8867344B2 (en) 2008-07-21 2014-10-21 Mediatek Inc. Methods for bus data transmission and systems utilizing the same
US8566480B2 (en) * 2010-06-23 2013-10-22 International Business Machines Corporation Load instruction for communicating with adapters
US8650335B2 (en) * 2010-06-23 2014-02-11 International Business Machines Corporation Measurement facility for adapter functions
JP5680466B2 (ja) 2011-03-29 2015-03-04 三菱重工業株式会社 並列処理システム及び並列処理システムの動作方法
US9524163B2 (en) 2013-10-15 2016-12-20 Mill Computing, Inc. Computer processor employing hardware-based pointer processing
CN103593169B (zh) * 2013-11-29 2017-09-05 深圳中微电科技有限公司 一种多线程处理器中的指令输出装置、方法及其处理器
US20150261535A1 (en) * 2014-03-11 2015-09-17 Cavium, Inc. Method and apparatus for low latency exchange of data between a processor and coprocessor
US10120681B2 (en) 2014-03-14 2018-11-06 International Business Machines Corporation Compare and delay instructions
US9588914B2 (en) 2014-04-09 2017-03-07 International Business Machines Corporation Broadcast and unicast communication between non-coherent processors using coherent address operations
US9460019B2 (en) * 2014-06-26 2016-10-04 Intel Corporation Sending packets using optimized PIO write sequences without SFENCEs
US9477481B2 (en) 2014-06-27 2016-10-25 International Business Machines Corporation Accurate tracking of transactional read and write sets with speculation
GB2531011A (en) * 2014-10-07 2016-04-13 Ibm Initializing I/O Devices
US9542201B2 (en) 2015-02-25 2017-01-10 Quanta Computer, Inc. Network bios management
US9971545B1 (en) * 2016-03-23 2018-05-15 Crossbar, Inc. Non-volatile write and read cache for storage media
US10248509B2 (en) 2016-11-16 2019-04-02 International Business Machines Corporation Executing computer instruction including asynchronous operation
EP4089531B1 (en) 2016-12-31 2024-06-26 Intel Corporation Systems, methods, and apparatuses for heterogeneous computing
US10452278B2 (en) 2017-03-24 2019-10-22 Western Digital Technologies, Inc. System and method for adaptive early completion posting using controller memory buffer
US10606591B2 (en) * 2017-10-06 2020-03-31 International Business Machines Corporation Handling effective address synonyms in a load-store unit that operates without address translation
EP3918467B1 (en) * 2019-01-31 2025-02-26 International Business Machines Corporation Handling an input/output store instruction
CN113366457B (zh) 2019-01-31 2024-06-14 国际商业机器公司 处理输入/输出存储指令
TWI773959B (zh) 2019-01-31 2022-08-11 美商萬國商業機器公司 用於處理輸入輸出儲存指令之資料處理系統、方法及電腦程式產品
TWI767175B (zh) 2019-01-31 2022-06-11 美商萬國商業機器公司 用於處理輸入輸出儲存指令之資料處理系統、方法及電腦程式產品

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