JPWO2020145891A5 - - Google Patents
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- JPWO2020145891A5 JPWO2020145891A5 JP2021540336A JP2021540336A JPWO2020145891A5 JP WO2020145891 A5 JPWO2020145891 A5 JP WO2020145891A5 JP 2021540336 A JP2021540336 A JP 2021540336A JP 2021540336 A JP2021540336 A JP 2021540336A JP WO2020145891 A5 JPWO2020145891 A5 JP WO2020145891A5
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- forming
- substrate
- thickness
- buffer layer
- semiconductor device
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- 239000000758 substrate Substances 0.000 claims description 14
- 238000000034 method Methods 0.000 claims description 12
- 238000005253 cladding Methods 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 4
- 238000004519 manufacturing process Methods 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 claims 7
- 229910004541 SiN Inorganic materials 0.000 claims 2
- 229910004298 SiO 2 Inorganic materials 0.000 claims 2
- 229910020160 SiON Inorganic materials 0.000 claims 2
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 238000005530 etching Methods 0.000 claims 1
- 238000005755 formation reaction Methods 0.000 claims 1
- WGTYBPLFGIVFAS-UHFFFAOYSA-M Tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 229920002799 BoPET Polymers 0.000 description 1
- 239000005041 Mylar™ Substances 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive Effects 0.000 description 1
Description
図1は、フォトニクスチップを製造するための典型的なプロセスの例を示す。基板100は、基板上に例えば埋め込み酸化物層(BOX:Buried Oxide Layer)レイヤ102を加えるプロセスである。導波路104が堆積され、クラッドレイヤ106が適用される。デバイスは、複数の深いトレンチ108(そのうちの二つを示す)を含むように処理される。これは、後の段階で個々のチップを互いに分離できるようにするためである。チップの処理が完了すると、バックグラインド処理がウエハ上で実行され(図示しない接着性裏当てシート上に載置される)、図1に示すような装置が得られる。厚さ要件があまり薄くない場合、最終的なウエハは、実行可能なデバイスの均一な広がりを有する。しかしながら、より薄いデバイスや、バックグラインドに関連する他の問題のため、バックグラインド後にチップが実質的に残っていないほどに、ウエハ全体が損傷する可能性がある。ウエハは、機械的なバックグラインドによって直接薄くされる。厚さ制御と歩留りは薄いチップでは非常に低い。 FIG. 1 shows an example of a typical process for manufacturing photonics chips. Substrate 100 is a process that adds, for example, a Buried Oxide Layer (BOX) layer 102 over the substrate. A waveguide 104 is deposited and a cladding layer 106 is applied. The device is processed to include a plurality of deep trenches 108 (two of which are shown). This is so that the individual chips can be separated from each other at a later stage. After chip processing is complete, a backgrinding process is performed on the wafer (which is placed on an adhesive backing sheet, not shown), resulting in the device shown in FIG. If the thickness requirement is not too thin, the final wafer will have a uniform spread of viable devices. However, thinner devices and other problems associated with backgrinding can damage the entire wafer so that virtually no chips remain after backgrinding. The wafer is thinned directly by mechanical backgrinding. Thickness control and yield are very poor for thin chips.
ウエハが製造され、トレンチが形成された後、ウエハは、マイラフィルム(図示せず)又はUVテープなどのフィルムに取り付けられる。フィルムがクラッドレイヤに適用され、プロセスの次の段階でチップを所定の位置に保持する。一旦フィルムによって支持されると、ウエハは、基板全体を除去するプロセスを受ける。これは、少なくとも部分的にはバックグラインドプロセスを含むことができる。バックグラインドを使用して、基板は元の厚さから約50μm(±25μm)に減少させ、残りの全厚さが約100μmになり、これは、バックグラインド歩留まりが十分であることを保証するための最小厚さである。これは、バックグラインディングによって除去される基板の量は、ウエハの上にある表面への損傷を防止するために最適であるように選択される。得られた装置を図2に示す。バックグラインドプロセスは、グラインダを用いてウエハをフィルム上に支持しながら基板の一部を研削することを含む。 After the wafer is fabricated and the trenches are formed, the wafer is attached to a film such as Mylar film (not shown) or UV tape. A film is applied to the cladding layer to hold the chip in place during the next stage of the process. Once supported by the film, the wafer undergoes a process that removes the entire substrate. This can include, at least in part, a background grinding process. Using backgrinding, the substrate is reduced from its original thickness to about 50 μm (±25 μm), leaving a total remaining thickness of about 100 μm, to ensure that the backgrinding yield is sufficient. is the minimum thickness of This is because the amount of substrate removed by backgrinding is selected to be optimal to prevent damage to the overlying surface of the wafer. The resulting device is shown in FIG . The backgrinding process involves grinding a portion of the substrate while supporting the wafer on the film using a grinder.
本発明の次の段階では、グラインドされたウエハはシリコンウェットエッチングプロセスを受け、図2に示すように、残りを基板に除去する。ウェットエッチングプロセスは、残りのシリコンを除去し、チップを自動的に分離するために、基板シリコンを水酸化テトラメチルアンモニウム(TMAH:Tetramethylammonium hydroxide)などの溶液に曝露することを含む。 In the next step of the invention, the ground wafer undergoes a silicon wet etch process to remove the remainder to the substrate as shown in FIG . The wet etching process involves exposing the substrate silicon to a solution such as tetramethylammonium hydroxide (TMAH) to remove residual silicon and automatically separate the chips.
図2に見られるように、ウェットエッチングプロセスは、深いトレンチの底部までのすべての材料を除去する。バッファレイヤはエッチング不可能な材料で作られているのでエッチングされない。バッファレイヤの厚さは、得られるチップが必要な厚さになるようにあらかじめ定められている。したがって、得られたデバイスは、通常この目的に役立つ基板ではなく、サポートレイヤとしてバッファレイヤを有する。
As seen in FIG. 2 , the wet etch process removes all material down to the bottom of the deep trench. The buffer layer is made of a non-etchable material and is not etched. The thickness of the buffer layer is predetermined so that the resulting chip has the required thickness. The resulting device therefore has a buffer layer as a support layer, rather than a substrate which normally serves this purpose.
Claims (8)
厚みが50μmより薄い、半導体装置。 a buffer layer comprising at least one of SiO 2 , SiON and SiN and having a predetermined thickness ; and an etch stop layer deposited over the buffer layer;
A semiconductor device having a thickness of less than 50 μm .
基板を形成し、
前記基板上に、SiO 2 、SiON、及びSiNの少なくとも1つから、前記半導体装置に要求される厚さに関連する所定の厚さを有するバッファレイヤを形成し、
前記バッファレイヤ上にエッチストップレイヤを形成し、
前記エッチストップレイヤ上に複数のデバイスを形成し、
前記デバイス上にクラッド材料の少なくとも1つのレイヤを形成し、
前記レイヤ内に少なくとも前記基板まで延びる複数のトレンチを形成し、
前記クラッド材料の上にフィルムを適用し、
各デバイスをウエハ上の他のものから分離するために、エッチングプロセスを用いて、少なくとも部分的に前記基板を除去することを有し、
前記デバイスの厚みは50μmより薄い、半導体装置の製造方法。 A method for manufacturing a plurality of semiconductor devices,
forming a substrate,
forming a buffer layer of at least one of SiO 2 , SiON and SiN on the substrate and having a predetermined thickness related to the thickness required for the semiconductor device;
forming an etch stop layer on the buffer layer;
forming a plurality of devices on the etch stop layer;
forming at least one layer of cladding material over the device;
forming a plurality of trenches in the layer extending to at least the substrate;
applying a film over the cladding material;
removing at least partially the substrate using an etching process to separate each device from others on the wafer ;
A method of manufacturing a semiconductor device, wherein the thickness of the device is less than 50 μm .
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
SG10201900239Y | 2019-01-11 | ||
SG10201900239YA SG10201900239YA (en) | 2019-01-11 | 2019-01-11 | An ultra-thin integrated chip and manufacture of the same |
PCT/SG2019/050641 WO2020145891A1 (en) | 2019-01-11 | 2019-12-26 | An ultra-thin integrated chip and manufacture of the same |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2022518001A JP2022518001A (en) | 2022-03-11 |
JPWO2020145891A5 true JPWO2020145891A5 (en) | 2023-01-06 |
Family
ID=71522291
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2021540336A Pending JP2022518001A (en) | 2019-01-11 | 2019-12-26 | Ultra-thin integrated chip and its manufacturing method |
Country Status (5)
Country | Link |
---|---|
US (1) | US20220043205A1 (en) |
JP (1) | JP2022518001A (en) |
CN (1) | CN113924643A (en) |
SG (1) | SG10201900239YA (en) |
WO (1) | WO2020145891A1 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
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GB2609636A (en) * | 2021-08-11 | 2023-02-15 | Ligentec Sa | Stress-relief structure for photonic integrated circuits |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5071792A (en) * | 1990-11-05 | 1991-12-10 | Harris Corporation | Process for forming extremely thin integrated circuit dice |
US6625357B2 (en) * | 1999-03-29 | 2003-09-23 | Tyco Electronics Corporation | Method for fabricating fiducials for passive alignment of opto-electronic devices |
CN100384038C (en) * | 2004-09-16 | 2008-04-23 | 中国科学院半导体研究所 | Method for producing stacked electric absorption modulated laser structure of selected zone epitaxial growth |
KR101343343B1 (en) * | 2012-01-02 | 2013-12-19 | 한국과학기술원 | 3d stack package of semi-conductor chip and manufacturing method thereof |
US9275916B2 (en) * | 2013-05-03 | 2016-03-01 | Infineon Technologies Ag | Removable indicator structure in electronic chips of a common substrate for process adjustment |
FR3007576B1 (en) * | 2013-06-19 | 2015-07-10 | Soitec Silicon On Insulator | METHOD OF TRANSFERRING A LAYER OF CIRCUITS. |
US20190057959A1 (en) * | 2015-06-06 | 2019-02-21 | Monolithic 3D Inc. | Semiconductor device and structure with thermal isolation |
CN105097480A (en) * | 2015-08-08 | 2015-11-25 | 海门市明阳实业有限公司 | Wafer thinning processing method |
-
2019
- 2019-01-11 SG SG10201900239YA patent/SG10201900239YA/en unknown
- 2019-12-26 US US17/415,024 patent/US20220043205A1/en active Pending
- 2019-12-26 JP JP2021540336A patent/JP2022518001A/en active Pending
- 2019-12-26 WO PCT/SG2019/050641 patent/WO2020145891A1/en active Application Filing
- 2019-12-26 CN CN201980088796.1A patent/CN113924643A/en active Pending
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