JPWO2020117377A5 - - Google Patents

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JPWO2020117377A5
JPWO2020117377A5 JP2021532113A JP2021532113A JPWO2020117377A5 JP WO2020117377 A5 JPWO2020117377 A5 JP WO2020117377A5 JP 2021532113 A JP2021532113 A JP 2021532113A JP 2021532113 A JP2021532113 A JP 2021532113A JP WO2020117377 A5 JPWO2020117377 A5 JP WO2020117377A5
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integrated circuit
extracted
instructions
predetermined
circuit
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JP2021532113A
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JP7510932B2 (ja
JP2022511528A5 (https=
JP2022511528A (ja
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JP2021532113A 2018-12-06 2019-10-16 集積回路、およびデータクエリを加速させる方法 Active JP7510932B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US16/212,134 US10963460B2 (en) 2018-12-06 2018-12-06 Integrated circuits and methods to accelerate data queries
US16/212,134 2018-12-06
PCT/US2019/056496 WO2020117377A1 (en) 2018-12-06 2019-10-16 Integrated circuits and methods to accelerate data queries

Publications (4)

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JP2022511528A JP2022511528A (ja) 2022-01-31
JPWO2020117377A5 true JPWO2020117377A5 (https=) 2022-09-26
JP2022511528A5 JP2022511528A5 (https=) 2022-09-26
JP7510932B2 JP7510932B2 (ja) 2024-07-04

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US (1) US10963460B2 (https=)
EP (1) EP3850499A1 (https=)
JP (1) JP7510932B2 (https=)
KR (1) KR102933455B1 (https=)
CN (1) CN113168409B (https=)
WO (1) WO2020117377A1 (https=)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11836171B2 (en) * 2020-11-13 2023-12-05 Google Llc Demand based dynamic creation of data analytics query accelerators
US20220321403A1 (en) * 2021-04-02 2022-10-06 Nokia Solutions And Networks Oy Programmable network segmentation for multi-tenant fpgas in cloud infrastructures
CN113535745B (zh) 2021-08-09 2022-01-18 威讯柏睿数据科技(北京)有限公司 一种层次化数据库操作加速系统和方法
US11880568B2 (en) 2021-11-17 2024-01-23 Seagate Technology Llc On demand configuration of FPGA interfaces
CN115827682B (zh) * 2023-02-10 2023-04-18 山东浪潮科学研究院有限公司 一种数据库查询加速引擎装置、方法及存储介质
CN116028541B (zh) * 2023-02-15 2023-06-20 山东浪潮科学研究院有限公司 一种数据向量化聚集方法、装置、设备及存储介质
CN116383240B (zh) * 2023-02-21 2025-10-10 山东浪潮数据库技术有限公司 基于fpga多数据库加速查询方法、装置、设备及介质
US12554507B2 (en) 2023-04-11 2026-02-17 Samsung Electronics Co., Ltd. Systems and methods for processing formatted data in computational storage
US12353916B2 (en) 2023-04-11 2025-07-08 Samsung Electronics Co., Ltd. Systems and methods for processing functions in computational storage
CN116991893B (zh) * 2023-07-10 2026-03-06 广东人工智能与先进计算研究院 Fpga加速数据库查询方法、装置、设备及介质

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5488729A (en) 1991-05-15 1996-01-30 Ross Technology, Inc. Central processing unit architecture with symmetric instruction scheduling to achieve multiple instruction launch and execution
US6223208B1 (en) 1997-10-03 2001-04-24 International Business Machines Corporation Moving data in and out of processor units using idle register/storage functional units
US6411951B1 (en) 1998-12-16 2002-06-25 Microsoft Corporation Evaluating SQL subqueries
US7580971B1 (en) 2001-01-11 2009-08-25 Oracle International Corporation Method and apparatus for efficient SQL processing in an n-tier architecture
US7856543B2 (en) 2001-02-14 2010-12-21 Rambus Inc. Data processing architectures for packet handling wherein batches of data packets of unpredictable size are distributed across processing elements arranged in a SIMD array operable to process different respective packet protocols at once while executing a single common instruction stream
US7149829B2 (en) 2003-04-18 2006-12-12 Sonics, Inc. Various methods and apparatuses for arbitration among blocks of functionality
US8407433B2 (en) 2007-06-25 2013-03-26 Sonics, Inc. Interconnect implementing internal controls
CN101021874B (zh) 2007-03-21 2010-05-26 金蝶软件(中国)有限公司 一种对查询sql请求进行优化的方法及装置
US8260803B2 (en) 2010-09-23 2012-09-04 Hewlett-Packard Development Company, L.P. System and method for data stream processing
CN102567944B (zh) 2012-03-09 2013-10-30 中国人民解放军信息工程大学 基于fpga的ct图像重建硬件加速方法
US9600522B2 (en) 2012-08-20 2017-03-21 Oracle International Corporation Hardware implementation of the aggregation/group by operation: filter method
JP6224359B2 (ja) * 2013-06-20 2017-11-01 株式会社Screenホールディングス 基板処理装置のためのスケジュール作成方法およびスケジュール作成プログラム
US10255320B1 (en) * 2014-01-27 2019-04-09 Microstrategy Incorporated Search integration
WO2015149830A1 (en) * 2014-03-31 2015-10-08 Huawei Technologies Co., Ltd. Event processing system
JP6316503B2 (ja) * 2015-05-18 2018-04-25 株式会社日立製作所 計算機システム、アクセラレータ及びデータベースの処理方法
US10185699B2 (en) * 2016-03-14 2019-01-22 Futurewei Technologies, Inc. Reconfigurable data interface unit for compute systems

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