JPWO2020026892A1 - Solid-state image sensor and electronic equipment - Google Patents

Abstract

The present technology relates to a solid-state image sensor and an electronic device capable of responding to fluctuations in characteristics depending on the direction in which a current flows. A pixel array unit in which pixels having a photoelectric conversion unit are arranged two-dimensionally is provided, and the transistor of the pixel has a different amount of overlap to the lower side of the gate in the LDD region on the source side and the LDD region on the drain side, and , A solid-state imaging device having a structure in which the bonding depth of the LDD region on the source side and the bonding depth of the LDD region on the drain side are different is provided. This technology can be applied to, for example, a CMOS image sensor.

Description

The present technology relates to a solid-state image sensor and an electronic device, and more particularly to a solid-state image sensor and an electronic device capable of responding to fluctuations in characteristics depending on the direction in which a current flows.

In recent years, CMOS (Complementary Metal Oxide Semiconductor) image sensors have become widespread. In a CMOS image sensor, a source follower pixel readout circuit is widely used as a circuit for reading out signal charges photoelectrically converted by a plurality of pixels arranged in a pixel array section. Further, as a circuit for reading a signal charge with high conversion efficiency, there are a source grounded pixel read circuit and a differential pixel read circuit.

Patent Document 1 discloses a structure of a pixel transistor in which the drain side is composed of only a high-concentration impurity region and the source side is composed of a combination of a high-concentration impurity region and a low-concentration impurity region. ..

Further, in Patent Document 2, as a structure of a pixel transistor, an N layer having a lower impurity concentration than the LDD layer is formed in an LDD (Lightly Doped Drain) layer constituting a drain layer of a MOSFET having Halo, and a channel is formed. A structure is disclosed in which the impurity concentration at the end of the drain region on the region side is reduced and the LDD layer on the source region side is formed at a shallow bonding depth concentration.

Japanese Unexamined Patent Publication No. 2013-45878 Japanese Unexamined Patent Publication No. 2013-69913

However, the technique disclosed in the above-mentioned patent document does not assume a case where the current flows in both directions in the pixel transistor, and therefore, in order to cope with the fluctuation of the characteristics according to the current flow direction. Technology is required.

This technology was made in view of such a situation, and makes it possible to deal with fluctuations in characteristics depending on the direction in which current flows.

The solid-state image sensor on one side of the present technology includes a pixel array unit in which pixels having a photoelectric conversion unit are arranged in a two-dimensional manner, and the transistors of the pixels are the LDD (Lightly Doped Drain) region on the source side and the drain side. This is a solid-state image sensor having a structure in which the amount of overlap to the lower side of the gate in the LDD region of the above is different, and the bonding depth of the LDD region on the source side and the bonding depth of the LDD region on the drain side are different.

The electronic device on one aspect of the present technology includes a pixel array unit in which pixels having a photoelectric conversion unit are arranged in a two-dimensional manner, and the transistor of the pixel is a gate in an LDD region on the source side and an LDD region on the drain side. This is an electronic device equipped with a solid-state image sensor having a structure in which the amount of overlap to the lower side is different and the bonding depth of the LDD region on the source side and the bonding depth of the LDD region on the drain side are different.

In a solid-state image sensor and an electronic device on one aspect of the present technology, in a pixel array unit in which pixels having a photoelectric conversion unit are arranged in a two-dimensional manner, the transistors of the pixels are the LDD region and drain on the source side. It is configured so that the amount of overlap of the gate to the lower side in the LDD region on the side is different, and the bonding depth of the LDD region on the source side and the bonding depth of the LDD region on the drain side are different.

The solid-state image sensor and the electronic device on one aspect of the present technology may be independent devices or internal blocks constituting one device.

According to one aspect of the present technology, it is possible to deal with fluctuations in characteristics depending on the direction in which current flows.

The effects described here are not necessarily limited, and may be any of the effects described in the present disclosure.

It is a figure which shows the structural example of one Embodiment of the solid-state image pickup apparatus to which this technique is applied. It is a circuit diagram which shows the structural example of the source grounded type inverting amplification pixel amplifier. It is a circuit diagram which shows the structural example of the differential type inverting amplification pixel amplifier. It is a circuit diagram which shows the structural example of the pixel amplifier which performs reading in a differential mode. It is a circuit diagram which shows the structural example of the pixel amplifier which performs reading in SF mode. It is sectional drawing which shows the example of the structure of the amplification transistor to which this technique is applied. It is a figure which shows the example of the manufacturing method of a general amplification transistor. It is a figure which shows the example of the manufacturing method of a general amplification transistor. It is a figure which shows the example of the manufacturing method of a general amplification transistor. It is a figure which shows the example of the manufacturing method of a general amplification transistor. It is a figure which shows the example of the manufacturing method of the amplification transistor which applied this technique. It is a figure which shows the example of the manufacturing method of the amplification transistor which applied this technique. It is a figure explaining the effect obtained by adopting the structure of the amplification transistor which applied this technology. It is a block diagram which shows the structural example of the electronic device which has the solid-state image sensor to which this technology is applied. It is a figure which shows the use example of the solid-state image sensor to which this technique is applied. It is a block diagram which shows an example of the schematic structure of a vehicle control system. It is explanatory drawing which shows an example of the installation position of the vehicle exterior information detection unit and the image pickup unit.

Hereinafter, embodiments of the technology (the present technology) according to the present disclosure will be described with reference to the drawings. The explanations will be given in the following order.

1. 1. Configuration of solid-state image sensor 2. Pixel amplifier configuration example (1) Source-grounded inverting amplification pixel amplifier (2) Differential type inverting amplification pixel amplifier 3. Example of structure of amplification transistor 4. Modification example 5. Configuration of electronic devices 6. Example of using a solid-state image sensor 7. Application example to mobile

<1. Configuration of solid-state image sensor>

(Configuration example of solid-state image sensor)
FIG. 1 is a diagram showing a configuration example of an embodiment of a solid-state image sensor to which the present technology is applied.

The CMOS image sensor 10 in FIG. 1 is an example of a solid-state image sensor using CMOS (Complementary Metal Oxide Semiconductor). The CMOS image sensor 10 captures incident light (image light) from a subject via an optical lens system (not shown) and converts the amount of incident light imaged on the imaging surface into an electric signal on a pixel-by-pixel basis. Is output as a pixel signal.

In FIG. 1, the CMOS image sensor 10 includes a pixel array unit 11, a vertical drive circuit 12, a column signal processing circuit 13, a horizontal drive circuit 14, an output circuit 15, a control circuit 16, and an input / output terminal 17. ..

A plurality of pixels 100 are arranged in a two-dimensional shape (matrix shape) in the pixel array unit 11. The pixel 100 includes a photodiode (PD: Photodiode) as a photoelectric conversion unit and a plurality of pixel transistors. For example, a pixel transistor is composed of a transfer transistor (Trg-Tr), a reset transistor (Rst-Tr), an amplification transistor (AMP-Tr), and a selection transistor (Sel-Tr).

As the pixels arranged in the pixel array unit 11, in addition to the pixel 100, the pixel 200 or the pixel 300 may be arranged, and the detailed contents thereof will be described later.

The vertical drive circuit 12 is composed of, for example, a shift register, selects a predetermined pixel drive line 21, supplies a pulse for driving the pixel 100 to the selected pixel drive line 21, and displays the pixel 100 in line units. Drive. That is, the vertical drive circuit 12 selectively scans each pixel 100 of the pixel array unit 11 in a row-by-row manner in the vertical direction, and is based on the signal charge (charge) generated in the photodiode of each pixel 100 according to the amount of light received. The pixel signal is supplied to the column signal processing circuit 13 through the vertical signal line 22.

The column signal processing circuit 13 is arranged for each column of the pixel 100, and performs signal processing such as noise removal for each pixel string of the signal output from the pixel 100 for one row. For example, the column signal processing circuit 13 performs signal processing such as correlated double sampling (CDS: Correlated Double Sampling) and AD (Analog Digital) conversion for removing fixed pattern noise peculiar to pixels.

The horizontal drive circuit 14 is composed of, for example, a shift register, and by sequentially outputting horizontal scanning pulses, each of the column signal processing circuits 13 is sequentially selected, and pixel signals are output from each of the column signal processing circuits 13 as horizontal signal lines. Output to 23.

The output circuit 15 performs signal processing on the signals sequentially supplied from each of the column signal processing circuits 13 through the horizontal signal line 23 and outputs the signals. The output circuit 15 may, for example, perform only buffering, or may perform black level adjustment, column variation correction, various digital signal processing, and the like.

The control circuit 16 controls the operation of each part of the CMOS image sensor 10.

Further, the control circuit 16 controls the clock signal and the control as a reference for the operation of the vertical drive circuit 12, the column signal processing circuit 13, the horizontal drive circuit 14, etc., based on the vertical synchronization signal, the horizontal synchronization signal, and the master clock signal. Generate a signal. The control circuit 16 outputs the generated clock signal and control signal to the vertical drive circuit 12, the column signal processing circuit 13, the horizontal drive circuit 14, and the like.

The input / output terminal 17 exchanges signals with the outside.

The CMOS image sensor 10 of FIG. 1 configured as described above is a CMOS image sensor called a column AD method in which a column signal processing circuit 13 that performs CDS processing and AD conversion processing is arranged for each pixel string. Further, the CMOS image sensor 10 of FIG. 1 can be, for example, a back-illuminated CMOS image sensor.

<2. Pixel amplifier configuration example>

(1) Source-grounded inverting amplification pixel amplifier

FIG. 2 is a diagram showing a configuration example of a source-grounded inverting amplification pixel amplifier.

In FIG. 2, the source grounded pixel readout circuit 50 having the function of a source grounded type inverting amplifier pixel amplifier has a read pixel 100 that reads out a signal charge, a load MOS circuit 51 that supplies a constant current to the pixels, and a voltage. It is composed of a constant voltage source 52 that is always constant. The load MOS circuit 51 is composed of a MOSFET transistor such as a MOSFET transistor 511 and a MOSFET transistor 512.

The read pixel 100 has four pixel transistors of, for example, a transfer transistor 112, a reset transistor 113, an amplification transistor 114, and a selection transistor 115, in addition to a photoelectric conversion unit 111 such as a photodiode (PD). ..

The anode electrode at one end of the photoelectric conversion unit 111 is grounded, and the cathode electrode at the other end is connected to the source of the transfer transistor 112. The drain of the transfer transistor 112 is connected to the source of the reset transistor 113 and the gate of the amplification transistor 114, respectively, and these connection points form a floating diffusion (FD) 121 as a floating diffusion region.

The drain of the reset transistor 113 is connected to the vertical reset input line 61. The source of the amplification transistor 114 is connected to the constant voltage source 52. The drain of the amplification transistor 114 is connected to the source of the selection transistor 115, and the drain of the selection transistor 115 is connected to the vertical signal line 22.

The gate of the transfer transistor 112, the gate of the reset transistor 113, and the gate of the selection transistor 115 are connected to the vertical drive circuit 12 (FIG. 1) via the pixel drive line 21 (FIG. 1), and a pulse as a drive signal is connected. Are supplied respectively.

Here, the vertical signal line 22 is connected to the vertical reset input line 61, the drain of the MOSFET transistor 511 of the load MOS circuit 51, and the output terminal 53 of the source grounded pixel readout circuit 50. Further, the vertical reset input line 61 is connected to the vertical signal line 22.

In the source ground pixel readout circuit 50 having the above configuration, the amplification transistor 114 and the MIMO transistor 511 form a source ground inverting amplifier, so that the voltage corresponding to the signal charge detected by the photoelectric conversion unit 111 is obtained. The signal is output via the output terminal 53.

(2) Differential type inverting amplification pixel amplifier

FIG. 3 is a diagram showing a configuration example of a source-grounded differential type inverting amplification pixel amplifier.

In FIG. 3, the differential pixel readout circuit 70 having the function of a source-grounded differential inverting amplification pixel amplifier includes a read pixel 200 that reads out a signal charge and a reference pixel 300 that gives a reference voltage without a signal charge. , A current mirror circuit 71 composed of a MIMO transistor, and a load MOS circuit 72 that supplies a constant current to the pixels.

The read pixel 200 has four pixel transistors, for example, a transfer transistor 212, a reset transistor 213, an amplification transistor 214, and a selection transistor 215, in addition to a photoelectric conversion unit 211 such as a photodiode (PD).

The anode electrode at one end of the photoelectric conversion unit 211 is grounded, and the cathode electrode at the other end is connected to the source of the transfer transistor 212. The drain of the transfer transistor 212 is connected to the source of the reset transistor 213 and the gate of the amplification transistor 214, respectively, and these connection points form a floating diffusion 221 as a floating diffusion region.

The drain of the reset transistor 213 is connected to the read-side vertical reset input line 61S. The source of the amplification transistor 214 is connected to the read-side vertical current supply line 62S. The drain of the amplification transistor 214 is connected to the source of the selection transistor 215, and the drain of the selection transistor 215 is connected to the read-side vertical signal line 22S.

The gate of the transfer transistor 212, the gate of the reset transistor 213, and the gate of the selection transistor 215 are connected to the vertical drive circuit 12 (FIG. 1) via the pixel drive line 21 (FIG. 1), and a pulse as a drive signal is connected. Are supplied respectively.

Here, the read-side vertical signal line 22S is connected to the read-side vertical reset input line 61S, the drain of the read-side MIMO transistor 711S of the current mirror circuit 71, and the output terminal 73 of the differential pixel read circuit 70.

Further, the read-side vertical reset input line 61S is connected to the read-side vertical signal line 22S, is connected to the floating diffusion 221 of the selected read pixel 200, that is, to the input terminal of the amplification transistor 214, and the reset transistor 213 is turned on. At this time, the output signal of the differential pixel readout circuit 70 is negatively fed back.

The reference pixel 300 has four pixel transistors such as a transfer transistor 312, a reset transistor 313, an amplification transistor 314, and a selection transistor 315, in addition to a photoelectric conversion unit 311 such as a photodiode (PD).

The anode electrode at one end of the photoelectric conversion unit 311 is grounded, and the cathode electrode at the other end is connected to the source of the transfer transistor 312. The drain of the transfer transistor 312 is connected to the source of the reset transistor 313 and the gate of the amplification transistor 314, respectively, and these connection points form a floating diffusion 321 as a floating diffusion region.

The drain of the reset transistor 313 is connected to the reference side vertical reset input line 61R. The source of the amplification transistor 314 is connected to the reference side vertical current supply line 62R. The drain of the amplification transistor 314 is connected to the source of the selection transistor 315, and the drain of the selection transistor 315 is connected to the reference side vertical signal line 22R.

The gate of the transfer transistor 312, the gate of the reset transistor 313, and the gate of the selection transistor 315 are connected to the vertical drive circuit 12 (FIG. 1) via the pixel drive line 21 (FIG. 1), and a pulse as a drive signal is connected. Are supplied respectively.

Here, the reference-side vertical signal line 22R is connected to the drain and gate of the reference-side PMOS transistor 711R of the current mirror circuit 71 and the gate of the reading-side PMOS transistor 711S.

Further, the reference side vertical reset input line 61R is connected to a predetermined power supply Vrst, and at the time of reset, it is desired to be connected to the floating diffusion 321 of the reference pixel 300 selected through this wiring, that is, the input terminal of the amplification transistor 314. An input voltage signal is applied.

The reference pixel 300 is a pixel in which the potential fluctuation of the terminal (FD terminal) of the floating diffusion 321 at the time of reset is equivalent to the potential fluctuation of the terminal (FD terminal) of the floating diffusion 221 of the read pixel 200. Is desirable. For example, as the reference pixel 300, an inactive effective pixel that has been read out and is arranged in the vicinity of the read pixel 200 in the pixel array unit 11 (FIG. 1) can be used. In that case, the reference pixel 300 can be used. The roles of the read pixel 200 and the reference pixel 300 in FIG. 3 are switched by a switch provided in the column signal processing circuit 13 (FIG. 1).

The read-side vertical current supply line 62S and the reference-side vertical current supply line 62R _{are connected to each other at a connection point (V common} ) and then connected to a load MOS circuit 72 which is a constant current source.

In the differential pixel reading circuit 70 having the above configuration, the amplification transistor 214 of the reading pixel 200 and the amplification transistor 314 of the reference pixel 300 form a differential amplifier to convert the reading pixel 200 into photoelectric light. A voltage signal corresponding to the signal charge detected by the unit 211 is output via the output terminal 73.

(Configuration that can switch between differential mode and SF mode)
By the way, in order to obtain high conversion efficiency in the differential type reading, for example, it is desirable that the reading is performed by the source follower type reading having a large dynamic range at bright times. That is, more appropriate reading may be performed by appropriately switching between the differential type reading (hereinafter referred to as differential mode) and the source follower type reading (hereinafter referred to as SF mode).

Therefore, next, with reference to FIGS. 4 and 5, a configuration capable of switching between reading in the differential mode and reading in the SF mode will be described.

(Differential mode)
FIG. 4 is a circuit diagram showing a configuration example of a pixel amplifier that reads out in a differential mode.

In FIG. 4, the read pixel 200 is configured in the same manner as the read pixel 200 of FIG. 3, and the read side vertical signal line 22S, the read side vertical reset input line 61S, and the read side vertical current supply line 62S are also shown in FIG. It is connected in the same manner as the connection form shown.

Further, in FIG. 4, the reference pixel 300 is configured in the same manner as the reference pixel 300 of FIG. 3, and the reference side vertical signal line 22R, the reference side vertical reset input line 61R, and the reference side vertical current supply line 62R are also shown in FIG. It is connected in the same manner as the connection form shown in 3. The reference pixel 300 is an equivalent effective pixel close to the read pixel 200, and is a pixel for determining a differential reference voltage.

Here, in FIG. 4, a pixel peripheral portion 400 is provided for the read pixel 200 and the reference pixel 300. Switches SW1 to SW9 are provided in the pixel peripheral portion 400, and the switches SW1 to SW9 perform a switching operation to switch between reading in the differential mode and reading in the SF mode.

Specifically, when reading in the differential mode, the switch SW1 performs a switching operation on the read pixel 200, so that the read-side vertical current supply line 62S connected to the source of the amplification transistor 214 is connected. , Connected to the load MOS circuit 72. Further, the switch SW8 performs a switching operation on the read pixel 200, so that the read side vertical reset input line 61S is connected to the read side vertical signal line 22S.

Further, when reading in the differential mode, the switch SW4 performs a switching operation with respect to the reference pixel 300, so that the reference side vertical current supply line 62R connected to the source of the amplification transistor 314 is loaded with MOS. It is connected to the circuit 72. Further, the switch SW9 performs a switching operation with respect to the reference pixel 300, so that the reference side vertical reset input line 61R is connected to the reference side vertical signal line 22R.

The pixel peripheral portion 400 has a current mirror circuit 71 including a readout-side PMOS transistor 711S and a reference-side PMOS transistor 711R.

When the switch SW2 and the switch SW3 perform a switching operation in the pixel peripheral portion 400, the read-side vertical signal line 22S is connected to the drain of the read-side PMOS transistor 711S of the current mirror circuit 71. On the other hand, in the pixel peripheral portion 400, the switch SW5 and the switch SW6 perform a switching operation, so that the reference side vertical signal line 22R is the drain and gate of the reference side PMOS transistor 711R of the current mirror circuit 71, and the read side PMOS transistor. It is connected to the gate of 711S. When reading in the differential mode, the switch SW7 is turned on.

In this way, the switches SW1 to SW9 of the pixel peripheral portion 400 perform the switching operation, so that the amplification transistor 214 of the read pixel 200 and the amplification transistor 314 of the reference pixel 300 form a differential amplifier to make a differential. Read in mode is performed. As a result, the voltage signal corresponding to the signal charge detected by the photoelectric conversion unit 211 of the read pixel 200 is transmitted to the column signal processing circuit 13 (FIG. 1) via the read-side vertical signal line 22S (and the output terminal 73). It is output to the AD converter (ADC).

Further, since the read pixel 200 and the reference pixel 300 can be exchanged by switching the switches SW1 to SW9 of the pixel peripheral portion 400, all the pixels arranged in the pixel array portion 11 can be replaced without increasing the extra pixels. It can be read.

In the configuration of the pixel amplifier for reading in the differential mode shown in FIG. 4, the case where the read pixels 200 and the reference pixels 300 are horizontally arranged in the same row in the pixel array unit 11 is illustrated. For example, the arrangement relationship between the reading pixel 200 and the reference pixel 300 is arbitrary, such as allowing the reading pixel 200 and the reference pixel 300 to be vertically arranged in the same row.

(SF mode)
FIG. 5 is a circuit diagram showing a configuration example of a pixel amplifier that reads in the SF mode.

In FIG. 5, the read pixel 200, the reference pixel 300, and the pixel peripheral portion 400 are configured in the same manner as shown in FIG. 4, but the switches SW1 to SW9 of the pixel peripheral portion 400 perform a switching operation. The operation mode has been switched from differential mode to SF mode.

Specifically, when reading in the SF mode, the switch SW1 performs a switching operation on the read pixel 200, so that the read-side vertical current supply line 62 connected to the source of the amplification transistor 214 powers the power supply. It is connected to the voltage Vdd and the vertical signal line 22 is connected to the load MOS circuit 72. Further, the switch SW8 performs a switching operation on the read pixel 200, so that the vertical reset input line 61 is connected to the power supply voltage Vdd.

Similarly, when reading in the SF mode, the switch SW4 performs a switching operation with respect to the read pixel 300, so that the read-side vertical current supply line 62 connected to the source of the amplification transistor 314 has a power supply voltage Vdd. And the vertical signal line 22 is connected to the load MOS circuit 72. Further, the switch SW9 performs a switching operation on the read pixel 300, so that the vertical reset input line 61 is connected to the power supply voltage Vdd.

Further, in the pixel peripheral portion 400, the switches SW2 and SW3 and the switches SW5 and SW6 perform a switching operation, so that the connection between the read side MIMO transistor 711S and the reference side MIMO transistor 711R is released, and the differential mode is performed. The current mirror circuit 71 for use is disconnected. When reading in SF mode, switch SW7 is turned off.

In this way, by switching the switches SW1 to SW9 of the pixel peripheral portion 400, the amplification transistor 214 of the read pixel 200 and the amplification transistor 314 of the read pixel 300 are separated (for each row) from the source follower. An inverting amplifier is configured to read in SF mode. As a result, the voltage signal corresponding to the signal charge detected by the photoelectric conversion unit 211 (311) of the read pixel 200 (300) is AD-converted by the column signal processing circuit 13 (FIG. 1) via the vertical signal line 22. It is output to the device (ADC).

As described above, when the switches SW1 to SW9 perform the switching operation in the pixel peripheral portion 400, the reading in the differential mode and the reading in the SF mode can be easily switched. For example, at light time, it is possible to switch to a source follower type read with a large dynamic range.

<3. Example of amplification transistor structure>

By the way, in the pixel amplifier, when a configuration capable of switching between reading in the differential mode and reading in the SF mode is adopted, the direction in which the current flows in the amplification transistor 214 (314) is determined for each of these modes. It is assumed that the configurations will be different, and in that case, various characteristics will fluctuate depending on the direction of the current. Therefore, as the structure of the amplification transistor to which the present technology is applied, the structure of the amplification transistor 214 corresponding to the fluctuation of the characteristics according to the direction in which the current flows will be described below.

(Example of structure)
FIG. 6 is a cross-sectional view showing an example of the structure of an amplification transistor to which the present technology is applied. In FIG. 6, the cross-sectional structure of the amplification transistor 214 is shown, and the Source and Drain described therein correspond to the terminal names in the current direction in the differential mode.

In the amplification transistor 214, LDD214B-S is formed on the source side, LDD214B-D is formed on the drain side, and each of LDD214B-S and LDD214B-D has a structure that overlaps with the gate. .. Further, an oxide film 214A is formed on the gate.

Here, LDD (Lightly Doped Drain) is a structure in which thinner impurities are layered and diffused in the vicinity of the drain and the source. The LDD214B-S on the source side and the LDD214B-D on the drain side are formed, for example, by injecting impurities into the n-type region.

Further, the impurities forming the LDD214B-S on the source side and the LDD214B-D on the drain side may be different impurities as well as the same impurities. The region forming the source (first region) and the region forming the drain (second region) are, for example, n-type regions and contain impurities such as phosphorus (P). be able to.

When the same impurities are used, for example, impurities such as arsenic (As) or phosphorus (P) can be used in each of the region of LDD214B-S on the source side and the region of LDD214B-D on the drain side. ..

On the other hand, when different impurities are used, for example, for the LDD214B-S on the source side, an ion species having a diffusion rate slower than that of the impurities on the drain side can be used as the impurities. Further, for example, for the LDD214B-D on the drain side, an ion species having a diffusion rate faster than that of the impurity on the source side can be used as an impurity. More specifically, a slow-diffusing impurity such as arsenic (As) is used in the region of LDD214B-S on the source side, and a fast-diffusing impurity such as phosphorus (P) is used in the region of LDD214B-D on the drain side. Impurities can be used.

Further, in the amplification transistor 214, the LDD214B-S and the LDD214B-D have a left-right asymmetric LDD structure. That is, the overlap length (ΔXd) of the LDD214B-D on the drain side to the lower side of the gate is shorter than the overlap length (ΔXs) of the LDD214B-S on the source side to the lower side of the gate, and the drain side. The LDD214B-D in the above has a structure in which the bonding depth (ΔZd) is deeper than the bonding depth (ΔZs) of the LDD214B-S on the source side.

Here, when the origin is 0 at the gate end (one-dot chain line in the vertical direction in the figure), the following equations (1) and (2) are satisfied.

ΔZd> ΔZs ・ ・ ・ (1)

0 ≤ ΔXd <ΔXs ・ ・ ・ (2)

If the bonding depths (ΔZs, ΔZd) of LDD214B-S and LDD214B-D are ΔZs'and ΔZd', respectively, and the depths of the portions overlapping with the gate are ΔZs'and ΔZd', the above equations (1) and Moreover, it can be said that the relation of the following formula (3) is satisfied as well as the relation of the formula (2).

ΔZd'> ΔZs' ・ ・ ・ (3)

As described above, in the amplification transistor 214, the amount of wraparound (overlap amount) of the LDD on the drain side to the lower side of the gate is minimized, and the junction depth of the LDD on the drain side is set to the LDD on the source side. By designing it to be deeper than the junction depth of, PRNU (Photo Response Non Uniformity) and RTN (Random Telegraph Signal) can be improved without deteriorating other characteristics.

In FIG. 6, as the cross-sectional structure of the amplification transistor 214, the source and the drain are made to correspond to the terminal names in the current direction in the differential mode, and the directions of the currents are shown in the figure. The direction is from the left side to the right side of the current, but the direction of the current in the SF mode is the opposite.

(Example of manufacturing method)
Next, a method of manufacturing the amplification transistor 214 will be described. Here, in order to clarify the difference between the process of the general method for manufacturing the amplification transistor and the process of the method of manufacturing the amplification transistor to which the present technology is applied, the general amplification is referred to with reference to FIGS. 7 to 10. After explaining the method for manufacturing the transistor, the method for manufacturing the amplification transistor to which the present technology is applied will be described with reference to FIGS. 11 and 12.

(General manufacturing method)
First, a general method for manufacturing an amplification transistor will be described with reference to FIGS. 7 to 10.

As shown in FIG. 7, in the first step, a chemical vapor deposition (CVD) or the like is performed, and an oxide film (SiO ₂ ) and polycrystalline silicon (Poly) are formed on a silicon (Si) substrate. It is formed (A in FIG. 7). Subsequently, in the second step, the oxide film and polycrystalline silicon are etched to form a gate (B in FIG. 7). Here, a part of the oxide film is left except for the part that becomes the gate oxide film, but in the third step, a part of the oxide film is peeled off by the DHF (dilute hydrofluoric acid) treatment. (C in FIG. 7).

Further, as shown in FIG. 8, in the fourth step, a thermal oxidation treatment is performed to form an oxide film on the entire surface (D in FIG. 8). Subsequently, in the fifth step, ion implantation is performed, and arsenic (As) is implanted as an impurity into each of the source side region and the drain side region (E in FIG. 8). Subsequently, in the sixth step, a SiO film is formed on the entire surface after ion implantation (F in FIG. 8).

Further, as shown in FIG. 9, in the seventh step, sidewall film growth is performed to form a nitride film (SiN) on the entire surface (G in FIG. 9). Subsequently, in the eighth step, sidewall etching (etchback) is performed, and a nitride film is left only on the side wall of the gate (H in FIG. 9). Here, a part of the oxide film is left in the region on the source side and the region on the drain side, but in the ninth step, a part of the oxide film is peeled off by the DHF treatment (FIG. 9). I).

Further, as shown in FIG. 10, in the tenth step, a SiO film is formed on the entire surface of the side wall of the gate after the nitride film is formed (J in FIG. 10). Subsequently, in the eleventh step, phosphorus (P) is injected as an impurity into the n-type region of the silicon substrate to form a source and a drain (K in FIG. 10). After that, steps such as silicidization of the gate, source, and drain, and wiring are performed to complete a general amplification transistor (L in FIG. 10).

As shown in L of FIG. 10, in a general amplification transistor, LDDs are formed on the source side and the drain side, but the overlap length (ΔXs) of the LDD on the source side and the LDD on the drain side are over. The lap length (ΔXd) is the same length. Further, the bonding depth (ΔZs) of the LDD on the source side and the bonding depth (ΔZd) on the drain side are the same depth.

That is, in the structure of a general amplification transistor, the relationship of the following equation (4) and equation (5) is satisfied.

ΔZs = ΔZd ・ ・ ・ (4)

ΔXs = ΔXd ・ ・ ・ (5)

(Manufacturing method of this technology)
Next, a method of manufacturing an amplification transistor to which the present technology is applied will be described with reference to FIGS. 11 and 12. However, in the process of the amplification transistor manufacturing method (manufacturing method of this technology) to which this technology is applied, the same steps as the above-mentioned general amplification transistor manufacturing method (general manufacturing method) step will be described. It shall be omitted as appropriate.

In the manufacturing method of the present technology, the first step to the fourth step is performed in the same manner as the general manufacturing method described above, and the oxide film (SiO ₂ ) and polycrystalline silicon formed on the silicon (Si) substrate are performed. (Poly) is etched to form a gate (A in FIG. 7 to D in FIG. 8).

After that, in the production method of the present technology, the fifth step to the seventh step is performed, and these steps are different from the fifth step to the sixth step of the general manufacturing method described above, in particular, ion implantation. The difference is that the implantation process is performed as a separate process on the source side and the drain side.

That is, as shown in FIG. 11, in the fifth step of the manufacturing method of the present technology, when the source side ion implantation is performed, the drain side region formed on the silicon substrate and a part region of the gate are covered. By allowing the photoresist 901 to act as a protective material (mask), arsenic (As) is implanted into the region on the source side (E'in FIG. 11).

Subsequently, in the sixth step, a SiO film is formed on the entire surface of the source side after ion implantation (F'in FIG. 11). The SiO film has a function of offsetting as a spacer so that impurities (arsenic (As)) of LDD do not wrap around under the gate (polycrystalline silicon (Poly)) when ion implantation is performed on the drain side. have.

Then, in the seventh step, when the ion implantation on the drain side is performed, the photoresist 901 covered with the region on the source side formed on the silicon substrate and a part of the region of the gate serves as a protective material (mask). Arsenic (As) is implanted into the drain side region (E'' in FIG. 11). Here, the SiO film (SiO film on the side wall on the drain side of the gate) formed in the sixth step serves as a spacer, so that the arsenic (As), which is an impurity of the LDD on the drain side, becomes the gate (polycrystalline silicon (polycrystalline silicon). I try not to go around to the underside of Poly)).

That is, here, by providing a spacer corresponding to the diffusion length of arsenic (As), when arsenic diffuses during ion implantation on the drain side, the diffused arsenic does not wrap around to the lower side of polycrystalline silicon (Poly). Can be done (so to speak, it can be stopped). For example, if the diffusion length of arsenic is several tens of nm, the width of the spacer may be set to match the width (the same width as the diffusion length of arsenic). Here, when other impurities such as phosphorus (P) are used, a spacer may be provided according to the diffusion length of the impurities. Further, here, it is not limited to the size stop, and it is sufficient that the relationship of the above-mentioned equation (2) is satisfied.

As described above, in the manufacturing method of the present technology, spacers are provided according to the diffusion length of impurities in anticipation of the diffusion of impurities during ion implantation. That is, in the case of the above-mentioned general manufacturing method, since arsenic (As) is injected at the gate (polycrystalline silicon (Poly)) (E in FIG. 8), the diffused arsenic is polycrystalline silicon. It wraps around to the underside of (Poly), but in the manufacturing method of this technology, by providing a spacer that matches the diffusion length of arsenic (As), the diffused arsenic is dimensioned when it is polycrystalline silicon (Poly). I try to stop it so that it doesn't wrap around underneath.

However, here, from the viewpoint of random noise (RN: Random Noise), it is essential that the N concentration of the surface under the sidewall (SW: Side Wall) is equal to or higher than the above-mentioned general manufacturing method. Will be done. In other words, in the manufacturing method of this technology, by providing a spacer (SiO film) that matches the diffusion length of arsenic (As), the through film increases by that amount, so when the SiO film is formed (through the SiO film). ), In order to satisfy this condition when forming the LDD on the drain side, it is necessary to have high energy and a high dose amount.

As a result, the diffusion length of the drain side region is different from that of the source side region, and the bonding depth of the LDD on the drain side is deeper than the bonding depth of the LDD on the source side. In other words, it can be said that the bonding depth of the LDD on the drain side inevitably increases after such a process.

In the manufacturing method of the present technology, as the eighth step to the twelfth step, the same steps as the seventh step to the eleventh step in the above-mentioned general manufacturing method are performed, and a nitride film is formed on the side wall of the gate. After this (G in FIG. 9 to I in FIG. 9), phosphorus (P) is injected as an impurity into the n-type region of the silicon substrate to form a source and a drain (J to J in FIG. 10). K in FIG. 10). After that, steps such as silicidization of the gate, source, and drain, and wiring are performed to complete an amplification transistor to which the present technology is applied (L'in FIG. 12).

As shown in L'in FIG. 12, in the amplification transistor to which this technique is applied, LDDs are formed on the source side and the drain side, but the overlap length (ΔXd) of the LDDs on the drain side is on the source side. It is shorter than the overlap length (ΔXs) of the LDD. Further, the bonding depth (ΔZd) of the LDD on the drain side is deeper than the bonding depth (ΔZs) of the LDD on the source side.

That is, in the amplification transistor to which this technique is applied, the relationship of the above-mentioned equation (1) and equation (2) is satisfied. Here, as described above, if the junction depth (ΔZs, ΔZd) between the source side and the drain side is defined as ΔZs', ΔZd', where the portion overlapping with the gate is defined as ΔZs', ΔZd', the above-mentioned equation (3) ) Is also satisfied.

(Effect of this technology)
By adopting the structure of the amplification transistor to which this technology is applied, the following four effects can be obtained in particular.

(A) Improvement of PRNU in differential mode (B) Improvement of conversion efficiency in differential mode (C) Improvement of RTS (D) Reduction of drain resistance

Here, the details of the four effects (A) to (D) will be described with reference to the structure of the amplification transistor 214 shown in FIG. However, in FIG. 13, the overlap capacitance of the gate on the drain side in the differential mode is represented by _{C gd.} Further, in FIG. 13, the flow of electrons (e-) under the gate is represented by a solid line or a dotted line arrow in the figure.

(A) Improvement of PRNU in differential mode As the first effect, by adopting the structure of amplification transistor 214, the overlap capacitance C _gd of the gate on the drain side in differential mode is reduced, and PRNU (Photo) Response Non Uniformity) can be improved.

Here, driving in the differential mode can obtain higher conversion efficiency than driving in the SF mode. The conversion efficiency in the differential mode can be expressed by the following equation (6).

In equation (6), C _{fd_total} represents the FD (Floating Diffusion) capacitance, Av represents the open loop gain, C _gd represents the overlap capacitance of the gate on the drain side, and C _{fd_vsl} represents the FD node and the vertical signal. Represents the wiring capacitance between wires (VSL).

Further, in a differential pixel amplifier having high conversion efficiency, it is easily affected by the variation in conversion efficiency, and the variation in signal output due to the variation in conversion efficiency increases. Here, the variation in the output signal of the vertical signal line (VSL) provided in the column direction of each pixel arranged two-dimensionally in the pixel array unit 11 is generally expressed by an amount called PRNU.

In this way, in the differential mode, the signal charge can be read out with high conversion efficiency, but _{by suppressing the variation in the overlap capacitance C gd} , the variation in conversion efficiency, that is, the sensitivity non-uniformity (PRNU) can be reduced. Can be lowered. On the other hand, _{in order to suppress the variation in the overlap capacity C gd} , it is most effective to shorten the overlap length (ΔXd) of the LDD214BD on the drain side. Further, the overlap capacitance C _gd is dominated by the overlap capacitance component of the gate due to the LDD, and _{in order to suppress the variation of the overlap capacitance C gd} , the overlap amount of the gate of the LDD214BD on the drain side is reduced. Is the most effective.

In the amplification transistor 214, as expressed by the above equation (2), the overlap length (ΔXd) of the LDD214BD on the drain side is shortened (the overlap amount of the gate on the drain side is reduced) to reduce the overlap capacitance. Since C _gd (variation) can be reduced ( _{the absolute value of C gd} is lowered), PRNU can be improved as a result.

(B) Improvement of conversion efficiency in differential mode As a second effect, by adopting the structure of the amplification transistor 214, the overlap length of the LDD214BD on the drain side is as shown by the above equation (2). Since (ΔXd) can be shortened, the overlap capacitance C _{gd in} the differential mode can be reduced and the conversion efficiency can be increased. That is, the conversion efficiency in the differential mode can be expressed by the above equation (6), but if the overlap capacitance C _gd of the gate on the drain side can be reduced (the absolute value of _{C gd is lowered),} It is clear that the conversion efficiency will increase.

Further, in the manufacturing method of the present technology, by providing a spacer according to the diffusion length of impurities, the diffused impurities are prevented from wrapping around to the lower side of the gate (Poly). By having it, it is possible to realize conversion efficiency as close as possible when LDD is not formed.

(C) Improvement of RTS As a third effect, by adopting the structure of the amplification transistor 214, the amount of LDD diffusion in the drain region is deep, so that electrons can flow deeper than the gate interface. Therefore, the electrons flow through the entire deepened region, and the electrons can be kept away from the trap at the interface under the sidewall (SW), so that the optimum structure that can improve the RTS (Random Telegraph Signal) can be improved. It has become.

That is, it is known that the cause of RTS noise is the random capture and emission of electrons by the interface state of MOS, but the LDD214BD on the drain side has the relationship of the above equation (1). In FIG. 13, as indicated by the dotted arrow, the electron (e-) flows deeper than the gate interface, so that the RTS can be improved.

(D) Reduction of drain resistance As a fourth effect, by adopting the structure of the amplification transistor 214, the junction depth (ΔZd) of the LDD214BD on the drain side in the differential mode is deep, so that the drain resistance is lowered. can do. That is, since the LDD214B-D on the drain side has the relationship of the above equation (1), the bonding depth (ΔZd) of the LDD214B-D is deep, and electrons flow (overall) in that region. And the drain resistance becomes low.

Here, in the amplification transistor 214, the junction depth (ΔZd) of the LDD214B-D becomes deeper because such a structure is inevitably obtained through the process of the manufacturing method of the present technology described above. By increasing the bonding depth (ΔZd) of −D, the effects of (C) improvement of RTS and (D) reduction of drain resistance can be obtained incidentally.

As shown in the relationship of the above equation (2), the overlap length (ΔXs) of the LDD214B-S on the source side is longer than the overlap length (ΔXd) of the LDD214B-D on the drain side. This is because the trap sensitivity is higher on the source side, and it is advantageous to increase the overlap amount of the LDD214B-S on the source side from the viewpoint of random noise (RN).

Further, assuming only when driving in the differential mode, a structure that does not form the LDD214BD on the drain side can be adopted, but the same amplification transistor 214 is used in the differential mode and the SF mode, and the same amplification transistor 214 is used. , When the source and drain are interchanged in the differential mode and the SF mode, such a structure is not the optimum structure.

That is, when a structure that does not form the LDD214BD on the drain side is adopted in the differential mode, the side that does not form the LDD is the source side in the SF mode, so that the random noise (RN) in the SF mode deteriorates. There is a problem of doing. In addition, hot carriers (HC) deteriorate even in the differential mode. Therefore, in order to make the differential mode and the SF mode compatible with each other in the amplification transistor 214, the structure shown in FIG. 13, that is, the structure satisfying the relations of the above equations (1) to (3) is required. It is considered suitable.

Further, as shown in FIG. 13, in the amplification transistor 214, it is preferable to use arsenic (As), which is difficult to diffuse, as an impurity forming the LDD214B-S on the source side and the LDD214B-D on the drain side. Other impurities such as phosphorus (P) may be used. Further, if the above-mentioned relations of the formulas (1) to (3) are satisfied, the impurities forming the LDD214B-S on the source side and the impurities forming the LDD214B-D on the drain side may be different from each other. good.

Note that the techniques disclosed in Patent Documents 1 and 2 described above do not assume a case where the current flows in both directions in the pixel transistor, so that the following problems may occur, for example. be. That is, first, when the side from which the LDD is removed is used as the drain, the electric field strength becomes stronger with respect to the region where the LDD is located, so that hot carrier (HC) deterioration may occur. Secondly, if the trap site generated by the above-mentioned hot carrier (HC) is used as a source in the presence of the trap site, the 1 / f noise characteristic may be deteriorated.

On the other hand, in the amplification transistor to which this technology is applied, for example, by using the amplification transistor in different directions of current flow between the differential mode and the SF mode (the direction of current flow is bidirectional), for example, In a circuit system that realizes multiple functions, the overlap length of the LDD on the drain side under the gate is smaller than that on the source side and on the drain side, assuming the direction of the current according to the differential mode. By having a structure in which the junction depth of the LDD is deeper than that on the source side, for example, the above-mentioned four effects (A) to (D) can be obtained, and the direction of current flow for each mode of the differential mode or the SF mode. It is possible to deal with fluctuations in characteristics according to the above.

<4. Modification example>

(Back-illuminated structure)
As described above, the CMOS image sensor 10 of FIG. 1 can be, for example, a back-illuminated CMOS image sensor. By adopting the back-illuminated type, it is possible to further improve the degree of freedom in the layout of the pixels.

Further, in the above description, the structure of the amplification transistor has been described as an example as the structure to which the present technology is applied, but the present technology can be applied not only to the amplification transistor but also to the structure of other pixel transistors. Further, the present technology can be applied not only to a solid-state image sensor (transistor structure) such as a CMOS image sensor, but also to a semiconductor device in general (transistor structure).

<5. Electronic device configuration>

FIG. 14 is a block diagram showing a configuration example of an electronic device having a solid-state image sensor to which the present technology is applied.

The electronic device 1000 is, for example, an electronic device such as an imaging device such as a digital still camera or a video camera, or a mobile terminal device such as a smartphone or a tablet terminal.

The electronic device 1000 includes a solid-state imaging device 1001, a DSP circuit 1002, a frame memory 1003, a display unit 1004, a recording unit 1005, an operation unit 1006, and a power supply unit 1007. Further, in the electronic device 1000, the DSP circuit 1002, the frame memory 1003, the display unit 1004, the recording unit 1005, the operation unit 1006, and the power supply unit 1007 are connected to each other via the bus line 1008.

The solid-state image sensor 1001 corresponds to the CMOS image sensor 10 (FIG. 1) described above, and is used for a plurality of pixels 100 (200, 300) two-dimensionally arranged in the pixel array unit 11 (FIG. 1). , Source grounded type or differential type is used for reading. Further, in the amplification transistor 214 (314) of each pixel 200 (300), the LDD214B-S and the LDD214B-D have a structure that satisfies the relationships of the above equations (1), (2), and (3). have.

The DSP circuit 1002 is a camera signal processing circuit that processes a signal supplied from the solid-state image sensor 1001. The DSP circuit 1002 outputs image data obtained by processing a signal from the solid-state image sensor 1001. The frame memory 1003 temporarily holds the image data processed by the DSP circuit 1002 in frame units.

The display unit 1004 comprises a panel-type display device such as a liquid crystal panel or an organic EL (Electro Luminescence) panel, and displays a moving image or a still image captured by the solid-state image sensor 1001. The recording unit 1005 records image data of a moving image or a still image captured by the solid-state imaging device 1001 on a recording medium such as a semiconductor memory or a hard disk.

The operation unit 1006 outputs operation commands for various functions of the electronic device 1000 according to the operation by the user. The power supply unit 1007 appropriately supplies various power sources for operating the DSP circuit 1002, the frame memory 1003, the display unit 1004, the recording unit 1005, and the operation unit 1006 to these supply targets.

The electronic device 1000 is configured as described above. As described above, this technique is applied to the solid-state image sensor 1001. Specifically, the CMOS image sensor 10 (FIG. 1) can be applied to the solid-state image sensor 1001. By applying this technology to the solid-state image sensor 1001, in the amplification transistor 214 (314) of each pixel 200 (300), the LDD214B-S and LDD214B-D are of the above-mentioned equations (1) to (3). Since the relationship is satisfied, it is possible to deal with fluctuations in characteristics depending on the direction in which the current flows when the differential mode and the SF mode can be switched.

<6. Example of using a solid-state image sensor>

FIG. 15 is a diagram showing a usage example of a solid-state image sensor to which the present technology is applied.

The CMOS image sensor 10 (FIG. 1) can be used in various cases for sensing light such as visible light, infrared light, ultraviolet light, and X-ray, as shown below. That is, as shown in FIG. 15, not only the field of appreciation for taking an image used for appreciation, but also, for example, the field of transportation, the field of home appliances, the field of medical / healthcare, the field of security, and the field of beauty. The CMOS image sensor 10 can also be used in an apparatus used in a field, a field of sports, a field of agriculture, or the like.

Specifically, in the field of appreciation, for example, a device for taking an image to be used for appreciation, such as a digital camera, a smartphone, or a mobile phone having a camera function (for example, the electronic device 1000 in FIG. 14). Therefore, the CMOS image sensor 10 can be used.

In the field of traffic, for example, for safe driving such as automatic stop and recognition of the driver's condition, in-vehicle sensors that photograph the front, rear, surroundings, inside of the vehicle, etc., and the traveling vehicle and the road are monitored. The CMOS image sensor 10 can be used in a device used for traffic such as a surveillance camera and a distance measuring sensor that measures a distance between vehicles.

In the field of home appliances, for example, a device used for home appliances such as a television receiver, a refrigerator, and an air conditioner in order to photograph a user's gesture and operate the device according to the gesture. Can be used. Further, in the field of medical care / healthcare, the CMOS image sensor 10 is used in a device used for medical care / healthcare such as an endoscope and a device for performing angiography by receiving infrared light. can do.

In the field of security, the CMOS image sensor 10 can be used in a device used for security such as a surveillance camera for crime prevention and a camera for person authentication. Further, in the field of cosmetology, the CMOS image sensor 10 can be used in a device used for cosmetology, such as a skin measuring device for photographing the skin and a microscope for photographing the scalp.

In the field of sports, the CMOS image sensor 10 can be used in a device used for sports, such as an action camera or a wearable camera for sports applications. Further, in the field of agriculture, the CMOS image sensor 10 can be used in a device used for agriculture such as a camera for monitoring the state of a field or a crop.

<7. Application example to mobile>

The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure is realized as a device mounted on a moving body of any kind such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility, an airplane, a drone, a ship, and a robot. You may.

FIG. 16 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile control system to which the technique according to the present disclosure can be applied.

The vehicle control system 12000 includes a plurality of electronic control units connected via the communication network 12001. In the example shown in FIG. 16, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside information detection unit 12030, an in-vehicle information detection unit 12040, and an integrated control unit 12050. Further, as a functional configuration of the integrated control unit 12050, a microcomputer 12051, an audio image output unit 12052, and an in-vehicle network I / F (Interface) 12053 are shown.

The drive system control unit 12010 controls the operation of the device related to the drive system of the vehicle according to various programs. For example, the drive system control unit 12010 provides a driving force generator for generating the driving force of the vehicle such as an internal combustion engine or a driving motor, a driving force transmission mechanism for transmitting the driving force to the wheels, and a steering angle of the vehicle. It functions as a control device such as a steering mechanism for adjusting and a braking device for generating braking force of the vehicle.

The body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a keyless entry system, a smart key system, a power window device, or a control device for various lamps such as headlamps, back lamps, brake lamps, blinkers or fog lamps. In this case, the body system control unit 12020 may be input with radio waves transmitted from a portable device that substitutes for the key or signals of various switches. The body system control unit 12020 receives inputs of these radio waves or signals and controls a vehicle door lock device, a power window device, a lamp, and the like.

The vehicle exterior information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, the image pickup unit 12031 is connected to the vehicle exterior information detection unit 12030. The vehicle outside information detection unit 12030 causes the image pickup unit 12031 to capture an image of the outside of the vehicle and receives the captured image. The vehicle exterior information detection unit 12030 may perform object detection processing or distance detection processing such as a person, a vehicle, an obstacle, a sign, or a character on the road surface based on the received image.

The imaging unit 12031 is an optical sensor that receives light and outputs an electric signal according to the amount of the light received. The image pickup unit 12031 can output an electric signal as an image or can output it as distance measurement information. Further, the light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

The in-vehicle information detection unit 12040 detects information in the vehicle. For example, a driver state detection unit 12041 that detects the driver's state is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that images the driver, and the in-vehicle information detection unit 12040 determines the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041. It may be calculated, or it may be determined whether or not the driver has fallen asleep.

The microcomputer 12051 calculates the control target value of the driving force generator, the steering mechanism, or the braking device based on the information inside and outside the vehicle acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, and the drive system control unit. A control command can be output to 12010. For example, the microcomputer 12051 realizes ADAS (Advanced Driver Assistance System) functions including vehicle collision avoidance or impact mitigation, follow-up driving based on inter-vehicle distance, vehicle speed maintenance driving, vehicle collision warning, vehicle lane deviation warning, and the like. It is possible to perform cooperative control for the purpose of.

Further, the microcomputer 12051 controls the driving force generator, the steering mechanism, the braking device, and the like based on the information around the vehicle acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040. It is possible to perform coordinated control for the purpose of automatic driving, etc., which runs autonomously without depending on the operation.

Further, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the vehicle exterior information detection unit 12030. For example, the microcomputer 12051 controls the headlamps according to the position of the preceding vehicle or the oncoming vehicle detected by the external information detection unit 12030, and performs coordinated control for the purpose of anti-glare such as switching the high beam to the low beam. It can be carried out.

The audio-image output unit 12052 transmits an output signal of at least one of audio and an image to an output device capable of visually or audibly notifying the passenger of the vehicle or the outside of the vehicle. In the example of FIG. 16, an audio speaker 12061, a display unit 12062, and an instrument panel 12063 are exemplified as output devices. The display unit 12062 may include, for example, at least one of an onboard display and a heads-up display.

FIG. 17 is a diagram showing an example of the installation position of the imaging unit 12031.

In FIG. 17, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

The imaging units 12101, 12102, 12103, 12104, and 12105 are provided at positions such as, for example, the front nose, side mirrors, rear bumpers, back doors, and the upper part of the windshield in the vehicle interior of the vehicle 12100. The imaging unit 12101 provided on the front nose and the imaging unit 12105 provided on the upper part of the windshield in the vehicle interior mainly acquire an image in front of the vehicle 12100. The imaging units 12102 and 12103 provided in the side mirrors mainly acquire images of the side of the vehicle 12100. The imaging unit 12104 provided on the rear bumper or the back door mainly acquires an image of the rear of the vehicle 12100. The imaging unit 12105 provided on the upper part of the windshield in the vehicle interior is mainly used for detecting a preceding vehicle, a pedestrian, an obstacle, a traffic light, a traffic sign, a lane, or the like.

Note that FIG. 17 shows an example of the photographing range of the imaging units 12101 to 12104. The imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, the imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and the imaging range 12114 indicates the imaging range of the imaging units 12102 and 12103. The imaging range of the imaging unit 12104 provided on the rear bumper or the back door is shown. For example, by superimposing the image data captured by the imaging units 12101 to 12104, a bird's-eye view image of the vehicle 12100 as viewed from above can be obtained.

At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the image pickup units 12101 to 12104 may be a stereo camera composed of a plurality of image pickup elements, or may be an image pickup element having pixels for phase difference detection.

For example, the microcomputer 12051 uses the distance information obtained from the imaging units 12101 to 12104 to obtain the distance to each three-dimensional object within the imaging range 12111 to 12114 and the temporal change of this distance (relative velocity with respect to the vehicle 12100). By obtaining can. Further, the microcomputer 12051 can set an inter-vehicle distance to be secured in front of the preceding vehicle in advance, and can perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), and the like. In this way, it is possible to perform coordinated control for the purpose of automatic driving or the like in which the vehicle travels autonomously without depending on the operation of the driver.

For example, the microcomputer 12051 converts three-dimensional object data related to a three-dimensional object into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on the distance information obtained from the imaging units 12101 to 12104. It can be classified and extracted and used for automatic avoidance of obstacles. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that can be seen by the driver of the vehicle 12100 and obstacles that are difficult to see. Then, the microcomputer 12051 determines the collision risk indicating the risk of collision with each obstacle, and when the collision risk is equal to or higher than the set value and there is a possibility of collision, the microcomputer 12051 via the audio speaker 12061 or the display unit 12062. By outputting an alarm to the driver and performing forced deceleration and avoidance steering via the drive system control unit 12010, driving support for collision avoidance can be provided.

At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether or not a pedestrian is present in the captured image of the imaging units 12101 to 12104. Such pedestrian recognition includes, for example, a procedure for extracting feature points in an image captured by an imaging unit 12101 to 12104 as an infrared camera, and pattern matching processing for a series of feature points indicating the outline of an object to determine whether or not the pedestrian is a pedestrian. It is done by the procedure to determine. When the microcomputer 12051 determines that a pedestrian is present in the captured images of the imaging units 12101 to 12104 and recognizes the pedestrian, the audio image output unit 12052 outputs a square contour line for emphasizing the recognized pedestrian. The display unit 12062 is controlled so as to superimpose and display. Further, the audio image output unit 12052 may control the display unit 12062 so as to display an icon or the like indicating a pedestrian at a desired position.

The example of the vehicle control system to which the technique according to the present disclosure can be applied has been described above. The technique according to the present disclosure can be applied to the imaging unit 12101 among the configurations described above. Specifically, the CMOS image sensor 10 of FIG. 1 can be applied to the imaging unit 12031. By applying the technique according to the present disclosure to the imaging unit 12031, for example, when the differential mode and the SF mode can be switched, it is possible to deal with fluctuations in characteristics according to the direction in which the current flows. Since it is possible to obtain a higher quality captured image by performing imaging in a mode suitable for the above, it becomes possible to recognize obstacles such as pedestrians more accurately.

The embodiment of the present technology is not limited to the above-described embodiment, and various changes can be made without departing from the gist of the present technology.

In addition, the present technology can have the following configurations.

(1)
A pixel array unit in which pixels having a photoelectric conversion unit are arranged two-dimensionally is provided.
The transistor of the pixel has a different amount of overlap to the lower side of the gate in the LDD (Lightly Doped Drain) region on the source side and the LDD region on the drain side, and the junction depth of the LDD region on the source side and the drain side. A solid-state image sensor having a structure in which the bonding depths of the LDD regions are different.
(2)
The first region forming the source and the LDD region on the source side are n-type regions.
The solid-state image sensor according to (1) above, wherein the second region forming the drain and the LDD region on the drain side are n-type regions.
(3)
The LDD region on the drain side has a structure in which the amount of overlap to the lower side of the gate is smaller than that of the LDD region on the source side and the bonding depth is deeper than that of the LDD region on the source side (1). ) Or (2).
(4)
The LDD region on the drain side has a structure in which the depth of the overlapping portion on the lower side of the gate is deeper than the depth of the overlapping portion on the lower side of the gate in the LDD region on the source side (3). The solid-state image sensor according to.
(5)
The solid-state image sensor according to (4), wherein the LDD region on the drain side has a structure in which the depth of the overlapping portion below the gate is shallower than the depth of the portion excluding the overlapping portion.
(6)
The solid according to (4) or (5) above, wherein the LDD region on the source side has a structure in which the depth of the overlapping portion under the gate is shallower than the depth of the portion excluding the overlapping portion. Image sensor.
(7)
The solid-state image sensor according to any one of (1) to (6) above, wherein the transistor includes an amplification transistor.
(8)
The solid-state image sensor according to (7) above, wherein the amplification transistor has a direction in which a current flows differs depending on the mode.
(9)
The pixel corresponds to a differential type readout and a source follower type readout as a readout method.
The solid-state image sensor according to (8) above, wherein the mode includes a first mode corresponding to differential type readout and a second mode corresponding to source follower type readout.
(10)
The solid-state image sensor according to (9), wherein the amplification transistor has a structure premised on the direction of current according to the first mode.
(11)
The first impurity forming the LDD region on the source side and the second impurity forming the LDD region on the drain side are the same impurities according to any one of (2) to (6). Solid-state image sensor.
(12)
The solid-state image sensor according to (11), wherein the first impurity and the second impurity contain arsenic (As) or phosphorus (P).
(13)
The solid according to any one of (2) to (6) above, wherein the first impurity forming the LDD region on the source side and the second impurity forming the LDD region on the drain side are different impurities. Image sensor.
(14)
The LDD region on the source side is formed by the first impurity having a slower diffusion rate than the second impurity.
The solid-state image sensor according to (13), wherein the LDD region on the drain side is formed by the second impurity having a diffusion rate faster than that of the first impurity.
(15)
The first impurity contains arsenic (As).
The solid-state image sensor according to (14) above, wherein the second impurity contains phosphorus (P).
(16)
A pixel array unit in which pixels having a photoelectric conversion unit are arranged two-dimensionally is provided.
The transistor of the pixel has a different amount of overlap to the lower side of the gate in the LDD region on the source side and the LDD region on the drain side, and the junction depth of the LDD region on the source side and the LDD region on the drain side are joined. An electronic device equipped with a solid-state image sensor having structures with different depths.

10 CMOS image sensor, 11 pixel array section, 22 vertical signal line, 22S read side vertical signal line, 22R reference side vertical signal line, 50 source grounded pixel read circuit, 51 load MOS circuit, 52 constant voltage source, 61 vertical reset input Line, 61S Read-side vertical reset input line, 61R Reference-side vertical reset input line, 62 Vertical current supply line, 62S Read-side vertical current supply line, 62R Reference-side vertical current supply line, 70 Differential pixel readout circuit, 71 Current mirror Circuit, 72 Load MOS circuit, 100 Read pixel (pixel), 111 Photoconverter, 112 Transfer transistor, 113 Reset transistor, 114 Amplification transistor, 115 Select transistor, 121 Floating diffusion, 200 Read pixel (pixel), 211 Photoconverter , 212 Transfer Transistor, 213 Reset Transistor, 214 Amplification Transistor, 214A Oxide, 214B-S Source Side LDD, 214B-D Drain Side LDD, 215 Selective Transistor, 221 Floating Diffusion, 300 Reference Pixels, 311 Photoelectric Conversion unit, 312 transfer transistor, 313 reset transistor, 314 amplification transistor, 315 selection transistor, 321 floating diffusion, 400 pixel peripheral part, 511, 512 facsimile transistor, 711S read side MIMO transistor, 711R reference side MIMO transistor, 1000 electronic device, 1001 Solid-state imaging device, 12031 Imaging unit, SW1 to SW9 switch

Claims (16)

A pixel array unit in which pixels having a photoelectric conversion unit are arranged two-dimensionally is provided.
The transistor of the pixel has a different amount of overlap to the lower side of the gate in the LDD (Lightly Doped Drain) region on the source side and the LDD region on the drain side, and the junction depth of the LDD region on the source side and the drain side. A solid-state image sensor having a structure in which the bonding depths of the LDD regions are different. The first region forming the source and the LDD region on the source side are n-type regions.
The solid-state image sensor according to claim 1, wherein the second region forming the drain and the LDD region on the drain side are n-type regions. The LDD region on the drain side has a structure in which the amount of overlap to the lower side of the gate is smaller than that of the LDD region on the source side and the bonding depth is deeper than that of the LDD region on the source side. The solid-state image sensor according to the above. According to claim 3, the LDD region on the drain side has a structure in which the depth of the overlapping portion on the lower side of the gate is deeper than the depth of the overlapping portion on the lower side of the gate in the LDD region on the source side. The solid-state image sensor according to the description. The solid-state image sensor according to claim 4, wherein the LDD region on the drain side has a structure in which the depth of the overlapping portion on the lower side of the gate is shallower than the depth of the portion excluding the overlapping portion. The solid-state image sensor according to claim 5, wherein the LDD region on the source side has a structure in which the depth of the overlapping portion under the gate is shallower than the depth of the portion excluding the overlapping portion. The solid-state image sensor according to claim 3, wherein the transistor includes an amplification transistor. The solid-state image sensor according to claim 7, wherein the amplification transistor has a direction in which a current flows differs depending on the mode. The pixel corresponds to a differential type readout and a source follower type readout as a readout method.
The solid-state image sensor according to claim 8, wherein the mode includes a first mode corresponding to differential type readout and a second mode corresponding to source follower type readout. The solid-state image sensor according to claim 9, wherein the amplification transistor has a structure premised on the direction of current according to the first mode. The solid-state image sensor according to claim 3, wherein the first impurity forming the LDD region on the source side and the second impurity forming the LDD region on the drain side are the same impurities. The solid-state image sensor according to claim 11, wherein the first impurity and the second impurity contain arsenic (As) or phosphorus (P). The solid-state image sensor according to claim 3, wherein the first impurity forming the LDD region on the source side and the second impurity forming the LDD region on the drain side are different impurities. The LDD region on the source side is formed by the first impurity having a slower diffusion rate than the second impurity.
The solid-state image sensor according to claim 13, wherein the LDD region on the drain side is formed by the second impurity having a diffusion rate faster than that of the first impurity. The first impurity contains arsenic (As).
The solid-state image sensor according to claim 14, wherein the second impurity contains phosphorus (P). A pixel array unit in which pixels having a photoelectric conversion unit are arranged two-dimensionally is provided.
The transistor of the pixel has a different amount of overlap to the lower side of the gate in the LDD region on the source side and the LDD region on the drain side, and the junction depth of the LDD region on the source side and the LDD region on the drain side are joined. An electronic device equipped with a solid-state image sensor having structures with different depths.

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