JPWO2020014441A5 - - Google Patents

Description

Cross-reference of related applications

The present application claims the priority benefit of US Provisional Patent Application No. 62 / 697,474 filed on 13 July 2018. The disclosures of such US provisional patent applications are incorporated herein by reference in their entirety.

(Field of invention)
The present invention generally relates to the field of semiconductor wafer manufacturing. More specifically, the present invention relates to a method of manufacturing a structure of a semiconductor-on-insulator (for example, silicon-on-insulator), which has excellent radio frequencies. It relates to a semiconductor on-insulator structure having radio frequency device performance.

(Background of invention)
Semiconductor wafers are generally prepared from single crystal ingots (eg, silicon ingots), such single crystal ingots trimmed to have one or more flats or notches for proper orientation of the semiconductor wafer in subsequent processing. And polished. The ingot is then sliced into individual wafers. Although the present specification refers to semiconductor wafers obtained from silicon, semiconductor wafers can also be prepared using other materials. For example, germanium, silicon carbide, silicon germanium, gallium arsenide, alloys of Group III and Group V elements such as gallium nitride or indium phosphate, or Group II such as cadmium sulfide or zinc oxide. A semiconductor wafer can be prepared by using an alloy of an element and a Group VI element.

Semiconductor wafers (eg, silicon wafers) can be used in the preparation of composite layer structures. For example, semiconductor-on-insulators, more specifically, composite layer structures such as silicon-on-insulator (SOI) structures, are handle wafers or handle layers, device layers, and between handle layers and device layers. It generally has an insulating (ie, dielectric) film (typically an oxide layer). Generally, the device layer has a thickness of 0.01 to 20 μm, for example, 0.05 to 20 μm. The thick film device layer (or thick film-like device layer) can have a device layer thickness of about 1.5 μm to about 20 μm. The thin film device layer (or thin film-like device layer) can have a thickness of about 0.01 μm to about 0.20 μm. In general, composite layer structures such as Silicon on Insulator (SOI), Silicon on Sapphire (SOS), and Silicon on Quartz bring two wafers into close contact, thereby van der Waals forces, hydrogen. Bonding is initiated by the bond or both, and subsequent heat treatment strengthens the bond. Annealing converts the terminal silanol group into a siloxane bond between the two interfaces, thus strengthening the bond.

After thermal annealing, the bonded structure is subjected to further processing to remove a significant portion of the donor wafer to achieve layer transfer. Where wafer thinning techniques such as etching or grinding can be used, it is often bond and etch SOI (ie, BESOI: bond and etch SOI) or bond and grind SOI (ie, BGSOI: bond and). It is called grind SOI). In such BESOI or BGSOI, the silicon wafer is bonded to the handle wafer and then the etching is slowly removed until only a thin layer of silicon remains on the handle wafer. See, for example, US Pat. No. 5,189,500. US Pat. No. 5,189,500 is incorporated herein by reference in its entirety. It should be noted that such a method is time consuming and costly, wastes one of a plurality of substrates, and generally does not provide adequate thickness uniformity for layers thinner than a few microns.

Another common method of achieving layer transfer utilizes hydrogen injection followed by thermally induced layer splitting. The particles (atoms or ionized atoms, such as hydrogen atoms or a combination of hydrogen and helium atoms) are embedded at a specific depth below the front surface of the donor wafer. The injected particles form a cleavage plane in the donor wafer at the specific depth of injection. By cleaning the surface of the donor wafer, organic compounds or other contaminants (eg, boron compounds and other particulate matter) deposited on the wafer during the injection process are removed.

The front side surface of the donor wafer is then bonded to the handle wafer to form a bonded wafer (or bonded wafer) by a hydrophilic bonding process. Prior to bonding, the donor wafer and / or handle wafer is activated by exposing the wafer surface to a plasma containing, for example, oxygen or nitrogen. Exposure to plasma modifies the structure of the surface in a process often referred to as surface activation, in which such activation processes make one or both surfaces of the donor and handle wafers hydrophilic. Make it sex. The surface of such a wafer can be additionally chemically activated by a wet treatment such as SC1 clean. The wet treatment and plasma activation may be performed in any order, or the wafer may be subjected to only one of the treatments. The wafers are then integrally pressed to form a bond between the wafers. This bond is relatively weak due to van der Waals forces and needs to be strengthened prior to further processing.

In some processes, the hydrophilic bond (or hydrophilic bond) between the donor wafer and the handle wafer (ie, the bonded wafer or the bonded wafer) is strengthened by heating or annealing a pair of bonded wafers. Be made. In some processes, wafer bonding can occur at low temperatures, such as approximately 300 ° C to 500 ° C. At lower bond temperatures, the adsorbed water vapor bridging layers on the surface decrease and the density of hydrogen bonds between silanol groups on each wafer surface increases. In some processes, wafer bonding can occur at high temperatures, such as approximately 800 ° C to 1100 ° C. Higher temperatures cause the formation of covalent bonds between the adjacent surfaces of the donor wafer and the handle wafer, for example, converting silanol hydrogen bonds into covalent siloxane bonds, thereby transforming the donor wafer and handle. -The bond with the wafer is strengthened. In parallel with heating or annealing the bonded wafer, the particles injected early by the donor wafer weaken the cleavage plane.

A portion of the donor wafer is then separated (ie, cleaved) from the bonded wafer along the cleavage plane to form an SOI wafer. Cleavage can be done by placing the bonded wafer on a fixture. In such a fixture, a mechanical force is applied perpendicular to the opposite side of the bonded wafer to pull (or peel) a portion of the donor wafer from the bonded wafer. According to some methods, a suction cup is utilized to apply a mechanical force. Separation of a portion of the donor wafer is initiated by applying a mechanical force to the edge of the bonded wafer at the cleavage plane to initiate crack propagation along the cleavage plane. The mechanical force applied by the suction cup then pulls (or pulls) a portion of the donor wafer from the bonded wafer, thus forming the SOI wafer.

Alternatively, the bonded pair may instead be exposed to high temperatures for a period of time, thereby separating a portion of the donor wafer from the bonded wafer. Exposure to high temperatures causes and propagates cracks along the cleavage plane, thus separating part of the donor wafer. Cracks are formed due to void formation from the injected ions, which grow by Ostwald ripening. Voids are filled with hydrogen and helium. Voids become platelets. Pressurized gas in the platelet propagates through the microcavities and microcracks, which weakens the silicon in the implant plane. When annealing is stopped at the right time, the weakened bonded wafer can be cleaved by a mechanical process. However, if the heat treatment is continued for a longer period of time and / or at a higher temperature, the propagation of microcracks reaches a level where all cracks meet along the cleavage plane, thus separating part of the donor wafer. Although this method further improves the uniformity of the transfer layer and allows the donor wafer to be recycled, it typically requires heating the injected and bonded pairs to temperatures close to 500 ° C.

The use of high resistivity semiconductor-on-insulator (such as silicon-on-insulator) wafers for RF-related devices such as antenna switches offers advantages over traditional substrates in terms of cost and integration. Be done. Although not sufficient, when using conductive substrates for high frequency applications, it is necessary to use substrate wafers with high resistivity to reduce parasitic power loss and minimize inherent harmonic distortion. Therefore, the resistance of the handle wafer of an RF device is generally greater than about 500 Ω · cm. As shown in FIG. 1, the silicon-on-insulator structure 2 comprises a silicon wafer 4 having a very high resistivity, an embedded oxide (BOX) layer 6, and a silicon device layer 10. Such substrates are likely to result in the formation of layers 12 of high conductive charge inversion or accumulation at the BOX / handle interface that causes the generation of free carriers (electrons or holes), which reduces the effective resistivity of the substrate. It causes parasitic power loss and device non-linearity when the device is operated at RF frequencies. Such inversion / storage layers can be due to BOX fixed charges, oxide trap charges, interfacial trap charges, and even DC bias applied to the device itself.

Therefore, there is a need for a method that suppresses the formation of induced inversion layers or accumulation layers and maintains a high resistivity of the substrate even in a very near surface region. It is known that a trap rich layer between a high resistivity handle substrate and an embedded oxide (BOX) can improve the performance of RF devices manufactured using SOI wafers. .. Methods for forming these high interface trap layers have been proposed. For example, as shown in FIG. 2, one method of creating a semiconductor-on-insulator multilayer structure 20 (eg, silicon-on-insulator, or SOI) with a trap-rich layer for RF device applications is An undoped polysilicon film 28 is deposited on a high resistivity silicon substrate 22, and a stack of an oxide (for example, an embedded oxide layer 24) and an uppermost silicon layer 26 is formed on the polysilicon film 28. Is based. The polysilicon silicon layer 28 functions as a high defectivity layer between the silicon substrate 22 and the embedded oxide layer 24. See FIG. FIG. 2 shows a polysilicon film used as a trap-rich layer 28 between the resistivity substrate 22 and the embedded oxide layer 24 in the silicon-on-insulator multilayer structure 20. An alternative method is heavy ion implantation to create a near surface damage layer. Devices such as radio frequency devices are incorporated in the top silicon layer 26.

Academic studies have shown that the polysilicon layer between the oxide and the substrate provides improved device insulation, reduced transmission line loss and reduced harmonic distortion. For example, H.S.Gamble et al. “Low-loss CPW lines on surface stabilized high resistivity silicon,” Microwave Guided Wave Lett., 9 (10), pp.395-397, 1999, D.Lederer, R.Lobet and J.-P. .Raskin, “Enhanced high resistivity SOI wafers for RF applications,” IEEE Intl. SOI Conf., Pp.46-47, 2004, D.Lederer and J.-P.Raskin, “New substrate passivation method dedicated to high resistivity SOI wafer foiling with increased substrate resistivity, ”IEEE Electron Device Letters, vol.26, no.11, pp.805-807, 2005, D.Lederer, B.Aspar, C.Laghae and J.-P.Raskin,“ Performance of RF passive structures and SOI MOSFETs transferred on a passivated HR SOI substrate, ”IEEE International SOI Conference, pp.29-30, 2006, and Daniel C. Kerr et al. See trap-rich layer ”, Silicon Monolithic Integrated Circuits in RF Systems, 2008. SiRF 2008 (IEEE Topical Meeting), pp.151-154, 2008.

Abstract of the Invention Briefly, the present invention targets the following multilayer structures (or multilayer structures).
A single crystal silicon wafer handle substrate comprising two substantially parallel main planes, a peripheral edge (or peripheral edge or outer edge), and a central plane (or central plane). One of the two substantially parallel main surfaces is the front surface of the single crystal silicon wafer handle substrate, and the other of the two substantially parallel main surfaces is the single crystal silicon wafer handle substrate. A single crystal silicon semiconductor handle, which is the back side surface, and a trap rich layer, which is in interface contact with the front side surface of the single crystal silicon wafer handle substrate, and a trap. -It consists of a dielectric layer that is in interface contact with the rich layer and a single crystal semiconductor device layer that is in interface contact with the dielectric layer.
In a single crystal silicon wafer handle substrate, the peripheral edge connects (or joins) the front side surface and the back side surface of the single crystal silicon wafer handle substrate, and the single crystal silicon wafer handle substrate is connected. The central surface of the substrate is between the front and back surfaces of the single crystal silicon wafer handle substrate.
The single crystal silicon wafer handle substrate has a bulk resistance of at least about 5000 Ω · cm, an interstitial oxygen concentration of less than about 1 × 10 ¹⁶ atoms / ^cm3 , and at least about 1 × 10 ¹³ atoms. Multilayer structure with a nitrogen concentration of / ^cm3 .

FIG. 1 shows a silicon-on-insulator wafer having a high resistivity substrate and an embedded oxide layer. FIG. 2 shows a silicon-on-insulator wafer, showing an SOI wafer having a polycrystalline silicon trap-rich layer between the resistivity substrate and the embedded oxide layer. FIG. 3 is a graph showing harmonic distortion using the substrate resistivity of the HR-SOI structure using the trap-rich layer as a function. FIG. 4 is a graph showing the resistivity depth profiles of the float zone-grown handle wafers and the Czochralski-grown handle wafers after SOI treatment using a trap-rich layer. FIG. 5 is a graph showing the average resistivity of the first 90 microns under the BOX / handle interface of a handle wafer for float zone growth after SOI treatment with a trap-rich layer. FIG. 6 is a graph showing a comparison of SOI multilayer slip windows in which the handle substrate is made using the float zone method or the Czochralski method. FIG. 7 is a graph showing the resistivity of the SOI multilayer structure in which the handle substrate is prepared by using the float zone method under the change of annealing conditions. FIG. 8 shows the harmonic distortion (HD2) pair pin of the SOI multilayer structure in which the handle substrate is created using the float zone method, and the SOI multilayer structure in which the handle substrate is created using the Czochralski method. It is a graph which shows the comparison with the harmonic | distortion (HD2) vs. pin of.

(Detailed description of aspects of the invention)
According to the present invention, methods and structures for manufacturing semiconductor on-insulator (eg, silicon-on-insulator) structures that enable excellent radio frequency (RF) device performance, device stability, and device manufacturing characteristics are provided. Will be done. In the present invention, float zone (FZ) silicon-based wafers (handle wafers) with high resistivity (eg, very high or ultra-high resistivity), and trap-rich layers are semiconductor-on-insulators (eg, eg). It is integrated (or integrated) into a silicon-on-insulator structure.

Radio frequency (RF) chip designs benefit greatly from higher substrate resistivity levels. Improving quality factors for passive elements such as inductors and capacitors, reducing transmission line attenuation, and electrical insulation of the substrate between integrated digital and RF and analog elements are achieved with higher resistivity silicon substrates. In the industry standard, the resistivity of the handle substrate exceeds 1000 Ω · cm, and a higher resistivity is preferred. Integrating a high resistivity substrate into a semiconductor-on-insulator (eg, silicon-on-insulator) structure (HRSOI) improves device insulation, reduces conductive coupling to substrate wafers, and junctions. The decrease in capacitance) further improves the RF function.

Growing an ultra-high resistivity Czochralski (CZ) crystal to a resistivity value exceeding 7500 Ω · cm entails severe challenges. Since the concentration of electrically active dopants added is significantly reduced, further control of dopants (such as boron and phosphorus) introduced from all raw materials and components used in the CZ crystal puller The emphasis needs to be placed. These materials and components include polysilicon source materials and quartz crucibles. In addition, due to the very low dopant levels in the melt, the mass transfer of the dopant to the boundary layer at the interface between the melt and the solid to achieve acceptable radial resistance variation, and such boundaries. Controlling the mass transfer of the dopant through the layer is important. Another important challenge in the growth of higher resistivity Czochralski silicon ingots is to control the behavior of interstitial oxygen incorporated during crystal growth. The interstitial oxygen concentration (or penetrating oxygen concentration) of silicon in chokralsky growth is usually higher than 5 × 10 ¹⁷ atoms / cm ³ (10PPMA new ASTM), for example up to about 1 × 10 ¹⁸ atoms / cm ³ (20PPMA new ASTM) and so on. The source of such interstitial oxygen is the dissolution of the SiO ₂ crucible during crystal growth. With high resistance CZ silicon, oxygen can be controlled in the range of about 5PPMA (2.5 × 10 ¹⁷ atoms / cm ³ ) and lower concentrations such as about 2PPMA (1 × 10 ¹⁷ atoms / cm ³ ), about. It can be controlled to 3PPMA (1.5 × 10 ¹⁷ atoms / cm ³ ) and about 4PPMA (2 × 10 ¹⁷ atoms / cm ³ ). However, even at low concentrations, interstitial oxygen is strongly dependent on both the interstitial oxygen concentration and the annealing time / temperature of 350-500 ° C. and can aggregate into electrically active thermal donors. At aggregation levels above four oxygen atoms, the thermal donor becomes electrically active and acts as a double donor. The formation of such donors is maximal at about 450 ° C., then diminishes, dissociates with annealing treatments above about 550 ° C., and can return to the electrically inactive state. However, longer annealing times and higher annealing temperatures such as 550 ° C to 850 ° C can form so-called new thermal donors. Peak new thermal donor formation occurs at temperatures between 750 ° C and 800 ° C. We recently discovered another class of excess donors in high resistivity silicon that undergoes high temperature heat treatment. Fast diffusing species, which have not yet been identified, are introduced into silicon wafers with very high T-anneals and rapidly cooled by wafer cooling. When then heated to 450 ° C to 650 ° C, these seeds rapidly form a complex with interstitial oxygen in the wafer to form an electrically active "excess donor". Such excess donors dissociate when heated above about 1050 ° C to 1100 ° C. Oxygen thermal double donors, new donors, and excess thermal donors contribute to the conduction of electrons, which vary the resistivity and type of wafer depending on the "number of donors produced" vs. the "background carrier concentration of the wafer". In p-type silicon, the thermal donor concentration increases the resistivity of the wafer to a point where the thermal donor concentration exceeds the p-type carrier concentration at which the wafer will be converted to n-type. Then, when further thermal donors are generated, the resistivity of the n-type wafer becomes lower and lower. Changes in resistivity during or at the end of the device manufacturing process can disrupt resistivity-sensitive manufacturing processes and reduce device performance. Thermal donors can, in principle, be extinguished with high T-annealing (higher than about 550 ° C for thermal double donors, about 1050 ° C to about 1100 ° C for new donors and excess donors), and in practice Most of these donors are formed after metallization by a low temperature annealing step (a step that can occur at a temperature of about 450 ° C.) that occurs in the second half of the integrated circuit manufacturing flow (“line back end, VOL”). Once the metal is deposited, the wafer cannot be heated to T above about 500 ° C., so none of the thermal donor species formed in BEOL can be extinguished. Although thermal donors formed at 350-500 ° C can be removed by high temperature annealing for a short period of time, the presence of excess thermal donors is particularly pronounced in high resistivity silicon with resistivity above 4000 Ω · cm, 7500 Ω. -It will be larger for materials with resistivity greater than cm. In such materials, the dopant concentration can be 1.8 × 10 ¹² / cm ³ (p-type) or N _d <5 × 10 ¹¹ / cm ³ (n-type). For comparison, the excess thermal donor concentration is about 1 × 10 ¹² / cm ³ for materials annealed at a temperature of about 1100-1125 ° C, and excess thermal donor concentration for materials annealed at about 1000 ° C. Is low, as low as 1 × 10 ¹¹ / cm ³ . Given the concentration of comparable dopant materials (eg boron, arsenic, phosphorus, etc.) and the concentration of excess thermal donors, materials identified as having high resistivity suffer from resistivity variability. It can also be difficult in terms of the obvious shift from p-type to n-type.

Float zone (FZ) silicon is an ultra-purity alternative to CZ silicon. The FZ can be manufactured at a resistivity level of more than 5000 Ω · cm, and can be manufactured at a resistivity level of more than 7500 Ω · cm, further more than 10000 Ω · cm, and even more than 20000 Ω · cm. The float zone process can minimize the introduction of oxygen into the growing single crystal and advantageously minimize the formation of oxygen thermal double donors, new thermal donors, and excess thermal donors. The associated reduction in thermal donor formation minimizes axial and radial resistivity variations of the ingot and the wafer sliced from it. Both of these can improve device performance and resistivity stabilization.

HRSOI wafers are the interface between the embedded oxide layer (BOX) and the high resistivity substrate, which can extend more than 10 microns within the underlying high resistivity substrate. ). This is caused by the combination of the normal oxide charge in the BOX and the very low doping concentration of the substrate. The effect of parasitic surface conduction shown in FIG. 1 (referred to in the literature as PSC) lowers the effective substrate resistivity and increases RF loss, substrate non-linearity and crosstalk. Placing the trap-rich layer 28 (see FIG. 2) between the BOX 24 and the high resistivity substrate 22 is a parasitic conduction layer 12 (FIG. 1) by trapping free carriers attracted to the BOX / substrate interface. (See) to prevent the formation of accumulation layers or inversion layers. Trap-rich layer and stable float zone silicon handle with resistivity of over 5000 Ω · cm, over 7500 Ω · cm, over 10000 Ω · cm, even over 20000 Ω · cm, and even over 30,000 Ω · cm When combined with a wafer, it is better than -80 dBm, better than -90 dBm, better than -100 dBm, or better than -110 dBm, such as second harmonic distortion or HD2 value. RF performance can be achieved. See FIG. 3, which shows the harmonic distortion with the substrate resistivity as a variable in the HR-SOI structure using the trap-rich layer. As shown there, wafers with higher resistivity exhibit better HD2 values. More specifically, a second harmonic distortion or HD2 value better than -100 dBm or better than -110 dBm is a float zone handle with a resistivity value greater than 20,000 Ω cm or more than 30,000 Ω cm. This can be achieved in an SOI structure with a substrate.

The use of float zone handle wafers is intended to solve some problems. That is, 1) FZ can be manufactured to a target level resistivity of more than 5000 Ω · cm, more than 7500 Ω · cm, more than 10000 Ω · cm, further more than 20000 Ω · cm, or even more than 30,000 Ω · cm. It provides a crystal growth path, which allows for improved RF performance when combined with a trap-rich layer. 2) The FZ has an oxygen content below the detection limit, which can reduce or eliminate the formation of electrically active thermal donors and excess thermal donors, resulting in the electrical performance of the RF. Prevents resistivity shifts that can reduce and interfere with the processing of wafers on the device manufacturing line. Float zone silicon is grown by vertical zone melting / purification of high purity polycrystalline rods. The seed crystal is placed at one end of the rod and single crystal growth is initiated. Such a process avoids the use of containment vessels that significantly reduce the introduction of impurities, including oxygen. For ultra-high resistivity silicon, it is essential to eliminate oxygen effects such as thermal donor formation. Nitrogen is typically added intentionally during the growth of the FZ to control point defect formation and improve mechanical strength. The doping level and dopant type of the ultra-high resistivity FZ depends on the purity of the polycrystalline source rod.

(I) Float Zone Handle Wafer According to the present invention, a wafer sliced from a single crystal silicon ingot grown by the float zone method is a semiconductor having the structure shown in FIG. 2 as a high resistivity handle structure. It is integrated into an on-insulator (eg, silicon-on-insulator) multilayer structure 20. That is, the semiconductor-on-insulator (for example, silicon-on-insulator) multilayer structure 20 has a float zone high resistivity handle structure 22 (or a high resistance float zone handle structure (for example, a semiconductor handle substrate 22)). It comprises a trap-rich layer 28, a dielectric layer 24, and a device layer 26.

The substrates used in the present invention include semiconductor handle substrates (eg, single crystal semiconductor handle wafers) and semiconductor donor substrates (eg, single crystal semiconductor donor wafers). The semiconductor device layer 26 in the semiconductor-on-insulator multilayer structure 20 is derived from the single crystal semiconductor donor wafer. The semiconductor device layer 26 may be transferred onto the semiconductor handle substrate 22 by a wafer thinning technique such as etching the semiconductor donor substrate, or by cleaving the semiconductor donor substrate including the damaged surface.

Generally, a single crystal semiconductor handle wafer and a single crystal semiconductor donor wafer have two substantially parallel main planes (or main planes or main planes). One of the substantially parallel main surfaces is the front surface (or front surface or front surface) of the substrate, and the other of the substantially parallel main surfaces is the back surface surface (or back surface or back surface) of the substrate. The substrate comprises a peripheral edge connecting the front and back surfaces, a bulk region between the front and back surfaces, and a central surface (or central surface) between the front and back surfaces. In addition, the substrate additionally has a virtual central axis perpendicular to the central plane and a radial length extending from the central axis to the peripheral edge. Also, in addition, semiconductor substrates such as silicon wafers can typically have total thickness variation (TTV), warp and bow, so that all points on the front surface It is possible that the midpoints of all the points on the back side will not fit exactly in the plane. However, in practice, TTV, deflection and warpage are typically very small, with the midpoint within a virtual central plane approximately equidistant between the front and back sides. Can be approximated to.

Prior to the operations described herein, the front and back surfaces of the substrate may be substantially identical. For convenience only, a surface is referred to as a "front surface" or "back surface" to distinguish between surfaces on which the operations of the methods of the invention are performed. In the context of the present invention, the "front side surface" of a single crystal semiconductor handle substrate (eg, a single crystal silicon handle wafer) refers to the main surface of the substrate which is the inner surface of the bonded structure. A trap-rich layer is formed on the front surface. Therefore, the "back side surface" of a single crystal semiconductor handle substrate (eg, handle wafer) refers to the main surface that is the outer surface of the bonded structure. Similarly, the "front side surface" of a single crystal semiconductor donor substrate (eg, a single crystal silicon donor wafer) refers to the main surface of the single crystal semiconductor donor substrate that is the inner surface of the coupled structure. The front surface of the single crystal semiconductor donor substrate often comprises a dielectric layer, such as a silicon dioxide layer, that constitutes part or all of the embedded oxide (BOX) layer in the final structure. The "backside" of a single crystal semiconductor donor substrate (eg, a single crystal silicon donor wafer) refers to the main surface that is the outer surface of the coupled structure. Upon completion of the conventional bonding and wafer thinning steps, the single crystal semiconductor donor substrate constitutes the semiconductor device layer of the semiconductor on-insulator (eg, silicon-on-insulator) composite structure.

The handle wafer comprises a material derived from an ingot grown by the float zone method, such as silicon. Single crystal silicon handle wafers sliced from ingots grown by the float zone method typically have a nominal diameter of at least about 20 mm, at least about 50 mm, at least about 100 mm, at least about 150 mm, and at least about 200 mm (eg,). It has a diameter of about 150 mm or about 200 mm). Due to the limitation of surface tension during the growth process, the diameter (or diameter) is commonly less than 250 mm, or less than about 200 mm. The thickness of the handle wafer is from about 100 micrometers to about 5000 micrometers, such as about 100 micrometers to about 1500 micrometers, about 250 micrometers to about 1500 micrometers, about 300 micrometers to about 1000 micrometers, and so on. It can vary between, preferably in the range of about 500 micrometers to about 1000 micrometers. In some specific embodiments, the wafer thickness may be about 725 micrometers. Also, in some embodiments, the wafer thickness may be about 775 micrometers.

In some embodiments, the float zone crystal ingot and the single crystal semiconductor handle substrate sliced from it have bulk resistivity and are at least about 5000 Ω · cm, at least about 7500 Ω · cm, eg, at least about 10000 Ω · cm. Has a bulk resistivity of at least about 15,000 Ω · cm, at least about 20,000 Ω · cm, at least about 25,000 Ω · cm, or at least about 30,000 Ω · cm. In some embodiments, the single crystal semiconductor handle substrate has a bulk resistivity of less than about 100,000 Ω · cm. Wafers with high resistance include boron (p type), gallium (p type), aluminum (p type), indium (p type), phosphorus (n type), antimony (n type), and arsenic (n type). Can contain electrically active dopants of, and generally at very low concentrations (eg, less than 1 × 10 ¹² atoms / cm ³ and even less than 1 × 10 ¹¹ atoms / cm ³ ) such electrically. May include active dopants. The method itself for preparing high resistivity wafers from float zone single crystal silicon ingots is known in the art, and such high resistivity wafers are obtained from commercial suppliers such as Global Wafers in Taiwan. You may.

Silicon handle wafers derived from float zone growth ingots can more reliably target ultra-high resistance values with minimal to maximum fluctuations of up to approximately double. For example, the minimum to maximum specifications for the two sides of the resistivity of a wafer can be accepted as 10,000 to 20,000 Ω · cm or more, which means that such specifications are generally one side and 7500 Ω · cm or more, etc. It is different from the UHR Cz wafer. Tolerance of ± 30-50% around the target value is acceptable. This not only allows the end user to improve the RF electrical performance level (eg, as shown in Figure 3), but also makes it more predictable and variable when compared to Czochralski growth silicon. Is reduced. The basic reason for this solution is that the float zone growing silicon handle wafer has an oxygen concentration below the detection limit, causing fluctuations in thermal donor formation and ultra-high resistivity Czochralski growing silicon. This is because the formation can be avoided. In some embodiments, the float zone grown silicon handle wafer is, for example, about 2.5 × 10 ¹⁶ atoms / cm ³ (0.5PPMA, new ASTM standard), about 2 × 10 ¹⁶ by metrology. Atoms / cm less than ³ (0.4PPMA, new ASTM standard), about 1 x 10 ¹⁶ atoms / cm ³ (0.2PPMA, new ASTM standard), or about 1 x 10 ¹⁵ atoms / cm ³ (0.02PPMA) , New ASTM standard), and eliminates the presence of oxygen thermal donors and excess donors formed on chokralsky-grown silicon wafers (wafers with detectable oxygen concentration) that have oxygen levels below the detection limits. There is. In some embodiments, the silicon handle wafer has an excess thermal donor concentration of less than 1 × 10 ¹¹ donor / cm ³ or less than 5 × 10 ¹⁰ donor / cm ³ . In some embodiments, the oxygen concentration is very low, the double donor thermal donor concentration, the new thermal donor concentration, and / or the excess thermal donor concentration is below the detectable limit, and the first approximation is for such donors. The concentration is at least an order of magnitude lower than the concentration of the p-type acceptor or n-type donor. In other words, either the double donor thermal donor concentration, the new thermal donor concentration and / or the excess thermal donor concentration, or the sum of the double donor thermal donor concentration, the new thermal donor concentration and / or the excess thermal donor concentration. Is at least an order of magnitude lower than the concentration of the p-type acceptor or n-type donor, that is, less than 1/10 of the concentration of the p-type dopant or n-type dopant. In CZ, thermal donors and excess donors can be below or above the background doping concentration, depending on the oxygen concentration and thermal cycle details. The thermal double donor concentration in CZ Si will continue to increase to very large values with annealing time at temperatures up to 450 ° C. The concentration will eventually saturate at some value that depends on Oi. For large Oi of ~ 15 nppma, the saturation concentration can be ~ 1 × 10 ¹⁶ / cm ³ or more. Saturated (maximum) TDD concentration decreases with decreasing Oi. It will be much higher than the actual dopant concentration associated with HR Si. Low donor concentrations in FZ wafers reduce fluctuations in RF performance, reduce the effects of resistivity fluctuations on wafer resistivity (electrostatic chucking) sensitive device manufacturing processes, and provide ultra-high resistivity / low oxygen. Sensitivity to new thermal donor formation, another source of variation in Czochralski-grown silicon wafers, is eliminated.

In addition, the spread resistance profile (SRP) of a Czochralski-grown silicon handle wafer rarely flattens over the first few tens of microns under the BOX / handle interface, for example after 450 ° C. annealing. The SRP of Czochralski-grown silicon handle wafers is often affected by TD formation and excess donors, and the profile changes significantly as shown in FIG. However, the SRP of float zone grown silicon handle wafers is very flat, showing that there are no thermal donors and excess donors in the 450 ° C and 600 ° C tests. See FIG. In the graph of FIG. 4, the diamond-shaped (◆) line shows the resistivity per depth of the float zone handle wafer before annealing of donor-generated annealing (DGA) at 450 ° C. The line shows the resistivity per depth of the float zone handle wafer after DGA annealing at 450 ° C. Further, in such a graph, the square (■) line shows the resistivity per depth of the Czochralski growth handle wafer p-type after DGA annealing at 450 ° C. Then, in this graph, the triangular (▲) line shows the resistivity per depth of the Czochralski growth handle wafer n type after DGA annealing at 450 ° C. See also FIG. FIG. 5 shows the first under the BOX / handle interface of a float zone growth handle wafer (wafer with resistivity greater than 5000 Ω · cm and higher resistance than 10000 Ω · cm) after SOI treatment with a trap-rich layer. It shows an average resistivity of 90 microns. The profile is very flat, showing the complete absence of thermal donors in the 450 ° C and 600 ° C tests.

If float zone grown silicon handle wafers have oxygen below the detectable limit, such wafers may be more prone to slip in the thermal process. However, nitrogen may be added during float zone crystal growth to control the formation of point defects and add strength to resist slippage. Uniform concentrations of impurities may be incorporated using specialized doping techniques such as core doping, pill doping, and gas doping with nitrogen or ammonia gas. In some embodiments, the nitrogen concentration of the float zone grown silicon handle wafer is at least about 1 × 10 ¹³ atoms / cm ³ , eg at least 0.5 × 10 ¹⁴ atoms / cm ³ , at least about 1 × 10 ¹⁴ atoms. / Cm ³ and so on. In some embodiments, the nitrogen concentration of the float zone grown silicon handle wafer is about 3 × 10 less than ¹⁵ atoms / cm ³ , about 1 × 10 less than ¹⁵ atoms / cm ³ , and about 7 × 10 ¹⁴ atoms / cm ³ . It may be less than, or less than about ³ × 10 ¹⁴ atoms / cm3. In some embodiments, the nitrogen concentration in the float zone grown silicon handle wafer may be at least about 0.5 × 10 ¹⁴ atoms / cm ³ and may be less than about 3 × 10 ¹⁴ atoms / cm ³ . .. Demonstrations of nitrogen-doped float zone grown silicon handle wafers on the SOI production line showed almost the same acceptable slip performance as Czochralski grown silicon handle wafers.

In this regard, float zone grown silicon handle wafers and Czochralski grown silicon handle wafers were subjected to oxidation at 800 ° C. and then annealed at 1100 ° C. for 2 hours for slip inspection. As a result, no slip was observed with either wafer type. Therefore, nitrogen-doped float zone handle wafers can withstand slip-free thermal cycles associated with trap-rich layer deposition and subsequent SOI wafer fabrication. In another furnace push test, the furnace was heated to 1000 ° C. and the float zone grown silicon handle wafers and the Czochralski grown silicon handle wafers were pushed through the furnace rapidly. In such a slip test, both wafer types showed similar behavior.

In some embodiments, the front and back surfaces of the single crystal semiconductor handle substrate, or both the front and back surfaces, are subjected to a process such as an oxidation process, such as a semiconductor oxide layer, a semiconductor nitride layer, or a semiconductor. A dielectric layer such as an oxynitride layer can be grown. In some embodiments, the dielectric layer comprises silicon dioxide (or silicon dioxide), which can be formed by oxidizing the front side surface of the silicon handle substrate. This can be achieved by thermal oxidation (thermal oxidation where some portion of the deposited semiconductor material film will be consumed) and / or CVD oxide deposition and / or atomic layer deposition. In some embodiments, the semiconductor handle substrate may be thermally oxidized in a furnace such as ASM A400. In an oxidizing environment, the temperature can range from 750 ° C to 1100 ° C. The atmosphere of the oxidizing environment can be a mixture of an inert gas such as Ar or N ₂ and O ₂ . Oxygen content can vary in the range of 1-10% or higher. In some embodiments, the atmosphere of the oxidizing environment may be up to 100% oxygen (“dry oxidation”). In some embodiments, the atmosphere of the oxidizing environment is oxygen and ammonia, which is suitable for the deposition of silicon nitride (or silicon nitride). In some embodiments, the environmental atmosphere may include a mixture of an inert gas such as Ar or N ₂ , an oxidizing gas such as O ₂ and water vapor (“wet oxidation”). In some embodiments, the environmental atmosphere comprises a mixture of an inert gas such as Ar or N ₂ , an oxidizing gas such as O ₂ , water vapor (“wet oxidation”), and a nitride gas such as ammonia. good. In some embodiments, the environmental atmosphere may consist of a mixture of an inert gas such as Ar or N ₂ and a nitride gas such as ammonia, which is suitable for the deposition of silicon nitride (or silicon nitride). be. As an exemplary embodiment, the semiconductor handle wafer may be charged in a vertical furnace such as A400. The temperature is raised to the oxidation temperature using a mixture of N ₂ and O ₂ . At the desired temperature, water vapor is introduced into the gas stream. Once the desired oxide thickness is obtained, steam and O ₂ are turned off, the furnace temperature is lowered and the wafer is removed from the furnace. The oxide layer on the front side, the back side, or both may be about 100 angstroms to about 100,000 angstroms, about 100 angstroms to about 10,000 angstroms, about 100 angstroms to about 1000 angstroms, and may be, for example, about 100 angstroms to about 700 angstroms. , About 100 angstroms to about 500 angstroms, or about 100 angstroms to about 250 angstroms.

In some embodiments, the oxidation layer is relatively thin, ranging from about 5 angstroms to about 25 angstroms, such as about 10 angstroms to about 15 angstroms. Thin oxide layers can be obtained on both sides of the semiconductor wafer by exposure to a standard cleaning solution such as the SC1 / SC2 cleaning solution. In some embodiments, the SC1 solution is 5 parts deionized water, 1 part NH ₄ OH aqueous solution (ammonium hydroxide, 29 wt% NH ₃ ), and 1 part H ₂ O ₂ aqueous solution (hydrogen peroxide). , 30%). In some embodiments, the handle substrate may be oxidized by exposure to an aqueous solution containing an oxidizing agent, such as an SC2 solution. In some embodiments, the SC2 solution comprises 5 parts deionized water, 1 part HCl aqueous solution (hydrochloric acid, 39% by weight), and 1 part _{H2O 2 aqueous} solution (hydrogen peroxide, 30%). Become.

(II) Trap-rich layer In the method of the present invention, a trap-rich layer containing a polycrystalline or amorphous semiconductor material is deposited on the exposed front side surface of a single crystal semiconductor handle wafer. Semiconductor materials suitable for use in trap-rich layer formation in semiconductor-on-insulator devices are capable of forming high defect layers in manufactured devices. Such materials include polycrystalline semiconductor materials and amorphous semiconductor materials. Polycrystalline or amorphous materials include silicon (Si), silicon germanium (SiGe), carbon-doped silicon (SiC), and germanium (Ge). Polycrystalline silicon represents a material comprising small silicon crystals with random crystal orientations. The polycrystalline silicon particles may be as small as about 20 nanometers in size. In the method of the present invention, the smaller the crystal particle size of the deposited polysilicon, the higher the defect rate in the trap-rich layer. Amorphous silicon includes non-crystalline allotropic forms of silicon that lack a short range and long range order. Silicon particles with a crystallinity of about 10 nanometers or less can also be considered amorphous in nature. Silicon-germanium comprises an alloy of silicon (or silicon) and silicon-germanium in any molar ratio of germanium. The carbon-doped silicon contains a compound of silicon and carbon, and the molar ratio of silicon to carbon may be different. The resistance of the polycrystalline silicon trap rich layer is at least 100 Ω · cm, at least about 500 Ω · cm, at least about 1000 Ω · cm, and at least about 3000 Ω · cm, for example about 100 Ω · cm to about 100,000 Ω ·. cm, or about 500Ω ・ cm to about 100,000Ω ・ cm, or about 1000Ω ・ cm to about 100,000Ω ・ cm, about 500Ω ・ cm to about 10,000Ω ・ cm, or about 750Ω ・ cm to about 10000Ω ・ cm, about 1000Ω -Cm to about 10000 Ω-cm, about 2000 Ω-cm to about 10000 Ω-cm, about 3000 Ω-cm to about 10000 Ω-cm, or about 3000 Ω-cm to about 8000 Ω-cm.

The material for the optional oxidation of the single crystal semiconductor handle wafer on the front side surface may be deposited by means known in the art. For example, semiconductor materials include metalorganic chemical vapor deposition (MOCVD), physical vapor deposition (PVD), chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), or molecular beams. It may be deposited using epitaxy (MBE). Silicon precursors for LPCVD or PECVD include, among other things, methylsilane, silicon tetrahydride (silane), trisilane, disilane, pentasilane, neopentasilane, tetrasilane, dichlorosilane (SiH ₂ Cl ₂ ), silicon tetrachloride (SiCl). ₄ ) can be mentioned. For example, polysilicon may be deposited on the surface oxide layer by thermally decomposing silane (SiH ₄ ) in a temperature range of about 550 ° C to about 690 ° C (eg, about 580 ° C to about 650 ° C). The chamber pressure may be in the range of about 70 to about 400 mTorr. Amorphous silicon may be deposited by plasma-enhanced chemical vapor deposition (PECVD), generally at temperatures in the range of about 75 ° C to about 300 ° C. Silicon-germanium, particularly amorphous silicon-germanium, may be deposited at temperatures up to about 300 ° C. by chemical vapor deposition by including organogermanium compounds such as isobutyl germanium, alkyl germanium trichloride and dimethylamino germanium trichloride. Carbon-doped silicon may be deposited by thermal plasma chemical vapor deposition in an epitaxial reactor using precursors such as silicon tetrachloride and methane. Suitable carbon precursors for CVD or PECVD include, among others, methylsilane, methane, ethane, and ethylene. Methylsilane is a particularly preferred precursor for LPCVD deposition as it provides both carbon and silicon. Preferred precursors for PECVD deposition include silane and methane. In some embodiments, the silicon layer may consist of a carbon concentration of at least about 1% on an atomic basis, such as about 1% to about 10% on an atomic basis.

In some embodiments, the deposition of the semiconductor material in the trap-rich layer may be temporarily interrupted to prepare a multi-layer of trap-rich material, at least once, preferably two or more times. May be done. The interim surface of the semiconductor material film may be exposed to an inert atmosphere, an oxidizing atmosphere, a nitrided atmosphere, or a passivated atmosphere, thereby poisoning or passivating the deposited semiconductor material. In other words, the method of the invention is carried out by a cycle process in which the semiconductor material is deposited, the deposition is interrupted, the layer of the semiconductor material is poisoned or passivated, and the next layer of the semiconductor material is deposited. It can include depositing multiple layers of trap-rich semiconductor material. In some embodiments, a multilayer consisting of one passivated semiconductor layer may be formed, and one additional semiconductor layer may be deposited to form a trap-rich layer. In some embodiments, the multilayer consists of a trap-rich layer with two or more passivation semiconductor layers and one additional semiconductor layer. By depositing the trap-rich layer in this way, for example, one or more passivation layers or two or more passivation layers of the semiconductor material, for example, at least three passivation layers of the semiconductor material, or a semiconductor. A multilayer consisting of at least four passivation layers of the material is deposited on the handle substrate, eg, 4 to about 100 passivation layers or 4 to about 60 passivation layers or 4 to about 50 passivation layers. A multilayer consisting of a passivation layer or 4 to about 25 passivation layers or 6 to about 20 passivation layers is deposited on the handle substrate. A large number of semiconductor layers can be deposited, partially limited by throughput requirements and by the minimum actual layer thickness that can be deposited, which is currently about 20 nanometers. Each of these layers of semiconductor material is said to be limited by the overall trap-rich layer thickness as in the conventional process during the high temperature process of manufacturing semiconductor-on-insulators. Rather, it is poisoned or passivated so that it is limited by the thickness of the passivated multilayer. In some embodiments, the semiconductor layer exposes the first semiconductor layer to an atmosphere comprising a nitrogen-containing gas such as nitrogen, nitrogen sulfite, ammonia (NH ₃ ), nitrogen plasma, and any combination thereof. May be demobilized with. In this regard, the atmosphere in which the semiconductor layer is deposited may contain a nitrogen-containing gas such as nitrogen, and the termination of the deposition process and subsequent exposure to the gas forms a thin passivation layer on the semiconductor layer. Can be enough to do. In some embodiments, the deposited gas may be discharged from the chamber and the chamber may be purged with a nitrogen-containing gas to result in the passivation of the previously deposited semiconductor layer. Exposure to nitrogen may, for example, nitride the deposited semiconductor layer, resulting in the formation of, for example, a thin layer of silicon nitride with a thickness of only a few angstroms. Alternative passivation methods may be used. For example, the semiconductor layer may be passivated by exposing the first semiconductor layer to an atmosphere containing an oxygen-containing gas such as oxygen, ozone, water vapor, or any combination thereof. According to such an embodiment, a thin layer of a semiconductor oxide formed on the semiconductor layer and sufficient for passivation of the layer may be formed. For example, a thin layer of silicon oxide may be formed between each layer of the multilayer. The oxide layer may have a thickness of only a few angstroms, such as between about 1 angstrom and about 20 angstroms, or between about 1 angstrom and about 10 angstroms. In some embodiments, air containing both nitrogen and oxygen may be used as the passivation gas. In some embodiments, the semiconductor layer is relative to a liquid selected from the group consisting of water, peroxides (eg, hydrogen peroxide solution), or SC1 solution (NH ₃ : H ₂ O ₂ : H ₂ O). It may be passivated by exposing the first semiconductor layer.

The overall thickness of the trap-rich layer is from about 0.3 micrometers to about 5 micrometers, for example about 0.3 micrometers to about 3 micrometers, or about 0.3 micrometers to about 2 micrometers, or It may be from about 2 micrometers to about 3 micrometers.

In some embodiments, the deposition of the trap-rich layer is followed by the formation of a dielectric layer on the surface of the trap-rich layer. In some embodiments, a single semiconductor handle substrate (eg, a single crystal silicon handle substrate) is oxidized to form a semiconductor oxide (eg, silicon dioxide) film on the trap-rich layer. In some embodiments, the trap-rich layer (eg, polycrystalline film) may be thermally oxidized (thermal oxidation that would consume some portion of the deposited semiconductor material film), or a semiconductor oxide (eg, a semiconductor oxide). For example, a film of silicon dioxide) may be grown by CVD oxide deposition. The oxide layer (eg, silicon dioxide layer) in contact with the polycrystalline or amorphous trap-rich layer (eg, polycrystalline or amorphous silicon trap-rich layer) is from about 0.1 micrometer to about 10. It may have a thickness of micrometers, eg, a thickness of about 0.1 micrometer to about 4 micrometers, a thickness of about 0.1 micrometer to about 2 micrometers, or a thickness of about 0.1 micrometer to It may have a thickness of about 1 micrometer. The oxidation process further oxidizes the backside of the single crystal semiconductor handle wafer, favorably reducing the deflection and warpage potentially caused by the different coefficients of thermal expansion of silicon and silicon dioxide.

(III) Preparation of Bonded Structure Next, a single crystal semiconductor handle wafer such as a single crystal silicon ndle wafer prepared according to the float zone method is transferred to a single crystal semiconductor donor wafer prepared according to a conventional layer transfer method. Combine against. In a preferred embodiment, the single crystal semiconductor donor wafer is a group consisting of silicon (or silicon), silicon carbide, silicon germanium, gallium arsenide, gallium nitride, indium phosphide, indium gallium arsenide, germanium, and combinations thereof. Consists of materials selected from. Donor wafers may be sliced from ingots prepared by the float zone method or the Czochralski method. Wafer thickness can vary between about 100 micrometers and about 5000 micrometers, eg, between about 100 micrometers and about 1500 micrometers, and between about 250 micrometers and about 1500 micrometers. , Such as between about 300 micrometers and about 1000 micrometers, preferably between about 500 micrometers and about 1000 micrometers. In some specific embodiments, the wafer thickness may be about 725 micrometers. In some embodiments, the wafer thickness may be about 775 micrometers. Depending on the desired properties of the final integrated circuit device, single crystal semiconductor (eg, silicon) donor wafers may be boron (p-type), gallium (p-type), aluminum (p-type), indium (p-type), It may contain an electrically active dopant such as phosphorus (n-type), antimony (n-type), and arsenic (n-type). The resistivity of the donor wafer of a single crystal semiconductor (for example, silicon) may be in the range of 1 to 100 Ω · cm, 1 to 50 Ω · cm, 5 to 25 Ω · cm. Single crystal semiconductor donor wafers may be subjected to standard process steps including oxidation, injection, and cleaning (or cleaning) after injection. Therefore, single crystal semiconductor donor wafers that are etched, polished, and optionally oxidized are subjected to ion implantation to form a damaged layer on the donor substrate.

In some embodiments, the single crystal semiconductor donor wafer comprises a dielectric layer. The dielectric layer may consist of one or more insulating layers formed on the front side surface of the single crystal semiconductor donor wafer. The insulating layer may comprise a material selected from the group consisting of silicon dioxide, silicon nitride, and silicon oxynitride. In some embodiments, the insulating layer may comprise a material selected from the group consisting of Al ₂ O ₃ , Al N, or a combination thereof. In some embodiments, the dielectric layer comprises multiple layers (or multiple layers) of insulating material, although other configurations are also within the scope of the present invention. Each insulating layer may contain a material selected from the group consisting of silicon dioxide, silicon nitride, and silicon oxynitride. In some embodiments, the dielectric layer comprises three layers of insulating material, silicon dioxide, silicon nitride, and silicon dioxide in that order. The thickness of each insulating layer may be at least about 10 nanometers, for example, about 10 nanometers to about 10,000 nanometers, about 10 nanometers to about 5000 nanometers, 50 nanometers to about 400 nanometers. It may be meters, or about 100 nanometers to about 400 nanometers, and may be, for example, about 50 nanometers, 100 nanometers, or 200 nanometers.

Ion implantation may be performed by commercially available equipment, such as Applied Materials' Quantum II, Quantum H, Quantum LEAP or Quantum X. You may go. The ions to be injected include He, H, H ₂ or a combination thereof. Ion implantation is performed at a density and duration sufficient to form a damaged layer on the semiconductor donor substrate. The injection density may be from about 10 ¹² ions / cm ² to about 10 ¹⁷ ions / cm ² , for example about 10 ¹⁴ ions / cm ² to about 10 ¹⁷ ions / cm ² , or about 10 ¹⁵ ions / cm ² to. It may be about 10 ¹⁷ ions / cm ² , or about 10 ¹⁶ ions / cm ² to about 10 ¹⁷ ions / cm ² . The injection energy may be in the range of about 1 keV to about 3000 keV, such as about 10 keV to about 3000 keV. The injection energy may be from about 1 keV to about 3000 keV, for example about 5 keV to about 1000 keV, about 5 keV to about 200 keV, or about 5 keV to about 100 keV, about 5 keV to about 80 keV. The injection depth determines the thickness of the single crystal semiconductor device layer transferred to the handle during the SOI process. Ions may be injected to a depth of about 100 angstroms to about 30,000 angstroms, eg, about 200 angstroms to about 20,000 angstroms, about 2000 angstroms to about 15,000 angstroms, about 15,000 angstroms to about 30,000. It may be injected to the depth of angstrom. In some embodiments, it may be desirable to wash the single crystal semiconductor donor wafer (eg, single crystal silicon donor wafer) after injection. In some preferred embodiments, the wash can include a piranha clean followed by a DI water rinse and an SC1 / SC2 wash.

In some aspects of the invention, a single crystal semiconductor donor wafer having an ion implantation region formed by ^ion implantation of He ⁺ , H ⁺ , H ₂₊ or any combination thereof is a single crystal semiconductor donor substrate. It is annealed at a temperature sufficient to form a thermally activated open surface. An example of a suitable tool could be a simple Box furnace, such as the Blue M model. In some preferred embodiments, the ion-implanted single crystal semiconductor donor substrate is annealed at a temperature of about 200 ° C. to about 350 ° C., about 225 ° C. to about 325 ° C., preferably about 300 ° C. Thermal annealing can be performed over a period of about 2 hours to about 10 hours (eg, about 2 hours to about 8 hours, etc.). Thermal annealing in these temperature ranges is sufficient for the formation of thermally activated cleavage planes. After thermal annealing to activate the cleavage plane, the single crystal semiconductor donor substrate surface is optionally cleaned.

In some embodiments, the ion-implanted, optionally cleaned and optionally annealed single crystal semiconductor donor wafer is exposed to surface activation of an oxygen plasma and / or a nitrogen plasma. In some embodiments, the oxygen plasma surface activation tool is a commercially available tool, eg, a tool available from the EV Group, such as the EVG® 810LT Low Temp Plasma Activation System. be. The single crystal semiconductor donor wafer, which is ion-injected and optionally washed, is charged into the chamber. The chamber is evacuated and the chamber is refilled with O ₂ to a pressure below atmospheric pressure, thereby generating plasma. The single crystal semiconductor donor wafer is exposed to such plasma for a desired time (a desired time which can be from about 1 second to about 120 seconds). Oxygen plasma surface oxidation is performed to make the front side surface of the single crystal semiconductor donor substrate hydrophilic so that it can be easily bonded to the single crystal semiconductor handle substrate prepared according to the above method.

Next, the hydrophilic front side surface of the single crystal semiconductor donor wafer and the front side surface of the single crystal semiconductor handle wafer are brought into close contact with each other to form a bonded structure. In the method of the present invention, each of the front side surface of the single crystal semiconductor donor wafer and the front side surface of the single crystal semiconductor handle wafer may have one or more insulating layers. The insulating layer constitutes a dielectric layer having a bonded structure.

Since the mechanical bond may be relatively weak, the bond structure may be further annealed to solidify the bond between the single crystal semiconductor donor wafer and the single crystal semiconductor handle wafer. In some aspects of the invention, the bonded structure is annealed at a temperature sufficient to form a thermally activated cleavage plane in the single crystal semiconductor donor substrate. An example of a suitable tool could be a simple box furnace such as the Blue M model. In some embodiments, the bond structure is annealed at a temperature of about 200 ° C. to about 400 ° C., about 300 ° C. to about 400 ° C., such as about 350 ° C. to about 400 ° C.

In some embodiments, the annealing is performed at a relatively high pressure, such as about 0.5 MPa to about 200 MPa, for example, about 0.5 MPa to about 100 MPa, about 0.5 MPa to about 50 MPa, or about 0.5 MPa. It can be carried out at ~ about 10 MPa, or about 0.5 MPa to about 5 MPa. In the conventional bonding method, the temperature is likely to be limited by cleavage. This is brought about when the platelet pressure on the injection surface exceeds the external isostatic pressure. Therefore, conventional annealing can be limited to a bonding temperature of about 350 ° C to about 400 ° C due to thermal cleavage. After pouring and bonding, the wafers are held together weakly together. However, the gaps between the wafers are sufficient to prevent gas ingress or leakage. The cavities formed during injection are filled with gas, although weak bonds can be strengthened by heat treatment. During heating, the gas in the cavity is pressurized. It is estimated that the pressure can reach 0.2-1 GPa depending on the injection volume (Cherkashin et al., J. Appl. Phys. 118, 245301 (2015)). When the pressure exceeds the critical value, the layer peels off. This is called a thermal cleave. This prevents higher temperatures or longer times in annealing. In some aspects of the invention, the bond occurs at a high pressure, eg, about 0.5 MPa to about 200 MPa, eg, about 0.5 MPa to about 100 MPa, or about 0.5 MPa to about 50 MPa, or about 0. It occurs at high pressures such as 5 MPa to about 10 MPa, about 0.5 MPa to about 5 MPa, thereby allowing coupling at high temperatures. In some embodiments, the bond structure is annealed at temperatures of about 300 ° C. to about 700 ° C., about 400 ° C. to about 600 ° C., eg, about 400 ° C. to about 450 ° C., about 450 ° C. to about 600 ° C. or about 350 ° C. It is annealed at a temperature of ° C to about 450 ° C. Increasing the thermal budget will have a positive effect on bond strength. Thermal annealing can be performed for about 0.5 hours to about 10 hours, such as about 0.5 hours to about 3 hours, preferably about 2 hours. Thermal annealing within such a temperature range is sufficient for the formation of thermally activated cleavage planes. In conventional bond annealing, roll off can cause the edges of both the handle wafer and the donor wafer to be significantly separated. There is no layer transfer in such areas. It is called the terrace. Pressurized bonds are expected to reduce this terrace and extend the SOI layer further towards the edges. This mechanism is based on the trapped air pockets being compressed and "zipped" outward. After thermal annealing to activate the cleavage plane, the bond structure may be cleavaged.

After thermal annealing, the bond between the single crystal semiconductor donor wafer and the single crystal semiconductor handle wafer is strong enough to initiate layer transfer through cleavage of the bonded structure at the cleavage plane. Cleavage may be performed according to techniques known in the art. In some embodiments, the coupling structure may be placed in a conventional cleavage station where one side is attached to a stationary suction cup and the other side is attached to a hinged arm with an additional suction cup. A crack begins near the suction cup attachment and the movable arm rotates around the hinge to cleave the wafer. Cleavage removes a portion of the semiconductor donor wafer, thereby leaving the single crystal semiconductor device layer 26 (preferably the silicon device layer) on the semiconductor on-insulator composite structure 20. See FIG.

After cleavage, the cleavage structure may be subjected to high temperature annealing to further strengthen the bond between the transferred device layer 26 and the single crystal semiconductor handle wafer 22. An example of a suitable tool may be a vertical furnace such as the ASM A400. In some preferred embodiments, the bond structure is annealed at a temperature of about 1000 ° C to about 1200 ° C, preferably about 1000 ° C. Thermal annealing may be carried out for a period of about 0.5 hours to about 8 hours, preferably about 4 hours. Thermal annealing in these temperature ranges is sufficient to strengthen the bond between the transferred device layer and the single crystal semiconductor handle substrate.

After cleavage and high temperature annealing, the bonding structure may be subjected to a cleaning process designed to remove thin thermal oxides from the surface and clean the granules. In some embodiments, the single crystal semiconductor device layer is subjected to a gas phase HCl etching process in a horizontal flow single wafer epitaxial reactor using H ₂ as the carrier gas to have the desired thickness and smoothness. May be made. In some embodiments, the semiconductor device layer 26 may have a thickness of about 20 nanometers to about 3 micrometers, eg, about 20 nanometers to about 2 micrometers, eg, about 20 micrometers. It may have a thickness of about 1.5 micrometers, or about 1.5 micrometers to about 3 micrometers.

In some embodiments, the epitaxial layer may be deposited on the transferred single crystal semiconductor device layer 26. The deposited epitaxial layer may consist of substantially the same electrical properties as the underlying single crystal semiconductor device layer 26. Alternatively, the epitaxial layer may have electrical properties different from those of the underlying single crystal semiconductor device layer 26. The epitaxial layer may comprise a material selected from the group consisting of silicon, silicon carbide, silicon-germanium, gallium arsenide, gallium nitride, indium phosphide, indium gallium arsenide, germanium, and combinations thereof. Depending on the desired properties of the final integrated circuit device, the epitaxial layer may be boron (p-type), gallium (p-type), aluminum (p-type), indium (p-type), phosphorus (n-type), antimony (n-type). It may contain an electrically active dopant such as type) and arsenic (n type). The resistivity of the epitaxial layer may be 1 to 1050 Ω · cm, 1 to 50 Ω · cm, and typically 5 to 25 Ω · cm. In some embodiments, the epitaxial layer may have a thickness of about 20 nanometers to about 3 micrometers, eg, about 20 nanometers to about 2 micrometers, about 20 nanometers to about 1.5 micrometers. It may have a thickness of meters, or about 1.5 micrometers to about 3 micrometers.

The completed SOI multilayer structure may consist of a single crystal semiconductor handle wafer 22, a trap rich layer 28, a dielectric layer 24, and a semiconductor device layer 26, which are then added at the end of the line measurement inspection. , Can be subjected to cleaning at the final point using a typical SC1-SC2 process. Thus, the present invention comprises an SOI multilayer structure comprising a trap-rich layer and a handle substrate made of a nitrogen-doped high resistivity (resistivity greater than 20 kΩ · cm) float zone material. It is targeted. Float zone wafers exhibit better resistivity stability than standard Czochralski handle wafers over a typical BEOL annealing. The higher resistivity that can be achieved using the FZ process allows for the improvement of substrate RF loss, crosstalk and harmonic strain step changes that cannot be easily achieved with traditional CZ silicon materials. We report a first demonstration of an FZ CTLSOI substrate with -110 dBm HD2 in our CPW structure.

The present invention is further described by the following examples (note that such examples do not limit the invention).

Example 1. Float Zone Wafer In this test, wafers obtained from commercially grown 200 mm high resistivity nitrogen-doped float zone crystals were used. The resistivity of the wafer was larger than 20 kΩ · cm. The oxygen concentration in the wafer was less than 1 × 10 ¹⁶ atoms / ^cm3 . Nitrogen concentrations ranged from 0.5 × 10 ¹⁴ / cm ³ to 3 × 10 ¹⁴ / cm ³ when wafers with different levels of nitrogen were evaluated due to the mechanical strength of the wafer. Next, a trap-rich layer was deposited on the FZ wafer. The wafers were then processed into SOI wafers under a high capacity manufacturing (HVM) process flow. At the end of the SOI wafer manufacturing flow, the wafers were subjected to standard quality inspections including surface inspection using KLA Tencol SP1, flatness, shape measurement using ADE9700, and slip inspection.

Example 2. Slip Stress Test SOI wafers manufactured to have handle substrates prepared by the float zone method with low and higher nitrogen concentrations are subjected to a rapid thermal process (RTP) with varying radial thermal gradients with respect to the wafer. ) Submitted to an enhanced thermal stress test by mimicking the thermal cycle. The purpose of such a thermal stress test is to intentionally induce slippage on the wafer, and the mechanical strength of the SOI structure having an FZ handle substrate and the SOI wafer having a handle substrate prepared by the Czochralski (CZ) method. Was tested for robustness. The SOI structure prepared on a CZ wafer having interstitial oxygen Oi of ~ 3.5PPMA (new ASTM) was included as a control wafer. The UHR SOI structure with the FZ handle substrate showed a slip-free “window” with an induced thermal gradient that was considered appropriate for safe processing in the subsequent device manufacturing process flow. However, the window was not as wide as that for higher oxygen CZ wafers. See FIG. FIG. 6 compares an SOI multilayer slip window in which a handle substrate is made using the float zone method or the Czochralski method. Within the nitrogen range tested on such wafers, a slight improvement is seen at higher N concentrations.

Example 3. Resistivity Stability The Spread Resistivity Profile (SRP) measurement was performed at the end of the line to examine the resistivity stability of the wafer. The resistivity of an SOI wafer having a handle substrate prepared by the Czochralski (CZ) method containing oxygen forms a thermal double donor at a temperature in the range of 350 ° C. to 500 ° C., and the generation rate is about 450 ° C. It peaks strongly. This can lead to reduced resistivity on the handle wafers during the BEOL metal annealing process, which often falls within such temperature ranges. The SOI structure with the FZ handle substrate is virtually free of oxygen and is therefore unaffected by such resistivity changes. See FIG. 7. FIG. 7 shows that, as expected, the resistivity of the SOI structure with the FZ handle substrate remains the same before and after 1 hour annealing at 450 ° C. As an additional matter, since the FZ handle substrate is nitrogen-doped, confirm that the NO-related donors that would be expected with CZ silicon if oxygen and nitrogen were present were not formed. An annealing was performed at 600 ° C. for 1 hour.

Example 4. Radio frequency (RF) tests were performed on several SOI structures with harmonic strain FZ handle substrates. The top silicon layer of the SOI wafer was removed (removed through wet chemical etching) to create a coplanar waveguide structure directly on the BOX layer. Second harmonic distortion (HD2) and third harmonic distortion ( HD3 ) were measured for inputs up to 35 dBm. The device was tested over the diameter of the wafer to determine the radial uniformity of the results. The results were then compared to a similarly produced planar waveguide structure on an SOI wafer with a handle substrate prepared by the Czochralski method.

FIG. 8 shows the HD2 performance of our 1st and 2nd generation SOI wafers with handle substrates prepared by the Czochralski method. For such wafers, the HD2 performance at Pin = 15 dBm is −80 dBm and −90 dBm, respectively. On the other hand, HD2 with an SOI structure having an FZ handle substrate shows a dramatic improvement of 20 dBm to a value of -110 dBm at pin = 15 dBm. The difference in performance is caused by the difference in resistivity between typical CZ wafers and Z wafers. HD2 was measured at many sites on the wafer, but no strong radial variation of HD2 was observed. The SOI structure with the FZ handle substrate consistently performed better than the SOI wafer with the handle substrate prepared by the Czochralski method.

When referring to elements of this disclosure or aspects thereof, articles such as "is", "an", "the", and "said" are one or more. It is intended to mean many elements. The terms "comprising," "including," and "having" mean inclusive and other than those listed. It means that additional elements of can also exist.

Since various changes can be made to the above-mentioned matters without departing from the scope of the present disclosure, all the matters included in the above description and shown in the drawings are understood as exemplary and have a limited meaning. It is intended not to be understood by.

Claims (31)

It has a multi-layer structure
A single crystal silicon wafer handle substrate having two substantially parallel main surfaces, a peripheral edge, and a central surface, and one of the two substantially parallel main surfaces is the single crystal silicon. The single crystal silicon wafer handle substrate, which is the front surface of the wafer handle substrate and the other of the two substantially parallel main surfaces is the back surface of the single crystal silicon wafer handle substrate.
A trap-rich layer in interface contact with the front side surface of the single crystal silicon wafer handle substrate,
The dielectric layer in interface contact with the trap-rich layer and
A single crystal semiconductor device layer that is in interfacial contact with the dielectric layer,
Made up of
In the single crystal silicon wafer handle substrate, the peripheral edge connects the front side surface and the back side surface of the single crystal silicon wafer handle substrate, and the single crystal silicon wafer handle substrate said. The central surface is between the front side surface and the back side surface of the single crystal silicon wafer handle substrate.
The single crystal silicon wafer handle substrate has a bulk resistivity of at least about 7500 Ω · cm, an interstitial oxygen concentration of less than about 1 × 10 ¹⁶ atoms / cm ³ , and at least about 1 × 10 ¹³ atoms / cm ³ . Has a nitrogen concentration of
The single crystal silicon wafer handle substrate comprises a p-type dopant at a concentration of less than 1 × 10 ^{12 atoms} / cm3 , plus an oxygen thermal double donor, a new donor, an excess thermal donor or any combination thereof. The concentration of the donor is at least an order of magnitude lower than the concentration of the p-type dopant.
The trap-rich layer has a resistivity greater than about 1000 Ω · cm and has a resistivity greater than about 1000 Ω · cm.
The multilayer structure shows an HD2 value of a second harmonic distortion better than −90 dBm at a radio input of 15 dBm . The multilayer structure according to claim 1, wherein the single crystal silicon wafer handle substrate has a silicon wafer sliced from a single crystal silicon ingot grown by a float zone method. The multilayer structure according to claim 2, wherein the silicon wafer sliced from the single crystal silicon ingot grown by the float zone method has a diameter of at least about 150 mm. The multilayer structure according to claim 2, wherein the silicon wafer sliced from the single crystal silicon ingot grown by the float zone method has a diameter of at least about 200 mm. The multilayer structure according to any one of claims 1 to 4, wherein the single crystal silicon wafer handle substrate has a bulk resistivity of at least about 10,000 Ω · cm. The multilayer structure according to any one of claims 1 to 4, wherein the single crystal silicon wafer handle substrate has a bulk resistivity of at least about 15,000 Ω · cm. The multilayer structure according to any one of claims 1 to 4, wherein the single crystal silicon wafer handle substrate has a bulk resistivity of at least about 20000 Ω · cm. The multilayer structure according to any one of claims 1 to 4, wherein the single crystal silicon wafer handle substrate has a bulk resistivity of less than about 100,000 Ω · cm. The multilayer structure according to any one of claims 1 to 8 , wherein the single crystal silicon wafer handle substrate has an excess thermal donor concentration of less than 1 × 10 ¹¹ donors / ^cm3 . The multilayer structure according to any one of claims 1 to 8 , wherein the single crystal silicon wafer handle substrate has an excess thermal donor concentration of less than 5 × 10 ¹⁰ donors / ^cm3 . The single crystal silicon wafer handle substrate comprises p-type dopan at a concentration of less than 1 × 10 ¹¹ atoms / ^cm3 .
Further, the one according to any one of claims 1 to 10 , wherein the concentration of the oxygen thermal double donor, the new donor and the excess thermal donor or any combination thereof is at least an order of magnitude smaller than the concentration of the p-type dopant. Multi-layer structure. The multilayer structure according to any one of claims 1 to 11 , wherein the single crystal silicon wafer handle substrate has an interstitial oxygen concentration of about 1 × 10 ¹⁵ atoms / ^cm3 or less. The multilayer structure according to any one of claims 1 to 12 , wherein the single crystal silicon wafer handle substrate has a nitrogen concentration of at least about 1 × 10 ¹⁴ atoms / ^cm3 . The multilayer structure according to any one of claims 1 to 12 , wherein the single crystal silicon wafer handle substrate has a nitrogen concentration of about 3 × 10 ¹⁵ atoms / ^cm3 or less. The multilayer structure according to any one of claims 1 to 12 , wherein the single crystal silicon wafer handle substrate has a nitrogen concentration of about 1 × 10 ¹⁵ atoms / ^cm3 or less. The multilayer structure according to any one of claims 1 to 12 , wherein the single crystal silicon wafer handle substrate has a nitrogen concentration of about 7 × 10 ¹⁴ atoms / ^cm3 or less. The single crystal silicon wafer handle substrate has a nitrogen concentration between about 5 × 10 ¹⁴ atoms / cm ³ and about 2 × 10 ¹⁵ atoms / cm ³ , according to any one of claims 1 to 12 . Described multi-layer structure. The trap-rich layer comprises one or more polycrystalline semiconductor layers, each of which comprises a material selected from the group consisting of silicon, SiGe, SiC and Ge. The multilayer structure according to any one of claims 1 to 17 . The trap-rich layer comprises one or more amorphous semiconductor layers, each of which comprises a material selected from the group consisting of silicon, SiGe, SiC and Ge. The multilayer structure according to any one of claims 1 to 17 . The multilayer structure according to any one of claims 1 to 19 , wherein the trap-rich layer has a resistivity larger than about 3000 Ω · cm. The multilayer structure according to any one of claims 1 to 19 , wherein the trap-rich layer has a resistivity between about 2000 Ω · cm and about 10000 Ω · cm. The multilayer structure according to any one of claims 1 to 19 , wherein the trap-rich layer has a resistivity between about 3000 Ω · cm and about 10000 Ω · cm. The multilayer structure according to any one of claims 1 to 19 , wherein the trap-rich layer has a resistivity between about 3000 Ω · cm and about 5000 Ω · cm. The multilayer structure according to any one of claims 1 to 23 , wherein the trap-rich layer has a thickness between about 0.1 micrometer and about 50 micrometers. The multilayer structure according to any one of claims 1 to 23 , wherein the trap-rich layer has a thickness between about 0.1 micrometer and about 20 micrometers. The multilayer structure according to any one of claims 1 to 23 , wherein the trap-rich layer has a thickness between about 0.1 micrometer and about 10 micrometers. The multilayer structure according to any one of claims 1 to 23 , wherein the trap-rich layer has a thickness between about 0.5 micrometer and about 5 micrometers. A material whose dielectric layer is selected from the group consisting of silicon dioxide, silicon nitride, silicon oxynitride, hafnium oxide, titanium oxide, zirconium oxide, lanthanum oxide, barium oxide, aluminum oxide, aluminum nitride and any combination thereof. The multilayer structure according to any one of claims 1 to 27 , which comprises. The dielectric layer comprises a material selected from the group consisting of silicon dioxide, silicon nitride, silicon oxynitride, hafnium oxide, titanium oxide, zirconium oxide, lanthanum oxide, barium oxide and any combination thereof. The multilayer structure according to any one of 1 to 27 . The multilayer structure according to claim 1, wherein the multilayer structure exhibits an HD2 value of a second harmonic distortion better than -100 dBm at a radio input of 15 dBm. The multilayer structure according to claim 1, wherein the multilayer structure exhibits an HD2 value of a second harmonic distortion better than −110 dBm at a radio input of 15 dBm.