JPWO2019140246A5 - - Google Patents
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- JPWO2019140246A5 JPWO2019140246A5 JP2020538839A JP2020538839A JPWO2019140246A5 JP WO2019140246 A5 JPWO2019140246 A5 JP WO2019140246A5 JP 2020538839 A JP2020538839 A JP 2020538839A JP 2020538839 A JP2020538839 A JP 2020538839A JP WO2019140246 A5 JPWO2019140246 A5 JP WO2019140246A5
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Claims (7)
電流源と、
前記電流源に結合されるチャネル入力と、制御入力と、ＵＳＢ２．０通信システムにおける正のデータ線に結合される出力とを有する第１のスイッチと、
前記電流源に結合されるチャネル入力と、制御入力と、前記ＵＳＢ２．０通信システムにおける負のデータ線に結合される出力とを有する第２のスイッチと、
前記負のデータ線に結合される第１の入力と、前記正のデータ線に結合される第２の入力と、出力とを有する第１の電圧閾値コンパレータと、
前記負のデータ線に結合される第１の入力と、前記正のデータ線に結合される第２の入力と、出力とを有する第２の電圧閾値コンパレータと、
前記正のデータ線に結合される第１の入力と、前記負のデータ線に結合される第２の入力と、出力とを有する第３の電圧閾値コンパレータと、
前記正のデータ線に結合される第１の入力と、前記負のデータ線に結合される第２の入力と、出力とを有する第４の電圧閾値コンパレータと、
前記第１の電圧閾値コンパレータの出力に結合される第１の入力と、前記第２の電圧閾値コンパレータの出力に結合される第２の入力と、前記第１のスイッチの制御入力に結合される出力とを有する第１のロジック回路と、
前記第３の電圧閾値コンパレータの出力に結合される第１の入力と、前記第４の電圧閾値コンパレータの出力に結合される第２の入力と、前記第２のスイッチの制御入力に結合される出力とを有する第２のロジック回路と、
を含む、ＵＳＢ２．０システム。 It ’s a USB 2.0 system,
With a current source
A first switch having a channel input coupled to the current source, a control input, and an output coupled to a positive data line in a USB 2.0 communication system .
A second switch having a channel input coupled to the current source, a control input, and an output coupled to a negative data line in the USB 2.0 communication system .
A first voltage threshold comparator having a first input coupled to the negative data line, a second input coupled to the positive data line, and an output .
A second voltage threshold comparator having a first input coupled to the negative data line, a second input coupled to the positive data line, and an output .
A third voltage threshold comparator having a first input coupled to the positive data line, a second input coupled to the negative data line, and an output .
A fourth voltage threshold comparator having a first input coupled to the positive data line, a second input coupled to the negative data line, and an output .
A first input coupled to the output of the first voltage threshold comparator, a second input coupled to the output of the second voltage threshold comparator, and a control input of the first switch. A first logic circuit with an output and
A first input coupled to the output of the third voltage threshold comparator, a second input coupled to the output of the fourth voltage threshold comparator, and a control input of the second switch. A second logic circuit with an output and
Including USB 2.0 system.
電流源と、
前記電流源に結合される第１のチャネル端子と、ＵＳＢ２．０通信システムにおける正又は負のデータ線に結合される第２のチャネル端子と、制御端子とを有するトランジスタと、
前記負のデータ線に結合される第１の入力と、前記正のデータ線に結合される第２の入力と、前記トランジスタの制御端子に結合される出力とを有する電圧閾値コンパレータと、
を含む、ＵＳＢ２．０システム。 It ’s a USB 2.0 system,
With a current source
A transistor having a first channel terminal coupled to the current source, a second channel terminal coupled to a positive or negative data line in a USB 2.0 communication system , and a control terminal .
A voltage threshold comparator having a first input coupled to the negative data line, a second input coupled to the positive data line, and an output coupled to the control terminal of the transistor .
Including USB 2.0 system.
前記電圧閾値コンパレータが演算増幅器であり、前記電圧閾値コンパレータの第１の入力が非反転入力であり、前記第１の電圧閾値コンパレータの第２の入力が反転入力である、システム。 The USB 2.0 system according to claim 2.
A system in which the voltage threshold comparator is an operational amplifier, the first input of the voltage threshold comparator is a non-inverting input, and the second input of the first voltage threshold comparator is an inverting input.
前記電圧閾値コンパレータが第１の電圧閾値コンパレータであり、
前記システムが、
前記第１の電圧閾値コンパレータの出力に結合される第１の入力と、第２の入力と、前記トランジスタの制御端子に結合される出力とを有するロジック回路と、
前記負のデータ線に結合される第１の入力と、前記正のデータ線に結合される第２の入力と、前記ロジック回路の第２の入力に結合される出力とを有する第２の電圧閾値コンパレータと、
を更に含む、システム。 The USB 2.0 system according to claim 2.
The voltage threshold value comparator is a first voltage threshold value comparator, and the voltage threshold value comparator is a first voltage threshold value comparator.
The system
A logic circuit having a first input coupled to the output of the first voltage threshold comparator, a second input, and an output coupled to the control terminal of the transistor .
A second voltage having a first input coupled to the negative data line, a second input coupled to the positive data line, and an output coupled to the second input of the logic circuit. Threshold comparator and
Further includes the system.
前記トランジスタが第１のスイッチであり、前記第１のスイッチの出力が前記正のデータ線に結合され、前記電圧閾値コンパレータが第１のコンパレータであり、
前記システムが、
前記電流源に結合されるチャネル入力と、制御入力と、前記負のデータ線に結合される出力とを有する第２のスイッチと、
前記正のデータ線に結合される第１の入力と、前記負のデータ線に結合される第２の入力と、前記第２のスイッチの制御入力に結合される出力とを有する第２の電圧閾値コンパレータと、
を更に含む、システム。 The USB 2.0 system according to claim 2.
The transistor is the first switch, the output of the first switch is coupled to the positive data line, and the voltage threshold comparator is the first comparator.
The system
A second switch having a channel input coupled to the current source, a control input, and an output coupled to the negative data line.
A second voltage having a first input coupled to the positive data line, a second input coupled to the negative data line, and an output coupled to the control input of the second switch. Threshold comparator and
Further includes the system.
前記電流源に結合されるチャネル入力と、制御入力と、接地に結合される出力とを有する第３のスイッチと、
前記第１の電圧閾値コンパレータの出力に結合される第１の入力と、前記第２の電圧閾値コンパレータの出力に結合される第２の入力と、前記第３のスイッチの制御入力に結合される出力とを有するロジック回路と、
を更に含む、システム。 The USB 2.0 system according to claim 5.
A third switch having a channel input coupled to the current source, a control input, and an output coupled to ground .
A first input coupled to the output of the first voltage threshold comparator, a second input coupled to the output of the second voltage threshold comparator, and a control input of the third switch. A logic circuit with an output and
Further includes the system.
前記電圧閾値コンパレータの出力がバッファを介して前記トランジスタの制御端子に結合される、システム。 The USB 2.0 system according to claim 2.
A system in which the output of the voltage threshold comparator is coupled to the control terminal of the transistor via a buffer.
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201862616201P | 2018-01-11 | 2018-01-11 | |
| US62/616,201 | 2018-01-11 | ||
| US15/967,883 US10733129B2 (en) | 2018-01-11 | 2018-05-01 | Compensating DC loss in USB 2.0 high speed applications |
| US15/967,883 | 2018-05-01 | ||
| PCT/US2019/013271 WO2019140246A1 (en) | 2018-01-11 | 2019-01-11 | Compensating dc loss in usb 2.0 high speed applications |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2021510874A JP2021510874A (en) | 2021-04-30 |
| JPWO2019140246A5 true JPWO2019140246A5 (en) | 2022-01-19 |
| JP7393088B2 JP7393088B2 (en) | 2023-12-06 |
Family
ID=67139849
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2020538839A Active JP7393088B2 (en) | 2018-01-11 | 2019-01-11 | DC loss compensation in USB2.0 high speed applications |
Country Status (5)
| Country | Link |
|---|---|
| US (4) | US10733129B2 (en) |
| EP (1) | EP3738043A4 (en) |
| JP (1) | JP7393088B2 (en) |
| CN (2) | CN118606248A (en) |
| WO (1) | WO2019140246A1 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11843376B2 (en) * | 2021-05-12 | 2023-12-12 | Gowin Semiconductor Corporation | Methods and apparatus for providing a high-speed universal serial bus (USB) interface for a field-programmable gate array (FPGA) |
| US11689201B2 (en) | 2021-07-26 | 2023-06-27 | Qualcomm Incorporated | Universal serial bus (USB) host data switch with integrated equalizer |
| US11764672B1 (en) * | 2022-06-28 | 2023-09-19 | Diodes Incorporated | Signal boosting in serial interfaces |
Family Cites Families (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4524291A (en) * | 1983-01-06 | 1985-06-18 | Motorola, Inc. | Transition detector circuit |
| US6867631B1 (en) * | 2003-04-18 | 2005-03-15 | Apple Computer, Inc. | Synchronous frequency convertor for timebase signal generation |
| US7161392B2 (en) * | 2004-06-23 | 2007-01-09 | Teradyne, Inc. | Comparator feedback peak detector |
| JP4578316B2 (en) * | 2005-05-02 | 2010-11-10 | ザインエレクトロニクス株式会社 | Transmitter |
| US8185682B2 (en) * | 2007-06-01 | 2012-05-22 | International Business Machines Corporation | USB 2.0 bi-directional bus channel with boost circuitry |
| US7394281B1 (en) * | 2008-01-31 | 2008-07-01 | International Business Machines Corporation | Bi-directional universal serial bus booster circuit |
| US8269522B2 (en) * | 2009-12-14 | 2012-09-18 | St-Ericsson Sa | Active eye opener for current-source driven, high-speed serial links |
| JP5730520B2 (en) * | 2010-09-03 | 2015-06-10 | スパンション エルエルシー | Switching regulator |
| US8610456B2 (en) * | 2011-09-23 | 2013-12-17 | Qualcomm Incorporated | Load detecting impedance matching buffer |
| US9710411B2 (en) * | 2013-01-24 | 2017-07-18 | Texas Instruments Incorporated | Signal conditioner |
| US9800235B2 (en) | 2014-06-04 | 2017-10-24 | Texas Instruments Incorporated | Adaptive edge-rate boosting driver with programmable strength for signal conditioning |
| US9483435B2 (en) * | 2014-07-06 | 2016-11-01 | Freescale Semiconductor, Inc. | USB transceiver |
| US10002101B2 (en) * | 2015-03-06 | 2018-06-19 | Apple Inc. | Methods and apparatus for equalization of a high speed serial bus |
-
2018
- 2018-05-01 US US15/967,883 patent/US10733129B2/en active Active
-
2019
- 2019-01-11 EP EP19738227.8A patent/EP3738043A4/en active Pending
- 2019-01-11 CN CN202410757828.5A patent/CN118606248A/en active Pending
- 2019-01-11 CN CN201980016418.2A patent/CN111801660B/en active Active
- 2019-01-11 JP JP2020538839A patent/JP7393088B2/en active Active
- 2019-01-11 WO PCT/US2019/013271 patent/WO2019140246A1/en unknown
-
2020
- 2020-06-29 US US16/915,751 patent/US20200327082A1/en not_active Abandoned
-
2022
- 2022-10-19 US US17/968,978 patent/US12026115B2/en active Active
-
2024
- 2024-05-23 US US18/672,723 patent/US20240320178A1/en active Pending
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