JPWO2018220920A1 - Solid-state imaging device and method of manufacturing solid-state imaging device - Google Patents

Abstract

Provided is a technique capable of suppressing noise charges. Each of the unit pixels (10) includes a photodiode section (130), a first charge transfer section (103A), a charge holding section (131), a second charge transfer section (103B), and a charge discharge section. (180), semiconductors of a photodiode section (130), a first charge transfer section (103A), a charge holding section (131), a second charge transfer section (103B), and a charge discharge section (180). The entire substrate surface is covered with the second conductivity type semiconductor region.

Description

  The present invention relates to a solid-state imaging device and a method for manufacturing the solid-state imaging device.

  Conventionally, the signal charge from the photodiode section is completely transferred to the charge holding section, and then is completely transferred to the charge detection section for each row in order to realize a global shutter operation, further suppressing noise and afterimages. 2. Description of the Related Art A solid-state imaging device capable of obtaining a focused image is known (for example, see Patent Document 1).

Japanese Patent Publication No. JP-A-2004-111590 (published on Apr. 08, 2004)

  However, in the above-described related art, noise charges generated at the silicon / silicon oxide film interface level are accumulated in the charge holding unit during the charge holding period, and the image noise difference due to the difference in read timing for each row is reduced. There is a problem that causes.

  The present invention has been made in view of the above circumstances, and has as its object to provide a technique capable of suppressing noise charges.

  In order to solve the above-described problems, a solid-state imaging device according to the present invention is a solid-state imaging device including a plurality of unit pixels provided on a semiconductor substrate, wherein each of the unit pixels converts light into a signal charge. A photodiode portion that generates a charge by performing photoelectric conversion, a first charge transfer portion that is adjacent to the photodiode portion and is covered with a first gate electrode, and that is covered with the first gate electrode, A charge holding portion including a first conductivity type semiconductor region holding the charge transferred from the photodiode portion by the first charge transfer portion; and a second charge holding portion adjacent to the charge holding portion and covered by a second gate electrode portion. A charge transfer section, and a charge discharge section adjacent to the photodiode section at a portion different from the first gate electrode and covered with a third gate electrode, wherein the photodiode section and the first charge transfer section are provided. , Charge protection Parts, the second charge transfer section, and a structure in which a semiconductor surface of the charge discharging portion is covered by all the second conductivity type semiconductor region.

  According to one embodiment of the present invention, noise charge is suppressed.

FIG. 1 is a diagram illustrating a schematic configuration of a solid-state imaging device according to an embodiment of the present invention. FIG. 3 is an equivalent circuit diagram illustrating a configuration of a unit pixel in an imaging unit of the solid-state imaging device. FIG. 3 is a cross-sectional view of a unit pixel. FIG. 4 is a diagram illustrating a first step of a unit pixel manufacturing process. FIG. 8 is a diagram illustrating a second step of the unit pixel manufacturing process. FIG. 14 is a diagram illustrating a third step of the unit pixel manufacturing process. FIG. 14 is a diagram illustrating a fourth step of the unit pixel manufacturing process. It is a figure showing the 5th step of a manufacturing process of a unit pixel. It is a figure showing the 6th step of a manufacturing process of a unit pixel.

[Structure of solid-state imaging device 1]
Hereinafter, embodiments of the present invention will be described in detail. In the present embodiment, a CMOS imaging device, which is an example of a solid-state imaging device in which two different field-effect transistors of a P-type layer MOS and an N-type layer MOS are connected so as to complement each other, is used. explain.

  FIG. 1 is a diagram illustrating a schematic configuration of a solid-state imaging device 1 according to an embodiment of the present invention. The solid-state imaging device 1 includes a plurality of unit pixels 10 arranged in a plurality of rows and a plurality of columns.

  In addition, the solid-state imaging device 1 includes a vertical scanning circuit 3 that transfers signal charges from each unit pixel 10 in the vertical direction, and a horizontal scanning circuit 4 that transfers signal charges from each unit pixel in the horizontal direction. I have.

  Although FIG. 1 shows only a part of the rows and columns of the solid-state imaging device 1, tens to thousands of unit pixels 10 are arranged in each row and each example of the solid-state imaging device 1.

  The vertical scanning circuit 3 and the horizontal scanning circuit 4 are configured by, for example, a shift register, and perform scanning according to a pulse signal generated by a control circuit (not shown). A pulse signal for driving each unit pixel is sent to each unit pixel 10 via the vertical control line 5. In each unit pixel 10, the wiring through which the pulse signal flows may be arranged in either the row direction or the column direction.

  The output signal from each unit pixel 10 is transmitted from the vertical signal line 6 to the horizontal signal line 7, then driven by the horizontal selection signal from the horizontal scanning circuit 4, and supplied to the output buffer 8. Note that between the vertical signal line 6 and the horizontal signal line 7, a circuit for removing noise, an amplifier circuit, an analog-to-digital conversion circuit, and the like for an output signal from each unit pixel 10 are appropriately disposed. Is also good.

  FIG. 2 is an equivalent circuit diagram illustrating a configuration of the unit pixel 10 in the imaging unit 2 of the solid-state imaging device 1. As illustrated in FIG. 2, the unit pixel 10 includes a photodiode unit 130 that photoelectrically converts light into a signal charge and stores the charge generated by the photoelectric conversion in a first conductivity type (n-type) semiconductor region. .

  The photodiode section 130 includes a first conductivity type (n-type) semiconductor region and a second conductivity type (p-type) semiconductor region. The photodiode unit 130 converts incident light into electrons and holes in a depletion layer of the first conductivity type semiconductor region and the second conductivity type semiconductor region. In the photodiode unit 130, the generated electrons and holes are respectively accumulated in the semiconductor region of the first conductivity type, and the electrons are accumulated in the semiconductor region of the second conductivity type.

  In the following description, n-type and N represent the first conductivity type, and p-type and P represent the second conductivity type.

  Further, the unit pixel 10 includes a transfer gate section (first charge transfer section) 103A adjacent to the photodiode section 130 and a charge holding section 131 holding signal charges transferred from the photodiode section 130 by the transfer gate section 103A. And Further, the unit pixel 10 includes a readout selection transistor (second charge transfer unit) 103B adjacent to the charge holding unit 131 and a reset transistor 135.

  The unit pixel 10 includes a vertical selection transistor 140 having a gate connected to a vertical selection line 142, a floating diffusion 150 which is an example of a charge injection unit having a function of a charge storage unit, and a potential of the floating diffusion 150. An amplification transistor 160 having a source follower configuration, which is an example of a detection element for detecting a change.

  Further, the unit pixel 10 includes a pixel signal generation unit 170 having a floating diffusion amplifier (FDA) configuration including a floating diffusion 150 which is an example of a charge injection unit having a function of a charge accumulation unit, and a charge discharge unit 180. Have.

  Further, as shown in FIG. 2, the unit pixel 10 of the solid-state imaging device 1 includes a signal processing circuit 201 to which the output signal line 200 is connected for each column.

  The source of the transfer gate unit 103A is connected to the cathode of the photodiode unit 130. The drain of the read selection transistor 103B is connected to the floating diffusion 150 which is a storage unit.

  The charge discharging section 180 has a source section connected to the photodiode section 130, and discharges all charges accumulated in the photodiode section 130 to the drain section when the transistor is ON. In the charge discharging section 180, the potential of the channel section is set such that, of the signal charges generated by the photodiode section 130 when the transistor is off, excess charges that do not contribute to image formation are discharged.

  The reset transistor 135 has a source connected to the floating diffusion 150, a drain connected to the power supply VDD, and a gate to which a reset pulse is input. The reset transistor 135 is configured such that, when it becomes electrically conductive, the charge held in the floating diffusion 150 flows out to the power supply VDD via the reset transistor 135, and returns the potential state of the floating diffusion 150 to the initial level. ing.

  The amplification transistor 160 has a gate connected to the floating diffusion 150, a drain connected to the power supply VDD, and a source connected to the drain of the vertical selection transistor 140.

  The drain of the vertical selection transistor 140 is connected to the amplification transistor 160, the source is connected to the output signal line 200, and the gate is connected to the vertical selection line 142 to which the vertical selection signal is input.

  When the vertical selection transistor 140 of the unit pixel 10 is turned ON, the signal charge read to the floating diffusion 150 is amplified by the amplification transistor 160 and output to the output signal line 200.

Subsequently, a cross-sectional structure of the unit pixel 10 will be described with reference to FIG. FIG. 3 is a sectional view of the unit pixel 10. As shown in FIG. 3, the unit pixel 10 includes a p-type well (buried semiconductor layer) that is a p-type layer for forming a substrate-side potential barrier in a semiconductor substrate 100 (n ⁻ type Si substrate) made of silicon. 101 are formed.

On the p-type well 101, an n ⁻ -type well 132 that is an n-type layer and a first semiconductor well region 102 (p-type layer) adjacent to the n ⁻ -type well 132 are formed.

  On the other hand, as shown in FIG. 3, the substrate surface of the unit pixel 10 is entirely covered with the gate oxide film 119. Further, on the gate oxide film 119, a gate electrode (third gate electrode) 111 of the charge discharging unit 180, a gate electrode (first gate electrode) 109 common to the transfer gate unit 103A and the charge holding unit 131. , A gate electrode (second gate electrode) 110 of the read selection transistor 103B, and a gate electrode 112 of the reset transistor 135.

  The gate electrode (third gate electrode) 111 of the charge discharging unit 180, the gate electrode (first gate electrode) 109 common to the transfer gate unit 103A and the charge holding unit 131, and the gate electrode (first gate electrode) of the readout selection transistor 103B The two gate electrodes 110 and the gate electrode 112 of the reset transistor 135 are formed in a single-layer or two-layer structure of, for example, polysilicon. A read pulse is input to the gate electrode (second gate electrode) 110 of the read selection transistor 103B. A reset pulse is input to the gate electrode 112 of the reset transistor 135.

  In addition, a storage pulse is input to a gate electrode (first gate electrode) 109 common to the transfer gate unit 103A and the charge holding unit 131.

  Further, a global reset pulse is input to the gate electrode (third gate electrode) 111 of the charge discharging unit 180.

  The signal lines OFG, TRX, TRG, and RST are connected to the gate electrode 111, the gate electrode 109, the gate electrode 110, and the gate electrode 112, respectively.

As shown in the cross-sectional view of FIG. 3, the unit pixel 10 includes a photodiode section 130, a transfer gate section (first charge transfer section) 103A, a charge holding section 131, and a readout selection transistor (second A charge transfer unit) 103B, an amplifying transistor (not shown), a floating diffusion N ⁺ region 114, and a charge discharging unit 180 are formed.

The photodiode section 130 is formed to include a photodiode surface P ⁺ layer 113 and a photodiode N region 104. A gate overlap portion surface P ⁻ layer 105 is formed in a region adjacent to the photodiode surface P ⁺ layer 113 and on the surface side of the photodiode N region 104. The photodiode unit 130 converts incident light into electrons and holes in a depletion layer. In the photodiode section 130, electrons and holes generated in the depletion layer flow and are accumulated in the photodiode N region 104 and holes are accumulated in the photodiode surface P ⁺ layer 113.

  Between the photodiode section 130 and the readout selection transistor 103B, a transfer gate section (first charge transfer section) 103A and a charge holding section 131 are formed in a horizontal direction.

  The transfer gate section (first charge transfer section) 103A is adjacent to the photodiode section 130, and the above-described gate electrode 109 is provided on the surface of the substrate by, for example, polysilicon.

Further, as shown in FIG. 3, a gate lower surface P ⁻ layer 103 is formed in a region adjacent to the charge holding portion 131.

Further, as shown in FIG. 3, gate subsurface P ^- floating diffusion N ⁺ region 114 on the surface side adjacent to the layer 103 is formed. Further, as shown in FIG. 3, a drain portion N ⁺ region 115 is also formed at a position adjacent to the n region of the reset transistor 135.

The floating diffusion 150 is provided with the floating diffusion N ⁺ region 114 as shown in FIG.

  Further, as shown in FIG. 3, the unit pixel 10 is separated from other pixel units by the element isolation region 120.

  The charge holding unit 131 has a function of holding the charge transferred from the photodiode unit 130 via the transfer gate unit (first charge transfer unit) 103A in the first conductivity type semiconductor region. The gate electrode 109 described above is provided on the substrate surface of the charge holding unit 131, for example, by polysilicon.

  The charge holding portion 131 includes, from the substrate surface side, a charge holding portion surface P layer 108 that is a second conductivity type semiconductor region, a charge holding portion N region 107 that is a first conductivity type semiconductor region, and a second conductivity type semiconductor region. Has a three-layer structure with the P layer 106 below the charge holding portion. In other words, the charge holding section 131 is formed by the charge holding section front P layer 108 from the substrate front side (gate oxide film 119 side) and by the charge holding section lower P layer 106 from the substrate back side (in other words, the semiconductor substrate 100 side). It is formed with the charge holding portion N region 107 sandwiched therebetween.

  In this manner, by surrounding the upper and lower portions of the charge holding portion N region 107 holding charges with the charge holding portion surface P layer 108 and the charge holding portion lower P layer 106, depletion as a neutral region of the P layer and the N layer is achieved. Layer elongation is suppressed. Accordingly, the junction capacitance between the P layer and the N layer increases, and the amount of charge that can be held by the charge holding unit 131 can be efficiently increased.

  In addition, the unit pixel 10 inputs a global reset pulse to the gate electrode 111 of the charge discharging unit 180 to discharge all the charges of the photodiode units 130 of all the pixels at the same time (global reset operation). After exposure, a signal pulse accumulated in the photodiode unit 130 is input to a gate electrode (first gate electrode, first transfer gate electrode) 109 with a storage pulse to be simultaneously transferred to the charge holding unit 131 for all pixels. Accordingly, it is possible to realize a global shutter function which is an electronic shutter function that does not cause a difference in accumulation time.

As described above, the substrate surface of the unit pixel 10 is covered with the second conductivity type (p-type) semiconductor regions 103, 105, 113, and 108 except for the drain portion N ⁺ region 115 and the floating diffusion N ⁺ region 114. As described above, the unit pixel 10 includes the gate electrode (third gate electrode) 111, the photodiode unit 130, the gate electrode (first gate electrode, first transfer gate electrode) 109, the charge holding unit 131, and A gate oxide film 119 connected to the gate electrode (second gate electrode) 110 is formed.

  According to these configurations, noise electrons generated inside the unit pixel 10 are trapped by holes existing in the second conductivity type (p-type) semiconductor regions 103, 105, 113, and 108. Therefore, it is possible to prevent noise electrons generated inside the unit pixel 10 from being mixed into the pixel output.

Further, the impurity concentration of the photodiode surface P ⁺ layer 113, which is the second conductivity type semiconductor surface region of the photodiode portion 130, is set to the concentration C1, and the charge holding portion surface P layer, which is the second conductivity type semiconductor surface region of the charge holding portion 131. The impurity concentration of the readout transistor 103B immediately below the gate electrode (second gate electrode) 110 is set to the concentration C3 (more generally, the semiconductor surface other than the photodiode portion 130 and the charge holding portion 131). The relationship between the concentrations C1, C2, and C3 in the case where the concentration is C3) of the second conductivity type semiconductor surface region is such that C1>C2> C3. According to this configuration, the hole concentration distribution required for each part depends on the structure of each part, such as the presence or absence of a gate electrode and the presence or absence of an N-type semiconductor region immediately below the gate oxide film 119 on the semiconductor surface. It is formed. With the above operation, it is possible to suppress a change in noise for each row due to a shift in read timing from the charge holding unit.

[About the manufacturing method of the unit pixel 10]
Next, a method of manufacturing the unit pixel 10 will be described with reference to FIGS. The method of manufacturing the unit pixel 10 described below is executed by, for example, the semiconductor manufacturing apparatus according to the present embodiment including an ion implantation unit that performs ion implantation and a photomask setting unit that sets a photomask.

The unit pixel 10 has a p-type well 101 formed on a semiconductor substrate 100, an n ⁻ -type well 132 on the p-type well 101, and a first semiconductor well region 102 adjacent to the n ⁻ -type well 132. Are formed, and a photoresist 190 is arranged as a photomask on the surface of the semiconductor whose entire surface is covered with the gate oxide film 119, and ion implantation is performed into the n ⁻ -type well 132 and the first semiconductor well region 102. It is formed by doing.

(First step)
FIG. 4 is a diagram illustrating a first step of the manufacturing process of the unit pixel 10. In this first step, first, the semiconductor surface outside the region where the photodiode section 130 is to be formed is covered with the photoresist 190A. Then, ions are implanted into the n ⁻ -type well 132 to form the photodiode N region 104 and the gate overlap portion surface P ⁻ layer 105 using the same photomask.

(2nd step)
Next, in the second step of the manufacturing process of the unit pixel 10 shown in FIG. 5, an ion implantation process for forming the charge holding portion 131 is performed. First, the semiconductor surface outside the region where the charge holding portion 131 is to be formed is covered with the photoresist 190B. Then, ion implantation is performed on the first semiconductor well region 102.

  This ion implantation step includes a first step of forming the charge holding portion lower P layer 106 by ion implantation, and a second step of forming the charge holding portion N region 107 by ion implantation after the first step. And a third step of forming the charge holding portion surface P layer 108 by ion implantation after the second step. The first step, the second step, and the third step include: This is performed using the same photomask.

(3rd step)
After the formation of the charge holding portion 131, in the third step of the manufacturing process of the unit pixel 10 shown in FIG. 6, the gate electrode 112 of the reset transistor 135 is covered with the photoresist 190C to form the gate electrode 112 of the reset transistor 135. Is performed outside the region to be ionized. Thereby, a gate lower surface P ⁻ layer 103 is formed. The gate lower surface P ⁻ layer 103 is configured as the above-described transfer gate unit 103A, readout selection transistor 103B, and charge discharging unit 180.

(4th step)
After forming the gate lower surface P ⁻ layer 103, in the fourth step of the manufacturing process of the unit pixel 10 shown in FIG. 7, the area outside the region where the reset transistor 135 is formed is covered with the photoresist 190 </ b> D and ion implantation is performed. A transistor N region 116 is formed.

  In the unit pixel 10, a gate electrode 111, a gate electrode 109, a gate electrode 110, and a gate electrode 112 are formed (not shown) by gate oxidation, polysilicon deposition, gate electrode photolithography, and dry etching processes.

(5th step)
Subsequently, in a fifth step of the manufacturing process of the unit pixel 10 illustrated in FIG. 8, the photoresist 190 </ b> E and the gate electrode 111, the gate electrode 109, the gate electrode 110, and the gate electrode 112 are used as a photomask, Implantation is performed to form a photodiode surface P ⁺ layer 113 of the photodiode section 130.

(6th step)
After the formation of the photodiode portion 130, the photoresist 190F, the gate electrode 111, the gate electrode 109, and the gate electrode 110 are photomasked in the sixth step of the manufacturing process of the unit pixel 10 shown in FIG. Is used to form a floating diffusion N ⁺ region 114 and an element isolation region (rain portion N ⁺ region) 120.

[Appendix]
By the way, when the positional relationship between the charge holding portion N region 107, the charge holding portion lower P layer 106, and the charge holding portion surface P layer 108 is shifted, the transfer to the readout selection transistor (second charge transfer portion) 103B is performed. Characteristics deteriorate rapidly. According to the above-described manufacturing method, the charge holding unit lower P layer 106, the charge holding unit N region 107, and the charge holding unit surface P layer 108 are formed by ion implantation using the same photoresist as a photomask. As a result, the formation regions of the charge holding portion lower P layer 106, the charge holding portion N region 107, and the charge holding portion surface P layer 108 are not shifted from each other, and it is possible to avoid deterioration in transfer characteristics due to manufacturing variations. .

[Summary]
The solid-state imaging device 1 according to the first aspect of the present invention is a solid-state imaging device 1 including a plurality of unit pixels 10 provided on a semiconductor substrate 100. Each of the unit pixels 10 converts light into a signal charge. A photodiode section 130 that generates charges by conversion, a transfer gate section (first charge transfer section) 103A adjacent to the photodiode section and covered with a first gate electrode 109, and the first gate The charge including the charge holding portion N region (first conductivity type semiconductor region) 107 which is covered with the electrode 109 and holds the charge transferred from the photodiode portion 130 by the transfer gate portion (first charge transfer portion) 103A. The holding unit 131, the readout selection transistor 103B adjacent to the charge holding unit 131 and covered with the second gate electrode 110, and the photodiode unit 130 A charge discharging portion 180 adjacent to a portion different from the first gate electrode and covered with a third gate electrode 111; the photodiode portion 130, the transfer gate portion 103A, the charge holding portion 131, and the readout selection transistor 103B. , And the semiconductor surface of the charge discharging section 180 are all covered with the second conductivity type semiconductor regions 103, 105, 113, and 108.

  According to the above configuration, after all the charges of the photodiode units 130 of all the pixels are simultaneously discharged through the charge discharging unit 180 (global reset operation), the signal charges accumulated in the photodiode units 130 for a certain period are changed to the first gate. By simultaneously transferring all pixels to the charge holding unit 131 by the electrode 109, a global shutter function, which is an electronic shutter function without causing a difference in accumulation time, can be realized.

  Further, according to this configuration, noise electrons generated inside the unit pixel 10 are trapped by holes existing in the second conductivity type (p-type) semiconductor regions 103, 105, 113, and 108. Therefore, it is possible to prevent noise electrons generated inside the unit pixel 10 from being mixed into the pixel output.

  In addition, the charge holding portion N region (first conductivity type semiconductor region) 107 includes second conductivity type semiconductor regions (charge holding portion surface P layer, charge holding portion lower P layer) 108 and 106 from the substrate front side and the substrate back side. May be interposed. According to this configuration, in the charge holding unit 131, since the N layer holding the charge is sandwiched between the P layers, the elongation of the depletion layer, which is the neutral region of the P layer and the N layer, is suppressed. Accordingly, the junction capacitance between the P layer and the N layer increases, and the amount of charge that can be held by the charge holding unit 131 can be efficiently increased.

The solid-state imaging device 1 according to the second aspect of the present invention is the same as the first aspect, except that the concentration C1 of the photodiode surface P ⁺ layer 113 of the photodiode unit 130 and the charge holding unit surface P layer 108 of the charge holding unit 131 are different. And the relationship between the concentration C2 of the P layer 106 under the charge holding portion and the concentration C3 of the P layer on the other semiconductor surface may be C1>C2> C3.

  According to the above configuration, the structure of each part depends on the presence or absence of the gate electrode and whether or not the N-type semiconductor region exists immediately below the second conductivity type (p-type) semiconductor regions 103, 105, 113, and 108. Thus, a necessary hole concentration distribution is formed in each portion. Thus, it is possible to suppress a change in noise for each row due to a shift in the read timing from the charge storage unit 131.

  The present invention is not limited to the embodiments described above, and various modifications are possible within the scope shown in the claims, and embodiments obtained by appropriately combining technical means disclosed in different embodiments. Is also included in the technical scope of the present invention. Furthermore, new technical features can be formed by combining the technical means disclosed in each embodiment.

Reference Signs List 1 solid-state imaging device 2 imaging unit 3 vertical scanning circuit 4 horizontal scanning circuit 5 vertical control line 6 vertical signal line 7 horizontal signal line 8 output buffer 10 unit pixel 135 reset transistor 140 vertical selection transistor 100 semiconductor substrate 101 p-type well 102 1 semiconductor well region 103 Gate lower surface P ⁻ layer 103A Transfer gate section (first charge transfer section)
103B Readout selection transistor (second charge transfer unit)
104 Photodiode N region 105 Gate overlap portion surface P ⁻ layer 106 Charge holding portion lower P layer 107 Charge holding portion N region 108 Charge holding portion surface P layer 109 Gate electrode (first gate electrode)
110 gate electrode (second gate electrode)
111 Gate electrode (third gate electrode)
112 gate electrode 113 photodiode surface ^{P +} layer 114 floating diffusion ^{N +} region 115 drain region ^{N +} region 116 reset transistor N region 119 a gate oxide film 120 isolation regions 130 photodiode 131 charge holding unit 132 n ^- -type well 135 resets Transistor 140 Vertical selection transistor 142 Vertical selection line 150 Floating diffusion 160 Amplification transistor 170 Pixel signal generator 180 Charge discharger 190, 190A, 190B, 190C, 190D, 190E, 190F Photoresist 200 Output signal line 201 Signal processing circuit Vdd Power supply

Claims (3)

A solid-state imaging device including a plurality of unit pixels provided on a semiconductor substrate,
Each of the unit pixels is
A photodiode unit that generates a charge by photoelectrically converting light into a signal charge;
A first charge transfer unit adjacent to the photodiode unit and covered with a first gate electrode;
A charge holding unit that includes a first conductivity type semiconductor region that is covered with the first gate electrode and holds the charge transferred from the photodiode unit by the first charge transfer unit;
A second charge transfer unit adjacent to the charge holding unit and covered with a second gate electrode;
A charge discharging portion adjacent to the photodiode portion at a portion different from the first gate electrode and covered with a third gate electrode;
With
The semiconductor surfaces of the photodiode section, the first charge transfer section, the charge holding section, the second charge transfer section, and the charge discharge section are all covered with a second conductivity type semiconductor region. Solid-state imaging device.   The concentration C1 of the second conductivity type semiconductor surface region of the photodiode portion, the concentration C2 of the second conductivity type semiconductor surface region of the charge holding portion, and the concentration C3 of the other semiconductor surface region of the second conductivity type. 2. The solid-state imaging device according to claim 1, wherein the relationship of density with respect to C1> C2> C3. A plurality of unit pixels provided on the semiconductor substrate,
Each of the unit pixels is
A photodiode unit that generates a charge by photoelectrically converting light into a signal charge;
A first charge transfer unit adjacent to the photodiode unit and covered with a first gate electrode;
Manufacturing of a solid-state imaging device comprising: a charge holding portion that is covered with the first gate electrode and holds a charge transferred from the photodiode portion by the first charge transfer portion in a first conductivity type semiconductor region. The method
In the ion implantation step of forming the charge holding unit,
A first step of forming a second conductivity type semiconductor region by ion implantation;
A second step of forming a first conductivity type semiconductor region by ion implantation;
A third step of forming a second conductivity type semiconductor region by ion implantation.
2. The method according to claim 1, wherein the first step, the second step, and the third step are performed using the same photomask. 3.

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