JPWO2018055667A1 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JPWO2018055667A1
JPWO2018055667A1 JP2018540511A JP2018540511A JPWO2018055667A1 JP WO2018055667 A1 JPWO2018055667 A1 JP WO2018055667A1 JP 2018540511 A JP2018540511 A JP 2018540511A JP 2018540511 A JP2018540511 A JP 2018540511A JP WO2018055667 A1 JPWO2018055667 A1 JP WO2018055667A1
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case housing
heat sink
semiconductor device
outer peripheral
semiconductor chip
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JP6699742B2 (en
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林田　幸昌
幸昌 林田
大介 大宅
大介 大宅
貴之 松本
貴之 松本
龍太郎 伊達
龍太郎 伊達
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Abstract

放熱板（１）上に配線基板（２）が設けられている。配線基板（２）上に半導体チップ（８）が設けられている。配線基板（２）及び半導体チップ（８）を囲うように放熱板（１）上にケース筐体（１０）が設けられている。ケース筐体（１０）の下面と放熱板（１）の上面外周部が接着剤（１１）により接着されている。封止材（１３）がケース筐体（１０）内に設けられ、配線基板（２）及び半導体チップ（８）を覆っている。ケース筐体（１０）の下面と放熱板（１）の上面外周部の少なくとも一方に段差部（１６，１７）が設けられている。放熱板（１）の側面とケース筐体（１０）の外側面が同一面である。  A wiring board (2) is provided on the heat sink (1). A semiconductor chip (8) is provided on the wiring board (2). A case housing (10) is provided on the heat sink (1) so as to surround the wiring board (2) and the semiconductor chip (8). The lower surface of the case housing (10) and the outer periphery of the upper surface of the heat radiating plate (1) are bonded together with an adhesive (11). A sealing material (13) is provided in the case housing (10) and covers the wiring board (2) and the semiconductor chip (8). Step portions (16, 17) are provided on at least one of the lower surface of the case housing (10) and the outer peripheral portion of the upper surface of the heat sink (1). The side surface of the heat sink (1) and the outer surface of the case housing (10) are the same surface.

Description

本発明は、例えば電鉄用機器又は自動車用機器のモータ制御に使用される半導体装置に関する。   The present invention relates to a semiconductor device used for motor control of, for example, electric railway equipment or automobile equipment.

ケース筐体内にゲルが充填される半導体装置では、ケース筐体と放熱板は接着剤により接着される。これにより、接合部からの水分侵入又はゲルの外部への漏れを防止することができる。ただし、放熱板に塗布した接着剤の一定のボリュームを確保するため、ケース筐体が放熱板を囲っていた。従って、放熱板のサイズをケース筐体より小さくしなければならなかった。また、ケース筐体側にも放熱板側にも段差部が無い場合（例えば、特許文献１参照）、接着剤を押しつぶして接着剤自身のボリュームが無くなり、シール機能を損なう懸念があった。   In a semiconductor device in which gel is filled in a case housing, the case housing and the heat sink are bonded by an adhesive. Thereby, it is possible to prevent moisture intrusion from the joint portion or leakage of the gel to the outside. However, in order to secure a certain volume of the adhesive applied to the heat sink, the case housing surrounds the heat sink. Therefore, the size of the heat sink has to be smaller than the case housing. Further, when there is no step portion on the case housing side or the heat sink side (see, for example, Patent Document 1), there is a concern that the adhesive is crushed and the volume of the adhesive itself is lost, and the sealing function is impaired.

日本特開平１１−２１４６１２号公報Japanese Unexamined Patent Publication No. 11-214612

放熱板のサイズをケース筐体より小さくすると、熱拡散範囲を拡大できない。また、放熱板サイズの制限により放熱機能を最大限に発揮できない。また、近年、半導体装置の縮小化が進むにあたり、放熱板サイズが制限されたままでは、冷却器へ取り付けるための取付穴径を放熱板上に確保することが困難になってきている。   If the size of the heat sink is smaller than the case housing, the heat diffusion range cannot be expanded. Also, the heat dissipation function cannot be maximized due to the limitation of the heat sink size. In recent years, as the size of semiconductor devices has been reduced, it has become difficult to secure a mounting hole diameter for mounting on a cooler on the heat sink if the size of the heat sink is limited.

本発明は、上述のような課題を解決するためになされたもので、その目的はシール効果を担保し、接触熱抵抗を低減させ、冷却設計の尤度を向上させることができる半導体装置を得るものである。   The present invention has been made to solve the above-described problems, and its object is to obtain a semiconductor device capable of ensuring a sealing effect, reducing contact thermal resistance, and improving the likelihood of cooling design. Is.

本発明に係る半導体装置は、放熱板と、前記放熱板上に設けられた配線基板と、前記配線基板上に設けられた半導体チップと、前記配線基板及び前記半導体チップを囲うように前記放熱板上に設けられたケース筐体と、前記ケース筐体の下面と前記放熱板の上面外周部を接着する接着剤と、前記ケース筐体内に充填され、前記配線基板及び前記半導体チップを覆う封止材とを備え、前記ケース筐体の前記下面と前記放熱板の前記上面外周部の少なくとも一方に段差部が設けられ、前記放熱板の側面と前記ケース筐体の外側面が同一面である。   The semiconductor device according to the present invention includes a heat sink, a wiring board provided on the heat sink, a semiconductor chip provided on the wiring board, and the heat sink so as to surround the wiring board and the semiconductor chip. A case housing provided on top, an adhesive that adheres the lower surface of the case housing and the outer periphery of the upper surface of the heat sink, and a seal that fills the case housing and covers the wiring substrate and the semiconductor chip A step portion is provided on at least one of the lower surface of the case housing and the outer peripheral portion of the upper surface of the heat radiating plate, and the side surface of the heat radiating plate and the outer surface of the case housing are the same surface.

本発明では、ケース筐体の下面と放熱板の上面外周部の少なくとも一方に段差部が設けられている。これにより、ケース筐体と放熱板を接着する接着剤の一定ボリュームを確保してシール効果を担保することができる。また、放熱板の側面とケース筐体の外側面が同一面である。これにより、放熱範囲を拡大することができるため、接触熱抵抗を低減させ、冷却設計の尤度を向上させることができる。   In this invention, the level | step-difference part is provided in at least one of the lower surface of a case housing | casing and the upper surface outer peripheral part of a heat sink. Thereby, a fixed volume of the adhesive that bonds the case housing and the heat sink can be secured to ensure a sealing effect. Moreover, the side surface of the heat sink and the outer surface of the case housing are the same surface. Thereby, since the thermal radiation range can be expanded, contact thermal resistance can be reduced and the likelihood of cooling design can be improved.

本発明の実施の形態１に係る半導体装置を示す断面図である。It is sectional drawing which shows the semiconductor device which concerns on Embodiment 1 of this invention. 本発明の実施の形態１に係る半導体装置を示す下面図である。1 is a bottom view showing a semiconductor device according to a first embodiment of the present invention. 本発明の実施の形態１に係る半導体装置のケース筐体と放熱板の接着部を拡大した断面図である。It is sectional drawing to which the adhesion part of the case housing | casing and heat sink of the semiconductor device which concerns on Embodiment 1 of this invention was expanded. 比較例に係る半導体装置のケース筐体と放熱板の接着部を拡大した断面図である。It is sectional drawing to which the adhesion part of the case housing | casing and heat sink of the semiconductor device which concerns on a comparative example was expanded. 本発明の実施の形態２に係る半導体装置のケース筐体と放熱板の接着部を拡大した断面図である。It is sectional drawing to which the adhesion part of the case housing | casing and heat sink of the semiconductor device which concerns on Embodiment 2 of this invention was expanded. 本発明の実施の形態３に係る半導体装置のケース筐体と放熱板の接着部を拡大した断面図である。It is sectional drawing to which the adhesion part of the case housing | casing and heat sink of the semiconductor device which concerns on Embodiment 3 of this invention was expanded. 本発明の実施の形態４に係る半導体装置のケース筐体と放熱板の接着部を拡大した断面図である。It is sectional drawing to which the adhesion part of the case housing | casing and heat sink of the semiconductor device which concerns on Embodiment 4 of this invention was expanded. 本発明の実施の形態５に係る半導体装置のケース筐体と放熱板の接着部を拡大した断面図である。It is sectional drawing to which the adhesion part of the case housing | casing and heat sink of the semiconductor device which concerns on Embodiment 5 of this invention was expanded. 本発明の実施の形態６に係る半導体装置のケース筐体と放熱板の接着部を拡大した断面図である。It is sectional drawing to which the adhesion part of the case housing | casing and heat sink of the semiconductor device which concerns on Embodiment 6 of this invention was expanded. 本発明の実施の形態７に係る半導体装置のケース筐体と放熱板の接着部を拡大した断面図である。It is sectional drawing to which the adhesion part of the case housing | casing and heat sink of the semiconductor device which concerns on Embodiment 7 of this invention was expanded. 本発明の実施の形態８に係る半導体装置のケース筐体と放熱板の接着部を拡大した断面図である。It is sectional drawing to which the adhesion part of the case housing | casing and heat sink of the semiconductor device which concerns on Embodiment 8 of this invention was expanded.

本発明の実施の形態に係る半導体装置について図面を参照して説明する。同じ又は対応する構成要素には同じ符号を付し、説明の繰り返しを省略する場合がある。   A semiconductor device according to an embodiment of the present invention will be described with reference to the drawings. The same or corresponding components are denoted by the same reference numerals, and repeated description may be omitted.

実施の形態１．
図１は、本発明の実施の形態１に係る半導体装置を示す断面図である。放熱板１上に配線基板２が設けられている。放熱板１は、Ｃｕ、ＡｌＳｉＣ又はＡｌなどの金属である。配線基板２は、セラミック基板などの下面に下面電極３が設けられ、上面に上面電極４，５，６が設けられたものである。配線基板２の下面電極３ははんだ７により放熱板１に接合されている。配線基板２の上面電極４上に半導体チップ８が設けられている。半導体チップ８の上面電極はワイヤ９により配線基板２の上面電極５に接続されている。Embodiment 1 FIG.
FIG. 1 is a cross-sectional view showing a semiconductor device according to the first embodiment of the present invention. A wiring board 2 is provided on the heat sink 1. The heat sink 1 is a metal such as Cu, AlSiC, or Al. The wiring board 2 is such that a lower surface electrode 3 is provided on the lower surface of a ceramic substrate or the like, and upper surface electrodes 4, 5, 6 are provided on the upper surface. The lower surface electrode 3 of the wiring board 2 is joined to the heat sink 1 by solder 7. A semiconductor chip 8 is provided on the upper surface electrode 4 of the wiring board 2. The upper surface electrode of the semiconductor chip 8 is connected to the upper surface electrode 5 of the wiring substrate 2 by a wire 9.

ケース筐体１０が配線基板２及び半導体チップ８を囲うように放熱板１上に設けられている。ケース筐体１０は、例えばＰＰＳ、ＰＢＴ又はＰＥＴ＋ＰＢＴなどのエンジニアリングプラスチックである。ケース筐体１０の下面と放熱板１の上面外周部が接着剤１１により接着されている。接着剤１１は、シリコーン系又はエポキシ系の材料などである。   A case housing 10 is provided on the heat sink 1 so as to surround the wiring substrate 2 and the semiconductor chip 8. The case housing 10 is an engineering plastic such as PPS, PBT, or PET + PBT. The lower surface of the case housing 10 and the outer peripheral portion of the upper surface of the heat radiating plate 1 are bonded with an adhesive 11. The adhesive 11 is a silicone-based or epoxy-based material.

電極端子１２が配線基板２の上面電極６に接続され、ケース筐体１０の外部に引き出されている。絶縁性を担保するために、シリコーンゲルなどの絶縁性の封止材１３がケース筐体１０内に充填され、配線基板２及び半導体チップ８などを覆っている。   The electrode terminal 12 is connected to the upper surface electrode 6 of the wiring board 2 and is drawn out of the case housing 10. In order to ensure insulation, an insulating sealing material 13 such as silicone gel is filled in the case housing 10 to cover the wiring substrate 2 and the semiconductor chip 8.

図２は、本発明の実施の形態１に係る半導体装置を示す下面図である。放熱板１の外周部には、冷却器への取付穴１４とケース取付ネジ穴１５が設けられている。   FIG. 2 is a bottom view showing the semiconductor device according to the first embodiment of the present invention. A mounting hole 14 for a cooler and a case mounting screw hole 15 are provided on the outer peripheral portion of the heat radiating plate 1.

図３は、本発明の実施の形態１に係る半導体装置のケース筐体と放熱板の接着部を拡大した断面図である。段差部として、ケース筐体１０の下面の外側部分に凸部１６が設けられ、放熱板１の上面外周部には凸部１６に対向する位置に凹部１７が設けられている。放熱板１の側面とケース筐体１０の外側面が同一面である。   FIG. 3 is an enlarged cross-sectional view of the bonding portion between the case housing and the heat sink of the semiconductor device according to the first embodiment of the present invention. As the stepped portion, a convex portion 16 is provided on the outer portion of the lower surface of the case housing 10, and a concave portion 17 is provided on the outer peripheral portion of the upper surface of the heat radiating plate 1 at a position facing the convex portion 16. The side surface of the heat sink 1 and the outer surface of the case housing 10 are the same surface.

金属融解により放熱板１を成型する場合は、金型又は鋳型に溝又は突起を設けて鋳造時に放熱板１の外周部を追加加工する。また、放熱板１の表面形状を成型した後に凹部１７を形成する場合は、凹部１７となる部分以外をレジストマスクで覆い、エッチングにより凹部１７を成形する。レジスト・エッチングを行わない場合は、プレスにより凹部１７を成形してもよい。   When the heat sink 1 is molded by metal melting, grooves or protrusions are provided in a mold or a mold, and the outer peripheral portion of the heat sink 1 is additionally processed during casting. Moreover, when forming the recessed part 17 after shape | molding the surface shape of the heat sink 1, the part other than the part used as the recessed part 17 is covered with a resist mask, and the recessed part 17 is shape | molded by etching. When resist etching is not performed, the concave portion 17 may be formed by pressing.

続いて、本実施の形態の効果を比較例と比較して説明する。図４は、比較例に係る半導体装置のケース筐体と放熱板の接着部を拡大した断面図である。比較例では、放熱板１に塗布した接着剤１１の一定のボリュームを確保するため、ケース筐体１０が放熱板１を囲っている。従って、放熱板１のサイズをケース筐体１０より小さくしなければならない。   Subsequently, the effect of the present embodiment will be described in comparison with a comparative example. FIG. 4 is an enlarged cross-sectional view of a bonding portion between a case housing and a heat sink of a semiconductor device according to a comparative example. In the comparative example, the case housing 10 surrounds the heat sink 1 in order to secure a certain volume of the adhesive 11 applied to the heat sink 1. Therefore, the size of the heat sink 1 must be smaller than the case housing 10.

一方、本実施の形態では、段差部として、ケース筐体１０の下面の外側部分に凸部１６が設けられ、放熱板１の上面外周部には凸部１６に対向する位置に凹部１７が設けられている。これにより、ケース筐体１０と放熱板１を接着する接着剤１１の一定ボリュームを確保してシール効果を担保することができる。また、放熱板１の側面とケース筐体１０の外側面が同一面である。これにより、放熱範囲を拡大することができるため、冷却器への取付穴１４とケース取付ネジ穴１５を確保するためのクリアランス範囲が拡大される。このため、接触熱抵抗を低減させ、冷却設計の尤度を向上させることができる。この結果、半導体装置の寿命設計が有利になる。   On the other hand, in the present embodiment, as the stepped portion, a convex portion 16 is provided on the outer portion of the lower surface of the case housing 10, and a concave portion 17 is provided on the outer peripheral portion of the upper surface of the heat sink 1 at a position facing the convex portion 16. It has been. Thereby, the fixed effect of the adhesive 11 which adhere | attaches the case housing | casing 10 and the heat sink 1 can be ensured, and the sealing effect can be ensured. Moreover, the side surface of the heat sink 1 and the outer surface of the case housing 10 are the same surface. Thereby, since the heat radiation range can be expanded, the clearance range for securing the mounting hole 14 and the case mounting screw hole 15 to the cooler is expanded. For this reason, contact thermal resistance can be reduced and the likelihood of cooling design can be improved. As a result, the life design of the semiconductor device becomes advantageous.

実施の形態２．
図５は、本発明の実施の形態２に係る半導体装置のケース筐体と放熱板の接着部を拡大した断面図である。実施の形態１の構成に加えて、ケース筐体１０の凸部１６に溝１８が設けられ、放熱板１の凹部１７には溝１８に対向する位置に突起１９が設けられている。Embodiment 2. FIG.
FIG. 5 is an enlarged cross-sectional view of the bonding portion between the case housing and the heat sink of the semiconductor device according to the second embodiment of the present invention. In addition to the configuration of the first embodiment, a groove 18 is provided in the convex portion 16 of the case housing 10, and a protrusion 19 is provided in the concave portion 17 of the heat radiating plate 1 at a position facing the groove 18.

実施の形態１と同様の効果に加え、ケース筐体１０の溝１８と放熱板１の突起１９がかみ合うことにより、封止材１３の漏れと接着剤１１のはみ出しを防ぐことができるため、生産性が向上する。また、ケース筐体１０の位置決め精度も向上する。   In addition to the effects similar to those of the first embodiment, the groove 18 of the case housing 10 and the protrusion 19 of the heat sink 1 are engaged with each other, so that leakage of the sealing material 13 and protrusion of the adhesive 11 can be prevented. Improves. Further, the positioning accuracy of the case housing 10 is also improved.

実施の形態３．
図６は、本発明の実施の形態３に係る半導体装置のケース筐体と放熱板の接着部を拡大した断面図である。段差部として、ケース筐体１０の下面の外側部分に凹部２０が設けられ、放熱板１の上面外周部には凹部２０に対向する位置に凸部２１が設けられている。実施の形態１と同様の効果に加え、放熱板１の凸部２１により封止材１３の漏れと接着剤１１のはみ出しを防ぐことができるため、生産性が向上する。Embodiment 3 FIG.
FIG. 6 is an enlarged cross-sectional view of the bonding portion between the case housing and the heat sink of the semiconductor device according to the third embodiment of the present invention. As the stepped portion, a concave portion 20 is provided on the outer portion of the lower surface of the case housing 10, and a convex portion 21 is provided on the outer peripheral portion of the upper surface of the radiator plate 1 at a position facing the concave portion 20. In addition to the effects similar to those of the first embodiment, the convex portion 21 of the heat radiating plate 1 can prevent the sealing material 13 from leaking and the adhesive 11 from protruding, so that productivity is improved.

実施の形態４．
図７は、本発明の実施の形態４に係る半導体装置のケース筐体と放熱板の接着部を拡大した断面図である。段差部として、ケース筐体１０の下面の中央部分に凸部１６が設けられ、放熱板１の上面外周部には凸部１６に対向する位置に凹部１７が設けられている。これにより、実施の形態３と同様の効果に加え、接着剤１１の塗布量を低減することができる。また、ケース筐体１０の位置決め精度も向上する。Embodiment 4 FIG.
FIG. 7 is an enlarged cross-sectional view of a bonding portion between a case housing and a heat sink of a semiconductor device according to Embodiment 4 of the present invention. As the stepped portion, a convex portion 16 is provided at the central portion of the lower surface of the case housing 10, and a concave portion 17 is provided on the outer peripheral portion of the upper surface of the heat radiating plate 1 at a position facing the convex portion 16. Thereby, in addition to the effect similar to Embodiment 3, the application quantity of the adhesive agent 11 can be reduced. Further, the positioning accuracy of the case housing 10 is also improved.

実施の形態５．
図８は、本発明の実施の形態５に係る半導体装置のケース筐体と放熱板の接着部を拡大した断面図である。段差部として、ケース筐体１０の下面の外側部分に凸部１６が設けられ、ケース筐体１０の下面の内側部分に面取り２２が設けられている。面取り２２に作用する表面張力により接着剤１１がケース筐体１０側に引き上げられるため、接着剤１１のボリュームを確保でき、シール効果が向上する。また、放熱板１を加工する必要がなくなるため、コストを削減し、放熱性を向上することができる。その他、実施の形態１と同様の効果を得ることができる。Embodiment 5. FIG.
FIG. 8 is an enlarged cross-sectional view of the bonding portion between the case housing and the heat sink of the semiconductor device according to the fifth embodiment of the present invention. As the stepped portion, a convex portion 16 is provided on the outer portion of the lower surface of the case housing 10, and a chamfer 22 is provided on the inner portion of the lower surface of the case housing 10. Since the adhesive 11 is pulled up toward the case housing 10 by the surface tension acting on the chamfer 22, the volume of the adhesive 11 can be secured and the sealing effect is improved. Moreover, since it becomes unnecessary to process the heat sink 1, cost can be reduced and heat dissipation can be improved. In addition, the same effects as those of the first embodiment can be obtained.

実施の形態６．
図９は、本発明の実施の形態６に係る半導体装置のケース筐体と放熱板の接着部を拡大した断面図である。実施の形態５の構成に加えて、段差部として、放熱板１の上面外周部に凹部１７が設けられている。また、ケース筐体１０の下面にエアだまり２３が設けられている。実施の形態５と同様の効果に加え、接着剤１１内の気泡２４が装置内部でなくエアだまり２３に抜けることで絶縁性を向上させることができる。Embodiment 6 FIG.
FIG. 9 is an enlarged cross-sectional view of the bonding portion between the case housing and the heat sink of the semiconductor device according to the sixth embodiment of the present invention. In addition to the configuration of the fifth embodiment, a recess 17 is provided on the outer peripheral portion of the upper surface of the radiator plate 1 as a stepped portion. An air reservoir 23 is provided on the lower surface of the case housing 10. In addition to the same effects as those of the fifth embodiment, the insulating property can be improved by allowing the bubbles 24 in the adhesive 11 to escape to the air pool 23 instead of the inside of the apparatus.

実施の形態７．
図１０は、本発明の実施の形態７に係る半導体装置のケース筐体と放熱板の接着部を拡大した断面図である。段差部として、ケース筐体１０の下面の内側部分に凸部１６が設けられている。また、ケース筐体１０の下面の外側部分に面取り２２が設けられている。接着剤１１内の気泡２４が装置外側に抜けることで絶縁性を向上させることができる。その他、実施の形態１と同様の効果を得ることができる。Embodiment 7 FIG.
FIG. 10 is an enlarged cross-sectional view of a bonding portion between a case housing and a heat sink of a semiconductor device according to Embodiment 7 of the present invention. As the stepped portion, a convex portion 16 is provided on an inner portion of the lower surface of the case housing 10. Further, a chamfer 22 is provided on the outer portion of the lower surface of the case housing 10. The insulating property can be improved by the bubbles 24 in the adhesive 11 being removed to the outside of the apparatus. In addition, the same effects as those of the first embodiment can be obtained.

実施の形態８．
図１１は、本発明の実施の形態８に係る半導体装置のケース筐体と放熱板の接着部を拡大した断面図である。実施の形態７の構成に加えて、ケース筐体１０の下面にエアだまり２３が設けられている。接着剤１１内の気泡２４が装置外側又はエアだまり２３に抜けることで絶縁性を向上させることができる。Embodiment 8 FIG.
FIG. 11 is an enlarged cross-sectional view of a bonding portion between a case housing and a heat sink of a semiconductor device according to Embodiment 8 of the present invention. In addition to the configuration of the seventh embodiment, an air reservoir 23 is provided on the lower surface of the case housing 10. The insulating property can be improved by the bubbles 24 in the adhesive 11 being removed from the outside of the apparatus or into the air pool 23.

なお、半導体チップ８は珪素によって形成されたＩＧＢＴ又はダイオードであるが、ワイドバンドギャップ半導体によって形成されたＳｉＣ−ＭＯＳＦＥＴ又はＳｉＣ−ＳＢＤでもよい。ワイドバンドギャップ半導体は、例えば、炭化珪素、窒化ガリウム系材料、又はダイヤモンドである。このようなワイドバンドギャップ半導体によって形成されたパワー半導体素子は、耐電圧性や許容電流密度が高いため、小型化できる。この小型化された素子を用いることで、この素子を組み込んだ半導体装置も小型化できる。また、素子の耐熱性が高いため、ヒートシンクの放熱フィンを小型化でき、水冷部を空冷化できるので、半導体装置を更に小型化できる。また、素子の電力損失が低く高効率であるため、半導体装置を高効率化できる。   The semiconductor chip 8 is an IGBT or a diode formed of silicon, but may be a SiC-MOSFET or SiC-SBD formed of a wide band gap semiconductor. The wide band gap semiconductor is, for example, silicon carbide, a gallium nitride-based material, or diamond. A power semiconductor element formed of such a wide band gap semiconductor can be miniaturized because of its high voltage resistance and allowable current density. By using this miniaturized element, a semiconductor device incorporating this element can also be miniaturized. Moreover, since the heat resistance of the element is high, the heat dissipating fins of the heat sink can be reduced in size and the water cooling part can be cooled in the air, so that the semiconductor device can be further reduced in size. In addition, since the power loss of the element is low and the efficiency is high, the semiconductor device can be highly efficient.

１ 放熱板、２ 配線基板、８ 半導体チップ、１０ ケース筐体、１１ 接着剤、１３ 封止材、１６，２１ 凸部、１７，２０ 凹部、１８ 溝、１９ 突起、２２ 面取り、２３ エアだまり DESCRIPTION OF SYMBOLS 1 Heat sink, 2 Wiring board, 8 Semiconductor chip, 10 Case housing, 11 Adhesive, 13 Sealing material, 16, 21 Convex part, 17, 20 Concave part, 18 groove | channel, 19 Protrusion, 22 Chamfer, 23 Air accumulation

Claims (10)

放熱板と、
前記放熱板上に設けられた配線基板と、
前記配線基板上に設けられた半導体チップと、
前記配線基板及び前記半導体チップを囲うように前記放熱板上に設けられたケース筐体と、
前記ケース筐体の下面と前記放熱板の上面外周部を接着する接着剤と、
前記ケース筐体内に充填され、前記配線基板及び前記半導体チップを覆う封止材とを備え、
前記ケース筐体の前記下面と前記放熱板の前記上面外周部の少なくとも一方に段差部が設けられ、
前記放熱板の側面と前記ケース筐体の外側面が同一面であることを特徴とする半導体装置。A heat sink,
A wiring board provided on the heat sink;
A semiconductor chip provided on the wiring board;
A case housing provided on the heat sink so as to surround the wiring substrate and the semiconductor chip;
An adhesive that adheres the lower surface of the case housing and the outer periphery of the upper surface of the heat sink;
A sealing material that fills the case housing and covers the wiring substrate and the semiconductor chip;
A step portion is provided on at least one of the lower surface of the case housing and the outer peripheral portion of the upper surface of the heat sink,
The side surface of the said heat sink and the outer surface of the said case housing | casing are the same surfaces, The semiconductor device characterized by the above-mentioned. 前記段差部として、前記ケース筐体の前記下面の外側部分に凸部が設けられ、前記放熱板の前記上面外周部には前記凸部に対向する位置に凹部が設けられていることを特徴とする請求項１に記載の半導体装置。   As the stepped portion, a convex portion is provided on an outer portion of the lower surface of the case housing, and a concave portion is provided on the outer peripheral portion of the upper surface of the heat radiating plate at a position facing the convex portion. The semiconductor device according to claim 1. 前記段差部として、前記ケース筐体の前記凸部に溝が設けられ、前記放熱板の前記凹部には前記溝に対向する位置に突起が設けられていることを特徴とする請求項２に記載の半導体装置。   The groove is provided in the convex part of the case casing as the stepped part, and a protrusion is provided in the concave part of the heat radiating plate at a position facing the groove. Semiconductor device. 前記段差部として、前記ケース筐体の前記下面の外側部分に凹部が設けられ、前記放熱板の前記上面外周部には前記凹部に対向する位置に凸部が設けられていることを特徴とする請求項１に記載の半導体装置。   As the stepped portion, a concave portion is provided on an outer portion of the lower surface of the case housing, and a convex portion is provided on the outer peripheral portion of the upper surface of the heat radiating plate at a position facing the concave portion. The semiconductor device according to claim 1. 前記段差部として、前記ケース筐体の前記下面の中央部分に凸部が設けられ、前記放熱板の前記上面外周部には前記凸部に対向する位置に凹部が設けられていることを特徴とする請求項１に記載の半導体装置。   As the stepped portion, a convex portion is provided at a central portion of the lower surface of the case housing, and a concave portion is provided at a position facing the convex portion on the outer peripheral portion of the upper surface of the heat sink. The semiconductor device according to claim 1. 前記段差部として、前記ケース筐体の前記下面の外側部分に凸部が設けられ、
前記ケース筐体の前記下面の内側部分に面取りが設けられていることを特徴とする請求項１に記載の半導体装置。As the step portion, a convex portion is provided on the outer portion of the lower surface of the case housing,
The semiconductor device according to claim 1, wherein a chamfer is provided in an inner portion of the lower surface of the case housing. 前記段差部として、前記放熱板の前記上面外周部に凹部が設けられ、
前記ケース筐体の前記下面にエアだまりが設けられていることを特徴とする請求項６に記載の半導体装置。As the stepped portion, a recess is provided in the outer peripheral portion of the upper surface of the heat sink,
The semiconductor device according to claim 6, wherein an air reservoir is provided on the lower surface of the case housing. 前記段差部として、前記ケース筐体の前記下面の内側部分に凸部が設けられ、
前記ケース筐体の前記下面の外側部分に面取りが設けられていることを特徴とする請求項１に記載の半導体装置。As the stepped portion, a convex portion is provided on an inner portion of the lower surface of the case housing,
The semiconductor device according to claim 1, wherein a chamfer is provided on an outer portion of the lower surface of the case housing. 前記ケース筐体の前記下面にエアだまりが設けられていることを特徴とする請求項８に記載の半導体装置。   The semiconductor device according to claim 8, wherein an air reservoir is provided on the lower surface of the case housing. 前記半導体チップはワイドバンドギャップ半導体によって形成されていることを特徴とする請求項１〜９の何れか１項に記載の半導体装置。   The semiconductor device according to claim 1, wherein the semiconductor chip is formed of a wide band gap semiconductor.
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Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6696480B2 (en) * 2017-03-22 2020-05-20 株式会社デンソー Semiconductor device
CN111211059B (en) * 2018-11-22 2023-07-04 矽品精密工业股份有限公司 Electronic package, manufacturing method thereof and heat dissipation part
CN113906663A (en) * 2019-06-21 2022-01-07 日立安斯泰莫株式会社 Power conversion device
US20220278004A1 (en) * 2019-11-27 2022-09-01 Mitsubishi Electric Corporation Semiconductor module
JP2021111669A (en) * 2020-01-08 2021-08-02 三菱電機株式会社 Semiconductor device and electric power conversion system
WO2021230621A1 (en) * 2020-05-15 2021-11-18 주식회사 아모센스 Power module
JP7351278B2 (en) 2020-09-18 2023-09-27 三菱電機株式会社 semiconductor equipment

Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS553617A (en) * 1978-06-21 1980-01-11 Hitachi Ltd Metallic base for hybrid integrated circuit
JPS63100842U (en) * 1986-12-19 1988-06-30
JPH0470752U (en) * 1990-10-30 1992-06-23
JPH05166950A (en) * 1991-12-16 1993-07-02 Fuji Electric Co Ltd Package structure of semiconductor device
JPH06268102A (en) * 1993-01-13 1994-09-22 Fuji Electric Co Ltd Resin sealed semiconductor device
JPH11186463A (en) * 1997-12-22 1999-07-09 Sanyo Electric Co Ltd Hybrid integrated circuit device
JP2000323593A (en) * 1999-05-06 2000-11-24 Yazaki Corp Semiconductor device
JP2005146198A (en) * 2003-11-19 2005-06-09 Shin Etsu Polymer Co Ltd Method for assembling electronics case and silicone adhesive used for the same
JP2005322784A (en) * 2004-05-10 2005-11-17 Mitsubishi Electric Corp Semiconductor device for electric power
WO2016016985A1 (en) * 2014-07-31 2016-02-04 三菱電機株式会社 Semiconductor device
JP2016178220A (en) * 2015-03-20 2016-10-06 富士電機株式会社 Semiconductor module and resin case

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6072239A (en) * 1995-11-08 2000-06-06 Fujitsu Limited Device having resin package with projections
JP3483720B2 (en) * 1997-02-12 2004-01-06 沖電気工業株式会社 Semiconductor device
JPH11214612A (en) 1998-01-26 1999-08-06 Hitachi Ltd Power semiconductor module
JPH11307658A (en) 1998-04-22 1999-11-05 Fuji Electric Co Ltd Package of semiconductor device
JP2000311959A (en) * 1999-04-27 2000-11-07 Sanyo Electric Co Ltd Semiconductor device and manufacture of the same
JP2002134674A (en) * 2000-10-20 2002-05-10 Hitachi Ltd Semiconductor device and its manufacturing method
JP3865055B2 (en) * 2001-12-28 2007-01-10 セイコーエプソン株式会社 Manufacturing method of semiconductor device
JP4029843B2 (en) * 2004-01-19 2008-01-09 豊田合成株式会社 Light emitting device
JP2005095977A (en) * 2003-08-26 2005-04-14 Sanyo Electric Co Ltd Circuit device
JP4765016B2 (en) 2004-04-06 2011-09-07 富士電機株式会社 Manufacturing method of semiconductor device
CN100565948C (en) * 2005-06-30 2009-12-02 松下电工株式会社 Light-emitting device
JP2008171936A (en) * 2007-01-10 2008-07-24 Toyota Motor Corp Cooling structure
JP2010074117A (en) * 2007-12-07 2010-04-02 Panasonic Electric Works Co Ltd Light emitting device
JP2010251614A (en) 2009-04-17 2010-11-04 Toyota Motor Corp Semiconductor module and method of manufacturing the same
JP2012244093A (en) * 2011-05-24 2012-12-10 Renesas Electronics Corp Manufacturing method of semiconductor device
JP5724710B2 (en) * 2011-07-21 2015-05-27 三菱電機株式会社 Plate stack type cooler
JP5823798B2 (en) * 2011-09-29 2015-11-25 ルネサスエレクトロニクス株式会社 Semiconductor device
JP2017181624A (en) * 2016-03-29 2017-10-05 セイコーエプソン株式会社 Electro-optical device, electro-optical unit, and electronic apparatus
JP6848802B2 (en) * 2017-10-11 2021-03-24 三菱電機株式会社 Semiconductor device

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS553617A (en) * 1978-06-21 1980-01-11 Hitachi Ltd Metallic base for hybrid integrated circuit
JPS63100842U (en) * 1986-12-19 1988-06-30
JPH0470752U (en) * 1990-10-30 1992-06-23
JPH05166950A (en) * 1991-12-16 1993-07-02 Fuji Electric Co Ltd Package structure of semiconductor device
JPH06268102A (en) * 1993-01-13 1994-09-22 Fuji Electric Co Ltd Resin sealed semiconductor device
JPH11186463A (en) * 1997-12-22 1999-07-09 Sanyo Electric Co Ltd Hybrid integrated circuit device
JP2000323593A (en) * 1999-05-06 2000-11-24 Yazaki Corp Semiconductor device
JP2005146198A (en) * 2003-11-19 2005-06-09 Shin Etsu Polymer Co Ltd Method for assembling electronics case and silicone adhesive used for the same
JP2005322784A (en) * 2004-05-10 2005-11-17 Mitsubishi Electric Corp Semiconductor device for electric power
WO2016016985A1 (en) * 2014-07-31 2016-02-04 三菱電機株式会社 Semiconductor device
JP2016178220A (en) * 2015-03-20 2016-10-06 富士電機株式会社 Semiconductor module and resin case

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