JPWO2017115209A1 - Oxide and production method thereof - Google Patents

Abstract

An oxide that can be used for a semiconductor of a transistor or the like is manufactured. After supplying a sputtering gas containing oxygen or / and a rare gas to the deposition chamber, a potential difference is applied between the target and the substrate to generate plasma having ions of the deposition gas. The ions are accelerated toward the target by the potential difference, and the ions of the deposition gas bombard the target, so that the atoms or the atomic aggregates constituting the target are separated from the target, and the atoms and the atomic aggregates are formed on the substrate. Depositing and causing migration by heating the substrate to form a plurality of tabular clusters, and atoms and atomic aggregates enter the region between the clusters, and the atoms and atomic aggregates are flat plates. Crystal region with a strain formed in the connecting part by connecting regions between the clusters by laterally growing the region between the cluster-like clusters It is formed.

Description

  One embodiment of the present invention relates to an oxide and a manufacturing method thereof.

  Alternatively, the present invention relates to an oxide, a transistor, a semiconductor device, and a manufacturing method thereof, for example. Alternatively, the present invention relates to an oxide, a display device, a light-emitting device, a lighting device, a power storage device, a memory device, an imaging device, a processor, and an electronic device, for example. Alternatively, the present invention relates to a method for manufacturing an oxide, a display device, a liquid crystal display device, a light-emitting device, a memory device, and an electronic device. Alternatively, the present invention relates to a driving method of a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a memory device, or an electronic device.

  Note that one embodiment of the present invention is not limited to the above technical field. The technical field of one embodiment of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, a manufacture, or a composition (composition of matter).

  Note that in this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. A display device, a light-emitting device, a lighting device, an imaging device, an electro-optical device, a semiconductor circuit, and an electronic device may include a semiconductor device.

  A technique for forming a transistor using a semiconductor over a substrate having an insulating surface has attracted attention. The transistor is widely applied to semiconductor devices such as integrated circuits and display devices. Silicon is known as a semiconductor applicable to a transistor.

  As silicon used for a semiconductor of a transistor, amorphous silicon and polycrystalline silicon are selectively used depending on the application. For example, when applied to a transistor included in a large display device, it is preferable to use amorphous silicon in which a technique for forming a film over a large-area substrate is established. On the other hand, when applied to a transistor included in a high-function display device in which a driver circuit and a pixel circuit are formed over the same substrate, it is preferable to use polycrystalline silicon that can manufacture a transistor with high field-effect mobility. It is. A method of forming polycrystalline silicon by performing heat treatment at high temperature or laser light treatment on amorphous silicon is known.

  In recent years, development of transistors using an oxide semiconductor (typically, In—Ga—Zn oxide) has been activated.

  An oxide semiconductor has a long history, and in 1988, it was disclosed that a crystalline In—Ga—Zn oxide was used for a semiconductor element (see Patent Document 1). In 1995, a transistor using an oxide semiconductor was invented, and its electrical characteristics were disclosed (see Patent Document 2).

  In 2013, a group reported that an amorphous In—Ga—Zn oxide has an unstable structure in which crystallization is accelerated by irradiation with an electron beam (see Non-Patent Document 1). ). In addition, it was reported that the amorphous In—Ga—Zn oxide produced by them could not be confirmed by the high resolution transmission electron microscope.

  In 2014, a transistor using a crystalline In—Ga—Zn oxide having superior electrical characteristics and reliability compared to a transistor using an amorphous In—Ga—Zn oxide was reported ( (See Non-Patent Document 2, Non-Patent Document 3, and Non-Patent Document 4.) Here, it has been reported that an In—Ga—Zn oxide having a CAAC-OS (C-Axis-Aligned Crystalline Oxide Semiconductor) does not clearly confirm a crystal grain boundary.

JP-A-63-239117 11-505377

T.A. Kamiya, Koji Kimoto, Naoki Ohashi, Katsumi Abe, Yuichiro Hanyu, Hideya Kumomi, Hideo Hosono: Proceedings of The 5th International Dispense 5 S. Yamazaki, H .; Suzuki, K .; Inoue, K .; Kato, T .; Hirohashi, K .; Okazaki, and N.K. Kimizuka: Japan Journal of Applied. Physics 2014 vol. 53 04ED18 S. Yamazaki, T .; Hirohashi, M .; Takahashi, S .; Adachi, M .; Tsubuku, J. et al. Koezuka, K .; Okazaki, Y .; Kanzaki, H .; Matsukizono, S .; Kaneko, S .; Mori, and T.M. Matsuo: Journal of the Society for Information Display, 2014, Volume 22, issue 1, p. 55-p. 67 S. Yamazaki: The Electrochemical Society Transactions, 2014, vol. 64 (10), pp155-164

  Another object is to provide a method for manufacturing an oxide that can be used for a semiconductor of a transistor or the like. In particular, an object is to provide a method for manufacturing an oxide with few defects such as a crystal grain boundary.

  Another object is to provide a semiconductor device using an oxide for a semiconductor. Another object is to provide a module including a semiconductor device using an oxide as a semiconductor. Another object is to provide an electronic device including a semiconductor device using an oxide as a semiconductor or a module including a semiconductor device using an oxide as a semiconductor.

  An object is to provide a transistor with favorable electrical characteristics. Another object is to provide a transistor with stable electrical characteristics. Another object is to provide a transistor having high frequency characteristics. Another object is to provide a transistor with a low off-state current. Another object is to provide a semiconductor device including the transistor. Another object is to provide a module including the semiconductor device. Another object is to provide an electronic device including the semiconductor device or the module.

  Note that the description of these problems does not disturb the existence of other problems. Note that one embodiment of the present invention does not have to solve all of these problems. Issues other than these will be apparent from the description of the specification, drawings, claims, etc., and other issues can be extracted from the descriptions of the specification, drawings, claims, etc. It is.

  One embodiment of the present invention is a method for forming an oxide film by a sputtering method using a film formation chamber, a target provided in the film formation chamber, and a substrate. Alternatively, after supplying a film forming gas containing a rare gas, a potential difference is applied between the target and the substrate, thereby generating plasma having film forming gas ions in the vicinity of the target. The ions are accelerated toward the target by the potential difference, and the accelerated deposition gas ions bombard the target, so that the atoms constituting the target and the aggregate of atoms constituting the target are separated from the target, and the atoms and atoms The aggregate is deposited on the substrate, undergoes migration by heating the substrate, forms a plurality of plate-like clusters, and forms one of the plurality of plate-like clusters. An atom and a collection of atoms enter a region between another one of the plurality of plate-like clusters, and the atoms and the collection of atoms grow laterally in the region between the plate-like clusters. As a result, a connecting portion is formed between one of the plurality of flat-plate clusters and another one of the plurality of flat-plate clusters, and a strained crystal structure is formed in the connecting portion. This is a feature of producing an oxide.

  Another embodiment of the present invention is the above method for manufacturing an oxide, in which flat clusters are stacked to form a thin film structure. In another embodiment of the present invention, the silicon oxide contained in the target is preferably less than 2% by weight. In another embodiment of the present invention, the number of water molecules contained in the deposition gas is preferably 0.5 sccm or less. Another embodiment of the present invention is that no other flat cluster is formed in a region between one of the plurality of flat clusters and another one of the plurality of flat clusters. Is preferred.

  In another embodiment of the present invention, the target preferably includes indium, zinc, an element M (the element M is aluminum, gallium, yttrium, or tin), and oxygen. In another embodiment of the present invention, the target may be a mixture target including indium oxide, an oxide of element M, and zinc oxide. In another embodiment of the present invention, it is preferable that the flat cluster has a surface formed of an element M, zinc, and oxygen on the surface. In another embodiment of the present invention, the flat cluster preferably has a surface perpendicular to the c-axis.

  A method for manufacturing an oxide which can be applied to a semiconductor of a transistor or the like can be provided. In particular, a method for manufacturing an oxide with few defects such as a crystal grain boundary can be provided.

  Alternatively, a semiconductor device using an oxide for a semiconductor can be provided. Alternatively, a module including a semiconductor device using an oxide as a semiconductor can be provided. Alternatively, an electronic device including a semiconductor device using an oxide as a semiconductor or a module including a semiconductor device using an oxide as a semiconductor can be provided.

  A transistor with favorable electrical characteristics can be provided. Alternatively, a transistor with stable electric characteristics can be provided. Alternatively, a transistor having high frequency characteristics can be provided. Alternatively, a transistor with low off-state current can be provided. Alternatively, a semiconductor device including the transistor can be provided. Alternatively, a module including the semiconductor device can be provided. Alternatively, an electronic device including the semiconductor device or the module can be provided.

  Note that the description of these effects does not disturb the existence of other effects. Note that one embodiment of the present invention need not have all of these effects. It should be noted that the effects other than these are naturally obvious from the description of the specification, drawings, claims, etc., and it is possible to extract the other effects from the descriptions of the specification, drawings, claims, etc. It is.

Diagram for explaining the crystal and nanoclusters InMZnO _4. 8A and 8B illustrate a method for forming a CAAC-OS. 8A and 8B illustrate a method for forming a CAAC-OS. 8A and 8B illustrate a method for forming a CAAC-OS. 8A and 8B illustrate a method for forming a CAAC-OS. FIG. 6 illustrates a structure of a CAAC-OS. The figure explaining the position where particle | grains adhere to a nanocluster. The figure explaining the position where particle | grains adhere to a nanocluster. 4A and 4B illustrate a crystal model of InGaZnO ₄ . 4A and 4B illustrate a crystal model of InGaZnO ₄ . 4A and 4B illustrate a crystal model of InGaZnO ₄ . 4A and 4B illustrate a crystal model of InGaZnO ₄ . The figure explaining the range of atomic ratio of the oxide which concerns on this invention. The band figure in the laminated structure of an oxide. FIG. 9 illustrates a sputtering apparatus. FIG. 9 illustrates a sputtering apparatus. FIG. 9 illustrates a sputtering apparatus. FIG. 9 illustrates a sputtering apparatus. The top view which shows an example of the film-forming apparatus. Sectional drawing which shows an example of the film-forming apparatus. FIGS. 4A to 4C illustrate structural analysis by XRD of a CAAC-OS and a single crystal oxide semiconductor, and a diagram illustrating a limited-field electron diffraction pattern of the CAAC-OS. FIGS. The cross-sectional TEM image of nc-OS. Sectional TEM image of CAAC-OS. The cross-sectional TEM image of nc-OS. Sectional TEM image of CAAC-OS. The figure which shows distribution of the size of a nanocluster. A planar TEM image of CAAC-OS and an image analysis image thereof. A planar TEM image of CAAC-OS and an image analysis image thereof. The figure explaining the method to derive | lead-out the rotation angle of a hexagon. A planar TEM image of CAAC-OS and an image analysis image thereof. A planar TEM image of CAAC-OS and an image analysis image thereof. A planar TEM image of CAAC-OS and an image analysis image thereof. A planar TEM image of CAAC-OS and an image analysis image thereof. Image analysis image of planar TEM image of CAAC-OS. The figure which shows the image-analysis image and deformation rate of the plane TEM image of CAAC-OS. The figure explaining the creation method of a Voronoi diagram. The Voronoi diagram and the figure which shows the ratio of the shape of a Voronoi area | region. Planar TEM image of CAAC-OS. The figure which shows the electron diffraction pattern of CAAC-OS. The figure which shows the electron diffraction pattern of CAAC-OS. Sectional TEM image of CAAC-OS. The figure which shows the electron diffraction pattern of CAAC-OS. The figure which shows the electron diffraction pattern of CAAC-OS. 4A to 4C illustrate a top view and a cross-sectional structure of a transistor according to an embodiment. 4A to 4C illustrate a top view and a cross-sectional structure of a transistor according to an embodiment. 4A to 4C illustrate a top view and a cross-sectional structure of a transistor according to an embodiment. 4A to 4C illustrate a top view and a cross-sectional structure of a transistor according to an embodiment. 4A to 4C illustrate a top view and a cross-sectional structure of a transistor according to an embodiment. 4A to 4C illustrate a top view and a cross-sectional structure of a transistor according to an embodiment. 4A to 4C illustrate a top view and a cross-sectional structure of a transistor according to an embodiment. 10A to 10D illustrate an example of a method for manufacturing a transistor according to an embodiment. 10A to 10D illustrate an example of a method for manufacturing a transistor according to an embodiment. 10A to 10D illustrate an example of a method for manufacturing a transistor according to an embodiment. 10A to 10D illustrate an example of a method for manufacturing a transistor according to an embodiment. FIG. 10 is a circuit diagram of a semiconductor device according to an embodiment. 8A and 8B illustrate a cross-sectional structure of a semiconductor device according to an embodiment. 8A and 8B illustrate a cross-sectional structure of a semiconductor device according to an embodiment. 8A and 8B illustrate a cross-sectional structure of a semiconductor device according to an embodiment. 8A and 8B illustrate a cross-sectional structure of a semiconductor device according to an embodiment. 8A and 8B illustrate a cross-sectional structure of a semiconductor device according to an embodiment. 8A and 8B illustrate a cross-sectional structure of a semiconductor device according to an embodiment. 8A and 8B illustrate a cross-sectional structure of a semiconductor device according to an embodiment. 8A and 8B illustrate a cross-sectional structure of a semiconductor device according to an embodiment. 8A and 8B illustrate a circuit diagram and a cross-sectional structure of a semiconductor device according to an embodiment. 8A and 8B illustrate a cross-sectional structure of a semiconductor device according to an embodiment. FIG. 10 is a circuit diagram illustrating a memory device according to one embodiment of the present invention. FIG. 10 is a circuit diagram illustrating a memory device according to one embodiment of the present invention. 6A and 6B are a circuit diagram and a timing chart for illustrating one embodiment of the present invention. 5A and 5B are a graph and a circuit diagram for illustrating one embodiment of the present invention. 6A and 6B are a circuit diagram and a timing chart for illustrating one embodiment of the present invention. 6A and 6B are a circuit diagram and a timing chart for illustrating one embodiment of the present invention. 4A and 4B are a block diagram, a circuit diagram, and a waveform diagram for illustrating one embodiment of the present invention. 6A and 6B are a circuit diagram and a timing chart for illustrating one embodiment of the present invention. FIG. 10 is a circuit diagram illustrating one embodiment of the present invention. FIG. 10 is a circuit diagram illustrating one embodiment of the present invention. FIG. 10 is a circuit diagram illustrating one embodiment of the present invention. FIG. 10 is a circuit diagram illustrating one embodiment of the present invention. FIG. 10 is a circuit diagram illustrating one embodiment of the present invention. 1 is a block diagram illustrating a semiconductor device according to one embodiment of the present invention. FIG. 10 is a circuit diagram illustrating a semiconductor device according to one embodiment of the present invention. FIG. 6 is a top view illustrating a semiconductor device according to one embodiment of the present invention. 1 is a block diagram illustrating a semiconductor device according to one embodiment of the present invention. FIG. 6 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. FIG. 6 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. FIG. 6 is a top view illustrating a semiconductor device according to one embodiment of the present invention. FIGS. 3A and 3B are a flowchart for illustrating one embodiment of the present invention and a perspective view illustrating a semiconductor device. FIGS. FIG. 11 is a perspective view illustrating an electronic device according to one embodiment of the present invention. The HAADF-STEM image of CAAC-OS which concerns on a present Example. The figure which shows the result of having performed crystallinity evaluation using XRD which concerns on a present Example. The figure which shows the result of having performed crystallinity evaluation using XRD which concerns on a present Example. The cross-sectional TEM image of the IGZO film which concerns on a present Example. The graph which shows the hole mobility of the IGZO film which concerns on a present Example. Sectional TEM image, HAADF-STEM image, and EDX profile of sample 4 according to this example. The cross-sectional TEM image of the sample 5 which concerns on a present Example. The cross-sectional TEM image and electron diffraction pattern of the sample 5 which concern on a present Example. The figure which shows arrangement | positioning of the sample of the polarization | polarized-light XANES measurement which concerns on a present Example. The X-ray absorption spectrum obtained by the polarization | polarized-light XANES measurement which concerns on a present Example. The figure which shows the relative value of the peak of the X-ray absorption spectrum which concerns on a present Example. The XRD spectrum which concerns on a present Example. The X-ray absorption spectrum obtained by the polarization | polarized-light XANES measurement which concerns on a present Example. The crystal model of InGaZnO ₄ used in the simulation according to this example. The spectrum obtained by the simulation which concerns on a present Example. The graph which shows the correlation of the hole mobility and carrier density which concern on a present Example.

  Embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be easily understood by those skilled in the art that modes and details can be variously changed. In addition, the present invention is not construed as being limited to the description of the embodiments below. Note that in describing the structure of the present invention with reference to drawings, the same portions are denoted by the same reference numerals in different drawings. In addition, when referring to the same thing, a hatch pattern is made the same and there is a case where it does not attach a code in particular. In addition, when referring to the description of the component of a different code | symbol, the description about the thickness of the referred component, a composition, a structure, or a shape can be used suitably.

  Note that the size, the thickness of films (layers), or regions in drawings is sometimes exaggerated for simplicity.

  Note that in this specification, the expression “film” and the expression “layer” can be interchanged with each other.

  In many cases, the voltage indicates a potential difference between a certain potential and a reference potential (for example, a ground potential (GND) or a source potential). Thus, a voltage can be rephrased as a potential. Generally, the potential (voltage) is relative and is determined by a relative magnitude from a reference potential. Therefore, even when “ground potential” is described, the potential is not always 0V. For example, the lowest potential in the circuit may be the “ground potential”. Alternatively, an intermediate potential in the circuit may be a “ground potential”. In that case, a positive potential and a negative potential are defined based on the potential.

  The ordinal numbers attached as the first and second are used for convenience and do not indicate the order of steps or the order of lamination. Therefore, for example, the description can be made by appropriately replacing “first” with “second” or “third”. In addition, the ordinal numbers described in this specification and the like may not match the ordinal numbers used to specify one embodiment of the present invention.

  Note that even when “semiconductor” is described, for example, when the conductivity is sufficiently low, the semiconductor device may have characteristics as an “insulator”. In addition, the boundary between “semiconductor” and “insulator” is ambiguous and may not be strictly discriminated. Therefore, a “semiconductor” in this specification can be called an “insulator” in some cases. Similarly, an “insulator” in this specification can be called a “semiconductor” in some cases.

  In addition, even when “semiconductor” is described, for example, when the conductivity is sufficiently high, the semiconductor device may have characteristics as a “conductor”. In addition, the boundary between “semiconductor” and “conductor” is ambiguous, and there are cases where it cannot be strictly distinguished. Therefore, a “semiconductor” in this specification can be called a “conductor” in some cases. Similarly, a “conductor” in this specification can be called a “semiconductor” in some cases.

  Note that the impurity of the semiconductor means, for example, a component other than the main component constituting the semiconductor. For example, an element having a concentration of less than 0.1 atomic% is an impurity. When the impurities are included, for example, DOS (Density of States) may be formed in the semiconductor, carrier mobility may be reduced, or crystallinity may be reduced. In the case where the semiconductor is an oxide semiconductor, examples of impurities that change the characteristics of the semiconductor include Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and components other than main components Examples include transition metals, and in particular, hydrogen (also included in water), lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen, and the like. In the case of an oxide semiconductor, oxygen vacancies may be formed by mixing impurities such as hydrogen, for example. In the case where the semiconductor is a silicon layer, examples of impurities that change the characteristics of the semiconductor include group 1 elements, group 2 elements, group 13 elements, and group 15 elements excluding oxygen and hydrogen.

  Note that the channel length refers to, for example, a region where a semiconductor (or a portion where current flows in the semiconductor when the transistor is on) and a gate electrode overlap with each other in a top view of the transistor, or a region where a channel is formed The distance between the source (source region or source electrode) and the drain (drain region or drain electrode) in FIG. Note that in one transistor, the channel length is not necessarily the same in all regions. That is, the channel length of one transistor may not be fixed to one value. Therefore, in this specification, the channel length is any one of values, the maximum value, the minimum value, or the average value in a region where a channel is formed.

  The channel width is, for example, a region in which a semiconductor (or a portion in which a current flows in the semiconductor when the transistor is on) and a gate electrode overlap each other, or a source and a drain in a region where a channel is formed. This is the length of the part. Note that in one transistor, the channel width is not necessarily the same in all regions. That is, the channel width of one transistor may not be fixed to one value. Therefore, in this specification, the channel width is any one of values, the maximum value, the minimum value, or the average value in a region where a channel is formed.

  Note that depending on the structure of the transistor, the channel width in a region where a channel is actually formed (hereinafter referred to as an effective channel width) and the channel width shown in a top view of the transistor (hereinafter, apparent channel width). May be different). For example, in a transistor having a three-dimensional structure, the effective channel width is larger than the apparent channel width shown in the top view of the transistor, and the influence may not be negligible. For example, in a transistor having a fine and three-dimensional structure, the ratio of the channel region formed on the side surface of the semiconductor may be large. In that case, the effective channel width in which the channel is actually formed is larger than the apparent channel width shown in the top view.

  By the way, in a transistor having a three-dimensional structure, it may be difficult to estimate an effective channel width by actual measurement. For example, in order to estimate the effective channel width from the design value, it is necessary to assume that the shape of the semiconductor is known. Therefore, it is difficult to accurately measure the effective channel width when the shape of the semiconductor is not accurately known.

  Therefore, in this specification, in the top view of a transistor, an apparent channel width which is a length of a portion where a source and a drain face each other in a region where a semiconductor and a gate electrode overlap with each other is expressed as “enclosed channel width ( SCW: Surrounded Channel Width). In this specification, in the case where the term “channel width” is simply used, it may denote an enclosed channel width or an apparent channel width. Alternatively, in this specification, in the case where the term “channel width” is simply used, it may denote an effective channel width. Note that the channel length, channel width, effective channel width, apparent channel width, enclosed channel width, and the like can be determined by obtaining a cross-sectional TEM image and analyzing the image. it can.

  Note that in the case where the field-effect mobility of a transistor, the current value per channel width, and the like are calculated and calculated, the calculation may be performed using the enclosed channel width. In that case, the value may be different from that calculated using the effective channel width.

  In this specification, “parallel” refers to a state in which two straight lines are arranged at an angle of −10 ° to 10 °. Therefore, the case of −5 ° to 5 ° is also included. Further, “substantially parallel” means a state in which two straight lines are arranged at an angle of −30 ° to 30 °. “Vertical” refers to a state in which two straight lines are arranged at an angle of 80 ° to 100 °. Therefore, the case of 85 ° to 95 ° is also included. Further, “substantially vertical” means a state in which two straight lines are arranged at an angle of 60 ° to 120 °.

  In this specification, when a crystal is trigonal or rhombohedral, it is represented as a hexagonal system.

  Note that in the specification, the term “semiconductor” can be read as “oxide semiconductor”. Other semiconductors include Group 14 semiconductors such as silicon and germanium, compound semiconductors such as silicon carbide, germanium silicide, gallium arsenide, indium phosphide, zinc selenide, and cadmium sulfide, and organic semiconductors. Can do.

  Note that in the specification, the term “oxide” can be read as an oxide semiconductor, an oxide insulator, or an oxide conductor.

(Embodiment 1)
<Film formation method>
An example of a CAAC-OS film formation model by a sputtering method is described below.

As an example, FIG. 1A illustrates a crystal structure of InMZnO ₄ (the element M is, for example, aluminum, gallium, yttrium, or tin). Note that FIG. 1A illustrates a crystal structure of InMZnO ₄ when observed from a direction parallel to the b-axis. As shown in FIG. 1A, InMZnO ₄ has a layered crystal structure (also referred to as a layered structure), with an In—O layer of 1 and an M—Zn—O layer of 2. Here, the In—O layer is a layer containing indium and oxygen, and can also be said to contain InO ₂ that is an oxide. The M-Zn-O layer is a layer containing the element M, zinc, and oxygen, and contains (M, Zn) O that is an oxide (for example, (Ga, Zn) O). It can also be said. In this case, the ratio of the element M and zinc shall be equal. The element M and zinc can be substituted and the arrangement is irregular.

When the cleavage energy was calculated for various crystal planes included in the crystal structure shown in FIG. 1A, it was found that the cleavage energy was the smallest in the cleavage plane 25 shown in FIG. The cleavage plane 25 is a plane sandwiched between two adjacent M—Zn—O layers, and corresponds to the (001) plane of the InMZnO ₄ crystal. Details of the cleavage energy of the crystal structure of InMZnO ₄ will be described later.

  In the two M-Zn-O layers positioned with the cleavage plane 25 interposed therebetween, the oxygen atoms and the oxygen atoms are positioned so as to face each other as shown in FIG. Since oxygen atoms repel each other due to Coulomb force, the binding energy between two adjacent M-Zn-O layers becomes weak, and a cleavage plane 25 is formed.

  Thus, the cleavage surface 25 having a small cleavage energy also has a small surface energy. Therefore, it is estimated that the plate-like structure in which the M—Zn—O layer is located on the surface is stable in terms of energy. A cluster having such a structure is referred to as a nanocluster in this specification. As an example, FIG. 1B shows a structure of the nanocluster 20 viewed from a direction perpendicular to the c-axis. FIG. 1C shows a structure of the nanocluster 20 viewed from a direction parallel to the c-axis.

As shown in FIG. 1B, for example, the nanocluster 20 includes two M-Zn-O layers and an In-O layer positioned therebetween. Further, as shown in FIG. 1A, the nanocluster 20 corresponds to a portion sandwiched between two cleavage planes 25 in the crystal structure of InMZnO ₄ .

  The nanocluster 20 is a flat cluster having a hexagonal plane, for example, a regular hexagonal plane. Alternatively, the nanocluster 20 is a flat cluster having a plane of a triangle, for example, an equilateral triangle. However, the shape of the nanocluster 20 is not limited to a triangle or a hexagon. For example, there are cases where a plurality of triangles are combined. For example, there may be a quadrangle (for example, a rhombus) in which two triangles (for example, regular triangles) are combined. For example, the hexagon may be deformed into a pentagon or heptagon shape.

  The thickness of the nanocluster 20 is determined according to the type of film forming gas. For example, the nanocluster 20 has a thickness of 0.4 nm to 1 nm, preferably 0.6 nm to 0.8 nm. Further, for example, the nanocluster 20 has a width of 1 nm to 100 nm, preferably 2 nm to 50 nm, and more preferably 3 nm to 30 nm.

When an oxide film such as InMZnO ₄ is formed by a sputtering method, nanoclusters are formed on the surface of the substrate or the base film, and the nanoclusters are grown in the lateral direction to form the CAAC-OS or the like. It is thought. The CAAC-OS growth mechanism through formation of nanoclusters is described below.

  A model in which the nanocluster 20 is cleaved from the target 33 will be described with reference to FIGS. 2 and 3. Here, FIG. 2 shows a film forming chamber of the sputtering apparatus. As shown in FIG. 2, a target 33 is provided in the film forming chamber. It is preferable that the target 33 is provided by being bonded to the backing plate and disposed so as to overlap the magnet via the backing plate.

The film formation chamber is mostly filled with a film forming gas (for example, oxygen, argon, or a mixed gas containing oxygen at a ratio of 5% by volume or more), and is 0.01 Pa to 100 Pa, preferably 0.1 Pa to 10 Pa. Controlled. Note that the deposition gas preferably does not contain impurities such as water. For example, water molecules contained in the deposition gas may be less than 0.5 sccm. Here, by applying a voltage of a certain level or higher to the target 33 side, discharge starts and the plasma 34 can be confirmed. A high-density plasma region is formed near the target 33 by the magnetic field of the magnet. In the high-density plasma region, ions 21 are generated by ionizing the deposition gas. A sputtering method that uses a magnetic field to increase the deposition rate is called a magnetron sputtering method. The ion 21 is, for example, an oxygen cation (O ⁺ ) or an argon cation (Ar ⁺ ).

It is preferable that the target 33 has a polycrystalline structure having a plurality of crystal grains, and any one of the crystal grains includes the cleavage plane 25. For example, the target 33 preferably includes an InMZnO ₄ (element M is, for example, aluminum, gallium, yttrium, or tin) crystal shown in FIG. The target 33 is preferably free of impurities such as silicon. For example, silicon oxide contained in the target 33 is less than 2% by weight, preferably 0.2% by weight or less, more preferably 0.02% by weight. It may be less than%.

  The ions 21 generated in the high-density plasma region are accelerated to the target 33 side by the electric field and eventually collide with the target 33. At this time, the nanocluster 20, which is a flat cluster, is peeled from the cleavage plane 25. As the nanocluster 20 is peeled off, the particles 23 are also ejected from the target 33. The particle 23 has an aggregate of one atom or several atoms. For this reason, the particles 23 can also be called atomic particles. Note that the structure of the nanocluster 20 may be distorted by the impact of the collision of the ions 21.

  The state of cleavage on the surface of the target will be described with reference to the cross-sectional view shown in FIG. FIG. 3A is a cross-sectional view of the target 33 having the cleavage plane 25 (broken line portion). When the ions 21 collide with the target 33, the bond starts to break from the end of the cleavage plane 25 (see FIG. 3B). Here, the cleaved surfaces repel each other by the Coulomb force due to the presence of electric charges having the same polarity. As the repulsion due to the Coulomb force progresses, the disconnected region gradually expands. Eventually, the nanoclusters 20 peel from the target 33 (see FIG. 3C).

  The nanoclusters 20 and the particles 23 that have passed through the plasma 34 reach the surface of the substrate 32. Here, since the nanocluster 20 has a flat plate shape, it is easily deposited with the plane side facing the surface of the substrate 32. Furthermore, by heating the substrate, it becomes easy to migrate the nanoclusters 20 and deposit the planar side toward the surface of the substrate 32. Note that some of the particles 23 may be discharged to the outside by a vacuum pump or the like because of a small mass. Alternatively, an insulator such as a base insulating film may be provided over the substrate 32.

  In FIG. 2, the target 33 and the substrate 32 are shown facing each other, but the oxide film forming method according to this embodiment is not necessarily limited thereto. For example, as shown in FIGS. 17 and 18 to be described later, two targets may be provided to face each other, and a substrate may be disposed between them.

  2 and 3, the target 33 has a polycrystalline structure of a complex oxide such as an In-M-Zn oxide having a plurality of crystal grains, and any one of the crystal grains includes a cleavage plane 25. Explained the case. A different growth model can be considered for the oxide film described in this embodiment. For example, the following growth mechanism in which nanoclusters are formed by self-organization can be considered.

  For example, unlike the cases shown in FIGS. 2 and 3, it is assumed that the nanoclusters 20 are formed by the mechanism shown in FIG. Here, even when the nanoclusters 20 are formed by the mechanism shown in FIG. 4, the film formation can be performed in the same state as when the film is formed in the film formation chamber shown in FIG.

  Therefore, in the same manner as described above, the deposition chamber is mostly filled with a deposition gas (for example, oxygen, argon, or a mixed gas containing oxygen at a ratio of 5% by volume or more), and is 0.01 Pa or more and 100 Pa or less, preferably Is controlled to 0.1 Pa or more and 10 Pa or less. Note that the deposition gas preferably does not contain impurities such as water. For example, water molecules contained in the deposition gas may be less than 0.5 sccm.

  The target 33 may be a mixture containing indium oxide, an oxide of element M, and zinc oxide. The target 33 is preferably free of impurities such as silicon. For example, silicon oxide contained in the target 33 is less than 2% by weight, preferably 0.2% by weight or less, more preferably 0.02% by weight. It may be less than%.

  The film forming method shown in FIG. 4 is preferably performed while heating the substrate 32. The surface temperature of the substrate 32 may be 100 ° C. or higher and lower than 500 ° C., preferably 140 ° C. or higher and lower than 450 ° C., more preferably 170 ° C. or higher and lower than 400 ° C.

  By applying a voltage of a certain level or more to the target 33 side, discharge starts, plasma 34 is generated, and ions 21 are generated. The ions 21 are accelerated toward the target 33 by the electric field and eventually collide with the target 33. At this time, the particles 23 are ejected from the target 33. The particle 23 has an aggregate of one atom or several atoms. The particles 23 may be ionized. Further, some of the particles 23 may be discharged to the outside by a vacuum pump or the like because of a small mass.

  Here, the particles 23 ejected from the target 33 are deposited on the surface of the substrate 32 (see FIG. 4A). At this time, by performing sputtering while heating the substrate 32, thermal energy is given to the particles 23 deposited on the surface of the substrate 32, and the particles 23 can be migrated. That is, it is considered that other particles 23 deposited on the surface of the substrate 32 cause migration in parallel with the deposition of the particles 23 on the surface of the substrate 32.

  As the particles 23 migrate, the particles 23 deposited on the substrate 32 are aligned in an energetically stable arrangement. The cleavage surface 25 having a low surface energy is in contact with the substrate 32 to form an M—Zn—O layer, an In—O layer is formed thereon, and the cleavage surface 25 having a lower surface energy is exposed on the surface. An M-Zn-O layer is formed. In this manner, nanoclusters 20 that are flat-shaped clusters with surfaces perpendicular to the c-axis appearing on the surface are formed (see FIG. 4B). In this step, the particles 23 are autonomously aligned so that the thermal energy given from the substrate 32 forms a highly ordered crystal structure. From this point, it can be said that the nanocluster 20 is formed by self-organization.

  When the nanoclusters 20 are formed by self-organization as described above, the nanoclusters 20 can also be formed by using a target of a mixture containing indium oxide, an oxide of element M and zinc oxide as the target 33. .

  The substrate 32 is preferably a substrate (such as a single crystal substrate) whose surface to be formed is a specific crystal plane, such as an yttria stabilized zirconia (YSZ) substrate. By using a single crystal substrate or the like as the substrate 32, the crystallinity of the nanocluster 20 can be improved.

  Next, a model in which the nanoclusters 20 formed on the surface of the substrate 32 grow according to the above growth mechanism will be described with reference to FIG.

  First, a plurality of nanoclusters 20 are formed on the surface of the substrate 32 according to any of the above models. Here, the plurality of nanoclusters 20 have random a-axis and b-axis directions.

  Next, the particles 23 reach the surface of the substrate 32. Although details will be described later, the particles 23 are more likely to be bonded to the side surface than the upper surface of the nanocluster 20. Accordingly, the particles 23 preferentially adhere to the side surfaces of the nanoclusters 20 so as to fill the regions where the nanoclusters 20 are not formed. The particle 23 is chemically connected to the nanocluster 20 to form a laterally grown portion 22 when the bond is in an active state (see FIG. 5A). It can also be said that the particles 23 enter the region between the nanoclusters 20. Note that the nanocluster 20 includes two M—Zn—O layers and an In—O layer positioned therebetween as shown in FIG.

  The lateral growth portion 22 grows in a lateral direction (lateral growth) so as to fill a region 26 between the nanoclusters 20 (the region 26 may also be referred to as a lateral growth buffer region (LGBR)). Here, the lateral direction refers to a direction perpendicular to the c-axis in the nanocluster 20, for example.

  Here, by heating the substrate at 450 ° C. or lower, preferably about 400 ° C. or lower, the particles 23 adhere to the laterally grown portions 22 of the nanoclusters 20, oxygen diffused via LGBR adheres to the particles 23, and the particles 23 again. The reaction of adhering in the same manner is likely to occur. It is presumed that the solid-phase growth in the horizontal direction is caused by this repetition. Such lateral growth of nanoclusters can also be called self-organization.

  Furthermore, the lateral growth part 22 collides with each other because the lateral growth part 22 grows laterally. Adjacent nanoclusters 20 are connected with a portion where the laterally growing portion 22 collides as a connecting portion 27 (see FIG. 5B). That is, the connecting portion 27 is formed in the region 26. It can also be said that the particles 23 form the lateral growth portions 22 on the side surfaces of the nanoclusters 20 and grow in the lateral direction, thereby filling the regions 26 between the nanoclusters 20. In this manner, the lateral growth portion 22 is formed until the region where the nanocluster 20 is not formed is filled. This mechanism is similar to the deposition mechanism of the atomic layer deposition (ALD) method.

  Therefore, even when the nanoclusters 20 are formed in different directions, the gap between the nanoclusters 20 and the nanoclusters 20 is filled while the particles 23 are laterally grown, so that a clear crystal grain boundary is not formed. .

Here, as shown in FIG. 1A, the crystal structure of InMZnO ₄ is a layered crystal structure that stably exists in a wide composition range, and the bond strength and equilibrium distance between metal atoms and oxygen atoms are as follows. Different for each metal atom. Therefore, it is presumed that the crystal structure of InMZnO ₄ takes a structure that is tolerant to strain. Therefore, since the particles 23 are smoothly connected (anchored) between the nanoclusters 20, a crystal structure different from the single crystal and the polycrystal is formed in the connection portion 27. In other words, a crystal structure having a strain is formed at the connecting portion 27 between the nanoclusters 20. Thereby, for example, in the connecting portion 27, the crystal structure whose upper surface has a hexagonal shape may be deformed into a pentagon or heptagon. As described above, since the region between the nanoclusters 20 is a distorted crystal region, it is considered inappropriate to refer to the region as an amorphous structure.

  Next, new nanoclusters 20 are formed with the planar side facing the surface of the substrate 32. Then, the particles 23 are deposited so as to fill a region where the nanoclusters 20 are not formed, thereby forming the lateral growth portion 22 (see FIG. 5C). Thus, the particles 23 adhere to the side surfaces of the nanoclusters 20 and the laterally grown portions 22 grow laterally, thereby connecting the nanoclusters 20 in the second layer (see FIG. 5D). Film formation continues until the m-th layer (m is an integer of 2 or more) is formed, and an oxide having a thin film structure having a stacked body is formed. Thus, when an oxide film is formed on the flat portion 35a of the substrate (or the base insulating film), nanoclusters 20 oriented in the c-axis direction substantially perpendicular to the upper surface of the flat portion 35a are formed (FIG. 6 (A).) Further, even when an oxide film is formed on the convex portion 35b of the substrate (or the base insulating film), the nanocluster 20 oriented in the c-axis direction substantially perpendicular to the upper surface of the convex portion 35b is formed (FIG. 6). (See (B).) Note that, as shown in FIGS. 6A and 6B, in some cases, an inclination may be generated between the nanoclusters 20 and the nanoclusters 20 to disturb the orientation.

  Note that the formation of the nanoclusters 20 also varies depending on the surface temperature of the substrate 32. For example, when the surface temperature of the substrate 32 is high, the particles 23 migrate on the surface of the nanocluster 20. As a result, the bonds of the particles 23 are more activated, and the formation of the lateral growth portions 22 can be promoted. The surface temperature of the substrate 32 in forming the CAAC-OS is 100 ° C. or higher and lower than 500 ° C., preferably 140 ° C. or higher and lower than 450 ° C., more preferably 170 ° C. or higher and lower than 400 ° C. Therefore, even when a large-area substrate of the eighth generation or higher is used as the substrate 32, it can be seen that almost no warpage or the like due to the formation of the CAAC-OS film occurs. Further, migration of the nanoclusters 20 increases the proportion of the nanoclusters 20 that are connected without the particles 23 therebetween, which may result in a CAAC-OS with higher orientation.

  On the other hand, when the surface temperature of the substrate 32 is low, the nanocluster 20 is less likely to cause migration on the surface of the substrate 32. As a result, the nanoclusters 20 are stacked to form an nc-OS (nanocrystalline Oxide Semiconductor) with low orientation. In the nc-OS, the nanoclusters 20 may be deposited at regular intervals. Therefore, although the orientation is low, a slight regularity results in a dense structure as compared with an amorphous oxide semiconductor.

  In CAAC-OS, a gap between nanoclusters may be extremely small, so that one large nanocluster may be formed. The inside of one large nanocluster has a single crystal structure. For example, the size of the nanocluster may be 10 nm to 200 nm, 15 nm to 100 nm, or 20 nm to 50 nm when viewed from above.

  It is considered that nanoclusters are deposited on the surface of the substrate by the film formation model as described above. Since the CAAC-OS film can be formed even when the formation surface does not have a crystal structure, it can be seen that the above-described film formation model, which is a growth mechanism different from epitaxial growth, has high validity. Further, since the above-described film formation model is used, it can be seen that the CAAC-OS and the nc-OS can form a uniform film even on a large-area glass substrate or the like. For example, the CAAC-OS can be formed even when the surface (formation surface) of the substrate has an amorphous structure (eg, amorphous silicon oxide).

  Further, it can be seen that even when the surface of the substrate that is the formation surface has irregularities, the nanoclusters are arranged along the shape.

  Further, from the above-described film formation model, it can be seen that the following may be performed in order to form a highly crystalline CAAC-OS. First, in order to lengthen the mean free path, the film is formed in a higher vacuum state. Next, in order to reduce damage in the vicinity of the substrate, the plasma energy is weakened. Next, thermal energy is applied to the surface to be formed, and the plasma damage is cured each time the film is formed.

  So far, the case where the nanocluster has a flat plate shape has been described. For example, when the nanocluster is a nanocluster having a small width such as a dice or a column, the nanocluster reaching the surface of the substrate is deposited in various directions. Then, in the nanocluster, the particles adhere to the side surfaces in the direction in which they are deposited, and the laterally grown portion undergoes lateral growth. As a result, the crystal orientation in the obtained thin film may not be uniform.

<Cleavage energy>
Below, the result calculated about the cleavage energy of the crystal structure of InMZnO ₄ is demonstrated. In the following, the calculation was performed for the case where the element M is Ga. The cleavage energy refers to energy per unit area necessary for cleaving a crystal at a certain crystal plane.

First, a cleavage plane of an InGaZnO ₄ crystal will be described with reference to FIGS. 9A to 9D. Here, FIG. 9A is a model of an InGaZnO ₄ crystal viewed from a direction perpendicular to the b-axis, and shows a crystal plane A, a crystal plane C, and a crystal plane D. FIG. 9B is a model of InGaZnO ₄ crystal viewed from a direction perpendicular to the c-axis, and shows a crystal plane E and a crystal plane F. FIG. 9C is a model of an InGaZnO ₄ crystal viewed from a direction perpendicular to the c-axis, and shows a crystal plane A, a crystal plane B, and a crystal plane D. FIG. 9D is an enlarged view of the vicinity of the crystal plane F shown in FIG.

The energy required for cleavage in each crystal plane of the InGaZnO ₄ crystal was calculated by first-principles calculation. For the calculation, a pseudo-potential and a density functional program (CASTEP) using plane wave bases were used. A PAW (Projector Augmented Wave) method was used for the pseudopotential of atoms. Moreover, PBEsol (Perdew-Burke-Ernzerhof revised for solid) type generalized gradient approximation (GGA) was used for the exchange correlation potential. The cut-off energy was 800 eV.

Based on the structure of the InGaZnO ₄ crystal shown in FIG. 9, a model of the InGaZnO ₄ crystal cleaved at any one of the crystal planes A to F is created, and the structure optimization calculation is performed with the cell size fixed. Here, the crystal plane A is a crystal plane corresponding to the (100) plane (see FIGS. 9A and 9C). The crystal plane B is a crystal plane in which the surface structure is cut so that the number per unit area of dangling bonds intersecting with the (100) plane is minimized (see FIG. 9C). The crystal plane C is a crystal plane corresponding to the (110) plane (see FIG. 9A). The crystal plane D is a crystal plane corresponding to the (201) plane (see FIGS. 9A and 9C). The crystal plane E corresponds to the (001) plane and is a crystal plane located between the Ga—Zn—O layer and the In—O layer. (See FIG. 9B.) The crystal plane F corresponds to the (001) plane and is a crystal plane located between the Ga—Zn—O layer and the Ga—Zn—O layer. (See FIG. 9B.) On the crystal plane F, as shown in FIG. 9D, two oxygen atom layers are positioned so as to face each other.

Under the conditions as described above, the cleavage energy σ [J / m ² ] when cleaved on each surface is calculated using Equation (1).

Here, E _bulk [J] is the energy of the crystal model, and E _cl [J] is the energy of the surface model cleaved on each face. Note that the energy of the crystal model is derived after structural optimization including the cell size. In addition, the energy of the surface model cleaved on each surface is derived after structural optimization of the atomic arrangement with the cell size fixed. In addition, the energy of the crystal model and the energy of the surface model cleaved on each face are the kinetic energy of electrons and the mutual relationship between atoms, atoms-electrons, and electrons. It is energy that takes into account the action. S _cl [m ² ] is the area of the cleavage plane.

As a result of the calculation, the cleavage energy of the crystal plane A is 3.45 J / m ² , the cleavage energy of the crystal plane B is 2.45 J / m ² , the cleavage energy of the crystal plane C is 2.23 J / m ² , and the crystal plane D It was found that the cleavage energy was 1.98 J / m ² , the cleavage energy of crystal plane E was 3.56 J / m ² , and the cleavage energy of crystal plane F was 0.90 J / m ² (see the table below).

According to this calculation, the cleavage energy at the crystal plane F is the lowest in the InGaZnO ₄ crystal structure shown in FIG. That is, it can be seen that the surface between the Ga—Zn—O layer and the Ga—Zn—O layer is the most easily cleaved. This also corresponds to the cleavage plane 25 shown in FIG.

<Lateral growth>
In the following, it will be described that the particles 23 adhere (also referred to as bonding or adsorption) in the lateral direction of the nanocluster 20 and laterally grow.

FIG. 7A, FIG. 7B, FIG. 7C, FIG. 7D, and FIG. 7E are diagrams showing the structure of the nanocluster 20 and the positions where metal ions adhere. The nanocluster 20 is assumed to be a cluster model in which 84 atoms are extracted from the crystal structure of InMZnO ₄ while maintaining the stoichiometric composition. Hereinafter, the case where the element M is gallium will be described. FIG. 7F shows a structure of the nanocluster 20 viewed from a direction parallel to the c-axis. FIG. 7G shows a structure of the nanocluster 20 viewed from a direction parallel to the a-axis.

  Positions where metal ions adhere are indicated by position A, position B, position a, position b, and position c. The position A is above the interstitial site surrounded by one gallium and two zincs on the upper surface of the nanocluster 20. The position B is above the interstitial site surrounded by two galliums and one zinc on the upper surface of the nanocluster 20. The position a is an indium site on the side surface of the nanocluster 20. The position b is an interstitial site between the In—O layer and the Ga—Zn—O layer on the side surface of the nanocluster 20. The position c is a gallium site on the side surface of the nanocluster 20.

Next, the relative energy when metal ions are arranged at the assumed position A, position B, position a, position b, and position c was evaluated by the first principle calculation. VASP (Vienna Ab initio Simulation Package) was used for the first principle calculation. Further, the PBE (Perdew-Burke-Ernzerhof) type generalized gradient approximation (GGA) was used as the exchange correlation potential, and the PAW (Projector Augmented Wave) method was used as the ion potential. The cut-off energy was 400 eV, and the k-point sampling was only the Γ point. The table below shows the relative energies when indium ions (In ³⁺ ), gallium ions (Ga ³⁺ ), and zinc ions (Zn ²⁺ ) are arranged at position A, position B, position a, position b, and position c. The relative energy is a relative value when the energy of the model with the lowest energy is 0 eV in the calculated model.

  As a result, it was found that all metal ions are more likely to adhere to the side surface than the top surface of the nanocluster 20. In particular, at the indium site at position a, not only indium ions but also zinc ions were most easily attached.

Similarly, the ease of attachment of oxygen ions (O ²⁻ ) to the nanoclusters 20 was evaluated. FIG. 8A, FIG. 8B, FIG. 8C, FIG. 8D, and FIG. 8E are diagrams showing the structure of the nanocluster 20 and the position where oxygen ions are attached. FIG. 8F shows a structure of the nanocluster 20 viewed from a direction parallel to the c-axis. FIG. 8G shows a structure of the nanocluster 20 viewed from a direction parallel to the b-axis.

  Positions where oxygen ions adhere are indicated by position C, position D, position d, position e, and position f. Note that the position C is a position where it bonds to gallium on the upper surface of the nanocluster 20. The position D is a position where it binds to zinc on the upper surface of the nanocluster 20. The position d is a position where it binds to indium on the side surface of the nanocluster 20. The position e is a position where it bonds with gallium on the side surface of the nanocluster 20. The position f is a position where it binds to zinc on the side surface of the nanocluster 20.

Next, the relative energy when oxygen ions are arranged at the assumed position C, position D, position d, position e, and position f is evaluated by the first principle calculation. The table below shows the relative energy when oxygen ions (O ²⁻ ) are arranged at position C, position D, position d, position e, and position f.

  As a result, it was found that oxygen ions are more likely to adhere to the side surface than the upper surface of the nanocluster 20.

  Therefore, it can be seen that the particles 23 approaching the nanocluster 20 preferentially adhere to the side surface of the nanocluster 20. That is, it can be said that the above-described film formation model in which the lateral growth of the nanocluster 20 is caused by the particles 23 attached to the side surface of the nanocluster 20 is highly valid.

<Crystal structure change of CAAC-OS due to Si contamination>
The following describes the results of calculation whether the crystal structure by Si is mixed into the crystal structure of InMZnO ₄ how the changes. In the following, the calculation was performed for the case where the element M is Ga.

The crystal model of InGaZnO ₄ used in this calculation is shown in FIG. In this calculation, the structure optimization was performed based on the first principle calculation for the model in which Si is arranged in the InGaZnO ₄ crystal shown in FIG. In addition, the area | region enclosed with the dashed-dotted line of FIG. 10 is the cell size used for this calculation, In this calculation, it calculated about the model comprised by 336 atoms. The charge state of the entire model was neutral.

  For this calculation, VASP (Vienna Ab initio Simulation Package) was used. The PAW method was used for the pseudopotential of atoms. The exchange correlation potential was PBE (Perdew-Burke-Ernzerhof) type generalized gradient approximation (GGA). The cut-off energy was 800 eV. The sample k point was 2 × 2 × 1.

FIGS. 11 and 12 show a structure after Si is arranged in the InGaZnO ₄ crystal model shown in FIG. 10 and the structure is optimized. FIG. 11A shows the structure after the structure optimization shown in FIG. 10 by replacing Zn with Si. FIG. 11B shows the structure after the structure optimization shown in FIG. 10 by substituting In for Si. FIG. 12A illustrates a structure after the structure optimization in which Si is disposed between the In—O layer and the Ga—Zn—O layer in the structure illustrated in FIG. FIG. 12B illustrates the structure after the structure optimization in which Si is disposed between the Ga—Zn—O layer and the Ga—Zn—O layer in the structure illustrated in FIG.

  As shown in FIG. 11A, when Zn is replaced by Si, the distance between O bonded to Si in the ab plane direction and Ga or Zn bonded to the O in the c-axis direction is increased. . Thereby, the Ga or Zn was close to tetracoordinate. Here, Si is tetracoordinate, and the average distance from the first adjacent O was about 0.167 nm. This is about 0.02 nm shorter than the distance between Ga—O or Ga—O. Therefore, it is presumed that the crystal structure is distorted when Si attracts O.

  As shown in FIG. 11B, even when In was replaced with Si, the position of O adjacent to Si was shifted. Here, the average distance between Si and O is 0.183 nm, which is shorter than the distance between In—O (about 0.22 nm). Therefore, as in the case where Zn is replaced with Si, it is presumed that the crystal structure is distorted when Si attracts O.

Thus, when Si is mixed into the metal site of the crystal of InGaZnO ₄ , since Si is tetracoordinate and the distance of Si—O is shorter than the distance of In, Ga, Zn, and O, the crystal structure is It is suggested that distortion occurs and crystal growth is inhibited.

  In addition, as illustrated in FIG. 12A, when Si is disposed between the In—O layer and the Ga—Zn—O layer, the distance between In—O is increased in the vicinity of Si. This is presumed to be because the Si—O bond is stronger than the In—O bond, so that Si attracts O and breaks the In—O bond.

  In addition, as illustrated in FIG. 12B, when Si is disposed between the Ga—Zn—O layer and the Ga—Zn—O layer, the position is shifted from the plane of the Ga—Zn—O layer in the vicinity of Si. Ga and Zn were found. This is because the Ga-Zn and O bonded in the c-axis direction are combined with Si, the distance between Ga-O and Zn-O is increased, and Ga and Zn are close to tetracoordinate. Guessed.

Thus, it is suggested that when Si is mixed between lattices of InGaZnO ₄ crystals, the structure in the vicinity of Si is disturbed.

<Composition>
Hereinafter, the composition of the In-M-Zn oxide will be described. The element M is aluminum, gallium, yttrium, tin, or the like. Other elements applicable to the element M include boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium. However, the element M may be a combination of a plurality of the aforementioned elements.

  First, with reference to FIGS. 13A, 13B, and 13C, a preferable range of the atomic ratio of indium, element M, and zinc included in the oxide according to the present invention will be described. Note that FIG. 13 does not describe the atomic ratio of oxygen. In addition, each term of the atomic ratio of indium, element M, and zinc included in the oxide is [In], [M], and [Zn].

  In FIG. 13A, FIG. 13B, and FIG. 13C, a broken line indicates an atomic ratio of [In]: [M]: [Zn] = (1 + α) :( 1-α): 1. Line that satisfies (−1 ≦ α ≦ 1), [In]: [M]: [Zn] = (1 + α) :( 1-α): line that has an atomic ratio of 2 [In]: [M] : [Zn] = (1 + α): (1-α): a line having an atomic ratio of 3; [In]: [M]: [Zn] = (1 + α): (1-α): number of atoms of 4 A line to be a ratio and a line to have an atomic ratio of [In]: [M]: [Zn] = (1 + α) :( 1−α): 5.

  A one-dot chain line is a line having an atomic ratio of [In]: [M]: [Zn] = 1: 1: β (β ≧ 0), [In]: [M]: [Zn] = 1: 2: A line with an atomic ratio of β, [In]: [M]: [Zn] = 1: 3: A line with an atomic ratio of β, [In]: [M]: [Zn] = 1: 4: Line with an atomic ratio of β, [In]: [M]: [Zn] = 2: 1: Line with an atomic ratio of β, and [In]: [M]: [Zn] = 5 : Represents a line with an atomic ratio of 1: β.

  In addition, an oxide having an atomic ratio of [In]: [M]: [Zn] = 0: 2: 1 or a value close to it shown in FIG. 13 tends to have a spinel crystal structure.

  FIG. 13A and FIG. 13B illustrate an example of a preferable range of the atomic ratio of indium, the element M, and zinc included in the oxide of one embodiment of the present invention.

InMZnO ₄ has a layered crystal structure (also referred to as a layered structure), and as shown in FIG. 1A, indium and oxygen have an In—O layer of 1, an element M, zinc, and oxygen. The M-Zn-O layer having 2 is 2.

  Indium and element M can be substituted for each other. Therefore, the element M in the M-Zn-O layer can be replaced with indium to represent an In-M-Zn-O layer. In that case, a layered structure in which the In—O layer is 1 and the In—M—Zn—O layer is 2 is employed.

An oxide having an atomic ratio of [In]: [M]: [Zn] = 1: 1: 2 has a layered structure in which the In—O layer is 1 and the M—Zn—O layer is 3. . That is, when [Zn] increases with respect to [In] and [M], the ratio of the M—Zn—O layer to the In—O layer increases when the oxide crystallizes.

  However, in the oxide, when the In—O layer is 1 and the M—Zn—O layer is a non-integer, the layered structure in which the In—O layer is 1 and the M—Zn—O layer is an integer. In some cases. For example, when [In]: [M]: [Zn] = 1: 1: 1.5, a layered structure in which the In—O layer is 1 and the M—Zn—O layer is 2; There may be a layered structure in which a layered structure having 3 Zn—O layers is mixed.

  For example, when an oxide is formed using a sputtering apparatus, a film having an atomic ratio that deviates from the atomic ratio of the target is formed. In particular, depending on the substrate temperature during film formation, [Zn] of the film may be smaller than [Zn] of the target.

  In addition, a plurality of phases may coexist in the oxide (two-phase coexistence, three-phase coexistence, etc.). For example, at an atomic ratio which is a value close to the atomic ratio of [In]: [M]: [Zn] = 0: 2: 1, two phases of a spinel crystal structure and a layered crystal structure coexist. Cheap. In addition, when the atomic ratio is a value close to the atomic ratio indicating [In]: [M]: [Zn] = 1: 0: 0, the biphasic crystal structure and the layered crystal structure have two phases. Easy to coexist. When a plurality of phases coexist in an oxide, a grain boundary (also referred to as a grain boundary) may be formed between different crystal structures.

  In addition, by increasing the indium content, the carrier mobility (electron mobility) of the oxide can be increased. This is because, in an oxide containing indium, element M and zinc, the s orbital of heavy metal mainly contributes to carrier conduction, and by increasing the content of indium, the region where the s orbital overlaps becomes larger. This is because an oxide having a high indium content has higher carrier mobility than an oxide having a low indium content.

  On the other hand, when the contents of indium and zinc in the oxide are lowered, the carrier mobility is lowered. Therefore, in the atomic number ratio indicating [In]: [M]: [Zn] = 0: 1: 0 and the atomic number ratio which is a neighborhood value thereof (for example, the region C shown in FIG. 13C), the insulating property Becomes higher.

  Therefore, the oxide of one embodiment of the present invention preferably has an atomic ratio shown by a region A in FIG. 13A which has a high carrier mobility and a tendency to form a layered structure with few grain boundaries.

  In addition, a region B illustrated in FIG. 13B indicates [In]: [M]: [Zn] = 4: 2: 3 to 4.1 and the vicinity thereof. The neighborhood value includes, for example, an atomic ratio of [In]: [M]: [Zn] = 5: 3: 4. The oxide having the atomic ratio shown in the region B is an excellent oxide having high crystallinity and high carrier mobility.

  Note that the conditions under which the oxide forms a layered structure are not uniquely determined by the atomic ratio. Depending on the atomic ratio, there is a difference in difficulty for forming a layered structure. On the other hand, even if the atomic ratio is the same, there may be a layered structure or a layered structure depending on the formation conditions. Therefore, the illustrated region is a region in which the oxide has an atomic ratio with a layered structure, and the boundaries between the regions A to C are not strict.

  Next, the case where the above oxide is used for a transistor will be described.

  Note that by using the above oxide for a transistor, carrier scattering and the like at grain boundaries can be reduced, so that a transistor with high field-effect mobility can be realized. In addition, a highly reliable transistor can be realized.

For the transistor, an oxide with low carrier density is preferably used. For example, the oxide has a carrier density of less than 8 × 10 ¹¹ / cm ³ , preferably less than 1 × 10 ¹¹ / cm ³ , more preferably less than 1 × 10 ¹⁰ / cm ³ , and 1 × 10 ⁻⁹ / cm 3. ^It may be ³ or more.

  Note that a high-purity intrinsic or substantially high-purity intrinsic oxide has few carrier generation sources, and thus can have a low carrier density. In addition, an oxide that is highly purified intrinsic or substantially highly purified intrinsic has a low defect level density and thus may have a low trap level density.

  In addition, the charge trapped in the trap level of the oxide takes a long time to disappear, and may behave as if it were a fixed charge. Therefore, a transistor in which a channel region is formed in an oxide having a high trap state density may have unstable electrical characteristics.

  Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the oxide. In order to reduce the impurity concentration in the oxide, it is preferable to reduce the impurity concentration in the adjacent film. Impurities include hydrogen, nitrogen, alkali metal, alkaline earth metal, iron, nickel, silicon, and the like.

  Here, the influence of each impurity in the oxide will be described.

In the oxide, when silicon or carbon which is one of Group 14 elements is included, a defect level is formed in the oxide. Therefore, the concentration of silicon and carbon in the oxide and the concentration of silicon and carbon in the vicinity of the interface with the oxide (concentration obtained by secondary ion mass spectrometry (SIMS)) are 2 × 10. ¹⁸ atoms / cm ³ or less, preferably 2 × 10 ¹⁷ atoms / cm ³ or less.

In addition, when the oxide contains an alkali metal or an alkaline earth metal, a defect level may be formed and carriers may be generated. Therefore, a transistor including an oxide containing an alkali metal or an alkaline earth metal is likely to be normally on. Therefore, it is preferable to reduce the concentration of alkali metal or alkaline earth metal in the oxide. Specifically, the concentration of alkali metal or alkaline earth metal in the oxide obtained by SIMS is set to 1 × 10 ¹⁸ atoms / cm ³ or less, preferably 2 × 10 ¹⁶ atoms / cm ³ or less.

In addition, when nitrogen is included in the oxide, electrons as carriers are generated, the carrier density is increased, and the oxide is likely to be n-type. As a result, a transistor in which an oxide containing nitrogen is used as a semiconductor is likely to be normally on. Therefore, in the oxide, it is preferable that nitrogen is reduced as much as possible. For example, the nitrogen concentration in the oxide is less than 5 × 10 ¹⁹ atoms / cm ³ , preferably 5 × 10 ¹⁸ atoms / cm ^{3 in} SIMS. cm ³ or less, more preferably 1 × 10 ¹⁸ atoms / cm ³ or less, and even more preferably 5 × 10 ¹⁷ atoms / cm ³ or less.

In addition, hydrogen contained in the oxide reacts with oxygen bonded to a metal atom to become water, so that oxygen vacancies may be formed in some cases. When hydrogen enters the oxygen vacancies, electrons serving as carriers may be generated. In addition, a part of hydrogen may be combined with oxygen bonded to a metal atom to generate electrons as carriers. Therefore, a transistor including an oxide containing hydrogen is likely to be normally on. For this reason, it is preferable that hydrogen in the oxide is reduced as much as possible. Specifically, in the oxide, the hydrogen concentration obtained by SIMS is less than 1 × 10 ²⁰ atoms / cm ³ , preferably less than 1 × 10 ¹⁹ atoms / cm ³ , more preferably 5 × 10 ¹⁸ atoms / cm ^3. Less than, more preferably less than 1 × 10 ¹⁸ atoms / cm ³ .

  By using an oxide in which impurities are sufficiently reduced for a channel formation region of a transistor, stable electric characteristics can be imparted.

  Subsequently, a case where the oxide has a two-layer structure or a three-layer structure will be described. FIG. 14 is used to describe the band diagram of the insulator in contact with the stacked structure of the oxide S1, the oxide S2, and the oxide S3 and the band diagram of the insulator in contact with the stacked structure of the oxide S2 and the oxide S3. explain.

  FIG. 14A illustrates an example of a band diagram in the film thickness direction of a stacked structure including the insulator I1, the oxide S1, the oxide S2, the oxide S3, and the insulator I2. FIG. 14B is an example of a band diagram in the film thickness direction of the stacked structure including the insulator I1, the oxide S2, the oxide S3, and the insulator I2. Note that the band diagram shows the energy level (Ec) at the lower end of the conduction band of the insulator I1, the oxide S1, the oxide S2, the oxide S3, and the insulator I2 for easy understanding.

  The oxide S1 and the oxide S3 have an energy level at the lower end of the conduction band closer to the vacuum level than the oxide S2. Typically, the energy level at the lower end of the conduction band of the oxide S2, and the oxide S1, The difference from the energy level at the lower end of the conduction band of the oxide S3 is preferably 0.15 eV or more, or 0.5 eV or more, and 2 eV or less, or 1 eV or less. That is, the difference between the electron affinity of the oxides S1 and S3 and the electron affinity of the oxide S2 is preferably 0.15 eV or more, or 0.5 eV or more, and 2 eV or less, or 1 eV or less.

  As shown in FIGS. 14A and 14B, in the oxide S1, the oxide S2, and the oxide S3, the energy level at the lower end of the conduction band changes gently. In other words, it can be said that it is continuously changed or continuously joined. In order to have such a band diagram, the density of defect states in the mixed layer formed at the interface between the oxide S1 and the oxide S2 or the interface between the oxide S2 and the oxide S3 is preferably low.

  Specifically, the oxide S1 and the oxide S2, and the oxide S2 and the oxide S3 have a common element other than oxygen (main component), thereby forming a mixed layer with a low density of defect states. be able to. For example, in the case where the oxide S2 is an In—Ga—Zn oxide, an In—Ga—Zn oxide, a Ga—Zn oxide, a gallium oxide, or the like may be used as the oxide S1 and the oxide S3.

  At this time, the main path of carriers is the oxide S2. Since the defect level density at the interface between the oxide S1 and the oxide S2 and the interface between the oxide S2 and the oxide S3 can be reduced, the influence on the carrier conduction due to interface scattering is small, and a high on-current is obtained. can get.

  When electrons are trapped in the trap level, the trapped electrons behave like fixed charges, so that the threshold voltage of the transistor shifts in the positive direction. By providing the oxide S1 and the oxide S3, the trap level can be kept away from the oxide S2. With this structure, the threshold voltage of the transistor can be prevented from shifting in the positive direction.

  As the oxide S1 and the oxide S3, a material having a sufficiently low conductivity as compared with the oxide S2 is used. At this time, the oxide S2, the interface between the oxide S2 and the oxide S1, and the interface between the oxide S2 and the oxide S3 mainly function as a channel region. For example, as the oxide S1 and the oxide S3, an oxide having an atomic ratio indicated by a region C in which the insulating property is increased in FIG. Note that a region C illustrated in FIG. 13C illustrates [In]: [M]: [Zn] = 0: 1: 0 or an atomic ratio that is a value in the vicinity thereof.

  In particular, when an oxide having an atomic ratio indicated by the region A is used for the oxide S2, the oxide S1 and the oxide S3 have an oxide [M] / [In] of 1 or more, preferably 2 or more. Is preferably used. In addition, as the oxide S3, it is preferable to use an oxide having [M] / ([Zn] + [In]) of 1 or more that can obtain sufficiently high insulation.

<Sputtering device>
Hereinafter, a parallel plate sputtering apparatus and a counter target sputtering apparatus according to one embodiment of the present invention will be described. As will be described later, in the film formation using the facing target sputtering apparatus, damage to the formation surface can be reduced, so that a film with high crystallinity is easily obtained. That is, in some cases, it is preferable to use a facing target sputtering apparatus for forming the CAAC-OS. Note that the sputtering apparatus described below is shown with a substrate, a target, and the like arranged in order to facilitate understanding or to explain operations during film formation. However, since the substrate, the target, and the like are things that a user installs, the sputtering apparatus according to one embodiment of the present invention may not have the substrate and the target.

  A film formation method using a parallel plate sputtering apparatus can also be called PESP (parallel electrode SP). In addition, a film formation method using an opposed target sputtering apparatus can also be referred to as a VDSP (vapor deposition SP).

  FIG. 15A is a cross-sectional view of a film formation chamber 601 which is a parallel plate type sputtering apparatus. A deposition chamber 601 illustrated in FIG. 15A includes a target holder 620, a backing plate 610, a target 600, a magnet unit 630, and a substrate holder 670. Note that the target 600 is disposed on the backing plate 610. In addition, the backing plate 610 is disposed on the target holder 620. In addition, the magnet unit 630 is disposed under the target 600 through the backing plate 610. Further, the substrate holder 670 is disposed to face the target 600. In this specification, a combination of a plurality of magnets (magnets) is called a magnet unit. The magnet unit can be called a cathode, a cathode magnet, a magnetic member, a magnetic component, or the like. The magnet unit 630 includes a magnet 630N, a magnet 630S, and a magnet holder 632. In the magnet unit 630, the magnet 630N and the magnet 630S are disposed on the magnet holder 632. Further, the magnet 630N is arranged at a distance from the magnet 630S. Note that when the substrate 660 is carried into the film formation chamber 601, the substrate 660 is disposed on the substrate holder 670.

  The target holder 620 and the backing plate 610 are fixed using screws (bolts or the like) and are equipotential. Further, the target holder 620 has a function of supporting the target 600 through the backing plate 610.

  Further, the target 600 is fixed to the backing plate 610. For example, the backing plate 610 and the target 600 can be fixed by a bonding material containing a low melting point metal such as indium.

  FIG. 15A shows magnetic lines of force 680 a and magnetic lines 680 b formed by the magnet unit 630.

  The magnetic force line 680 a is one of magnetic force lines that form a horizontal magnetic field in the vicinity of the upper surface of the target 600. The vicinity of the upper surface of the target 600 is, for example, a region having a vertical distance from the target 600 of 0 mm to 10 mm, particularly 0 mm to 5 mm.

  The magnetic force line 680b is one of magnetic force lines that form a horizontal magnetic field at a vertical distance d from the upper surface of the magnet unit 630. The vertical distance d is, for example, 0 mm or more and 20 mm or less, or 5 mm or more and 15 mm or less.

  At this time, by using the strong magnet 630N and the strong magnet 630S, a strong magnetic field can be generated even in the vicinity of the upper surface of the substrate 660. Specifically, the strength of the horizontal magnetic field on the upper surface of the substrate 660 can be set to 10G to 100G, preferably 15G to 60G, and more preferably 20G to 40G.

  Note that the horizontal magnetic field strength may be measured by measuring the value when the vertical magnetic field strength is 0G.

  By setting the strength of the magnetic field in the deposition chamber 601 to be in the above range, an oxide with high density and high crystallinity can be formed. In addition, the obtained oxide hardly contains a plurality of types of crystal phases, and becomes an oxide containing almost a single crystal phase.

  FIG. 15B shows a top view of the magnet unit 630. In the magnet unit 630, a circular or substantially circular magnet 630N and a circular or substantially circular magnet 630S are fixed to a magnet holder 632. Then, the magnet unit 630 can be rotated with the normal vector at the center or substantially the center on the upper surface of the magnet unit 630 as the rotation axis. For example, the magnet unit 630 may be rotated at a beat of 0.1 Hz to 1 kHz (in other words, rhythm, time signature, pulse, frequency, period, or cycle).

  Therefore, the strong magnetic field region on the target 600 changes as the magnet unit 630 rotates. Since the region having a strong magnetic field is a high-density plasma region, the sputtering phenomenon of the target 600 tends to occur in the vicinity thereof. For example, when a region having a strong magnetic field is a specific location, only a specific region of the target 600 is used. On the other hand, since the plasma 640 is generated between the target 600 and the substrate 660 by rotating the magnet unit 630 as shown in FIG. 15B, the target 600 can be used uniformly. Further, by rotating the magnet unit 630, a film having a uniform thickness and uniform quality can be formed.

  Further, by rotating the magnet unit 630, the direction of the lines of magnetic force on the upper surface of the substrate 660 can be changed.

  Note that although the example in which the magnet unit 630 is rotated is shown here, one embodiment of the present invention is not limited to this. For example, the magnet unit 630 may be swung up and down or / and left and right. For example, the magnet unit 630 may be swung with a beat of 0.1 Hz to 1 kHz. Alternatively, the target 600 may be rotated or moved. For example, the target 600 may be rotated or oscillated with a beat of 0.1 Hz to 1 kHz. Alternatively, the direction of the magnetic lines of force on the upper surface of the substrate 660 may be relatively changed by rotating the substrate 660. Or you may combine these.

  The film formation chamber 601 may have a water channel inside or below the backing plate 610. Then, by flowing a fluid (air, nitrogen, rare gas, water, oil, etc.) through the water channel, discharge abnormality due to a rise in the temperature of the target 600 during sputtering, damage to the film formation chamber 601 due to member deformation, and the like are suppressed. be able to. At this time, it is preferable that the backing plate 610 and the target 600 are brought into close contact with each other through a bonding material because cooling performance is improved.

  Note that it is preferable to provide a gasket between the target holder 620 and the backing plate 610 because impurities are unlikely to enter the film formation chamber 601 from the outside or a water channel.

  In the magnet unit 630, the magnet 630N and the magnet 630S are arranged with different poles facing the target 600 side. Here, a case will be described in which the magnet 630N is arranged so that the target 600 side has an N pole, and the magnet 630S is arranged so that the target 600 side has an S pole. However, the arrangement of magnets and poles in the magnet unit 630 is not limited to this arrangement. Further, the arrangement is not limited to that shown in FIG.

  During film formation, the potential V1 applied to the terminal V1 connected to the target holder 620 is lower than the potential V2 applied to the terminal V2 connected to the substrate holder 670, for example. The potential V2 applied to the terminal V2 connected to the substrate holder 670 is, for example, a ground potential. The potential V3 applied to the terminal V3 connected to the magnet holder 632 is, for example, a ground potential. Note that the potential applied to the terminal V1, the terminal V2, and the terminal V3 is not limited to the above potential. Further, the potential may not be applied to all of the target holder 620, the substrate holder 670, and the magnet holder 632. For example, the substrate holder 670 may be electrically floating. Note that FIG. 15A illustrates an example of a so-called DC sputtering method in which the potential V1 is applied to the terminal V1 connected to the target holder 620; however, one embodiment of the present invention is not limited thereto. For example, a so-called RF sputtering method in which a high-frequency power source having a frequency of 13.56 MHz or 27.12 MHz is connected to the target holder 620 may be used.

  FIG. 15A illustrates an example in which the backing plate 610 and the target holder 620 are not electrically connected to the magnet unit 630 and the magnet holder 632, but the present invention is not limited to this. For example, the backing plate 610 and the target holder 620, the magnet unit 630, and the magnet holder 632 may be electrically connected and may be equipotential.

  Further, the temperature of the substrate 660 may be increased in order to further increase the crystallinity of the obtained oxide. By increasing the temperature of the substrate 660, migration of sputtered particles on the upper surface of the substrate 660 can be promoted. Therefore, an oxide with higher density and higher crystallinity can be formed. Note that the temperature of the substrate 660 may be, for example, 100 ° C to 450 ° C, preferably 150 ° C to 400 ° C, and more preferably 170 ° C to 350 ° C.

  Also, if the oxygen partial pressure in the deposition gas is too high, oxides containing multiple types of crystal phases are likely to be deposited, so the deposition gas can be a rare gas such as argon (in addition to helium, neon, krypton, xenon). Etc.) and oxygen are preferably used. For example, the proportion of oxygen in the whole may be less than 50% by volume, preferably 33% by volume or less, more preferably 20% by volume or less, more preferably 15% by volume or less.

  The vertical distance between the target 600 and the substrate 660 is 10 mm to 600 mm, preferably 20 mm to 400 mm, more preferably 30 mm to 200 mm, and more preferably 40 mm to 100 mm. By reducing the vertical distance between the target 600 and the substrate 660 to the above-described range, a decrease in energy before the sputtered particles reach the substrate 660 may be suppressed. Further, by increasing the vertical distance between the target 600 and the substrate 660 to the above range, the incident direction of the sputtered particles to the substrate 660 can be made closer to the vertical, so that the damage to the substrate 660 due to the collision of the sputtered particles is reduced. Sometimes it can be made smaller.

  FIG. 16A illustrates an example of a deposition chamber which is different from that in FIG.

  A deposition chamber 601 illustrated in FIG. 16A includes a target holder 620a, a target holder 620b, a backing plate 610a, a backing plate 610b, a target 600a, a target 600b, a magnet unit 630a, and a magnet unit 630b. , A member 642 and a substrate holder 670. The target 600a is disposed on the backing plate 610a. The backing plate 610a is disposed on the target holder 620a. Moreover, the magnet unit 630a is arrange | positioned under the target 600a via the backing plate 610a. The target 600b is disposed on the backing plate 610b. The backing plate 610b is disposed on the target holder 620b. Moreover, the magnet unit 630b is arrange | positioned under the target 600b via the backing plate 610b.

  The magnet unit 630a includes a magnet 630N1, a magnet 630N2, a magnet 630S, and a magnet holder 632. In the magnet unit 630a, the magnet 630N1, the magnet 630N2, and the magnet 630S are disposed on the magnet holder 632. Further, the magnet 630N1 and the magnet 630N2 are arranged with a gap from the magnet 630S. The magnet unit 630b has the same structure as the magnet unit 630a. Note that when the substrate 660 is carried into the film formation chamber 601, the substrate 660 is disposed on the substrate holder 670.

  The target 600a, the backing plate 610a, and the target holder 620a are separated from the target 600b, the backing plate 610b, and the target holder 620b by a member 642. Note that the member 642 is preferably an insulator. However, the member 642 may be a conductor or a semiconductor. Further, the member 642 may be a conductor or semiconductor whose surface is covered with an insulator.

  The target holder 620a and the backing plate 610a are fixed using screws (bolts or the like) and are equipotential. Further, the target holder 620a has a function of supporting the target 600a via the backing plate 610a. In addition, the target holder 620b and the backing plate 610b are fixed using screws (bolts or the like) and are equipotential. Further, the target holder 620b has a function of supporting the target 600b via the backing plate 610b.

  The backing plate 610a has a function of fixing the target 600a. Further, the backing plate 610b has a function of fixing the target 600b.

  FIG. 16A shows a magnetic force line 680a and a magnetic force line 680b formed by the magnet unit 630a.

  The magnetic force line 680a is one of magnetic force lines that form a horizontal magnetic field in the vicinity of the upper surface of the target 600a. The vicinity of the upper surface of the target 600a is, for example, a region where the vertical distance from the target 600a is 0 mm to 10 mm, particularly 0 mm to 5 mm.

  The magnetic force line 680b is one of magnetic force lines that form a horizontal magnetic field at a vertical distance d from the upper surface of the magnet unit 630a. The vertical distance d is, for example, 0 mm or more and 20 mm or less, or 5 mm or more and 15 mm or less.

  At this time, a strong magnetic field can be generated even in the vicinity of the upper surface of the substrate 660 by using the strong magnet 630N1, the magnet 630N2, and the strong magnet 630S. Specifically, the strength of the horizontal magnetic field on the upper surface of the substrate 660 can be set to 10G to 100G, preferably 15G to 60G, and more preferably 20G to 40G.

  By setting the strength of the magnetic field in the deposition chamber 601 to be in the above range, an oxide with high density and high crystallinity can be formed. In addition, the obtained oxide hardly contains a plurality of types of crystal phases, and becomes an oxide containing almost a single crystal phase.

  The magnet unit 630b also has the same lines of magnetic force as the magnet unit 630a.

  FIG. 16B shows a top view of the magnet unit 630a and the magnet unit 630b. It can be seen that the magnet unit 630 a has a rectangular or substantially rectangular magnet 630 N 1, a rectangular or substantially rectangular magnet 630 N 2, and a rectangular or substantially rectangular magnet 630 S fixed to the magnet holder 632. Then, the magnet unit 630a can be swung left and right as shown in FIG. For example, the magnet unit 630a may be swung with a beat of 0.1 Hz to 1 kHz.

  Therefore, the region where the magnetic field is strong on the target 600a changes as the magnet unit 630a swings. Since the region having a strong magnetic field is a high-density plasma region, the sputtering phenomenon of the target 600a tends to occur in the vicinity thereof. For example, when a region having a strong magnetic field is a specific location, only a specific region of the target 600a is used. On the other hand, since the plasma 640 is generated between the target 600a and the substrate 660 by swinging the magnet unit 630a as shown in FIG. 16B, the target 600a can be used uniformly. Further, a film having a uniform thickness and quality can be formed by swinging the magnet unit 630a.

  Further, the state of the magnetic lines of force on the upper surface of the substrate 660 can be changed by swinging the magnet unit 630a. The same applies to the magnet unit 630b.

  Note that although the example in which the magnet unit 630a and the magnet unit 630b are swung is shown here, one embodiment of the present invention is not limited thereto. For example, the magnet unit 630a and the magnet unit 630b may be rotated. For example, the magnet unit 630a and the magnet unit 630b may be rotated at a beat of 0.1 Hz to 1 kHz. Alternatively, the target 600 may be rotated or moved. For example, the target 600 may be rotated or oscillated with a beat of 0.1 Hz to 1 kHz. Alternatively, the state of the lines of magnetic force on the upper surface of the substrate 660 can be relatively changed by rotating the substrate 660. Alternatively, these may be combined.

  The film formation chamber 601 may have a water channel inside or below the backing plate 610a and the backing plate 610b. Then, by causing fluid (air, nitrogen, rare gas, water, oil, etc.) to flow through the water channel, abnormal discharge due to a rise in temperature of the target 600a and the target 600b during sputtering, damage to the film formation chamber 601 due to deformation of members, and the like. Can be suppressed. At this time, it is preferable that the backing plate 610a and the target 600a are in close contact with each other through a bonding material because the cooling performance is improved. In addition, it is preferable that the backing plate 610b and the target 600b are in close contact with each other through a bonding material because the cooling performance is improved.

  Note that it is preferable to provide a gasket between the target holder 620a and the backing plate 610a because impurities are less likely to enter the film formation chamber 601 from the outside or a water channel. In addition, it is preferable to provide a gasket between the target holder 620b and the backing plate 610b because impurities hardly enter the film formation chamber 601 from the outside or a water channel.

  In the magnet unit 630a, the magnet 630N1, the magnet 630N2, and the magnet 630S are arranged with different poles facing the target 600a. Here, a case will be described in which the magnet 630N1 and the magnet 630N2 are arranged so that the target 600a side has an N pole, and the magnet 630S is arranged so that the target 600a side has an S pole. However, the arrangement of the magnets and poles in the magnet unit 630a is not limited to this arrangement. Further, the arrangement is not limited to that shown in FIG. The same applies to the magnet unit 630b.

  At the time of film formation, a potential at which the level is alternately switched may be applied between the terminal V1 connected to the target holder 620a and the terminal V4 connected to the target holder 620b. The potential V2 applied to the terminal V2 connected to the substrate holder 670 is, for example, a ground potential. The potential V3 applied to the terminal V3 connected to the magnet holder 632 is, for example, a ground potential. Note that the potential applied to the terminal V1, the terminal V2, the terminal V3, and the terminal V4 is not limited to the above potential. In addition, the potential may not be applied to all of the target holder 620a, the target holder 620b, the substrate holder 670, and the magnet holder 632. For example, the substrate holder 670 may be electrically floating. In FIG. 16A, an example of a so-called AC sputtering method in which a potential that alternates between high and low is applied between a terminal V1 connected to the target holder 620a and a terminal V4 connected to the target holder 620b. Although shown, one embodiment of the present invention is not limited thereto.

  FIG. 16A shows an example in which the backing plate 610a and the target holder 620a are not electrically connected to the magnet unit 630a and the magnet holder 632, but the present invention is not limited to this. For example, the backing plate 610a and the target holder 620a, and the magnet unit 630a and the magnet holder 632 may be electrically connected and may be equipotential. Further, although the example in which the backing plate 610b and the target holder 620b are not electrically connected to the magnet unit 630b and the magnet holder 632 has been shown, the present invention is not limited to this. For example, the backing plate 610a and the target holder 620b, the magnet unit 630b, and the magnet holder 632 are electrically connected and may be equipotential.

  Further, the temperature of the substrate 660 may be increased in order to further increase the crystallinity of the obtained oxide. By increasing the temperature of the substrate 660, migration of sputtered particles on the upper surface of the substrate 660 can be promoted. Therefore, an oxide with higher density and higher crystallinity can be formed. Note that the temperature of the substrate 660 may be, for example, 100 ° C to 450 ° C, preferably 150 ° C to 400 ° C, and more preferably 170 ° C to 350 ° C.

  Also, if the oxygen partial pressure in the deposition gas is too high, oxides containing multiple types of crystal phases are likely to be deposited, so the deposition gas can be a rare gas such as argon (in addition to helium, neon, krypton, xenon). Etc.) and oxygen are preferably used. For example, the proportion of oxygen in the whole may be less than 50% by volume, preferably 33% by volume or less, more preferably 20% by volume or less, more preferably 15% by volume or less.

  In addition, the vertical distance between the target 600a and the substrate 660 is 10 mm to 600 mm, preferably 20 mm to 400 mm, more preferably 30 mm to 200 mm, and more preferably 40 mm to 100 mm. By reducing the vertical distance between the target 600a and the substrate 660 to the above-described range, a decrease in energy before the sputtered particles reach the substrate 660 may be suppressed. Further, by increasing the vertical distance between the target 600a and the substrate 660 to the above range, the incident direction of the sputtered particles to the substrate 660 can be made closer to the vertical, so that damage to the substrate 660 due to the collision of the sputtered particles is reduced. Sometimes it can be made smaller.

  The vertical distance between the target 600b and the substrate 660 is 10 mm to 600 mm, preferably 20 mm to 400 mm, more preferably 30 mm to 200 mm, and more preferably 40 mm to 100 mm. By reducing the vertical distance between the target 600b and the substrate 660 to the above-described range, a decrease in energy before the sputtered particles reach the substrate 660 may be suppressed. Further, by increasing the vertical distance between the target 600b and the substrate 660 to the above-described range, the incident direction of the sputtered particles to the substrate 660 can be made closer to the vertical, so that damage to the substrate 660 due to the collision of the sputtered particles can be reduced. Sometimes it can be made smaller.

  FIG. 17A illustrates an example of a cross-sectional view of a deposition chamber which is different from FIGS. 15A and 16A. FIG. 17A illustrates an opposed target sputtering apparatus.

  FIG. 17A is a schematic cross-sectional view of a film formation chamber in a sputtering apparatus. 17A includes a target 600a and a target 600b, a backing plate 610a and a backing plate 610b that respectively hold the target 600a and the target 600b, and the target 600a and the backing plate 610b via the backing plate 610a and the backing plate 610b. The magnet unit 630a and the magnet unit 630b are disposed on the back surface of the target 600b. The substrate holder 670 is disposed between the target 600a and the target 600b. The substrate holder 670 is disposed above an area (also referred to as an inter-target area) between the target 600a and the target 600b. Note that when the substrate 660 is placed in the film formation chamber, the substrate 660 is fixed by the substrate holder 670.

  Further, as shown in FIG. 17A, the substrate holder 670 is disposed on the upper side of the inter-target region, but may be disposed on the lower side. Moreover, you may arrange | position on the lower side and the upper side. By disposing the substrate holders 670 on the lower side and the upper side, two or more substrates can be simultaneously formed, so that productivity can be improved.

  As shown in FIG. 17A, a power source 690 and a power source 691 for applying a potential are connected to the backing plate 610a and the backing plate 610b. It is preferable to use a so-called AC power source in which a potential at which the potential level is alternately switched is applied between a power source 690 connected to the backing plate 610a and a power source 691 connected to the backing plate 610b. Moreover, although the power supply 690 and the power supply 691 which are shown to FIG. 17 (A) have shown the example using AC power supply, it is not restricted to this. For example, an RF power source, a DC power source, or the like may be used as the power source 690 and the power source 691. Alternatively, different types of power sources may be used for the power source 690 and the power source 691.

  The substrate holder 670 is preferably connected to GND. Further, the substrate holder 670 may be in a floating state.

  FIGS. 17B and 17C illustrate the potential distribution of the plasma 640 between the dashed-dotted line AB in FIG. 17A. The potential distribution shown in FIG. 17B shows a state in which a high potential is applied to the backing plate 610a and a low potential is applied to the backing plate 610b. That is, positive ions are accelerated toward the target 600b. The potential distribution shown in FIG. 17C shows a state in which a low potential is applied to the backing plate 610a and a high potential is applied to the backing plate 610b. That is, positive ions are accelerated toward the target 600a. Film formation can be performed so that the states shown in FIGS. 17B and 17C are alternately switched.

  In the configuration illustrated in FIG. 17A, the target 600a and the target 600b are arranged to face each other in parallel. In addition, the magnet unit 630a and the magnet unit 630b are arranged so that different poles of the magnet face each other. At this time, the lines of magnetic force are directed from the magnet unit 630b to the magnet unit 630a. Therefore, at the time of film formation, the plasma 640 is confined in the magnetic field formed by the magnet unit 630a and the magnet unit 630b. Therefore, the substrate holder 670 and the substrate 660 are located outside the plasma 640. Since the substrate 660 is not exposed to the high electric field region of the plasma 640, damage due to the plasma 640 can be reduced.

  The facing target sputtering apparatus can stably generate plasma even in a high vacuum. For example, film formation is possible even at 0.005 Pa or more and 0.09 Pa or less. Therefore, the concentration of impurities mixed during film formation can be reduced.

  By using an opposed target sputtering apparatus, a film can be formed at a high vacuum, and a film can be formed with little damage by plasma. Therefore, even when the temperature of the substrate 660 is low, a highly crystalline film can be formed. A film can be formed. For example, a film with high crystallinity can be formed even when the temperature of the substrate 660 is 10 ° C. or higher and lower than 100 ° C.

  The configuration illustrated in FIG. 18A is different from the configuration illustrated in FIG. 17A in that the target 600a and the target 600b are not parallel but are disposed to face each other in an inclined state (in a V shape). . Therefore, the description of FIG. 17A is referred to except for the arrangement of the target. Further, the magnet unit 630a and the magnet unit 630b are arranged so that different poles face each other. The substrate holder 670 and the substrate 660 are disposed on the inter-target region. By arranging the target 600a and the target 600b as shown in FIG. 18A, the ratio of sputtered particles reaching the substrate 660 increases, so that the deposition rate can be increased.

  FIG. 18B illustrates another example of a counter target sputtering apparatus.

  FIG. 18B is a schematic cross-sectional view of a film formation chamber in the facing target sputtering apparatus. Unlike the film formation chamber illustrated in FIG. 17A, a target shield 622 and a target shield 623 are provided. Further, the power supply 691 is connected to the backing plate 610a and the backing plate 610b. The substrate holder 670 is disposed above the inter-target region. Accordingly, since the substrate 660 is not exposed to the high electric field region of the plasma 640, damage due to the plasma 640 can be reduced.

  Further, as shown in FIG. 18B, the substrate holder 670 is arranged on the upper side of the inter-target region, but may be arranged on the lower side. Moreover, you may arrange | position on the lower side and the upper side. By disposing the substrate holders 670 on the lower side and the upper side, two or more substrates can be simultaneously formed, so that productivity can be improved.

  As shown in FIG. 18B, the target shield 622 and the target shield 623 are connected to GND. That is, the plasma 640 is formed by the potential difference applied between the backing plate 610a and the backing plate 610b to which the potential of the power source 691 is applied and the target shield 622 and the target shield 623 to which GND is applied.

  The counter target sputtering apparatus described above can reduce plasma damage to the substrate because the plasma is confined to the magnetic field between the targets. Further, since the incident angle of the sputtered particles on the substrate can be made shallow by the inclination of the target, the step coverage of the deposited film can be improved. In addition, since film formation in a high vacuum is possible, the concentration of impurities mixed in the film can be reduced.

  Note that a parallel plate sputtering apparatus or an ion beam sputtering apparatus may be applied to the film formation chamber.

<Deposition system>
Hereinafter, a film formation apparatus including a film formation chamber in which the sputtering target according to one embodiment of the present invention can be installed is described.

  First, a structure of a film formation apparatus in which impurities are hardly mixed in a film during film formation will be described with reference to FIGS.

  FIG. 19 schematically shows a top view of a single-wafer multi-chamber film forming apparatus 2700. The film formation apparatus 2700 includes an atmosphere-side substrate supply chamber 2701 that includes a cassette port 2761 that accommodates a substrate and an alignment port 2762 that aligns the substrate, and an atmosphere-side substrate that transports the substrate from the atmosphere-side substrate supply chamber 2701. A transfer chamber 2702, a load lock chamber 2703a for carrying in a substrate and changing the pressure in the chamber from atmospheric pressure to reduced pressure, or switching from reduced pressure to atmospheric pressure, a substrate for carrying out the substrate, and reducing the pressure in the chamber from reduced pressure to atmospheric pressure. Alternatively, an unload lock chamber 2703b for switching from atmospheric pressure to reduced pressure, a transfer chamber 2704 for transferring a substrate in a vacuum, a substrate heating chamber 2705 for heating the substrate, and a film formation chamber 2706a for forming a film with a target disposed. A film formation chamber 2706b and a film formation chamber 2706c. Note that the above-described structure of the film formation chamber can be referred to for the film formation chamber 2706a, the film formation chamber 2706b, and the film formation chamber 2706c.

  The atmosphere-side substrate transfer chamber 2702 is connected to the load lock chamber 2703a and the unload lock chamber 2703b, the load lock chamber 2703a and the unload lock chamber 2703b are connected to the transfer chamber 2704, and the transfer chamber 2704 is heated to the substrate. The chamber 2705, the film formation chamber 2706a, the film formation chamber 2706b, and the film formation chamber 2706c are connected.

  Note that a gate valve 2764 is provided at a connection portion of each chamber, and each chamber can be kept in a vacuum state independently of the atmosphere-side substrate supply chamber 2701 and the atmosphere-side substrate transfer chamber 2702. In addition, the atmosphere-side substrate transfer chamber 2702 and the transfer chamber 2704 have a transfer robot 2763 and can transfer a substrate.

  The substrate heating chamber 2705 is preferably used also as a plasma processing chamber. The film formation apparatus 2700 can transport the substrate between the processes without being exposed to the atmosphere, and thus can suppress the adsorption of impurities to the substrate. In addition, the order of film formation and heat treatment can be established freely. Note that the number of transfer chambers, film formation chambers, load lock chambers, unload lock chambers, and substrate heating chambers is not limited to the above-described numbers, and an optimal number can be provided as appropriate in accordance with installation space and process conditions.

  Next, FIG. 20 shows a cross section corresponding to one-dot chain line X1-X2, one-dot chain line Y1-Y2, and one-dot chain line Y2-Y3 shown in FIG.

  FIG. 20A illustrates a cross section of the substrate heating chamber 2705 and the transfer chamber 2704. The substrate heating chamber 2705 includes a plurality of heating stages 2765 that can accommodate substrates. Note that the substrate heating chamber 2705 is connected to a vacuum pump 2770 through a valve. As the vacuum pump 2770, for example, a dry pump, a mechanical booster pump, or the like can be used.

  As a heating mechanism that can be used for the substrate heating chamber 2705, for example, a heating mechanism that heats using a resistance heating element or the like may be used. Alternatively, a heating mechanism that heats by heat conduction or heat radiation from a medium such as a heated gas may be used. For example, RTA (Rapid Thermal Anneal) such as GRTA (Gas Rapid Thermal Anneal) and LRTA (Lamp Rapid Thermal Anneal) can be used. LRTA heats an object to be processed by radiation of light (electromagnetic waves) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high pressure sodium lamp, or a high pressure mercury lamp. GRTA performs heat treatment using a high-temperature gas. An inert gas is used as the gas.

  The substrate heating chamber 2705 is connected to a purifier 2781 via a mass flow controller 2780. Note that the mass flow controller 2780 and the purifier 2781 are provided as many as the number of gas types, but only one is shown for easy understanding. As the gas introduced into the substrate heating chamber 2705, a gas having a dew point of −80 ° C. or lower, preferably −100 ° C. or lower can be used. For example, oxygen gas, nitrogen gas, and rare gas (such as argon gas) can be used. Use.

The transfer chamber 2704 has a transfer robot 2863. The transfer robot 2763 can transfer a substrate to each chamber. The transfer chamber 2704 is connected to a vacuum pump 2770 and a cryopump 2771 through valves. With such a configuration, the transfer chamber 2704 is evacuated using a vacuum pump 2770 from atmospheric pressure to low vacuum or medium vacuum (about 0.1 to several hundred Pa), and the valve is switched to switch from medium vacuum to high vacuum. A vacuum or ultra-high vacuum (0.1 Pa to 1 × 10 ⁻⁷ Pa) is exhausted using a cryopump 2771.

  For example, two or more cryopumps 2771 may be connected in parallel to the transfer chamber 2704. With such a configuration, even if one cryopump is being regenerated, the remaining cryopump can be used to exhaust. In addition, the regeneration mentioned above refers to the process which discharge | releases the molecule | numerator (or atom) accumulated in the cryopump. The cryopump is periodically regenerated because the exhaust capacity is reduced if molecules (or atoms) are accumulated too much.

  FIG. 20B illustrates a cross section of the deposition chamber 2706b, the transfer chamber 2704, and the load lock chamber 2703a.

  Here, the details of the film formation chamber (sputtering chamber) will be described with reference to FIG. A film formation chamber 2706b illustrated in FIG. 20B includes a target 2766a, a target 2766b, a target shield 2767a, a target shield 2767b, a magnet unit 2790a, a magnet unit 2790b, a substrate holder 2768, a power supply 2791, Have Although not shown, the target 2766a and the target 2766b are each fixed to a target holder via a backing plate. A power source 2791 is electrically connected to the target 2766a and the target 2766b. Magnet unit 2790a and magnet unit 2790b are arranged on the back of target 2766a and target 2766b, respectively. Target shield 2767a and target shield 2767b are arranged to surround the ends of target 2766a and target 2766b, respectively. Here, a substrate 2769 is supported by the substrate holder 2768. The substrate holder 2768 is fixed to the film formation chamber 2706b through the variable member 2784. The substrate holder 2768 can be moved by the variable member 2784. The substrate holder 2768 is disposed above an area between the targets 2766a and 2766b (also referred to as an inter-target area). For example, by placing the substrate holder 2768 supporting the substrate 2769 on the upper side of the inter-target region, damage due to plasma can be reduced. Although not shown, the substrate holder 2768 may include a substrate holding mechanism that holds the substrate 2769, a heater that heats the substrate 2769 from the back surface, and the like.

  As shown in FIG. 20B, the substrate holder 2768 is arranged on the upper side of the inter-target region, but may be arranged on the lower side. Moreover, you may arrange | position on the lower side and the upper side. By disposing the substrate holder 2768 on the lower side and the upper side, two or more substrates can be formed at the same time, so that productivity can be improved.

  Further, the target shield 2767 can suppress deposition of particles sputtered from the target 2766 in an unnecessary region. The target shield 2767 is desirably processed so that accumulated sputtered particles do not peel off. For example, blast treatment for increasing the surface roughness, or unevenness may be provided on the surface of the target shield 2767.

  In addition, the film formation chamber 2706b is connected to the mass flow controller 2780 via the gas heating mechanism 2782, and the gas heating mechanism 2784 is connected to the purifier 2781 via the mass flow controller 2780. With the gas heating mechanism 2782, the gas introduced into the deposition chamber 2706b can be heated to 40 ° C. or higher and 400 ° C. or lower. Note that the gas heating mechanism 2782, the mass flow controller 2780, and the purifier 2781 are provided as many as the number of gas types, but only one is shown for easy understanding. As the gas introduced into the film formation chamber 2706b, a gas having a dew point of −80 ° C. or lower, preferably −100 ° C. or lower can be used. For example, oxygen gas, nitrogen gas, and a rare gas (such as argon gas) are used. Use.

  Note that in the case where a purifier is provided immediately before the gas inlet, the length of the pipe from the purifier to the film formation chamber 2706b is 10 m or less, preferably 5 m or less, and more preferably 1 m or less. By setting the length of the pipe to 10 m or less, 5 m or less, or 1 m or less, the influence of the gas released from the pipe can be reduced according to the length. Further, a metal pipe whose inside is covered with iron fluoride, aluminum oxide, chromium oxide or the like may be used for the gas pipe. The above-described piping has a smaller amount of gas containing impurities compared to, for example, SUS316L-EP piping, and can reduce the entry of impurities into the gas. Moreover, it is good to use a high performance ultra-small metal gasket joint (UPG joint) for the joint of piping. In addition, it is preferable that the pipes are all made of metal, because the influence of the generated released gas and external leakage can be reduced as compared with the case where resin or the like is used.

  The film formation chamber 2706b is connected to a turbo molecular pump 2772 and a vacuum pump 2770 through valves.

  The film formation chamber 2706b is provided with a cryotrap 2751.

  The cryotrap 2751 is a mechanism that can adsorb molecules (or atoms) having a relatively high melting point such as water. The turbo molecular pump 2772 stably exhausts large-sized molecules (or atoms) and has a low maintenance frequency, so that it is excellent in productivity, but has a low exhaust capability of hydrogen or water. Therefore, a cryotrap 2751 is connected to the film formation chamber 2706b in order to increase the exhaust capability of water or the like. The temperature of the cryotrap 2751 refrigerator is 100K or less, preferably 80K or less. Further, in the case where the cryotrap 2751 has a plurality of refrigerators, it is preferable to change the temperature for each refrigerator because exhaust can be efficiently performed. For example, the temperature of the first stage refrigerator may be 100K or less, and the temperature of the second stage refrigerator may be 20K or less. In some cases, a higher vacuum can be achieved by using a titanium sublimation pump instead of the cryotrap. In some cases, an even higher vacuum can be achieved by using an ion pump instead of the cryopump or the turbo molecular pump.

  Note that the exhaust method of the film formation chamber 2706b is not limited thereto, and a structure similar to the exhaust method (exhaust method of a cryopump and a vacuum pump) described in the above transfer chamber 2704 may be employed. Needless to say, the evacuation method of the transfer chamber 2704 may have a configuration similar to that of the film formation chamber 2706b (evacuation method using a turbo molecular pump and a vacuum pump).

  Note that the back pressure (total pressure) of the transfer chamber 2704, the substrate heating chamber 2705, and the film formation chamber 2706b, and the partial pressure of each gas molecule (atom) are preferably as follows. In particular, since impurities may be mixed into the formed film, it is necessary to pay attention to the back pressure of the film formation chamber 2706b and the partial pressure of each gas molecule (atom).

The back pressure (total pressure) of each chamber described above is 1 × 10 ⁻⁴ Pa or less, preferably 3 × 10 ⁻⁵ Pa or less, and more preferably 1 × 10 ⁻⁵ Pa or less. The partial pressure of gas molecules (atoms) having a mass-to-charge ratio (m / z) of 18 in each chamber described above is 3 × 10 ⁻⁵ Pa or less, preferably 1 × 10 ⁻⁵ Pa or less, more preferably 3 ×. 10 ⁻⁶ Pa or less. Moreover, the partial pressure of the gas molecule (atom) whose m / z of each chamber is 28 is 3 × 10 ⁻⁵ Pa or less, preferably 1 × 10 ⁻⁵ Pa or less, more preferably 3 × 10 ^−6. Pa or less. Moreover, the partial pressure of the gas molecule (atom) whose m / z of each chamber is 44 is 3 × 10 ⁻⁵ Pa or less, preferably 1 × 10 ⁻⁵ Pa or less, more preferably 3 × 10 ^−6. Pa or less.

  In addition, the total pressure and partial pressure in a vacuum chamber can be measured using a mass spectrometer. For example, a quadrupole mass spectrometer (also referred to as Q-mass) Qulee CGM-051 manufactured by ULVAC, Inc. may be used.

  In addition, the transfer chamber 2704, the substrate heating chamber 2705, and the film formation chamber 2706b described above preferably have a structure with little external or internal leakage.

For example, the leakage rate of the transfer chamber 2704, the substrate heating chamber 2705, and the film formation chamber 2706b described above is 3 × 10 ⁻⁶ Pa · m ³ / s or less, preferably 1 × 10 ⁻⁶ Pa · m ³ / s or less. It is. The leak rate of gas molecules (atoms) having an m / z of 18 is 1 × 10 ⁻⁷ Pa · m ³ / s or less, preferably 3 × 10 ⁻⁸ Pa · m ³ / s or less. The leak rate of gas molecules (atoms) having an m / z of 28 is 1 × 10 ⁻⁵ Pa · m ³ / s or less, preferably 1 × 10 ⁻⁶ Pa · m ³ / s or less. Further, the leak rate of gas molecules (atoms) having an m / z of 44 is 3 × 10 ⁻⁶ Pa · m ³ / s or less, preferably 1 × 10 ⁻⁶ Pa · m ³ / s or less.

  The leak rate may be derived from the total pressure and partial pressure measured using the mass spectrometer described above.

  The leak rate depends on the external leak and the internal leak. An external leak is a gas flowing from outside the vacuum system due to a minute hole or a seal failure. The internal leak is caused by leakage from a partition such as a valve in the vacuum system or gas released from an internal member. In order to make the leak rate below the above-mentioned numerical value, it is necessary to take measures from both the external leak and the internal leak.

  For example, the open / close portion of the film formation chamber 2706b may be sealed with a metal gasket. The metal gasket is preferably a metal covered with iron fluoride, aluminum oxide, or chromium oxide. Metal gaskets have higher adhesion than O-rings and can reduce external leakage. In addition, by using the passivation of a metal covered with iron fluoride, aluminum oxide, chromium oxide, or the like, emission gas containing impurities released from the metal gasket can be suppressed, and internal leakage can be reduced.

  Further, aluminum, chromium, titanium, zirconium, nickel, or vanadium that emits less impurities and contains less impurities is used as a member that forms the film formation apparatus 2700. Further, the above-described member may be used by being coated with an alloy containing iron, chromium, nickel and the like. Alloys containing iron, chromium, nickel, etc. are rigid, heat resistant and suitable for processing. Here, if the surface irregularities of the member are reduced by polishing or the like in order to reduce the surface area, the emitted gas can be reduced.

  Alternatively, the member of the film formation apparatus 2700 described above may be covered with iron fluoride, aluminum oxide, chromium oxide, or the like.

  The member of the film forming apparatus 2700 is preferably made of only metal as much as possible. For example, when a viewing window made of quartz or the like is installed, the surface is made of iron fluoride, aluminum oxide, It is good to coat thinly with chromium oxide.

  The adsorbate present in the film forming chamber does not affect the pressure in the film forming chamber because it is adsorbed on the inner wall or the like, but causes gas emission when the film forming chamber is exhausted. Therefore, although there is no correlation between the leak rate and the exhaust speed, it is important to desorb the adsorbate present in the film formation chamber as much as possible and exhaust it in advance using a pump having a high exhaust capability. Note that the deposition chamber may be baked to promote desorption of the adsorbate. Baking can increase the desorption rate of the adsorbate by about 10 times. Baking may be performed at 100 ° C to 450 ° C. At this time, if the adsorbate is removed while introducing the inert gas into the film formation chamber, the desorption rate of water or the like that is difficult to desorb only by exhausting can be further increased. In addition, by heating the inert gas to be introduced to the same degree as the baking temperature, the desorption rate of the adsorbate can be further increased. Here, it is preferable to use a rare gas as the inert gas. Further, depending on the type of film to be formed, oxygen or the like may be used instead of the inert gas. For example, when an oxide film is formed, it may be preferable to use oxygen which is a main component. Note that baking is preferably performed using a lamp.

  Alternatively, it is preferable to perform a process of increasing the pressure in the deposition chamber by introducing an inert gas such as a heated rare gas or oxygen, and exhausting the deposition chamber again after a predetermined time. By introducing the heated gas, the adsorbate in the deposition chamber can be desorbed, and impurities present in the deposition chamber can be reduced. In addition, it is effective when this treatment is repeated 2 times or more and 30 times or less, preferably 5 times or more and 15 times or less. Specifically, by introducing an inert gas or oxygen having a temperature of 40 ° C. or higher and 400 ° C. or lower, preferably 50 ° C. or higher and 200 ° C. or lower, the pressure in the deposition chamber is 0.1 Pa or higher and 10 kPa or lower, preferably The pressure may be 1 Pa or more and 1 kPa or less, more preferably 5 Pa or more and 100 Pa or less, and the period for maintaining the pressure may be 1 minute or more and 300 minutes or less, preferably 5 minutes or more and 120 minutes or less. After that, the film formation chamber is evacuated for a period of 5 minutes to 300 minutes, preferably 10 minutes to 120 minutes.

  Further, the desorption rate of the adsorbate can be further increased by performing dummy film formation. Dummy film formation is performed by depositing a film on the dummy substrate by sputtering or the like, thereby depositing a film on the dummy substrate and the inner wall of the film forming chamber, and depositing impurities on the film forming chamber and adsorbed material on the inner wall of the film forming film. It means confining inside. The dummy substrate is preferably a substrate that emits less gas. By performing dummy film formation, the impurity concentration in a film to be formed later can be reduced. The dummy film formation may be performed simultaneously with baking.

  Next, details of the transfer chamber 2704 and the load lock chamber 2703a illustrated in FIG. 20B and the atmosphere-side substrate transfer chamber 2702 and the atmosphere-side substrate supply chamber 2701 illustrated in FIG. 20C will be described below. Note that FIG. 20C illustrates a cross section of the atmosphere-side substrate transfer chamber 2702 and the atmosphere-side substrate supply chamber 2701.

  For the transfer chamber 2704 illustrated in FIG. 20B, the description of the transfer chamber 2704 illustrated in FIG.

  The load lock chamber 2703 a has a substrate transfer stage 2752. The load lock chamber 2703a raises the pressure from the reduced pressure state to the atmosphere, and when the pressure in the load lock chamber 2703a reaches the atmospheric pressure, the transfer robot 2763 provided in the atmosphere side substrate transfer chamber 2702 moves to the substrate transfer stage 2752. Receive the board. After that, the load lock chamber 2703a is evacuated to a reduced pressure state, and then the transfer robot 2762 provided in the transfer chamber 2704 receives the substrate from the substrate transfer stage 2752.

  The load lock chamber 2703a is connected to a vacuum pump 2770 and a cryopump 2771 through valves. Since the connection method of the exhaust system of the vacuum pump 2770 and the cryopump 2771 can be connected by referring to the connection method of the transfer chamber 2704, description thereof is omitted here. Note that the unload lock chamber 2703b shown in FIG. 19 can have the same configuration as the load lock chamber 2703a.

  The atmosphere-side substrate transfer chamber 2702 has a transfer robot 2763. The transfer robot 2763 can transfer the substrate between the cassette port 2761 and the load lock chamber 2703a. Further, a mechanism for cleaning dust or particles such as a HEPA filter (High Efficiency Particulate Air Filter) may be provided above the atmosphere side substrate transfer chamber 2702 and the atmosphere side substrate supply chamber 2701.

  The atmosphere side substrate supply chamber 2701 has a plurality of cassette ports 2761. The cassette port 2761 can accommodate a plurality of substrates.

  The target has a surface temperature of 100 ° C. or lower, preferably 50 ° C. or lower, more preferably about room temperature (typically 25 ° C.). In a sputtering apparatus corresponding to a large area substrate, a large area target is often used. However, it is difficult to seamlessly produce a target having a size corresponding to a large area. In reality, a large number of targets are arranged side by side with as little gap as possible, but a slight gap is inevitably generated. From such a slight gap, the surface temperature of the target is increased, so that zinc and the like are volatilized, and the gap may gradually widen. When the gap is widened, the backing plate or the metal of the bonding material used for joining the backing plate and the target may be sputtered, which increases the impurity concentration. Therefore, it is preferable that the target is sufficiently cooled.

  Specifically, a metal (specifically, copper) having high conductivity and high heat dissipation is used as the backing plate. Moreover, a target can be efficiently cooled by forming a water channel in the backing plate and flowing a sufficient amount of cooling water through the water channel.

  Note that in the case where the target includes zinc, an oxide semiconductor in which plasma damage is reduced and zinc is less likely to volatilize can be obtained by forming the film in an oxygen gas atmosphere.

By using the above-described film formation apparatus, the hydrogen concentration is 2 × 10 ²⁰ atoms / cm ³ or less, preferably 5 × 10 ¹⁹ atoms / cm ^{3 in} secondary ion mass spectrometry (SIMS). Hereinafter, an oxide semiconductor with a thickness of 1 × 10 ¹⁹ atoms / cm ³ or less, more preferably 5 × 10 ¹⁸ atoms / cm ³ or less can be formed.

Further, the nitrogen concentration in SIMS is less than 5 × 10 ¹⁹ atoms / cm ³ , preferably 1 × 10 ¹⁹ atoms / cm ³ or less, more preferably 5 × 10 ¹⁸ atoms / cm ³ or less, and further preferably 1 × 10 9. ^An oxide semiconductor with a density of ¹⁸ atoms / cm ³ or less can be formed.

In addition, the carbon concentration in SIMS is less than 5 × 10 ¹⁹ atoms / cm ³ , preferably 5 × 10 ¹⁸ atoms / cm ³ or less, more preferably 1 × 10 ¹⁸ atoms / cm ³ or less, and even more preferably 5 × 10. ^An oxide semiconductor with a density of ¹⁷ atoms / cm ³ or less can be formed.

An oxide semiconductor with few impurities and oxygen vacancies is an oxide semiconductor with low carrier density. Specifically, the carrier density is less than 8 × 10 ¹¹ / cm ³ , preferably less than 1 × 10 ¹¹ / cm ³ , more preferably less than 1 × 10 ¹⁰ / cm ³ , and 1 × 10 ⁻⁹ / cm ^3. This can be done. Such an oxide semiconductor is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. The CAAC-OS has a low impurity concentration and a low density of defect states. That is, it can be said that the oxide semiconductor has stable characteristics.

In addition, a gas molecule (atom) in which m / z is 2 (such as a hydrogen molecule) by a temperature desorption gas spectroscopy (TDS) analysis, a gas molecule (atom) in which m / z is 18, m The release amount of gas molecules (atoms) with / z of 28 and gas molecules (atoms) with m / z of 44 is 1 × 10 ¹⁹ pieces / cm ³ or less, preferably 1 × 10 ¹⁸ pieces / cm ^{3, respectively.} The following oxide semiconductor can be formed.

  By using the above film formation apparatus, entry of impurities into the oxide semiconductor can be suppressed. Further, by using the above deposition apparatus to form a film in contact with the oxide semiconductor, the entry of impurities from the film in contact with the oxide semiconductor into the oxide semiconductor can be suppressed.

<CAAC-OS>
First, the CAAC-OS will be described.

  A CAAC-OS is a kind of oxide semiconductor having a plurality of c-axis aligned crystal parts (also referred to as nanoclusters).

A case where the CAAC-OS is analyzed by X-ray diffraction (XRD: X-Ray Diffraction) is described. For example, when CAAC-OS having an InGaZnO ₄ crystal classified into the space group R-3m is subjected to structural analysis by an out-of-plane method, a diffraction angle (2θ) as illustrated in FIG. Shows a peak near 31 °. Since this peak is attributed to the (009) plane of the InGaZnO ₄ crystal, in CAAC-OS, the crystal has a c-axis orientation, and the plane on which the c-axis forms a CAAC-OS film (formation target) It can also be confirmed that it faces a direction substantially perpendicular to the upper surface. In addition to the peak where 2θ is around 31 °, a peak may also appear when 2θ is around 36 °. The peak where 2θ is around 36 ° is attributed to the crystal structure classified into the space group Fd-3m. Therefore, the CAAC-OS preferably does not show the peak.

On the other hand, when structural analysis is performed on the CAAC-OS by an in-plane method in which X-rays are incident from a direction parallel to a formation surface, a peak appears at 2θ of around 56 °. This peak is attributed to the (110) plane of the InGaZnO ₄ crystal. Even if 2θ is fixed in the vicinity of 56 ° and the analysis (φ scan) is performed while rotating the sample with the normal vector of the sample surface as the axis (φ axis), as shown in FIG. No peak appears. On the other hand, when φ scan is performed with 2θ fixed at around 56 ° with respect to single crystal InGaZnO ₄ , six peaks attributed to a crystal plane equivalent to the (110) plane are observed as shown in FIG. Is done. Therefore, structural analysis using XRD can confirm that the CAAC-OS has irregular orientations in the a-axis and the b-axis.

Next, a CAAC-OS analyzed by electron diffraction will be described. For example, when an electron beam with a probe diameter of 300 nm is incident on a CAAC-OS including an InGaZnO ₄ crystal in parallel with a formation surface of the CAAC-OS, a diffraction pattern (restricted field of view) illustrated in FIG. Sometimes referred to as an electron diffraction pattern). This diffraction pattern includes spots caused by the (009) plane of the InGaZnO ₄ crystal. Therefore, electron diffraction shows that the nanocluster included in the CAAC-OS has c-axis alignment, and the c-axis is in a direction substantially perpendicular to the formation surface or the top surface. On the other hand, FIG. 21E shows a diffraction pattern obtained when an electron beam with a probe diameter of 300 nm is incident on the same sample in a direction perpendicular to the sample surface. A ring-shaped diffraction pattern is confirmed from FIG. Therefore, even by electron diffraction using an electron beam with a probe diameter of 300 nm, it can be seen that the a-axis and b-axis of the nanocluster included in the CAAC-OS have no orientation. Note that the first ring in FIG. 21E is considered to be derived from the (010) plane and the (100) plane of the InGaZnO ₄ crystal. Further, the second ring in FIG. 21E is considered to be due to the (110) plane or the like.

<Structure of oxide semiconductor>
An oxide semiconductor is classified into a single crystal oxide semiconductor and a non-single-crystal oxide semiconductor. As examples of the non-single-crystal oxide semiconductor, a CAAC-OS, a polycrystalline oxide semiconductor, an nc-OS, a pseudo-like oxide semiconductor (a-like OS), an amorphous oxide semiconductor, and the like There is.

  From another viewpoint, oxide semiconductors are classified into amorphous oxide semiconductors and other crystalline oxide semiconductors. Examples of a crystalline oxide semiconductor include a single crystal oxide semiconductor, a CAAC-OS, a polycrystalline oxide semiconductor, and an nc-OS.

  The nc-OS has a region where a crystal part can be confirmed and a region where a clear crystal part cannot be confirmed in a high-resolution TEM image. In many cases, a crystal part included in the nc-OS has a size of 1 nm to 10 nm, or 1 nm to 3 nm. Note that an oxide semiconductor in which the size of a crystal part is greater than 10 nm and less than or equal to 100 nm is sometimes referred to as a microcrystalline oxide semiconductor. In nc-OS, for example, a crystal grain boundary may not be clearly confirmed in a high-resolution TEM image. Note that the nanocrystal may have the same origin as the nanocluster in the CAAC-OS. Therefore, in the following, the crystal part of the nc-OS may be referred to as a nanocluster.

  The nc-OS has periodicity in atomic arrangement in a minute region (for example, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In addition, the nc-OS has no regularity in crystal orientation between different nanoclusters. Therefore, orientation is not seen in the whole film. Therefore, the nc-OS may not be distinguished from an a-like OS or an amorphous oxide semiconductor depending on an analysis method. For example, when an X-ray having a diameter larger than that of the nanocluster is used for nc-OS, a peak indicating a crystal plane is not detected by analysis by the out-of-plane method. Further, when electron diffraction using an electron beam with a probe diameter (for example, 50 nm or more) larger than that of the nanocluster is performed on the nc-OS, a diffraction pattern such as a halo pattern is observed. On the other hand, spots are observed when nc-OS is subjected to nanobeam electron diffraction using an electron beam having a probe diameter close to or smaller than that of the nanocluster. Further, when nanobeam electron diffraction is performed on the nc-OS, a region with high luminance may be observed like a circle (in a ring shape). Furthermore, a plurality of spots may be observed in the ring-shaped region.

  Thus, since the crystal orientation does not have regularity between nanoclusters (nanocrystals), nc-OS is replaced with an oxide semiconductor having RANC (Random Aligned Nanocrystals), or NANC (Non-Aligned nanocrystals). It can also be called an oxide semiconductor.

  The nc-OS is an oxide semiconductor that has higher regularity than an amorphous oxide semiconductor. Therefore, the nc-OS has a lower density of defect states than an a-like OS or an amorphous oxide semiconductor. However, nc-OS does not show regularity in crystal orientation between different nanoclusters. Therefore, the nc-OS has a higher density of defect states than the CAAC-OS.

  The a-like OS is an oxide semiconductor having a structure between the nc-OS and the amorphous oxide semiconductor.

  In the a-like OS, a void may be observed in a high-resolution TEM image. Moreover, in a high-resolution TEM image, it has the area | region which can confirm a crystal part clearly, and the area | region which cannot confirm a crystal part.

  Since it has a void, the a-like OS has an unstable structure. Hereinafter, in order to show that the a-like OS has an unstable structure as compared with the CAAC-OS and the nc-OS, changes in the structure due to electron irradiation are shown. For example, in the a-like OS, a crystal part may be grown by electron irradiation. On the other hand, in the nc-OS and the CAAC-OS, the crystal part is hardly grown by electron irradiation. That is, it can be seen that the a-like OS has an unstable structure compared to the nc-OS and the CAAC-OS.

  In addition, since it has a void, the a-like OS has a lower density than the nc-OS and the CAAC-OS. Specifically, the density of the a-like OS is 78.6% or more and less than 92.3% of the density of the single crystal having the same composition. Further, the density of the nc-OS and the density of the CAAC-OS are 92.3% or more and less than 100% of the density of the single crystal having the same composition. An oxide semiconductor that is less than 78% of the density of a single crystal is difficult to form.

For example, in an oxide semiconductor satisfying In: Ga: Zn = 1: 1: 1 [atomic ratio], the density of single crystal InGaZnO ₄ having a rhombohedral structure is 6.357 g / cm ³ . Thus, for example, in an oxide semiconductor that satisfies In: Ga: Zn = 1: 1: 1 [atomic ratio], the density of a-like OS is 5.0 g / cm ³ or more and less than 5.9 g / cm ^3. . For example, in the oxide semiconductor satisfying In: Ga: Zn = 1: 1: 1 [atomic ratio], the density of the nc-OS and the density of the CAAC-OS is 5.9 g / cm ³ or more and 6.3 g / less than cm ³ .

  Note that there may be no single crystal having the same composition. In that case, the density corresponding to the single crystal in a desired composition can be estimated by combining single crystals having different compositions at an arbitrary ratio. What is necessary is just to estimate the density corresponding to the single crystal of a desired composition using a weighted average with respect to the ratio which combines the single crystal from which a composition differs. However, the density is preferably estimated by combining as few kinds of single crystals as possible.

  As the definition of the amorphous structure, it is generally known that it is not fixed in a metastable state, isotropic and does not have a heterogeneous structure, and the like. Moreover, it can be paraphrased as a structure having a flexible bond angle and short-range order, but not long-range order.

  In other words, an intrinsically stable oxide semiconductor cannot be referred to as a complete amorphous oxide semiconductor. In addition, an oxide semiconductor that is not isotropic (eg, has a periodic structure in a minute region) cannot be referred to as a completely amorphous oxide semiconductor. However, the a-like OS has a periodic structure in a minute region, but has a void and an unstable structure as described later. Therefore, it can be said that it is close to an amorphous oxide semiconductor in terms of physical properties.

  As described above, an amorphous oxide semiconductor whose definition is unstable is, for example, not likely to be practical as a product even if it can be a channel formation region of a transistor. The same applies to the a-like OS. Therefore, when used in a product, it is preferable that the amorphous oxide semiconductor and the a-like OS have few or no components.

  In addition, although a single crystal oxide semiconductor has high crystallinity, a high process temperature is required for formation; therefore, it may not be practical in consideration of productivity. In addition, although a polycrystalline oxide semiconductor has high crystallinity in crystal grains, it has a crystal grain boundary and thus may easily vary.

  On the other hand, the CAAC-OS and the nc-OS have high stability and can be formed even at a substrate temperature of less than 500 ° C. by the above-described film formation method. Moreover, since there is no clear crystal grain boundary, it is homogeneous and hardly causes variations. For example, it can be said that the structure has high reliability and high practicality because it can be uniformly formed on a large-area substrate of the eighth generation or higher.

<Analysis by electron microscope>
In the following, CAAC-OS and nc-OS are analyzed by a transmission electron microscope (TEM: Transmission Electron Microscope).

  First, the sample to be analyzed will be described.

  Sample X1 was formed by PESP using an In—Ga—Zn oxide (In: Ga: Zn = 1: 4: 5 [atomic ratio]) target (circular with a diameter of 101.6 mm) on a quartz glass substrate. It has a 100 nm-thick In—Ga—Zn oxide film. In addition, the deposition power is 200 W (DC), the deposition pressure is 0.4 Pa, the target-substrate distance (distance from the target to the substrate holder) is 130 mm, the deposition gas is 30 sccm of argon gas and 10 sccm of oxygen gas, and the substrate is heated. None.

  Sample X2 was formed by PESP using an In—Ga—Zn oxide (In: Ga: Zn = 1: 4: 5 [atomic ratio]) target (circular with a diameter of 101.6 mm) on a quartz glass substrate. It has a 100 nm-thick In—Ga—Zn oxide film. In addition, the deposition power is 200 W (DC), the deposition pressure is 0.4 Pa, the target-substrate distance (distance from the target to the substrate holder) is 130 mm, the deposition gas is 30 sccm of argon gas and 10 sccm of oxygen gas, and the substrate is heated. Yes (substrate temperature 200 ° C.).

  Sample X3 was formed by VDSP using two In—Ga—Zn oxide (In: Ga: Zn = 1: 4: 5 [atomic ratio]) targets (125 mm × 190 mm rectangle) on a quartz glass substrate. It has a 100 nm-thick In—Ga—Zn oxide film. In addition, the deposition power is 1200 W (DC), the deposition pressure is 0.3 Pa, the target-substrate distance (the distance from the line connecting the centers of the pair of targets to the substrate holder) is 250 mm, and the deposition gas is an argon gas of 30 sccm. The oxygen gas was 10 sccm and the substrate was not heated.

  Sample X4 was formed by VDSP using two In—Ga—Zn oxide (In: Ga: Zn = 1: 4: 5 [atomic ratio]) targets (125 mm × 190 mm rectangle) on a quartz glass substrate. It has a 100 nm-thick In—Ga—Zn oxide film. In addition, the deposition power is 1200 W (DC), the deposition pressure is 0.05 Pa, the distance between the target and the substrate (the distance from the line connecting the centers of the pair of targets to the substrate holder) is 250 mm, and the deposition gas is an argon gas of 30 sccm. The oxygen gas was 10 sccm and the substrate was not heated.

<Cross-section TEM>
Hereinafter, features of the CAAC-OS and the nc-OS that appear in the cross-sectional TEM image are described.

  First, image analysis of a cross-sectional image (also referred to as a cross-sectional TEM image) in TEM is performed. The cross-sectional TEM image was observed using a spherical aberration corrector function. Moreover, JEOL Co., Ltd. atomic resolution analytical electron microscope JEM-ARM200F was used for acquisition of a cross-sectional TEM image. Note that a region sandwiched by white arrows in the cross-sectional TEM image indicates one nanocluster.

  FIG. 22A shows a cross-sectional TEM image of the sample X1 observed from a direction substantially parallel to the sample surface. A spherical aberration correction function was used for observation of the cross-sectional TEM image. FIG. 22B is a cross-sectional TEM image obtained by further enlarging FIG. From FIG. 22B, nanoclusters can be confirmed. Since the orientation of the nanocluster is irregular, it can be seen that the sample X1 is nc-OS.

  FIG. 23A shows a cross-sectional TEM image of the sample X2 observed from a direction substantially parallel to the sample surface. A spherical aberration correction function was used for observation of the cross-sectional TEM image. FIG. 23B is a cross-sectional TEM image obtained by further enlarging FIG. From FIG. 23B, nanoclusters can be confirmed. The orientation of the nanocluster reflects the unevenness of the surface (also referred to as a surface to be formed) or the upper surface of the film, and is parallel to the surface or upper surface of the film. As described above, the sample X2 can observe crystal distortion even in a cross-sectional TEM image. Since the direction of the nanocluster is aligned with the c-axis, it can be seen that the sample X2 is a CAAC-OS.

  FIG. 24A shows a cross-sectional TEM image of the sample X3 observed from a direction substantially parallel to the sample surface. A spherical aberration correction function was used for observation of the cross-sectional TEM image. FIG. 24B is a cross-sectional TEM image obtained by further enlarging FIG. From FIG. 24B, nanoclusters can be confirmed. Since the orientation of the nanocluster is irregular, it can be seen that the sample X3 is nc-OS.

  FIG. 25A shows a cross-sectional TEM image of the sample X4 observed from a direction substantially parallel to the sample surface. A spherical aberration correction function was used for observation of the cross-sectional TEM image. FIG. 25B is a cross-sectional TEM image obtained by further enlarging FIG. From FIG. 25B, nanoclusters can be confirmed. The orientation of the nanocluster reflects the unevenness of the surface (also referred to as a surface to be formed) or the upper surface of the film, and is parallel to the surface or upper surface of the film to be formed. Thus, the sample X4 can observe crystal distortion even in a cross-sectional TEM image. Since the direction of the nanocluster is aligned with the c-axis, it can be seen that the sample X4 is a CAAC-OS.

  The following table shows the average value, standard deviation σ, maximum value and minimum value of nanocluster size (length in the planar direction of the nanocluster), and the maximum value of the nanocluster in Sample X1, Sample X2, Sample X3, and Sample X4. The orientation distribution is shown. The direction of the nanocluster is the inclination of the nanocluster plane with respect to the surface of the quartz glass substrate. In addition, the nanocluster size distributions of Sample X1, Sample X2, Sample X3, and Sample X4 are shown in FIGS. 26 (A), 26 (B), 26 (C), and 26 (D), respectively.

  From the above table and the like, it was found that in an In—Ga—Zn oxide formed by PESP, a CAAC-OS and an nc-OS were separately formed depending on the presence or absence of substrate heating. In addition, it was found that an In—Ga—Zn oxide film formed by VDSP has a low film formation pressure even without substrate heating and becomes a CAAC-OS when a high vacuum is applied. In addition, it was found that the In—Ga—Zn oxide formed by VDSP has a larger average nanocluster and a larger standard deviation than the In—Ga—Zn oxide formed by PESP. In particular, in sample X4, the average size of the nanoclusters was as large as 3 nm or more, and the standard deviation was large.

  As shown in FIGS. 23B and 25B, the CAAC-OS has a characteristic atomic arrangement. In addition, from FIG. 26, the size of one nanocluster is often about 1 nm to 10 nm. From such characteristics, the nanocluster can also be called a nanocrystal (nc). The CAAC-OS can also be referred to as an oxide semiconductor including c-axis aligned nanocrystals (CANC: C-Axis Aligned nanocrystals).

  Further, as shown in FIGS. 22B and 24B, it can be seen that the nc-OS does not have a layered atomic arrangement. Therefore, the nc-OS can also be referred to as an oxide semiconductor including nanocrystals (RANC: Random Aligned nanocrystals or NANC: Non-Aligned nanocrystals) that are not oriented in a specific direction.

<Plane TEM>
Not only the cross-section TEM but also a plurality of methods can be used to specify a more strict structure. In the following, image analysis of a planar image (also referred to as a planar TEM image) in TEM is performed. The planar TEM image was observed using a spherical aberration correction function. Moreover, JEOL atomic resolution analytical electron microscope JEM-ARM200F was used for acquisition of a planar TEM image.

FIG. 27A is a planar TEM image of sample X4. FIG. 27B is an image obtained by performing image processing on FIG. In the image processing, first, an FFT image is acquired by performing Fast Fourier Transform (FFT) processing on FIG. Next, mask processing, leaving the scope of 5.0 nm ^-1 from 2.8 nm ^-1 in the FFT image acquired. Next, an FFT filtered image is obtained by performing an inverse fast Fourier transform (IFFT) process on the masked FFT image. FIG. 27B is the FFT filtered image of FIG. 27A and 27B show that sample X4 has a hexagonal and triangular atomic arrangement, and the boundary between regions having different crystal orientations is not clear. Therefore, it can be seen that the sample X4 has the characteristics of CAAC-OS from the planar TEM image.

  FIG. 28A is a planar TEM image showing the regions A, B, C, and D in FIG. FIG. 28B is an image obtained by analyzing the image of FIG. 27B, and shows a region A, a region B, a region C, and a region D at the same position as FIG.

  An image analysis method will be described. First, lattice points are extracted from the FFT filtered image. The extraction of grid points is performed according to the following procedure. First, processing for removing noise from the FFT filtered image is performed. The process of removing noise is performed by smoothing the luminance within a radius of 0.05 nm by the following equation (2).

  Here, S_Int (x, y) indicates the smoothed luminance at the coordinates (x, y), r indicates the distance between the coordinates (x, y) and the coordinates (x ′, y ′), and Int ( x ′, y ′) indicates the luminance at the coordinates (x ′, y ′). When r is 0, r is set as 1.

  Next, a lattice point is searched. The condition of the lattice point is a coordinate having the highest luminance within a radius of 0.22 nm. Here, lattice point candidates are extracted. If the radius is within 0.22 nm, the frequency of erroneous detection of grid points due to noise can be reduced. In the TEM image, since there is a certain distance between the lattice points, it is unlikely that two or more lattice points are included in the radius of 0.22 nm.

  Next, centering on the extracted lattice point candidate, the coordinate having the highest luminance within the radius of 0.22 nm is extracted, and the lattice point candidate is updated. In this way, extraction of grid point candidates is repeated, and the coordinates when no new grid point candidates appear are recognized as grid points. Similarly, a new lattice point is recognized at a position separated by 0.22 nm or more from the recognized lattice point. In this way, the grid points are recognized over the entire range. The obtained plurality of lattice points are collectively referred to as a lattice point group.

  Next, a method for deriving the angle of the hexagonal lattice from the extracted lattice point group is shown in the schematic diagrams shown in FIGS. 29A, 29B, and 29C, and FIG. 29D. This will be described with reference to a flowchart. First, a reference lattice point is determined, and the six closest lattice points that are the closest are connected to form a hexagonal lattice (see step S101 in FIGS. 29A and 29D). Thereafter, an average value R of the distances from the reference lattice point that is the center point of the hexagonal lattice to each lattice point that is the vertex is derived. The calculated R is the distance to each vertex, and a regular hexagon with the reference grid point as the center point is formed (see step S102 in FIG. 29D). At this time, the distances between the apexes of the regular hexagon and the closest neighboring lattice points are distance d1, distance d2, distance d3, distance d4, distance d5, and distance d6 (see step S103 in FIG. 29D). ). Next, the regular hexagon is rotated from 0 ° to 60 ° in increments of 0.1 ° with respect to the center point, and the average deviation [D = (d1 + d2 + d3 + d4 + d5 + d6) / 6] between the rotated regular hexagon and the hexagonal lattice is calculated. Calculate (see step S104 in FIG. 29D). Then, the rotation angle θ of the regular hexagon when the average deviation D is the minimum is obtained and set as the angle of the hexagonal lattice (step S105 in FIG. 29D).

  Next, in the observation range of the planar TEM image, adjustment is performed so that the ratio at which the angle of the hexagonal lattice is 30 ° is the highest. Then, an average value of the angles of the hexagonal lattice is calculated in a radius range of 1 nm. The result of the image analysis of the planar TEM image obtained in this way can be displayed in a color or shade corresponding to the angle of the hexagonal lattice. FIG. 28B is an image obtained by analyzing the image of FIG. 28A by the above-described method and showing the light and shade according to the angle of the hexagonal lattice.

  FIG. 28B shows that the sample X4 has a plurality of hexagonal lattice-shaped regions. FIG. 30A is a planar TEM image in which the region A is enlarged. FIG. 30B is a planar TEM image showing, in the region A, the boundary where the angle of the hexagonal lattice changes with a white dotted line. FIG. 30C is an FFT filtered image in the region A. FIG. 30D is an FFT filtered image in which a boundary where the angle of the hexagonal lattice changes in the region A is indicated by a white dotted line. FIG. 30E is an image showing light and shade according to the angle of the hexagonal lattice in the region A. In FIG. 30E, the white dotted line indicates the boundary where the angle of the hexagonal lattice changes, and the black dotted line indicates the change in the angle of the hexagonal lattice. FIG. 30 (E) shows that the lattice points are continuously observed without interruption even at the boundary where the angle of the hexagonal lattice changes.

  FIG. 31A is a planar TEM image in which the region B is enlarged. FIG. 31B is a planar TEM image in which a boundary portion where the angle of the hexagonal lattice changes in the region B is indicated by a white dotted line. FIG. 31C is an FFT filtered image in the region B. FIG. 31D is an FFT filtered image in which a boundary portion where the angle of the hexagonal lattice changes in the region B is indicated by a white dotted line. FIG. 31E is an image showing light and shade according to the angle of the hexagonal lattice in the region B. In FIG. 31E, the white dotted line indicates the boundary where the angle of the hexagonal lattice changes, and the black dotted line indicates the change in the angle of the hexagonal lattice. FIG. 31 (E) shows that the lattice points are continuously observed without interruption even at the boundary where the angle of the hexagonal lattice changes.

  FIG. 32A is a planar TEM image in which the region C is enlarged. FIG. 32B is a planar TEM image in which a boundary portion where the angle of the hexagonal lattice changes in the region C is indicated by a white dotted line. FIG. 32C is an FFT filtered image in region C. FIG. 32D is an FFT filtered image in which a boundary where the angle of the hexagonal lattice changes in the region C is indicated by a white dotted line. FIG. 32E is an image showing light and shade according to the angle of the hexagonal lattice in the region C. In FIG. 32E, a white dotted line indicates a boundary portion where the angle of the hexagonal lattice changes. FIG. 32E shows that the lattice points are continuously observed without interruption even at the boundary where the angle of the hexagonal lattice changes.

  FIG. 33A is a planar TEM image in which the region D is enlarged. FIG. 33B is a planar TEM image in the region D where the boundary where the angle of the hexagonal lattice changes is indicated by a white dotted line. FIG. 33C is an FFT filtered image in the region D. FIG. 33 (D) is an FFT filtered image in which a boundary portion where the angle of the hexagonal lattice changes in the region D is indicated by a white dotted line. FIG. 33E is an image showing light and shade according to the angle of the hexagonal lattice in the region D. In FIG. 33E, a white dotted line indicates a boundary portion where the angle of the hexagonal lattice changes. FIG. 33 (E) shows that the lattice points are continuously observed without interruption even at the boundary where the angle of the hexagonal lattice changes.

  Here, a new sample X5 is prepared. Sample X5 is an In—Ga—Zn oxide (In: Ga: Zn = 1: 1: 1 [atomic ratio]) target (diameter is on a single crystal silicon substrate on which a thermal oxide film having a thickness of 25 nm is formed. A 100 nm thick In—Ga—Zn oxide formed by PESP using a 101.6 mm circle). In addition, the deposition power is 200 W (DC), the deposition pressure is 0.4 Pa, the target-substrate distance (distance from the target to the substrate holder) is 130 mm, the deposition gas is 20 sccm of argon gas and 10 sccm of oxygen gas, and the substrate is heated. None. For the sample X5, heat treatment was performed at 450 ° C. for 1 hour in a nitrogen atmosphere after the In—Ga—Zn oxide film was formed.

  FIG. 34 is an image showing light and shade according to the angle of the hexagonal lattice of the sample X5. From FIG. 34, it can be seen that Sample X5 has a plurality of hexagonal lattice-shaped regions.

  Thus, by analyzing the image of the planar TEM image, it is possible to evaluate the boundary portion where the angle of the hexagonal lattice of the CAAC-OS changes. In the method shown in FIG. 29, the average deviation D between the obtained regular hexagon and the hexagonal lattice is divided by the distance R between the center point of the regular hexagon and each vertex, thereby obtaining the deformation rate of the hexagonal lattice. Can be derived. FIG. 35 shows the deformation rate of the hexagonal lattice of Sample X4 and Sample X5. FIG. 35A is an image in which a region where the deformation rate of the hexagonal lattice is 0.15 or less is shown in light gray in the observation range of the planar TEM image of the sample X4. FIG. 35C is an image in which a region where the deformation rate of the hexagonal lattice is 0.15 or less is shown in light gray in the observation range of the planar TEM image of the sample X5. FIG. 35B is a diagram showing a distribution of deformation rate of the hexagonal lattice of the sample X4. FIG. 35D is a diagram showing a distribution of deformation rates of the hexagonal lattice of the sample X5.

  Here, in the sample X4, the ratio of the region where the deformation rate is 0.4 or less is approximately 99%, the ratio of the region where the deformation rate is 0.3 or less is approximately 95%, and the deformation rate is 0.2 or less. The ratio of the area was about 74%, and the ratio of the area where the deformation rate was 0.15 or less was about 60%. Further, in the sample X5, the ratio of the region where the deformation rate is 0.4 or less is approximately 99%, the ratio of the region where the deformation rate is 0.3 or less is approximately 88%, and the deformation rate is 0.2 or less. The ratio of the area was approximately 51%, and the ratio of the area having a deformation rate of 0.15 or less was approximately 32%. Thus, it can be seen that Sample X4 and Sample X5 have a high ratio of the regions having a small deformation rate of the hexagonal lattice. In particular, it can be seen that Sample X4 has a high ratio of the hexagonal lattice with a low deformation rate. A CAAC-OS having a high ratio of a region having a small deformation rate of a hexagonal lattice is considered to have properties closer to a single crystal oxide semiconductor.

  Next, a Voronoi diagram is created from the lattice points of sample X4 and sample X5. The Voronoi diagram is a diagram obtained by dividing a lattice point group in a region closest to the lattice point. In the following, using the schematic diagram shown in FIGS. 36A, 36B, 36C, and 36D, and the flowchart shown in FIG. Details will be described.

  First, a lattice point group is extracted by the method shown in FIG. 29 or the like (see step S111 in FIGS. 36A and 36E). Next, adjacent lattice points are connected by line segments (see step S112 in FIGS. 36B and 36E). Next, a vertical bisector of each line segment is drawn (see step S113 in FIGS. 36C and 36E). Next, a point where three vertical bisectors intersect is extracted (see step S114 in FIG. 36E). This point is called the Voronoi point. Next, adjacent Voronoi points are connected with line segments (see step S115 in FIGS. 36D and 36E). At this time, the polygonal region surrounded by the line segment is called a Voronoi region. The Voronoi diagram can be created by the above method.

  Here, a new sample X6 is prepared. Sample X6 has an In—Ga—Zn oxide (In: Ga: Zn = 1: 1: 1.5 [atomic ratio]) target (diameter is on a single crystal yttria stabilized zirconia (also referred to as YSZ) substrate. A 100 nm thick In—Ga—Zn oxide formed by PESP using a 101.6 mm circle). In addition, the deposition power is 200 W (DC), the deposition pressure is 0.4 Pa, the target-substrate distance (distance from the target to the substrate holder) is 130 mm, the deposition gas is 20 sccm of argon gas and 10 sccm of oxygen gas, and the substrate is heated. Yes (substrate temperature 300 ° C.). Sample X6 was subjected to heat treatment at 1200 ° C. for 1 hour in an oxygen atmosphere after the In—Ga—Zn oxide film was formed.

  FIG. 37A is a Voronoi diagram constructed from the lattice point group of the sample X4. FIG. 37B shows a ratio in which the shape of the Voronoi region in FIG. FIG. 37C is a Voronoi diagram constructed from the lattice point group of the sample X5. FIG. 37D shows a ratio in which the shape of the Voronoi region in FIG. FIG. 37 (E) is a Voronoi diagram drawn from the lattice point group of sample X6. FIG. 37F shows the ratio of the shape of the Voronoi region in FIG. Further, the ratios of the shape of the Voronoi region of the sample X4, the sample X5, and the sample X6, which are any one of a square shape and a nine-sided shape, are shown in the following table.

  From FIG. 37 and the above table, it can be seen that the ratio of the Voronoi region in the hexagonal shape is very high in the sample X6, and then the ratio of the Voronoi region in the hexagonal shape is high in the order of the sample X4 and the sample X5. In the case of having an ideal hexagonal single crystal structure, the ratio of the shape of the Voronoi region to a hexagon is 100%. Therefore, it can be seen that Sample X6, Sample X4, and Sample X5 have crystallinity close to an ideal single crystal structure in this order. For example, in the CAAC-OS having high crystallinity, the ratio of the shape of the Voronoi region to a hexagon is 50% to 100%, preferably 65% to 100%, more preferably 78% to 100%, and more Preferably they are 80% or more and 100% or less.

  Since the sample X6 uses a single crystal YSZ substrate and is subjected to heat treatment at 1200 ° C. after film formation, the productivity may be lower than other conditions. On the other hand, since the heat treatment after film formation is relatively low at 450 ° C., the sample X5 has higher productivity than the sample X6. In addition, since the sample X4 is not subjected to heat treatment after film formation, the productivity is higher than that of the sample X5. That is, in view of productivity, it can be seen that Sample X4 and Sample X5, particularly Sample X4 are preferable conditions.

  In each sample, the regions where the Voronoi regions are pentagonal and heptagonal are considered to be because the hexagonal shape is deformed in the lateral growth region of the nanoclusters to form a connecting portion.

  Further, it is presumed that the formation of crystal grain boundaries is suppressed by distorting the lattice arrangement in the vicinity of the connecting portion. This is because the CAAC-OS can tolerate distortion due to the fact that the atomic arrangement is not dense in the ab plane direction and the bond distance between atoms changes due to substitution of metal elements. Conceivable.

<Electron diffraction>
Furthermore, an electron diffraction pattern is acquired by irradiating the sample X4 with an electron beam having a probe diameter of 1 nm (also referred to as a nanobeam electron beam).

  FIG. 38 shows a planar TEM image of sample X4. In FIG. 38, electron diffraction patterns in a range indicated by dotted lines and broken lines were continuously observed. The electron diffraction pattern is observed while moving at a constant speed from the 0 second position to the 35 second position while irradiating the electron beam. The result of the dotted line range is shown in FIG. 39, and the result of the broken line range is shown in FIG. 39 and 40, one of the crystal axes appearing in the electron diffraction pattern is indicated by a one-dot chain line. From FIG. 39 and FIG. 40, it was found that the angle of the crystal axis of Sample X4 changed gently in the range shown in FIG. 38, and a clear crystal grain boundary was not confirmed.

  FIG. 41 shows a cross-sectional TEM image of sample X4. In FIG. 41, electron diffraction patterns in a range indicated by a dotted line and a broken line were continuously observed. The electron diffraction pattern is observed while moving at a constant speed from the 0 second position to the 28 second position while irradiating the electron beam. The result of the dotted line range is shown in FIG. 42, and the result of the broken line range is shown in FIG. 42 and 43, one of the crystal axes appearing in the electron diffraction pattern is indicated by a one-dot chain line. 42 and 43, it was found that the angle of the crystal axis of Sample X4 changed gently in the range shown in FIG. 41, and no clear crystal grain boundary was confirmed.

  Thus, it is found that the CAAC-OS has a periodic structure and a fluctuation in atomic arrangement, unlike a polycrystalline oxide semiconductor. In other words, the CAAC-OS can be said to have a displacement distribution in the periodic structure. Since it has such characteristics, it can be said that the CAAC-OS has a structure different from that of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, or a single crystal oxide semiconductor.

  The CAAC-OS has a c-axis orientation and a crystal structure in which a plurality of nanoclusters (nanocrystals) are laterally grown on the ab plane so that the growth points collide with each other and are connected to each other. Therefore, it can be more precisely called an oxide semiconductor having CAA crystal (c-axis-aligned a-b-plane-anchored crystal).

  As described above, a paracrystal is known as a crystal structure that retains the remnant of an ideal atomic arrangement while having distortion. Paracrystals have been reported for organic fibers, but there are few reports on inorganic materials. However, the following points are different between Paracrystal and CAAC-OS. For example, a paracrystal has a planar structure (an image like a cloth), but a CAAC-OS has a shape along a formation surface, and is different in that it has a thin film structure in a stacked body. The CAAC-OS is different in that a denser structure is formed by heat treatment performed at a temperature higher than or equal to a film formation temperature (for example, higher than 300 ° C. and lower than 1500 ° C., preferably higher than 350 ° C. and lower than 800 ° C.). . Another difference is that the structure is deformed into a single crystal structure by heat treatment at a temperature higher than the temperature at which the crystal structure is deformed (for example, 1000 ° C. or higher and 1500 ° C. or lower). Therefore, it can be seen that the CAAC-OS has a novel crystal structure different from that of paracrystal.

  The characteristics observed in the cross-sectional TEM image and the planar TEM image as described above are obtained by capturing the structure of the oxide semiconductor. For example, when a conductor is formed over the CAAC-OS, physical damage or chemical damage may occur and defects may be formed.

  This embodiment can be implemented in appropriate combination with at least part of the other embodiments described in this specification.

(Embodiment 2)
In this embodiment, one embodiment of a semiconductor device using the oxide described in any of the above embodiments as a semiconductor layer will be described with reference to FIGS.

<Transistor structure 1>
An example of a transistor according to one embodiment of the present invention using the oxide described in the above embodiment will be described below. 44A, 44B, and 44C are a top view and a cross-sectional view of a transistor according to one embodiment of the present invention. 44A is a top view, FIG. 44B is a cross-sectional view corresponding to the dashed-dotted line X1-X2 shown in FIG. 44A, and FIG. 44C is a cross-sectional view corresponding to the dashed-dotted line Y1-Y2. . Note that for simplification of the drawing, some components are not illustrated in the top view in FIG.

  The transistor 200 includes a conductor 205 (a conductor 205a and a conductor 205b) that functions as a gate electrode, and a conductor 260 (a conductor 260a and a conductor 260b), an insulator 220 that functions as a gate insulating layer, and an insulator. The body 222, the insulator 224, and the insulator 250, the oxide 230 having a region where a channel is formed (the oxide 230a, the oxide 230b, and the oxide 230c), and the conductor functioning as one of a source and a drain 240a, a conductor 240b functioning as the other of the source and the drain, an insulator 280 having excess oxygen, and an insulator 282 having a barrier property. The conductor 205 is preferably provided so as to be embedded in an opening formed in the insulator 216. The conductor 205 and the insulator 216 are preferably provided over the insulator 214.

  The oxide 230 includes an oxide 230a, an oxide 230b over the oxide 230a, and an oxide 230c over the oxide 230b. Note that when the transistor 200 is turned on, a current flows mainly in the oxide 230b (a channel is formed). On the other hand, in the oxide 230a and the oxide 230c, a current may flow in the vicinity of the interface with the oxide 230b (which may be a mixed region), but the other region may function as an insulator. .

  As shown in FIG. 44, the oxide 230c is preferably provided so as to cover the side surfaces of the oxide 230a and the oxide 230b. When the oxide 230c is interposed between the insulator 280 and the oxide 230b having a region where a channel is formed, impurities such as hydrogen, water, and halogen are transferred from the insulator 280 to the oxide 230b. Diffusion can be suppressed.

  The conductor 205 includes a metal film containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium, or a metal nitride film containing any of the above elements as a component (tantalum nitride, nitride). Titanium film, molybdenum nitride film, tungsten nitride film). In particular, a metal nitride film such as tantalum nitride is preferable because it has a barrier property against hydrogen or oxygen and is difficult to oxidize (high oxidation resistance). Or indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, silicon oxide added It is also possible to apply a conductive material such as indium tin oxide.

  For example, tantalum nitride or the like may be used as the conductor 205a as a conductor having a barrier property against hydrogen, and tungsten having high conductivity may be stacked as the conductor 205b. By using the combination, diffusion of hydrogen into the oxide 230 can be suppressed while maintaining conductivity as a wiring. Note that FIG. 44 illustrates a two-layer structure of the conductor 205a and the conductor 205b; however, the structure is not limited thereto, and may be a single layer or a stacked structure including three or more layers. For example, a conductor having a high barrier property and a conductor having a high barrier property may be formed between a conductor having a barrier property and a conductor having a high conductivity.

  The insulator 220 and the insulator 224 are preferably insulators containing oxygen such as a silicon oxide film or a silicon oxynitride film. In particular, as the insulator 224, an insulator containing excess oxygen (containing oxygen in excess of the stoichiometric composition) is preferably used. By providing such an insulator containing excess oxygen in contact with the oxide included in the transistor 200, oxygen vacancies in the oxide can be compensated. Note that the insulator 222 and the insulator 224 are not necessarily made of the same material. The insulator 216 can also be formed using a material similar to that of the insulator 220 and the insulator 224.

The insulator 222 is formed of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO ₃ ), or (Ba, An insulator containing a so-called high-k material such as Sr) TiO ₃ (BST) is preferably used in a single layer or a stacked layer. In particular, an insulating film having a barrier property against oxygen and hydrogen, such as aluminum oxide and hafnium oxide, is preferably used. In the case of using such a material, it functions as a layer which prevents release of oxygen from the oxide 230 and entry of impurities such as hydrogen from the outside.

  Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. Silicon insulator, silicon oxynitride, or silicon nitride may be stacked over the above insulator.

  Note that the insulator 220, the insulator 222, and the insulator 224 may have a stacked structure of two or more layers. In that case, it is not limited to the laminated structure which consists of the same material, The laminated structure which consists of a different material may be sufficient.

  By including the insulator 222 including a high-k material between the insulator 220 and the insulator 224, the insulator 222 can capture electrons under a specific condition and increase the threshold voltage. That is, the insulator 222 may be negatively charged.

  For example, in the case where silicon oxide is used for the insulator 220 and the insulator 224 and a material with many electron capture levels such as hafnium oxide, aluminum oxide, or tantalum oxide is used for the insulator 222, the operating temperature of the semiconductor device Or under a temperature higher than the storage temperature (eg, 125 ° C. or higher and 450 ° C. or lower, typically 150 ° C. or higher and 300 ° C. or lower), the potential of the conductor 205 is higher than the potential of the source electrode or the drain electrode. By maintaining for 10 milliseconds or longer, typically 1 minute or longer, electrons move from the oxide included in the transistor 200 toward the conductor 205. At this time, some of the moving electrons are captured by the electron capture level of the insulator 222.

  The threshold voltage of the transistor that captures an amount of electrons necessary for the electron trap level of the insulator 222 is shifted to the positive side. Note that the amount of electrons captured can be controlled by controlling the voltage of the conductor 205, and the threshold voltage can be controlled accordingly. With this structure, the transistor 200 is a normally-off transistor that is non-conductive (also referred to as an off state) even when the gate voltage is 0 V.

  Further, the process for capturing electrons may be performed in the manufacturing process of the transistor. For example, either after the formation of the conductor connected to the source conductor or drain conductor of the transistor, after the completion of the previous process (wafer processing), after the wafer dicing process, after packaging, etc. This should be done in stages.

  In addition, the threshold voltage can be controlled by appropriately adjusting the film thicknesses of the insulator 220, the insulator 222, and the insulator 224. For example, when the total thickness of the insulator 220, the insulator 222, and the insulator 220 is reduced, a voltage from the conductor 205 is efficiently applied, so that a transistor with low power consumption can be provided. The total film thickness of the insulator 220, the insulator 222, and the insulator 224 is 65 nm or less, preferably 20 nm or less.

  Accordingly, it is possible to provide a transistor with small leakage current when non-conducting. In addition, a transistor having stable electrical characteristics can be provided. Alternatively, a transistor with high on-state current can be provided. Alternatively, a transistor with a small subthreshold swing value can be provided. Alternatively, a highly reliable transistor can be provided.

  The oxide 230a, the oxide 230b, and the oxide 230c are formed using a metal oxide such as an In-M-Zn oxide (M is Al, Ga, Y, or Sn). Here, as the oxide 230a, the oxide 230b, and the oxide 230c, an oxide formed by the above film formation mechanism can be used. For example, the oxide S1 can be used as the oxide 230a, the oxide S2 can be used as the oxide 230b, and the oxide S3 can be used as the oxide 230c. Further, as the oxide 230, an In—Ga oxide or an In—Zn oxide may be used.

The insulator 250 is formed of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO ₃ ), or (Ba, An insulator containing a so-called high-k material such as Sr) TiO ₃ (BST) can be used as a single layer or a stacked layer. Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators. Alternatively, these insulators may be nitrided. Silicon insulator, silicon oxynitride, or silicon nitride may be stacked over the above insulator.

  The insulator 250 is preferably formed using an oxide insulator containing oxygen in excess of the stoichiometric composition, like the insulator 224. By providing such an insulator containing excess oxygen in contact with the oxide 230, oxygen vacancies in the oxide 230 can be reduced.

  The insulator 250 has a barrier property against oxygen and hydrogen such as aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, and silicon nitride. An insulating film can be used. In the case of using such a material, it functions as a layer which prevents release of oxygen from the oxide 230 and entry of impurities such as hydrogen from the outside.

  Note that the insulator 250 may have a stacked structure similar to that of the insulator 220, the insulator 222, and the insulator 224. When the insulator 250 includes an insulator that captures an amount of electrons necessary for the electron capture level, the transistor 200 can shift the threshold voltage to the positive side. With this structure, the transistor 200 is a normally-off transistor that is non-conductive (also referred to as an off state) even when the gate voltage is 0 V.

  In the semiconductor device illustrated in FIG. 44, a barrier film may be provided between the oxide 230 and the conductor 260 in addition to the insulator 250. Alternatively, the oxide 230c having a barrier property may be used.

  For example, by providing an insulating film containing excess oxygen in contact with the oxide 230 and encapsulating the oxide film with a barrier film, oxygen may be in a state in which the oxide substantially matches the stoichiometric composition or in a stoichiometric composition. Many supersaturated states can be obtained. In addition, entry of impurities such as hydrogen into the oxide 230 can be prevented.

  One of the conductor 240a and the conductor 240b functions as a source electrode, and the other functions as a drain electrode.

  For the conductor 240a and the conductor 240b, a metal such as aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, or tungsten, or an alloy containing the same as a main component can be used. . In particular, a metal nitride film such as tantalum nitride is preferable because it has a barrier property against hydrogen or oxygen and has high oxidation resistance.

  Further, although a single layer structure is shown in the figure, a stacked structure of two or more layers may be used. For example, a tantalum nitride and tungsten film may be stacked. In addition, a titanium film and an aluminum film are preferably stacked. Also, a two-layer structure in which an aluminum film is stacked on a tungsten film, a two-layer structure in which a copper film is stacked on a copper-magnesium-aluminum alloy film, a two-layer structure in which a copper film is stacked on a titanium film, and a tungsten film A two-layer structure in which copper films are stacked may be used.

  In addition, a titanium film or a titanium nitride film and a three-layer structure in which an aluminum film or a copper film is laminated on the titanium film or the titanium nitride film, and a titanium film or a titanium nitride film is further formed thereon, a molybdenum film or There is a three-layer structure in which a molybdenum nitride film and an aluminum film or a copper film are stacked over the molybdenum film or the molybdenum nitride film and a molybdenum film or a molybdenum nitride film is further formed thereon. Note that a transparent conductive material containing indium oxide, tin oxide, or zinc oxide may be used.

  The conductor 260 having a function as a gate electrode is, for example, a metal selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, tungsten, an alloy containing the above-described metal as a component, or a combination of the above-described metals. It can be formed using an alloy or the like. In particular, a metal nitride film such as tantalum nitride is preferable because it has a barrier property against hydrogen or oxygen and has high oxidation resistance. Further, a metal selected from one or more of manganese and zirconium may be used. Alternatively, a semiconductor typified by polycrystalline silicon doped with an impurity element such as phosphorus, or silicide such as nickel silicide may be used. Further, although a two-layer structure is shown in the figure, a single layer or a stacked structure of three or more layers may be used.

  Note that the two-layer structure may be formed by stacking the same materials. For example, the conductor 260a is formed using a thermal CVD method, an MOCVD method, or an ALD method. In particular, it is preferably formed by using an atomic layer deposition (ALD) method. By forming by the ALD method or the like, damage during film formation on the insulator 250 can be reduced. Moreover, it is preferable because the coverage can be improved. Therefore, the transistor 200 with high reliability can be provided.

  Subsequently, the conductor 260b is formed by a sputtering method. At this time, by including the conductor 260 a over the insulator 250, it is possible to suppress the damage during the deposition of the conductor 260 a from affecting the insulator 250. Further, since the sputtering method has a higher film formation rate than the ALD method, the yield is high and the productivity can be improved.

  For example, a two-layer structure in which a titanium film is stacked over aluminum is preferable. Alternatively, a two-layer structure in which a titanium film is stacked on a titanium nitride film, a two-layer structure in which a tungsten film is stacked on a titanium nitride film, or a two-layer structure in which a tungsten film is stacked on a tantalum nitride film or a tungsten nitride film may be employed. .

  Further, there are a titanium film and a three-layer structure in which an aluminum film is stacked on the titanium film and a titanium film is further formed thereon. Alternatively, an alloy film or a nitride film in which one or more metals selected from aluminum, titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium are combined may be used.

  The conductor 260 includes indium tin oxide, indium oxide including tungsten oxide, indium zinc oxide including tungsten oxide, indium oxide including titanium oxide, indium tin oxide including titanium oxide, and indium zinc oxide. Alternatively, a light-transmitting conductive material such as indium tin oxide to which silicon oxide is added can be used. Alternatively, a stacked structure of the above light-transmitting conductive material and the above metal can be used.

  Subsequently, an insulator 280 and an insulator 282 are provided above the transistor 200.

  For the insulator 280, an oxide containing more oxygen than that in the stoichiometric composition is preferably used. That is, the insulator 280 is preferably formed with a region where oxygen is present in excess of the stoichiometric composition (hereinafter also referred to as an excess oxygen region). In particular, in the case where an oxide semiconductor is used for the transistor 200, reliability is improved by providing an insulator having an excess oxygen region in an interlayer film or the like in the vicinity of the transistor 200 to reduce oxygen vacancies in the transistor 200. Can do.

Specifically, an oxide material from which part of oxygen is released by heating is preferably used as the insulator having an excess oxygen region. The oxide which desorbs oxygen by heating means that the amount of desorbed oxygen converted to oxygen atoms is 1.0 × 10 ¹⁸ atoms / cm ³ or more, preferably 3.0 × 10 ²⁰ in TDS analysis. An oxide film having atoms / cm ³ or more. The surface temperature of the film at the time of TDS analysis is preferably in the range of 100 ° C. to 700 ° C., or 100 ° C. to 500 ° C.

  For example, as such a material, a material containing silicon oxide or silicon oxynitride is preferably used. Alternatively, a metal oxide can be used. Note that in this specification, silicon oxynitride refers to a material having a higher oxygen content than nitrogen as its composition, and silicon nitride oxide refers to a material having a higher nitrogen content than oxygen as its composition. Indicates.

  Further, the insulator 280 that covers the transistor 200 may function as a planarization film that covers the uneven shape below the transistor 200.

  The insulator 282 is preferably formed using an insulating film having a barrier property against oxygen and hydrogen, such as aluminum oxide and hafnium oxide. In the case of using such a material, it functions as a layer which prevents release of oxygen from the oxide 230 and entry of impurities such as hydrogen from the outside. The insulator 214 can also be formed using a material similar to that of the insulator 282.

  With the above structure, a transistor including an oxide semiconductor with high on-state current can be provided. Alternatively, a transistor including an oxide semiconductor with low off-state current can be provided. Alternatively, by using the transistor having the above structure in a semiconductor device, variation in electrical characteristics of the semiconductor device can be suppressed and reliability can be improved. Alternatively, a semiconductor device with reduced power consumption can be provided.

<Transistor structure 2>
FIG. 45 illustrates an example of a structure that can be applied to the transistor 200. FIG. 45A illustrates the top surface of the transistor 200. Note that some films are omitted in FIG. 45A for clarity. FIG. 45B is a cross-sectional view corresponding to the alternate long and short dash line X1-X2 illustrated in FIG. 45A, and FIG. 45C is a cross-sectional view corresponding to Y1-Y2.

  Note that in the transistor 200 illustrated in FIG. 45, the structure having the same function as the structure of the transistor 200 illustrated in FIG.

  In the structure illustrated in FIG. 45, an insulator 270 is provided so as to cover the conductor 260. In the case where an oxide material from which oxygen is released is used for the insulator 280, the insulator 270 is formed using a substance having a barrier property against oxygen in order to prevent the conductor 260 from being oxidized by the released oxygen. .

  For example, the insulator 270 can be formed using a metal oxide such as aluminum oxide. The insulator 270 may be provided to such an extent that the conductor 260 is prevented from being oxidized. For example, the thickness of the insulator 270 is 1 nm to 10 nm, preferably 3 nm to 7 nm.

  With this configuration, the range of material selection for the conductor 260 can be increased. For example, a material having low conductivity while having low oxidation resistance such as aluminum can be used. For example, a conductor that can be easily formed or processed can be used.

  Accordingly, oxidation of the conductor 260 can be suppressed, and oxygen released from the insulator 280 can be efficiently supplied to the oxide 230. In addition, by using a highly conductive conductor for the conductor 260, the transistor 200 with low power consumption can be provided.

<Transistor structure 3>
FIG. 46 illustrates an example of a structure that can be applied to the transistor 200. FIG. 46A illustrates the top surface of the transistor 200. Note that some films are omitted in FIG. 46A for clarity. 46B is a cross-sectional view corresponding to the dashed-dotted line X1-X2 illustrated in FIG. 46A, and FIG. 46C is a cross-sectional view corresponding to Y1-Y2.

  46, the structure having the same function as the structure of the transistor 200 illustrated in FIG. 44 is denoted by the same reference numeral.

  In the structure illustrated in FIG. 46, the conductor 260 functioning as a gate electrode includes a conductor 260a, a conductor 260b, and a conductor 260c. The oxide 230c only needs to cover the side surface of the oxide 230b, and may be cut on the insulator 224.

  The conductor 260a is formed using a thermal CVD method, an MOCVD method, or an ALD method. In particular, it is preferably formed by using an atomic layer deposition (ALD) method. By forming by the ALD method or the like, damage to the insulator 250 due to plasma can be reduced. Moreover, it is preferable because the coverage can be improved. Therefore, the transistor 200 with high reliability can be provided.

  The conductor 260b is formed using a highly conductive material such as tantalum, tungsten, copper, or aluminum. Further, the conductor 260c formed over the conductor 260b is preferably formed using a conductor having high oxidation resistance such as tungsten nitride.

  For example, in the case where an oxide material from which oxygen is released is used for the insulator 280, a conductor having high oxidation resistance is used for the conductor 260c having a large area in contact with the insulator 280 having an excess oxygen region, thereby preventing excess oxygen from It is possible to suppress the desorbed oxygen from being absorbed by the conductor 260. Further, oxidation of the conductor 260 can be suppressed, and oxygen released from the insulator 280 can be efficiently supplied to the oxide 230. In addition, by using a highly conductive conductor for the conductor 260b, the transistor 200 with low power consumption can be provided.

  As shown in FIG. 46C, the transistor 230 and the oxide 230b are covered with the conductor 205 and the conductor 260 in the channel width direction. In addition, since the insulator 224 has a protrusion, the side surface of the oxide 230 b can be covered with the conductor 260. For example, it is preferable that the shape of the protrusion of the insulator 224 be adjusted so that the bottom surface of the conductor 260 is closer to the substrate side than the bottom surface of the oxide 230b on the side surface of the oxide 230b. In other words, the transistor 200 has a structure in which the oxide 230 b can be electrically surrounded by the electric fields of the conductor 205 and the conductor 260. In this manner, the structure of the transistor that electrically surrounds the oxide 230b by the electric field of the conductor is referred to as a surrounded channel (s-channel) structure. In the transistor 200 having an s-channel structure, a channel can be formed in the entire oxide 230b (bulk). In the s-channel structure, the drain current of the transistor can be increased, and a larger on-current (current flowing between the source and the drain when the transistor is on) can be obtained. Further, the entire region of the channel formation region formed in the oxide 230b can be depleted by the electric fields of the conductor 205 and the conductor 260. Therefore, in the s-channel structure, the off-state current of the transistor can be further reduced. Note that by reducing the channel width, the effect of increasing the on-current, the effect of reducing the off-current, and the like by the s-channel structure can be enhanced.

  In the structure illustrated in FIG. 46, a conductor functioning as a source or a drain has a stacked structure. The conductor 240a and the conductor 240b are preferably formed using a conductor that has high adhesion to the oxide 230b, and the conductor 241a and the conductor 241b are preferably formed using a material having high conductivity. In addition, the conductor 240a and the conductor 240b are preferably formed by using an atomic layer deposition (ALD) method. By forming by ALD method or the like, the coverage can be improved.

  For example, in the case where a metal oxide containing indium is used for the oxide 230b, titanium nitride or the like may be used for the conductor 240a and the conductor 240b. Further, by using a highly conductive material such as tantalum, tungsten, copper, or aluminum for the conductor 241a and the conductor 241b, the transistor 200 with high reliability and low power consumption can be provided.

<Transistor structure 4>
FIG. 47 illustrates an example of a structure that can be applied to the transistor 200. FIG. 47A illustrates the top surface of the transistor 200. Note that some films are omitted in FIG. 47A for clarity. 47B is a cross-sectional view corresponding to the dashed-dotted line X1-X2 illustrated in FIG. 47A, and FIG. 47C is a cross-sectional view corresponding to Y1-Y2.

  47, the structure having the same function as the structure of the transistor 200 illustrated in FIG. 44 is denoted by the same reference numeral.

  As illustrated in FIG. 47C, the transistor 230 and the oxide 230b are covered with the conductor 205 and the conductor 260 in the channel width direction. In addition, since the insulator 222 has a convex portion, the side surface of the oxide 230 b can be covered with the conductor 260.

Here, in the case where a high-k material such as hafnium oxide is used for the insulator 222, the dielectric constant of the insulator 222 is large, so that the equivalent SiO ₂ film thickness (EOT: Equivalent Oxide Thickness) can be reduced. . Therefore, the distance between the conductor 205 and the oxide 230 can be increased by the physical thickness of the insulator 222 without weakening the influence of the electric field from the conductor 205 on the oxide 230. Therefore, the distance between the conductor 205 and the oxide 230 can be adjusted by the thickness of the insulator 222.

  For example, it is preferable that the shape of the protrusion of the insulator 224 be adjusted so that the bottom surface of the conductor 260 is closer to the substrate side than the bottom surface of the oxide 230b on the side surface of the oxide 230b. In other words, the transistor 200 has a structure in which the oxide 230 b can be electrically surrounded by the electric fields of the conductor 205 and the conductor 260. In this manner, the structure of the transistor that electrically surrounds the oxide 230b by the electric field of the conductor is referred to as a surrounded channel (s-channel) structure. In the transistor 200 having an s-channel structure, a channel can be formed in the entire oxide 230b (bulk). In the s-channel structure, the drain current of the transistor can be increased, and a larger on-current (current flowing between the source and the drain when the transistor is on) can be obtained. Further, the entire region of the channel formation region formed in the oxide 230b can be depleted by the electric fields of the conductor 205 and the conductor 260. Therefore, in the s-channel structure, the off-state current of the transistor can be further reduced. Note that by reducing the channel width, the effect of increasing the on-current, the effect of reducing the off-current, and the like by the s-channel structure can be enhanced.

  In addition, as illustrated in FIGS. 47B and 47C, the oxide 230c may be formed so that the side surfaces of the oxide 230c substantially coincide with the side surfaces of the insulator 250 and the conductor 260. Accordingly, pattern formation of the oxide 230c, the insulator 250, and the conductor 260 can be performed at a time, so that the process can be simplified. Here, as the conductor 240a and the conductor 240b, a metal nitride such as tantalum nitride which has a barrier property against hydrogen or oxygen and is difficult to be oxidized (high oxidation resistance) can be used. 240b can be prevented from being oxidized. In addition, excess oxygen can be easily supplied from the insulator 280 to the oxide 230b.

<Transistor structure 5>
FIG. 48 illustrates an example of a structure that can be applied to the transistor 200. FIG. 48A illustrates the top surface of the transistor 200. Note that some films are omitted in FIG. 48A for clarity. FIG. 48B is a cross-sectional view corresponding to the dashed-dotted line X1-X2 illustrated in FIG. 48A, and FIG. 48C is a cross-sectional view corresponding to Y1-Y2.

  Note that in the transistor 200 illustrated in FIG. 48, the structure having the same function as the structure of the transistor 200 illustrated in FIG.

  In the transistor 200 illustrated in FIG. 48, the oxide 230 c, the insulator 250, and the conductor 260 are formed in the opening formed in the insulator 280. In addition, one end portion of the conductor 240a, the conductor 240b, the conductor 241a, and the conductor 241b is aligned with the end portion of the opening formed in the insulator 280. Further, three end portions of the conductor 240 a, the conductor 240 b, the conductor 241 a, and the conductor 241 b coincide with part of the end portion of the oxide 230. Therefore, the conductor 240a, the conductor 240b, the conductor 241a, and the conductor 241b can be simultaneously shaped with the opening of the oxide 230 or the insulator 280. Therefore, masks and processes can be reduced. In addition, yield and productivity can be improved.

  The conductor 240a, the conductor 240b, the oxide 230c, and the oxide 230b are in contact with the insulator 280 having an excess oxygen region through the oxide 230d. Therefore, the oxide 230d is interposed between the insulator 280 and the oxide 230b having a region where a channel is formed, so that impurities such as hydrogen, water, and halogen can be extracted from the insulator 280. It is possible to suppress diffusion to 230b.

  Further, the transistor 200 illustrated in FIG. 48 has a structure in which the conductor 240a, the conductor 240b, the conductor 241a, the conductor 241b, and the conductor 260 hardly overlap with each other, so that the parasitic capacitance applied to the conductor 260 is reduced. Can be small. That is, the transistor 200 having a high operating frequency can be provided.

<Transistor structure 6>
FIG. 49 illustrates an example of a structure that can be applied to the transistor 200. FIG. 49A illustrates the top surface of the transistor 200. Note that some films are omitted in FIG. 49A for clarity. FIG. 49B is a cross-sectional view corresponding to the dashed-dotted line X1-X2 shown in FIG. 49A, and FIG. 49C is a cross-sectional view corresponding to Y1-Y2.

  49, the structure having the same function as the structure of the transistor 200 illustrated in FIG. 44 is denoted by the same reference numeral.

  A transistor 200 illustrated in FIG. 49 has a structure without the oxide 230d. For example, when a conductor having high oxidation resistance is used for the conductor 240a and the conductor 240b, the oxide 230d is not necessarily provided. Therefore, masks and processes can be reduced. In addition, yield and productivity can be improved.

  The insulator 224 may be provided only in a region overlapping with the oxide 230a and the oxide 230b. In this case, the oxide 230a, the oxide 230b, and the insulator 224 can be processed using the insulator 222 as an etching stopper. Therefore, yield and productivity can be increased.

  Further, the transistor 200 illustrated in FIG. 49 has a structure in which the conductor 240a, the conductor 240b, the conductor 241a, and the conductor 241b and the conductor 260 hardly overlap with each other, so that the parasitic capacitance applied to the conductor 260 is reduced. Can be small. That is, the transistor 200 having a high operating frequency can be provided.

<Transistor structure 7>
FIG. 50 illustrates an example of a structure that can be applied to the transistor 200. FIG. 50A illustrates the top surface of the transistor 200. Note that some films are omitted in FIG. 50A for clarity. 50B is a cross-sectional view corresponding to the dashed-dotted line X1-X2 illustrated in FIG. 50A, and FIG. 50C is a cross-sectional view corresponding to Y1-Y2.

  50, the structure having the same function as the structure of the transistor 200 illustrated in FIG. 48 is denoted by the same reference numeral.

  An insulator 285 and an insulator 286 are formed over the insulator 282.

  An oxide 230c, an insulator 250, and a conductor 260 are formed in openings formed in the insulator 280, the insulator 282, and the insulator 285. In addition, one end portion of the conductor 240a, the conductor 240b, the conductor 241a, and the conductor 241b is aligned with the end portion of the opening formed in the insulator 280. Further, three end portions of the conductor 240a, the conductor 240b, the conductor 241a, and the conductor 241b coincide with part of the end portions of the oxide 230a and the oxide 230b. Therefore, the conductor 240a, the conductor 240b, the conductor 241a, and the conductor 241b can be simultaneously shaped with the opening portion of the oxide 230a and the oxide 230b or the insulator 280. Therefore, masks and processes can be reduced. In addition, yield and productivity can be improved.

  The conductor 240a, the conductor 240b, the oxide 230c, and the oxide 230b are in contact with the insulator 280 having an excess oxygen region through the oxide 230d. Therefore, the oxide 230d is interposed between the insulator 280 and the oxide 230b having a region where a channel is formed, so that impurities such as hydrogen, water, and halogen can be extracted from the insulator 280. It is possible to suppress diffusion to 230b.

  50 does not have a high-resistance offset region, the on-state current of the transistor 200 can be increased.

<Method for Manufacturing Transistor>
An example of a method for manufacturing the transistor illustrated in FIGS. 44A to 44C is described below with reference to FIGS.

  First, a substrate is prepared (not shown). There is no particular limitation on a substrate that can be used as the substrate, but it is preferable that the substrate have heat resistance enough to withstand at least heat treatment performed later. For example, a glass substrate such as barium borosilicate glass or alumino borosilicate glass, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like can be used. In addition, a single crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate made of silicon germanium, gallium arsenide, indium arsenide, or indium gallium arsenide, an SOI (Silicon On Insulator) substrate, or a GOI (Germanium On Insulator). A substrate or the like can also be applied, and a substrate in which a semiconductor element is provided over these substrates may be used.

  Further, a semiconductor device may be manufactured using a flexible substrate as the substrate. In order to manufacture a flexible semiconductor device, a transistor may be directly manufactured over a flexible substrate, or a transistor is manufactured over another manufacturing substrate, and then peeled off and transferred to the flexible substrate. Also good. Note that in order to separate the transistor from the manufacturing substrate and transfer it to the flexible substrate, a separation layer may be provided between the manufacturing substrate and the transistor including an oxide semiconductor.

  Next, the insulator 214 and the insulator 216 are formed. Next, a resist mask 290 is formed over the insulator 216 by a lithography method or the like, and the insulator 214 and unnecessary portions of the insulator 216 are removed (see FIG. 51A). After that, by removing the resist mask 290, an opening can be formed.

  Here, a method for processing a film to be processed will be described. In the case of finely processing a film to be processed, various fine processing techniques can be used. For example, a method of performing a slimming process on a resist mask formed by a lithography method or the like may be used. Alternatively, a dummy pattern may be formed by lithography or the like, a sidewall may be formed on the dummy pattern, the dummy pattern may be removed, and the processed film may be etched using the remaining sidewall as a resist mask. In order to realize a high aspect ratio, it is preferable to use anisotropic dry etching as etching of the film to be processed. Further, a hard mask made of an inorganic film or a metal film may be used.

  As light used for forming the resist mask, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or light obtained by mixing them can be used. In addition, ultraviolet light, KrF laser light, ArF laser light, or the like can be used. Further, exposure may be performed by an immersion exposure technique. Further, extreme ultraviolet light (EUV: Extreme Ultra-violet) or X-rays may be used as light used for exposure. Further, an electron beam can be used instead of the light used for exposure. It is preferable to use extreme ultraviolet light, X-rays, or an electron beam because extremely fine processing is possible. Note that a photomask is not necessary when exposure is performed by scanning a beam such as an electron beam.

  Further, an organic resin film having a function of improving the adhesion between the film to be processed and the resist film may be formed before forming the resist film to be a resist mask. The organic resin film can be formed, for example, by a spin coating method so as to cover the level difference below and flatten the surface, and variations in the thickness of the resist mask provided above the organic resin film Can be reduced. In particular, when performing fine processing, it is preferable to use a material that functions as an antireflection film for light used for exposure as the organic resin film. Examples of the organic resin film having such a function include a BARC (Bottom Anti-Reflection Coating) film. The organic resin film may be removed at the same time as the resist mask is removed or after the resist mask is removed.

  Subsequently, the conductor 205A and the conductor 205B are formed over the insulator 214 and the insulator 216. The conductors 205A and 205B can be formed by a sputtering method, an evaporation method, a CVD method (including a thermal CVD method, an MOCVD method, a PECVD method, or the like). In order to reduce plasma damage, thermal CVD, MOCVD, or ALD is preferable (see FIG. 51B).

  Subsequently, unnecessary portions of the conductor 205A and the conductor 205B are removed. For example, by removing a part of the conductor 205A and the conductor 205B until the insulator 216 is exposed by an etch-back process or a mechanical chemical polishing (CMP) process or the like, A conductor 205 is formed (see FIG. 51C). At this time, the insulator 216 can also be used as a stopper layer, and the insulator 216 may be thin.

  Here, the CMP process is a technique for flattening the surface of a workpiece by a combined chemical and mechanical action. More specifically, a polishing cloth is attached on the polishing stage, and the polishing stage and the workpiece are rotated or swung while supplying slurry (abrasive) between the workpiece and the polishing cloth. In this method, the surface of the workpiece is polished by a chemical reaction between the slurry and the surface of the workpiece and by mechanical polishing between the polishing cloth and the workpiece.

  The CMP process may be performed only once or a plurality of times. When performing the CMP process in a plurality of times, it is preferable to perform primary polishing at a low polishing rate after performing primary polishing at a high polishing rate. In this way, polishing with different polishing rates may be combined.

  Next, the insulator 220, the insulator 222, and the insulator 224 are formed (see FIG. 51D).

  The insulator 220, the insulator 222, and the insulator 224 can be formed using a material and a method similar to those of the insulator 320. In particular, the insulator 222 is preferably formed using a high-k material such as hafnium oxide.

  The insulator 220, the insulator 222, and the insulator 224 are formed using, for example, a sputtering method, a chemical vapor deposition (CVD) method (thermal CVD method, a metal organic chemical vapor deposition (MOCVD) method, or a chemical vapor deposition (MOCVD) method, Plasma-excited CVD (including PECVD: Plasma Enhanced Chemical Deposition) method, molecular epitaxy (MBE) method, atomic layer deposition (ALD: Atomic Layer Deposition Laser deposition) ) Method or the like. In particular, it is preferable to form the insulator by a CVD method, preferably an ALD method, because coverage can be improved. In order to reduce damage caused by plasma, thermal CVD, MOCVD, or ALD is preferable. Alternatively, a silicon oxide film with good step coverage formed by reacting TEOS (Tetra-Ethyl-Ortho-Silicate) or silane with oxygen, nitrous oxide, or the like can be used.

  Note that the insulator 220, the insulator 222, and the insulator 224 are preferably formed successively. By forming a film continuously, an insulator with high reliability can be formed without an impurity adhering to the interface between the insulator 220 and the insulator 222 and the interface between the insulator 222 and the insulator 224. it can.

  Subsequently, an oxide 230A to be the oxide 230a and an oxide 230B to be the oxide 230b are sequentially formed. For the film formation method of the oxide 230A and the oxide 230B, the description on the oxide can be referred to. The oxide is preferably formed continuously without being exposed to the air.

  After that, a conductive film 240A to be the conductor 240a and the conductor 240b is formed over the oxide 230A. The conductive film 240A is preferably formed using a material that has a barrier property against hydrogen or oxygen and also has high oxidation resistance. In addition, although a single layer is shown in the figure, a stacked structure of two or more layers may be used. Subsequently, a resist mask 292 is formed by a method similar to the above (see FIG. 51E).

  Using the resist mask 292, an unnecessary portion of the conductive film 240A is removed by etching, so that an island-shaped conductive layer 240B is formed (see FIG. 52A). After that, unnecessary portions of the oxide 230a and the oxide 230b are removed by etching using the conductive layer 240B as a mask.

  At this time, the insulator 224 may be processed into an island shape at the same time. For example, by using the insulator 222 having a barrier property as an etching stopper film, even in a structure where the total thickness of the insulator 220, the insulator 222, and the insulator 220 is thin, over-etching is performed up to the wiring layer below. Can be prevented. In addition, since the voltage from the conductor 205 is efficiently applied by reducing the total thickness of the insulator 220, the insulator 222, and the insulator 220, a transistor with low power consumption can be provided.

  After that, by removing the resist mask, a stacked structure of the island-shaped oxide 230a, the island-shaped oxide 230b, and the island-shaped conductive layer 240B can be formed (see FIG. 52B).

  Subsequently, heat treatment is preferably performed (see FIG. 52C, an arrow in the drawing represents heat treatment). The heat treatment may be performed at a temperature of 250 ° C. to 400 ° C., preferably 320 ° C. to 380 ° C., in an inert gas atmosphere, an atmosphere containing an oxidizing gas of 10 ppm or more, or in a reduced pressure state. The atmosphere for the heat treatment may be an atmosphere containing 10 ppm or more of an oxidizing gas in order to supplement the desorbed oxygen after the heat treatment in an inert gas atmosphere. By the heat treatment, hydrogen or water which is an impurity of the oxide 230a and the oxide 230b can be removed. Further, oxygen is supplied to the oxide 230a and the oxide 230b from the insulator formed below the oxide 230a, so that oxygen vacancies in the oxide can be reduced.

  Next, a resist mask 294 is formed over the island-shaped conductive layer 240B by a method similar to the above (see FIG. 52D). Subsequently, after unnecessary portions of the conductive film are removed by etching, the resist mask 294 is removed, so that the conductors 240a and 240b are formed (see FIG. 53A). At this time, the insulator 224 or the insulator 222 may be over-etched to have an s-channel structure.

  Subsequently, it is preferable to perform heat treatment (see FIG. 53B, arrows in the drawing represent heat treatment). The heat treatment may be performed at a temperature of 250 ° C. to 400 ° C., preferably 320 ° C. to 380 ° C., in an inert gas atmosphere, an atmosphere containing an oxidizing gas of 10 ppm or more, or in a reduced pressure state. The atmosphere for the heat treatment may be an atmosphere containing 10 ppm or more of an oxidizing gas in order to supplement the desorbed oxygen after the heat treatment in an inert gas atmosphere. By the heat treatment, hydrogen or water which is an impurity of the oxide 230a and the oxide 230b can be removed. Further, oxygen is supplied to the oxide 230a and the oxide 230b from the insulator formed below the oxide 230a, so that oxygen vacancies in the oxide can be reduced. Further, in the case where heat treatment is performed with an oxidizing gas, oxygen vacancies in the region where the channel is formed can be efficiently reduced by contacting the oxidizing gas directly with the region where the channel is formed.

  Subsequently, an oxide 230c, an insulator 250, and a conductive film 260A to be the conductor 260 are sequentially formed. For the film formation method of the oxide 230c, the description on the oxide can be referred to. The conductive film 260A is preferably formed using a material having a barrier property against hydrogen or oxygen and high oxidation resistance. In addition, although a single layer is shown in the figure, a stacked structure of two or more layers may be used.

  For example, the two-layer structure may be provided by stacking the same material. The first conductive film is formed using a thermal CVD method, an MOCVD method, or an ALD method. In particular, it is preferable to form using the ALD method. By forming by the ALD method or the like, damage during film formation on the insulator 250 can be reduced. Moreover, it is preferable because the coverage can be improved. Therefore, the transistor 200 with high reliability can be provided.

  Subsequently, the second conductive film is formed by a sputtering method. At this time, by having the first conductive film over the insulator 250, it is possible to suppress the damage during the deposition of the second conductive film from affecting the insulator 250. Further, since the sputtering method has a higher film formation rate than the ALD method, the yield is high and the productivity can be improved. Note that it is preferable that the conductive film 260A be formed using a deposition gas that does not contain chlorine.

  Next, a resist mask 296 is formed over the conductive film 260A by a method similar to the above (see FIG. 53C). Next, unnecessary portions of the conductive film 260A are removed by etching, whereby the conductor 260 is formed, and then the resist mask 296 is removed (see FIG. 53D).

  Subsequently, the insulator 280 is formed over the conductor 260. The insulator 280 is an insulator containing oxygen, such as a silicon oxide film or a silicon oxynitride film. As a method for forming an insulator containing excess oxygen, a film formation condition in a CVD method or a sputtering method can be set as appropriate to form a silicon oxide film or a silicon oxynitride film containing a large amount of oxygen in the film. . Alternatively, oxygen may be added by an ion implantation method, an ion doping method, or plasma treatment after the silicon oxide film or the silicon oxynitride film is formed.

  In particular, oxygen plasma treatment is preferably performed (see FIG. 54A, arrows in the drawing represent plasma treatment). A typical oxygen plasma treatment is to treat the surface of an oxide semiconductor with radicals generated by glow discharge plasma of oxygen gas. As a gas for generating plasma, not only oxygen but also oxygen gas and rare gas are used. The mixed gas may be used. For example, the temperature may be 250 ° C. or higher and 400 ° C. or lower, preferably 300 ° C. or higher and 400 ° C. or lower.

  By the oxygen plasma treatment, the insulator 280 and the oxide 230 are dehydrated or dehydrogenated, and an excess oxygen region can be formed by introducing excess oxygen into the insulator 280. In addition, oxygen vacancies are generated in the dehydrated or dehydrogenated oxide 230, and the resistance is reduced. On the other hand, oxygen deficiency in the oxide 230 is filled with excess oxygen in the insulator 280. Therefore, by the oxygen plasma treatment, the insulator 280 and the oxide 230 can remove hydrogen or water as impurities while filling oxygen vacancies. Accordingly, improvement in electrical characteristics of the transistor 200 and variation in electrical characteristics can be reduced.

  Subsequently, an insulator 282 is formed over the insulator 280. The insulator 282 is preferably formed with a sputtering apparatus. By using the sputtering method, an excess oxygen region can be easily formed in the insulator 280 which is the lower layer of the insulator 282.

  During film formation by sputtering, ions and sputtered particles exist between the target and the substrate. For example, the target is connected to a power source and is supplied with the potential E0. The substrate is given a potential E1 such as a ground potential. However, the substrate may be electrically floating. In addition, there is a region having the potential E2 between the target and the substrate. The magnitude relationship between the potentials is E2> E1> E0.

  Ions in the plasma are accelerated by the potential difference E2-E0 and collide with the target, whereby particles sputtered from the target are ejected. The sputtered particles adhere to and deposit on the film formation surface to form a film. In addition, some ions recoil by the target and may be taken into the insulator 280 below the formed film through the film formed as recoil ions. Further, ions in the plasma are accelerated by the potential difference E2-E1, and impact the film formation surface. At this time, some of the ions reach the inside of the insulator 280. When the ions are taken into the insulator 280, a region into which the ions are taken is formed in the insulator 280. That is, when the ions are oxygen-containing ions, an excess oxygen region is formed in the insulator 280.

  By introducing excess oxygen into the insulator 280, an excess oxygen region can be formed. Excess oxygen in the insulator 280 is supplied to the oxide 230 by heat treatment or the like, so that oxygen vacancies in the oxide 230 can be filled. Further, for example, when the insulator 282 is formed by a sputtering method, oxygen can be supplied to the oxide 230 without performing overheating after the film formation by heating the substrate. There are cases where it is possible.

  At this time, in the oxide 230, excess oxygen (such as active oxygen or atomic oxygen) is bonded to the side surface of the crystal part having orientation. Further, a metal such as In, M, or Zn is bonded to the bonded active oxygen. In this way, it can be considered that the active oxygen and a metal such as In, M, or Zn are repeatedly bonded to each other so that solid phase growth occurs laterally from the side surface of the crystal part having orientation. In addition, by performing heat treatment on the oxide 230a and the oxide 230b in advance to perform dehydration and dehydrogenation, impurities such as water or hydrogen contained in the oxide 230 can be reduced. Accordingly, the diffusion of oxygen due to impurities such as water or hydrogen contained in the oxide 230 is reduced, so that oxygen can be supplied to the oxide 230 more efficiently.

  Here, in the case where a highly oxidation-resistant conductor is used for the conductor 260, the conductor 240a, and the conductor 240b that are in contact with the insulator 280, excessive oxygen in the insulator 280 is generated by the conductor 260, the conductor 240a, And it can supply to the oxide 230 efficiently, without being absorbed by the conductor 240b. Accordingly, improvement in electrical characteristics of the transistor 200 and variation in electrical characteristics can be reduced.

  Through the above steps, the transistor 200 of one embodiment of the present invention can be manufactured.

<Configuration example of semiconductor device>
One example of a semiconductor device (memory device) using a capacitor which is one embodiment of the present invention is illustrated in FIGS. FIG. 55A is a circuit diagram of FIGS. 56 to 59 and FIGS. 61 to 62. 60 and 61 show end portions of regions where the semiconductor devices shown in FIGS. 56 to 59 and FIGS. 61 to 62 are formed.

<Circuit Configuration 1 of Semiconductor Device>
The semiconductor device illustrated in FIG. 55A and FIGS. 56 to 59 includes the transistor 300, the transistor 200, and the capacitor 100.

  The transistor 200 is a transistor in which a channel is formed in a semiconductor layer including an oxide semiconductor. Since the transistor 200 has a small off-state current, stored data can be held for a long time by using the transistor 200 for a semiconductor device (memory device). In other words, the semiconductor device (memory device) which does not require a refresh operation or has a very low frequency of the refresh operation can be used, so that power consumption can be sufficiently reduced.

  In FIG. 55A, the wiring 3001 is electrically connected to the source of the transistor 300, and the wiring 3002 is electrically connected to the drain of the transistor 300. The wiring 3003 is electrically connected to one of a source and a drain of the transistor 200, and the wiring 3004 is electrically connected to the gate of the transistor 200. The gate of the transistor 300 and the other of the source and the drain of the transistor 200 are electrically connected to one of the electrodes of the capacitor 100, and the wiring 3005 is electrically connected to the other of the electrodes of the capacitor 100. .

  The semiconductor device illustrated in FIG. 55A has the property that the potential of the gate of the transistor 300 can be held; thus, information can be written, held, and read as described below.

  Information writing and holding will be described. First, the potential of the fourth wiring 3004 is set to a potential at which the transistor 200 is turned on, so that the transistor 200 is turned on. Accordingly, the potential of the third wiring 3003 is supplied to the node FG that is electrically connected to one of the gate of the transistor 300 and the electrode of the capacitor 100. That is, predetermined charge is given to the gate of the transistor 300 (writing). Here, it is assumed that one of two charges that give two different potential levels (hereinafter referred to as a Low level charge and a High level charge) is given. After that, the potential of the fourth wiring 3004 is set to a potential at which the transistor 200 is turned off and the transistor 200 is turned off, so that charge is held at the node FG (holding).

  When the off-state current of the transistor 200 is small, the charge of the node FG is held for a long time.

Next, reading of information will be described. When an appropriate potential (reading potential) is applied to the fifth wiring 3005 in a state where a predetermined potential (constant potential) is applied to the first wiring 3001, the second wiring 3002 has a charge held in the node FG. Take a potential according to the amount. This is because, when the transistor 300 is an n-channel type, the apparent threshold voltage V _{th_H} when the gate of the transistor 300 is _supplied with a high level charge is the low level charge applied to the gate of the transistor 300. This is because it becomes lower than the apparent threshold voltage V _{th_L in the} case of being present. Here, the apparent threshold voltage refers to the potential of the fifth wiring 3005 necessary for bringing the transistor 300 into a “conductive state”. Therefore, by _setting the potential of the fifth wiring 3005 to a potential V ₀ between V _{th_H} and V _{th_L} , the charge given to the node FG can be determined. For example, in writing, when a high-level charge is applied to the node FG, the transistor 300 is turned “on” when the potential of the fifth wiring 3005 is V ₀ (> V _{th_H} ). On the other hand, when a low-level charge is _{supplied to} the node FG, the transistor 300 remains in a “non-conduction state” even when the potential of the fifth wiring 3005 becomes V ₀ (<V _{th_L} ). Therefore, by determining the potential of the second wiring 3002, information held in the node FG can be read.

  A memory device (memory cell array) can be formed by arranging the semiconductor devices illustrated in FIG. 55A in a matrix.

Note that when memory cells are arranged in an array, information of a desired memory cell must be read at the time of reading. In a memory cell from which information is not read, a potential that _{causes the} transistor 300 to be “non-conductive” regardless of the charge applied to the node FG, that is, a potential lower than V _{th_H} is _supplied to the fifth wiring 3005. A configuration in which only information of a desired memory cell can be read out is sufficient. _{Alternatively} , in a memory cell from which information is not read, the fifth wiring 3005 is _{supplied with} a potential at which the transistor 300 becomes “conductive” regardless of the charge applied to the node FG, that is, a potential higher than V _{th_L.} Thus, only the desired memory cell information may be read.

<Circuit Configuration 2 of Semiconductor Device>
The semiconductor device illustrated in FIG. 55B is different from the semiconductor device illustrated in FIG. 55A in that the transistor 300 is not provided. In this case as well, data can be written and held by operations similar to those of the semiconductor device shown in FIG.

  Information reading in the semiconductor device illustrated in FIG. 55B is described. When the transistor 200 is turned on, the third wiring 3003 in a floating state and the capacitor 100 are brought into conduction, and charge is redistributed between the third wiring 3003 and the capacitor 100. As a result, the potential of the third wiring 3003 changes. The amount of change in potential of the third wiring 3003 varies depending on one potential of the electrode of the capacitor 100 (or charge accumulated in the capacitor 100).

  For example, the potential of one electrode of the capacitor 100 is V, the capacitance of the capacitor 100 is C, the capacitance component of the third wiring 3003 is CB, and the potential of the third wiring 3003 before charge is redistributed. Assuming VB0, the potential of the third wiring 3003 after the charge is redistributed is (CB × VB0 + CV) / (CB + C). Therefore, when the potential of one of the electrodes of the capacitor 100 assumes two states of V1 and V0 (V1> V0) as the state of the memory cell, the third wiring 3003 in the case where the potential V1 is held. It can be seen that the potential (= (CB × VB0 + CV1) / (CB + C)) is higher than the potential of the third wiring 3003 when the potential V0 is held (= (CB × VB0 + CV0) / (CB + C)). .

  Then, information can be read by comparing the potential of the third wiring 3003 with a predetermined potential.

  In this case, a transistor to which the first semiconductor is applied is used as a driver circuit for driving a memory cell, and a transistor to which the second semiconductor is applied is stacked on the driver circuit as the transistor 200. do it.

  The semiconductor device described above can hold stored data for a long time by using a transistor with an off-state current that includes an oxide semiconductor. That is, a refresh operation is unnecessary or the frequency of the refresh operation can be extremely low, so that a semiconductor device with low power consumption can be realized. In addition, stored data can be held for a long time even when power is not supplied (note that a potential is preferably fixed).

  In addition, since the semiconductor device does not require a high voltage for writing information, the element hardly deteriorates. For example, unlike the conventional nonvolatile memory, since electrons are not injected into the floating gate and electrons are not extracted from the floating gate, there is no problem of deterioration of the insulator. In other words, unlike a conventional nonvolatile memory, the semiconductor device according to one embodiment of the present invention has no limitation on the number of rewritable times, and is a semiconductor device in which reliability is dramatically improved. Further, since data is written depending on the conductive state and non-conductive state of the transistor, high-speed operation is possible.

<Structure of semiconductor device>
The semiconductor device of one embodiment of the present invention includes a transistor 300, a transistor 200, and a capacitor 100 as illustrated in FIG. The transistor 200 is provided above the transistor 300, and the capacitor 100 is provided above the transistor 300 and the transistor 200.

  The transistor 300 includes a conductor 316, an insulator 314, a semiconductor region 312 formed of part of the substrate 311, a low resistance region 318a functioning as a source region or a drain region, and a low resistance region 318b. Have.

  The transistor 300 may be either a p-channel type or an n-channel type.

  The region in which the channel of the semiconductor region 312 is formed, the region in the vicinity thereof, the low resistance region 318a serving as the source region or the drain region, the low resistance region 318b, and the like preferably include a semiconductor such as a silicon-based semiconductor. It preferably contains crystalline silicon. Alternatively, a material containing Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), or the like may be used. A structure using silicon in which effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing may be employed. Alternatively, the transistor 300 may be a HEMT (High Electron Mobility Transistor) by using GaAs, GaAlAs, or the like.

  The low-resistance region 318 a and the low-resistance region 318 b provide an n-type conductivity element such as arsenic or phosphorus, or a p-type conductivity property such as boron, in addition to the semiconductor material applied to the semiconductor region 312. Containing elements.

  The conductor 316 functioning as a gate electrode includes a semiconductor material such as silicon, a metal material, an alloy containing an element imparting n-type conductivity such as arsenic or phosphorus, or an element imparting p-type conductivity such as boron. A conductive material such as a material or a metal oxide material can be used.

  Note that the threshold voltage can be adjusted by determining the work function depending on the material of the conductor. Specifically, it is preferable to use a material such as titanium nitride or tantalum nitride for the conductor. Further, in order to achieve both conductivity and embeddability, it is preferable to use a metal material such as tungsten or aluminum as a laminate for the conductor, and tungsten is particularly preferable from the viewpoint of heat resistance.

  In the transistor 300 illustrated in FIGS. 56A and 56B, a semiconductor region 312 (a part of the substrate 311) where a channel is formed has a convex shape. In addition, the conductor 316 is provided so as to cover a side surface and an upper surface of the semiconductor region 312 with an insulator 314 interposed therebetween. Note that the conductor 316 may be formed using a material that adjusts a work function. Such a transistor 300 is also called a FIN-type transistor because it uses a convex portion of a semiconductor substrate. Note that an insulator functioning as a mask for forming the convex portion may be provided in contact with the upper portion of the convex portion. Although the case where a part of the semiconductor substrate is processed to form the convex portion is described here, the SOI substrate may be processed to form a semiconductor film having a convex shape.

  Note that the transistor 300 illustrated in FIGS. 56A and 56B is an example, and is not limited to the structure, and an appropriate transistor may be used depending on a circuit configuration or a driving method. For example, as illustrated in FIG. 46, the structure of the transistor 300 may be provided as a planar type. In the case of the circuit configuration illustrated in FIG. 55B, the transistor 300 is not necessarily provided.

  An insulator 320, an insulator 322, an insulator 324, and an insulator 326 are sequentially stacked so as to cover the transistor 300.

  As the insulator 320, the insulator 322, the insulator 324, and the insulator 326, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like is used. That's fine.

  The insulator 322 functions as a planarization film that planarizes a step generated by the transistor 300 or the like provided below the insulator 322. The top surface of the insulator 322 may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like in order to improve planarity.

  For the insulator 324, for example, a film having a barrier property so that hydrogen and impurities do not diffuse from the substrate 311, the transistor 300, or the like into a region where the transistor 200 is provided is preferably used.

  For example, as an example of a film having a barrier property against hydrogen, silicon nitride formed by a CVD method can be used. Here, when hydrogen diffuses into a semiconductor element including an oxide semiconductor such as the transistor 200, characteristics of the semiconductor element may be reduced. Therefore, a film for suppressing hydrogen diffusion is preferably used between the transistor 200 and the transistor 300. Specifically, the film that suppresses the diffusion of hydrogen is a film with a small amount of hydrogen desorption.

The amount of desorption of hydrogen can be analyzed using, for example, a temperature desorption gas analysis method (TDS (Thermal Desorption Spectroscopy)). For example, the amount of hydrogen desorbed from the insulator 324 is 10 × 10 5 in terms of the amount of desorbed hydrogen atoms converted to hydrogen atoms per area of the insulator 324 in the range of 50 ° C. to 500 ° C. in TDS analysis. It may be ¹⁵ atoms / cm ² or less, preferably 5 × 10 ¹⁵ atoms / cm ² or less.

  Note that the insulator 326 preferably has a lower dielectric constant than the insulator 324. For example, the dielectric constant of the insulator 326 is preferably less than 4, and more preferably less than 3. For example, the relative dielectric constant of the insulator 324 is preferably equal to or less than 0.7 times that of the insulator 326, and more preferably equal to or less than 0.6 times. By using a material having a low dielectric constant as the interlayer film, parasitic capacitance generated between the wirings can be reduced.

  The insulator 320, the insulator 322, the insulator 324, and the insulator 326 are embedded with a conductor 328, a conductor 330, and the like that are electrically connected to the capacitor 100 or the transistor 200. Note that the conductor 328 and the conductor 330 function as plugs or wirings. Note that, as will be described later, a conductor having a function as a plug or a wiring may be given the same reference numeral by collecting a plurality of structures. In this specification and the like, the wiring and the plug electrically connected to the wiring may be integrated. That is, a part of the conductor may function as a wiring, and a part of the conductor may function as a plug.

  As a material of each plug and wiring (conductor 328, conductor 330, etc.), a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material is used as a single layer or a stacked layer. Can be used. It is preferable to use a high melting point material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is preferable to use tungsten. Alternatively, it is preferably formed using a low-resistance conductive material such as aluminum or copper. Wiring resistance can be lowered by using a low-resistance conductive material.

  A wiring layer may be provided over the insulator 326 and the conductor 330. For example, in FIG. 56, an insulator 350, an insulator 352, and an insulator 354 are sequentially stacked. A conductor 356 is formed in the insulator 350, the insulator 352, and the insulator 354. The conductor 356 functions as a plug or a wiring. Note that the conductor 356 can be provided using a material similar to that of the conductor 328 and the conductor 330.

  For example, as the insulator 350, an insulator having a barrier property against hydrogen is preferably used as in the case of the insulator 324. The conductor 356 preferably includes a conductor having a barrier property against hydrogen. In particular, a conductor having a barrier property against hydrogen is formed in an opening portion of the insulator 350 having a barrier property against hydrogen. With this structure, the transistor 300 and the transistor 200 can be separated by a barrier layer, and hydrogen diffusion from the transistor 300 to the transistor 200 can be suppressed.

  For example, tantalum nitride may be used as the conductor having a barrier property against hydrogen. Further, by stacking tantalum nitride and tungsten having high conductivity, diffusion of hydrogen from the transistor 300 can be suppressed while maintaining conductivity as a wiring. In this case, it is preferable that the tantalum nitride layer having a barrier property against hydrogen be in contact with the insulator 350 having a barrier property against hydrogen.

  Over the insulator 354, the insulator 358, the insulator 210, the insulator 212, the insulator 213, the insulator 214, and the insulator 216 are sequentially stacked. A substance having a barrier property against oxygen or hydrogen is preferably used for any or all of the insulator 358, the insulator 210, the insulator 212, the insulator 213, the insulator 214, and the insulator 216.

  For example, as the insulator 358 and the insulator 212, a film having a barrier property so that hydrogen and impurities do not diffuse from a region where the substrate 311 or the transistor 300 is provided to a region where the transistor 200 is provided, for example. Is preferred. Therefore, a material similar to that of the insulator 324 can be used.

  As an example of a film having a barrier property against hydrogen, silicon nitride formed by a CVD method can be used. Here, when hydrogen diffuses into a semiconductor element including an oxide semiconductor such as the transistor 200, characteristics of the semiconductor element may be reduced. Therefore, a film for suppressing hydrogen diffusion is preferably used between the transistor 200 and the transistor 300. Specifically, the film that suppresses the diffusion of hydrogen is a film with a small amount of hydrogen desorption.

  For example, the insulator 213 and the insulator 214 are preferably formed using a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide.

  In particular, aluminum oxide has a high blocking effect that prevents the film from permeating both oxygen and impurities such as hydrogen and moisture, which cause variation in electrical characteristics of the transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and moisture from entering the transistor 200 during and after the manufacturing process of the transistor. In addition, release of oxygen from the oxide included in the transistor 200 can be suppressed. Therefore, it is suitable for use as a protective film for the transistor 200.

  For example, the insulator 210 and the insulator 216 can be formed using a material similar to that of the insulator 320. For example, as the insulator 216, a silicon oxide film, a silicon oxynitride film, or the like can be used.

  The insulator 358, the insulator 210, the insulator 212, the insulator 213, the insulator 214, and the insulator 216 are embedded with a conductor 218, a conductor (the conductor 205) included in the transistor 200, and the like. ing. Note that the conductor 218 functions as a plug or a wiring electrically connected to the capacitor 100 or the transistor 300. The conductor 218 can be provided using a material similar to that of the conductor 328 and the conductor 330.

  In particular, the insulator 358, the insulator 212, the insulator 213, and the conductor 218 in a region in contact with the insulator 214 are preferably conductors having a barrier property against oxygen, hydrogen, and water. With this structure, the transistor 300 and the transistor 200 are layers having a barrier property against oxygen, hydrogen, and water and can be completely separated from each other, so that diffusion of hydrogen from the transistor 300 to the transistor 200 can be suppressed. .

  A transistor 200 is provided above the insulator 216. Note that the transistor described above may be used as the structure of the transistor 200. The transistor 200 illustrated in FIGS. 56A and 56B is an example and is not limited to the structure, and an appropriate transistor may be used depending on a circuit configuration or a driving method.

  An insulator 280 is provided above the transistor 200. For the insulator 280, an oxide containing more oxygen than that in the stoichiometric composition is preferably used. That is, the insulator 280 is preferably formed with a region where oxygen is present in excess of the stoichiometric composition (hereinafter also referred to as an excess oxygen region). In particular, in the case where an oxide semiconductor is used for the transistor 200, reliability is improved by providing an insulator having an excess oxygen region in an interlayer film or the like in the vicinity of the transistor 200 to reduce oxygen vacancies in the transistor 200. Can do.

Specifically, an oxide material from which part of oxygen is released by heating is preferably used as the insulator having an excess oxygen region. The oxide which desorbs oxygen by heating means that the amount of desorbed oxygen converted to oxygen atoms is 1.0 × 10 ¹⁸ atoms / cm ³ or more, preferably 3.0 × 10 ²⁰ in TDS analysis. An oxide film having atoms / cm ³ or more. The surface temperature of the film at the time of TDS analysis is preferably in the range of 100 ° C. to 700 ° C., or 100 ° C. to 500 ° C.

  For example, as such a material, a material containing silicon oxide or silicon oxynitride is preferably used. Alternatively, a metal oxide can be used. Note that in this specification, silicon oxynitride refers to a material having a higher oxygen content than nitrogen as its composition, and silicon nitride oxide refers to a material having a higher nitrogen content than oxygen as its composition. Indicates.

  Further, the insulator 280 that covers the transistor 200 may function as a planarization film that covers the uneven shape below the transistor 200. Further, a conductor 244 and the like are embedded in the insulator 280.

  The conductor 244 functions as a plug or a wiring electrically connected to the capacitor 100, the transistor 200, or the transistor 300. The conductor 244 can be provided using a material similar to that of the conductor 328 and the conductor 330.

  For example, in the case where the conductor 244 is provided as a stacked structure, a conductor having high oxidation resistance is preferably included. In particular, a conductor having high oxidation resistance is preferably provided in a region in contact with the insulator 280 having an excess oxygen region. With this structure, the conductor 244 can suppress excessive oxygen from the insulator 280. The conductor 244 preferably includes a conductor having a barrier property against hydrogen. In particular, by providing a conductor having a barrier property against impurities such as hydrogen in a region in contact with the insulator 280 having an excess oxygen region, diffusion of impurities in the conductor 244 and part of the conductor 244, It can be suppressed that it becomes a diffusion path of impurities from.

  Further, a barrier layer 245 may be provided over the conductor 244. By including the barrier layer 245, impurities contained in the conductor 244 and diffusion of part of the conductor 244 can be suppressed.

  For the barrier layer 245, for example, a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide, or a metal nitride such as tantalum nitride is preferably used. In particular, aluminum oxide has a high blocking effect that prevents the film from permeating both oxygen and impurities such as hydrogen and moisture, which cause variation in electrical characteristics of the transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and moisture from entering the transistor 200 during and after the manufacturing process of the transistor.

  Over the barrier layer 245 and the insulator 280, the insulator 282, the insulator 283, the insulator 284, and the insulator 110 are sequentially stacked. A conductor 124 and the like are embedded in the insulator 282, the insulator 283, the insulator 284, and the insulator 110. Note that the conductor 124 functions as a plug or a wiring electrically connected to the capacitor 100, the transistor 200, or the transistor 300. The conductor 124 can be provided using a material similar to that of the conductor 356.

  A substance having a barrier property against oxygen or hydrogen is preferably used for any or all of the insulator 282, the insulator 283, the insulator 284, and the insulator 110. Therefore, the insulator 282 can be formed using a material similar to that of the insulator 214. The insulator 283 can be formed using a material similar to that of the insulator 213. For the insulator 284, an insulator similar to the insulator 212 can be used. The insulator 110 can be formed using a material similar to that of the insulator 216.

  For example, the insulator 282 and the insulator 283 are preferably formed using a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide.

  In particular, aluminum oxide has a high blocking effect that prevents the film from permeating both oxygen and impurities such as hydrogen and moisture, which cause variation in electrical characteristics of the transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and moisture from entering the transistor 200 during and after the manufacturing process of the transistor. In addition, release of oxygen from the oxide included in the transistor 200 can be suppressed. Therefore, it is suitable for use as a protective film for the transistor 200.

  The insulator 284 is preferably formed using a film having a barrier property so that hydrogen and impurities do not diffuse from a region where the capacitor 100 is provided to a region where the transistor 200 is provided. Therefore, a material similar to that of the insulator 324 can be used.

  For example, as an example of a film having a barrier property against hydrogen, silicon nitride formed by a CVD method can be used. Here, when hydrogen diffuses into a semiconductor element including an oxide semiconductor such as the transistor 200, characteristics of the semiconductor element may be reduced. Therefore, a film for suppressing hydrogen diffusion is preferably used between the transistor 200 and the transistor 300. Specifically, the film that suppresses the diffusion of hydrogen is a film with a small amount of hydrogen desorption.

  Therefore, the transistor 200 and the insulator 280 including an excess oxygen region are sandwiched between the stacked structure of the insulator 212, the insulator 213, and the insulator 214 and the stacked structure of the insulator 282, the insulator 283, and the insulator 284. It can be configured. The insulator 212, the insulator 213, the insulator 214, the insulator 282, the insulator 283, and the insulator 284 have barrier properties that suppress diffusion of impurities such as oxygen, hydrogen, and water.

  The oxygen released from the insulator 280 and the transistor 200 can be prevented from diffusing into the layer in which the capacitor 100 or the transistor 300 is formed. Alternatively, diffusion of impurities such as hydrogen and water from the layer above the insulator 282 and the layer below the insulator 214 into the transistor 200 can be suppressed.

  That is, oxygen can be efficiently supplied from the excess oxygen region of the insulator 280 to the oxide in which a channel in the transistor 200 is formed, so that oxygen vacancies can be reduced. Further, oxygen vacancies can be prevented from being formed due to impurities in the oxide in which the channel in the transistor 200 is formed. Thus, an oxide in which a channel in the transistor 200 is formed can be an oxide semiconductor with low defect state density and stable characteristics. That is, variation in electrical characteristics of the transistor 200 can be suppressed and reliability can be improved.

  Here, FIG. 60 shows a cross-sectional view in the vicinity of the scribe line.

  For example, as illustrated in FIG. 60A, an insulator 212, an insulator 213, and an insulator are formed in the vicinity of a region overlapping with a scribe line (indicated by a one-dot chain line in the drawing) provided at the outer edge of the memory cell including the transistor 200. 214, the insulator 216, the insulator 220, the insulator 222, the insulator 224, and the insulator 280 are provided with openings. The insulator 212, the insulator 213, the insulator 214, the insulator 216, the insulator 220, the insulator 222, the insulator 224, and the insulator 280 so as to cover the side surfaces thereof, the insulator 282, the insulator 283, and An insulator 284 is provided.

  Therefore, the insulator 212, the insulator 213, and the insulator 214 and the insulator 282 are in contact with each other in the opening. Further, the insulator 213 and the insulator 214 are stacked over the insulator 282. At this time, adhesion can be improved by forming at least one of the insulator 212, the insulator 213, and the insulator 214 and the insulator 282 using the same material and the same method.

  With this structure, the insulator 280 and the transistor 200 can be wrapped with the insulator 212, the insulator 213, the insulator 214, the insulator 282, the insulator 283, and the insulator 284. The insulator 212, the insulator 213, the insulator 214, the insulator 282, the insulator 283, and the insulator 284 have a function of suppressing diffusion of oxygen, hydrogen, and water; Even when the semiconductor device shown is scribed, hydrogen or water can be prevented from entering from the side surfaces of the insulator 220, the insulator 222, the insulator 224, and the insulator 280 and diffusing into the transistor 200.

  Further, with this structure, excess oxygen in the insulator 280 can be prevented from diffusing outside the insulator 282 and the insulator 214. Accordingly, excess oxygen in the insulator 280 is supplied to the oxide in which the channel in the transistor 200 is efficiently formed. With the oxygen, oxygen vacancies in the oxide in which a channel in the transistor 200 is formed can be reduced. Accordingly, an oxide in which a channel in the transistor 200 is formed can be an oxide semiconductor having a low defect level density and stable characteristics. That is, variation in electrical characteristics of the transistor 200 can be suppressed and reliability can be improved.

  In addition, for example, as illustrated in FIG. 60B, in the regions on both sides of the scribe line (indicated by a one-dot chain line in the drawing), the insulator 212, the insulator 213, the insulator 214, the insulator 216, and the insulator 220, the insulator 222, the insulator 224, and the insulator 280 may be provided with openings. In the figure, there are two openings, but a plurality of openings may be provided if necessary.

  Therefore, in the openings provided on both sides of the scribe line, the insulator 212, the insulator 213, and the insulator 214 and the insulator 282 are in contact with each other in at least two places, so that a structure with higher adhesion is obtained. Note that also in this case, the adhesiveness can be improved by forming the insulator 282 using the same material and the same method as at least one of the insulator 212, the insulator 213, and the insulator 214.

  Further, by providing a plurality of openings, the insulator 282, the insulator 212, the insulator 213, and the insulator 214 can be in contact with each other in a plurality of regions. Further, in the case where impurities entering from the scribe line diffuse to the region closest to the transistor 200 in the region where the insulator 214 and the insulator 282 are in contact, the impurity diffusion distance can be increased.

  With this structure, the transistor 200 and the insulator 280 can be tightly sealed. Therefore, an oxide in which a channel is formed in the transistor 200 can be an oxide semiconductor having a low defect level density and stable characteristics. That is, variation in electrical characteristics of the transistor 200 can be suppressed and reliability can be improved.

  Subsequently, the insulator 110, the capacitor 100, and the conductor 124 are provided above the insulator 284. The capacitor 100 is provided over the insulator 110 and includes the conductor 112 (the conductor 112a and the conductor 112b), the insulator 130, the insulator 132, the insulator 134, and the conductor 116. Note that the conductor 124 functions as a plug or a wiring electrically connected to the capacitor 100, the transistor 200, or the transistor 300.

  Note that the conductor 124 can be provided using a material similar to that of the conductor 356.

  The conductor 112 can be formed using a conductive material such as a metal material, an alloy material, or a metal oxide material. It is preferable to use a high-melting-point material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is particularly preferable to use tungsten. In the case of forming simultaneously with other structures such as a conductor, Cu (copper), Al (aluminum), or the like, which is a low resistance metal material, may be used.

  An insulator 130, an insulator 132, and an insulator 134 are provided over the conductor 112. Examples of the insulator 130, the insulator 132, and the insulator 134 include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, and oxynitride Hafnium, nitrided hafnium oxide, hafnium nitride, or the like may be used. In the figure, a three-layer structure is shown, but a single layer, two layers, or a stacked structure of four or more layers may be used.

  For example, the insulator 130 and the insulator 134 are preferably formed using a material having high dielectric strength such as silicon oxynitride, and the insulator 132 is preferably formed using a high dielectric constant (high-k) material such as aluminum oxide. . With this structure, the capacitor 100 has an insulator with a high dielectric constant (high-k), so that a sufficient capacitance can be secured, and the insulator having a high dielectric strength can improve the dielectric strength, The electrostatic breakdown of the element 100 can be suppressed.

  A conductor 116 is provided over the conductor 112 with an insulator 114 interposed therebetween. Note that the conductor 116 can be formed using a conductive material such as a metal material, an alloy material, or a metal oxide material. It is preferable to use a high-melting-point material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is particularly preferable to use tungsten. In the case of forming simultaneously with other structures such as a conductor, Cu (copper), Al (aluminum), or the like, which is a low resistance metal material, may be used.

  For example, as illustrated in FIG. 56, in the conductor 112 functioning as one of the electrodes, a structure having a convex shape like the conductor 112b can increase the capacitance per projected area of the capacitor. it can. Therefore, the semiconductor device can be reduced in area, highly integrated, and miniaturized.

  An insulator 150 is sequentially stacked over the conductor 116 and the insulator 134. The insulator 110 and the insulator 150 can be provided using a material similar to that of the insulator 320. Further, the insulator 110 serving as the lower portion of the capacitor element 100 and the insulator 150 covering the capacitor element 100 may function as a planarization film that covers the concave and convex shapes below the insulator 110.

  The above is the description of the configuration example. By using this structure, in a semiconductor device using a transistor including an oxide semiconductor, variation in electrical characteristics can be suppressed and reliability can be improved. Alternatively, a transistor including an oxide semiconductor with high on-state current can be provided. Alternatively, a transistor including an oxide semiconductor with low off-state current can be provided. Alternatively, a semiconductor device with reduced power consumption can be provided.

<Modification 1>
As a modification of this embodiment, a conductor 244 may be formed as shown in FIG. That is, a plug may be embedded in the insulator 282, and a conductor serving as a wiring and the barrier layer 245 may be provided over the plug in a stacked structure. In this case, in the conductor constituting the conductor 244, it is preferable to use a conductor having high oxidation resistance as the conductor functioning as a wiring.

<Modification 2>
As a modification of this embodiment, the capacitor 100 does not necessarily have the conductor 122.

  For example, in the structure illustrated in FIG. 58, the conductor 244 is formed after the insulator 280, the insulator 282, the insulator 284, and the insulator 110 are formed. Therefore, the conductor 124 and the conductor 112 serving as one electrode of the capacitor 100 can be formed at the same time. Therefore, since it can produce with few processes, production cost can be reduced and productivity can be improved.

  Further, the conductor 116 is provided over the conductor 112 with the insulator 130, the insulator 132, and the insulator 134 interposed therebetween. Note that the conductor 116 can be formed using a conductive material such as a metal material, an alloy material, or a metal oxide material. It is preferable to use a high-melting-point material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is particularly preferable to use tungsten. In the case of forming simultaneously with other structures such as a conductor, Cu (copper), Al (aluminum), or the like, which is a low resistance metal material, may be used.

  Note that as illustrated in FIG. 58, the conductor 116 is provided so as to cover the top surface and the side surface of the conductor 112 with the insulator 130, the insulator 132, and the insulator 134 interposed therebetween. That is, the side surface of the conductor 112 also functions as a capacitor, so that the capacitance per projected area of the capacitor can be increased. Therefore, the semiconductor device can be reduced in area, highly integrated, and miniaturized.

  Note that in this structure, when the conductor 112 is formed, the top surface of the insulator 110 is preferably removed larger than the total thickness of the insulator 130, the insulator 132, and the insulator 134. For example, part of the insulator 110 can be removed at the same time by performing the over-etching process. In addition, by forming the conductor 112 and the like by over-etching, etching can be performed without leaving an etching residue.

  In addition, part of the insulator 110 can be efficiently removed by switching the type of etching gas during the etching process.

  Further, for example, after the conductor 112 and the conductor 124 are formed, part of the insulator 110 may be removed using the conductor 112 as a hard mask.

  Further, after the conductor 112 is formed, the surface of the conductor 112 may be cleaned. Etching residues and the like can be removed by performing the cleaning process.

  As shown in FIG. 58, the insulator 213 and the insulator 283 are not necessarily provided. Also in this structure, the transistor 200 and the insulator 280 including the excess oxygen region are sandwiched between the stacked structure of the insulator 212 and the insulator 214 and the stacked structure of the insulator 282 and the insulator 284. it can. The insulator 212, the insulator 214, the insulator 282, and the insulator 284 have barrier properties that suppress diffusion of impurities such as oxygen, hydrogen, and water.

  Therefore, diffusion of oxygen released from the insulator 280 and the transistor 200 to the layer where the capacitor 100 or the transistor 300 is formed can be suppressed. Alternatively, diffusion of impurities such as hydrogen and water from the layer above the insulator 282 and the layer below the insulator 214 into the transistor 200 can be suppressed.

  That is, oxygen can be efficiently supplied from the excess oxygen region of the insulator 280 to the oxide in which a channel in the transistor 200 is formed, so that oxygen vacancies can be reduced. Further, oxygen vacancies can be prevented from being formed due to impurities in the oxide in which the channel in the transistor 200 is formed. Thus, an oxide in which a channel in the transistor 200 is formed can be an oxide semiconductor with low defect state density and stable characteristics. That is, variation in electrical characteristics of the transistor 200 can be suppressed and reliability can be improved.

  In addition, cross-sectional views in the vicinity of the scribe line in this modification are shown in FIGS. 61 (A) and 61 (B).

  For example, as illustrated in FIG. 61A, the insulator 214 and the insulator 282 are in contact with each other in the vicinity of a region overlapping with a scribe line (indicated by a one-dot chain line in the drawing), and the insulator 212, the insulator 214, and the insulator 282 and an insulator 284 are stacked. At this time, the insulator 214 and the insulator 282 are formed using the same material and the same method, whereby a stacked structure with high adhesion is obtained.

  With this structure, the insulator 212, the insulator 214, the insulator 282, and the insulator 284 can enclose the insulator 216, the insulator 220, the insulator 222, the insulator 224, and the insulator 280. The insulator 212, the insulator 214, the insulator 282, and the insulator 284 have a function of suppressing diffusion of oxygen, hydrogen, and water; therefore, even if the semiconductor device described in this embodiment is scribed, In addition, hydrogen or water can be prevented from entering from the side surfaces of the insulator 216, the insulator 220, the insulator 222, the insulator 224, and the insulator 280 and diffusing into the transistor 200.

  Further, with this structure, excess oxygen in the insulator 280 can be prevented from diffusing outside the insulator 282 and the insulator 214. Accordingly, excess oxygen in the insulator 280 is supplied to the oxide in which the channel in the transistor 200 is efficiently formed. With the oxygen, oxygen vacancies in the oxide in which a channel in the transistor 200 is formed can be reduced. Accordingly, an oxide in which a channel in the transistor 200 is formed can be an oxide semiconductor having a low defect level density and stable characteristics. That is, variation in electrical characteristics of the transistor 200 can be suppressed and reliability can be improved.

  For example, as illustrated in FIG. 61B, in the vicinity of a region overlapping with a scribe line (indicated by a one-dot chain line in the drawing), the insulator 214, the insulator 216, the insulator 220, the insulator 222, and the insulator 224 And an opening in the insulator 280. Further, the insulator 282 is provided so as to cover side surfaces of the insulator 214, the insulator 216, the insulator 220, the insulator 222, the insulator 224, and the insulator 280. Furthermore, openings are provided in the insulator 212 and the insulator 282, and the insulator 284 is provided so as to cover the side surfaces of the insulator 212 and the insulator 282 and the exposed upper surface of the insulator 210.

  That is, the insulator 214 and the insulator 282 are in contact with each other in the opening. Furthermore, the insulator 212 and the insulator 282 are in contact with each other outside. At this time, the insulator 214 and the insulator 282 are formed using the same material and the same method, whereby a stacked structure with high adhesion is obtained. Further, when the insulator 212 and the insulator 284 are formed using the same material and the same method, a stacked structure with high adhesion can be obtained.

  With this structure, the transistor 200 and the insulator 280 can be tightly sealed. Therefore, an oxide in which a channel is formed in the transistor 200 can be an oxide semiconductor having a low defect level density and stable characteristics. That is, variation in electrical characteristics of the transistor 200 can be suppressed and reliability can be improved.

<Modification 3>
An example of a modification of the present embodiment is shown in FIG. FIG. 59 differs from FIG. 58 in the configuration of the transistor 300 and the transistor 200.

  In the transistor 300 illustrated in FIG. 59, a semiconductor region 312 (a part of the substrate 311) where a channel is formed has a convex shape. In addition, the conductor 316 is provided so as to cover a side surface and an upper surface of the semiconductor region 312 with an insulator 314 interposed therebetween. Note that the conductor 316 may be formed using a material that adjusts a work function. Such a transistor 300 is also called a FIN-type transistor because it uses a convex portion of a semiconductor substrate. Note that an insulator functioning as a mask for forming the convex portion may be provided in contact with the upper portion of the convex portion. Although the case where a part of the semiconductor substrate is processed to form the convex portion is described here, the SOI substrate may be processed to form a semiconductor film having a convex shape.

  The structure of the transistor 200 illustrated in FIG. 59 is the structure described with reference to FIGS. In the opening formed in the insulator 280, the oxide 230c, the insulator 250, and the conductor 260 are formed. In addition, one end of each of the conductors 240a and 240b and the end of the opening formed in the insulator 280 coincide with each other. Further, the three ends of the conductor 240 a and the conductor 240 b coincide with part of the end of the oxide 230. Therefore, the conductor 240a and the conductor 240b can be shaped simultaneously with the opening of the oxide 230 or the insulator 280. Therefore, masks and processes can be reduced. In addition, yield and productivity can be improved.

  Further, the transistor 200 illustrated in FIG. 59 has a structure in which the conductors 240a and 240b and the conductor 260 do not overlap with each other, so that the parasitic capacitance applied to the conductor 260 can be reduced. That is, the transistor 200 having a high operating frequency can be provided.

<Modification 4>
An example of a modification of the present embodiment is shown in FIG. 62A and 62B each illustrate a channel length and a channel width direction cross section of the transistor 200 using the dashed-dotted line A1-A2 as an axis.

  As shown in FIG. 62, the transistor 200 and the insulator 280 including an excess oxygen region may be wrapped with a stacked structure of the insulator 212 and the insulator 214 and a stacked structure of the insulator 282 and the insulator 284. Good. At that time, the insulator 212, the insulator 214, the insulator 282, and the insulator 284 may have a stacked structure between the transistor 200 and the through electrode that connects the transistor 300 and the capacitor 100. preferable.

  Therefore, diffusion of oxygen released from the insulator 280 and the transistor 200 to the layer where the capacitor 100 or the transistor 300 is formed can be suppressed. Alternatively, diffusion of impurities such as hydrogen and water into the transistor 200 from a layer above the insulator 282 and a layer below the insulator 214 can be suppressed.

  That is, oxygen can be efficiently supplied from the excess oxygen region of the insulator 280 to the oxide in which a channel in the transistor 200 is formed, so that oxygen vacancies can be reduced. Further, oxygen vacancies can be prevented from being formed due to impurities in the oxide in which the channel in the transistor 200 is formed. Thus, an oxide in which a channel in the transistor 200 is formed can be an oxide semiconductor with low defect state density and stable characteristics. That is, variation in electrical characteristics of the transistor 200 can be suppressed and reliability can be improved.

<Modification 5>
An example of a modification of the present embodiment is shown in FIG. 63 differs from FIG. 59 in the structure of the capacitor.

  As shown in FIG. 63, the capacitor 105 may be formed. In the capacitor 105, part of the wiring to the transistor 300 also functions as a capacitor. Accordingly, the capacitance per projected area of the capacitive element can be increased. Therefore, the semiconductor device can be reduced in area, highly integrated, and miniaturized. In addition, the insulator 212, the insulator 214, the insulator 282, and the insulator 284 preferably have a stacked structure between the capacitor 105 and the transistor 200.

  Therefore, oxygen can be efficiently supplied from the excess oxygen region of the insulator 280 to the oxide in which the channel in the transistor 200 is formed, so that oxygen vacancies can be reduced. Further, oxygen vacancies can be prevented from being formed due to impurities in the oxide in which the channel in the transistor 200 is formed. Thus, an oxide in which a channel in the transistor 200 is formed can be an oxide semiconductor with low defect state density and stable characteristics. That is, variation in electrical characteristics of the transistor 200 can be suppressed and reliability can be improved.

<Modification 6>
An example of a modification of the present embodiment is shown in FIG. FIG. 64A is a circuit diagram in which part of a row is extracted in the case where the semiconductor device illustrated in FIG. 55A is arranged in a matrix. FIG. 64B is a cross-sectional view of the semiconductor device corresponding to the circuit diagram of FIG.

  FIG. 64 illustrates a semiconductor device including the transistor 300, the transistor 200, and the capacitor 100, a semiconductor device including the transistor 301, the transistor 201, and the capacitor 101, and a semiconductor including the transistor 301, the transistor 201, and the capacitor 101. The devices are arranged on the same line.

  As shown in FIG. 64B, a plurality of transistors (the transistor 200 and the transistor 201 in the figure) and the insulator 280 including an excess oxygen region are insulated from the stacked structure of the insulator 212 and the insulator 214. A structure in which the structure is wrapped by a stacked structure of the body 282 and the insulator 284 may be employed. At that time, insulation is performed between the through electrode that connects the transistor 300, the transistor 301, or the transistor 302 and the capacitor 100, the capacitor 101, or the capacitor 102 and the transistor 200, the transistor 201, or the transistor 202. It is preferable that the body 212, the insulator 214, the insulator 282, and the insulator 284 have a stacked structure.

  Therefore, diffusion of oxygen released from the insulator 280 and the transistor 200 to the layer where the capacitor 100 or the transistor 300 is formed can be suppressed. Alternatively, diffusion of impurities such as hydrogen and water from the layer above the insulator 282 and the layer below the insulator 214 into the transistor 200 can be suppressed.

  That is, oxygen can be efficiently supplied from the excess oxygen region of the insulator 280 to the oxide in which a channel in the transistor 200 is formed, so that oxygen vacancies can be reduced. Further, oxygen vacancies can be prevented from being formed due to impurities in the oxide in which the channel in the transistor 200 is formed. Thus, an oxide in which a channel in the transistor 200 is formed can be an oxide semiconductor with low defect state density and stable characteristics. That is, variation in electrical characteristics of the transistor 200 can be suppressed and reliability can be improved.

<Modification 7>
An example of a modification of the present embodiment is shown in FIG. FIG. 65 is a cross-sectional view of the semiconductor device in which the transistor 201 and the transistor 202 are integrated in the semiconductor device illustrated in FIG. 64.

  As shown in FIG. 65, the function of the conductor 112 serving as one of the electrodes of the capacitor 101 may also serve as the conductor 240a serving as the source electrode or the drain electrode of the transistor 201. In that case, the region extending over the oxide 230a of the transistor 201 and the conductor 240a of the insulator 250 functioning as a gate insulator of the transistor 201 functions as an insulator of the capacitor 101. Therefore, the conductor 116 serving as the other electrode of the capacitor 101 may be stacked over the conductor 240a with the insulator 250 and the oxide 230a interposed therebetween. With this configuration, the semiconductor device can be reduced in area, highly integrated, and miniaturized.

  Alternatively, the transistor 201 and the transistor 202 may be provided to overlap each other. With this configuration, the semiconductor device can be reduced in area, highly integrated, and miniaturized.

  In addition, a plurality of transistors (the transistor 201 and the transistor 202 in the drawing), and an insulator 280 including an excess oxygen region, a stacked structure of the insulator 212 and the insulator 214, the insulator 282, and the insulator 284 It is good also as a structure wrapped up with a laminated structure. At that time, insulation is performed between the through electrode that connects the transistor 300, the transistor 301, or the transistor 302 and the capacitor 100, the capacitor 101, or the capacitor 102 and the transistor 200, the transistor 201, or the transistor 202. It is preferable that the body 212, the insulator 214, the insulator 282, and the insulator 284 have a stacked structure.

  Therefore, diffusion of oxygen released from the insulator 280 and the transistor 200 to the layer where the capacitor 100 or the transistor 300 is formed can be suppressed. Alternatively, diffusion of impurities such as hydrogen and water into the transistor 200 from a layer above the insulator 282 and a layer below the insulator 214 can be suppressed.

  That is, oxygen can be efficiently supplied from the excess oxygen region of the insulator 280 to the oxide in which a channel in the transistor 200 is formed, so that oxygen vacancies can be reduced. Further, oxygen vacancies can be prevented from being formed due to impurities in the oxide in which the channel in the transistor 200 is formed. Thus, an oxide in which a channel in the transistor 200 is formed can be an oxide semiconductor with low defect state density and stable characteristics. That is, variation in electrical characteristics of the transistor 200 can be suppressed and reliability can be improved.

  A transistor including the above oxide semiconductor has low off-state current. Circuit elements such as a CMOS inverter, a CMOS analog switch, and a memory element can be formed using such a transistor. In addition to a transistor including an oxide semiconductor, a transistor including a semiconductor other than an oxide semiconductor such as silicon may be combined. A semiconductor device such as a display device, a light-emitting device, a lighting device, a power storage device, a memory device, an imaging device, a processor, or an electronic device can be manufactured using such a transistor, a circuit element, or the like.

  This embodiment can be implemented in appropriate combination with at least part of the other embodiments described in this specification.

(Embodiment 3)
In this embodiment, an example of a circuit of a semiconductor device using a transistor or the like according to one embodiment of the present invention will be described.

<Circuit>
Hereinafter, an example of a circuit of a semiconductor device using a transistor or the like according to one embodiment of the present invention will be described with reference to FIGS.

<Storage device 1>
The semiconductor device illustrated in FIG. 66 is different from the semiconductor device described in the above embodiment in that the transistor 3500 and the sixth wiring 3006 are provided. Also in this case, information writing and holding operations can be performed by the same operation as the semiconductor device described in the above embodiment. The transistor 3500 may be a transistor similar to the transistor 3200 described above.

  The sixth wiring 3006 is electrically connected to the gate of the transistor 3500, one of the source and the drain of the transistor 3500 is electrically connected to the drain of the transistor 3200, and the other of the source and the drain of the transistor 3500 is the third It is electrically connected to the wiring 3003.

<Storage device 2>
A modification of the semiconductor device (memory device) is described with reference to a circuit diagram shown in FIG.

  A semiconductor device illustrated in FIG. 67 includes transistors 4100 to 4400, a capacitor 4500, and a capacitor 4600. Here, the transistor 4100 can be a transistor similar to the transistor 300 described above, and the transistors 4200 to 4400 can be transistors similar to the transistor 200 described above. Here, as the capacitor 4500 and the capacitor 4600, the same transistor as the capacitor 100 described above can be used. 67, although not shown in FIG. 67, a plurality of semiconductor devices are provided in a matrix. The semiconductor device illustrated in FIG. 67 can control writing and reading of a data voltage in accordance with a signal or a potential supplied to the wiring 4001, the wiring 4003, and the wirings 4005 to 4009.

  One of a source and a drain of the transistor 4100 is connected to the wiring 4003. The other of the source and the drain of the transistor 4100 is connected to the wiring 4001. Note that although the conductivity type of the transistor 4100 is shown as a p-channel type in FIG. 67, it may be an n-channel type.

  The semiconductor device illustrated in FIG. 67 includes two data holding units. For example, the first data holding portion holds electric charge between one of a source and a drain of the transistor 4400 connected to the node FG1, one electrode of the capacitor 4600, and one of the source and the drain of the transistor 4200. The second data holding portion is between the gate of the transistor 4100 connected to the node FG2, the other of the source and the drain of the transistor 4200, one of the source and the drain of the transistor 4300, and one electrode of the capacitor 4500. Holds charge.

  The other of the source and the drain of the transistor 4300 is connected to the wiring 4003. The other of the source and the drain of the transistor 4400 is connected to the wiring 4001. A gate of the transistor 4400 is connected to the wiring 4005. A gate of the transistor 4200 is connected to the wiring 4006. A gate of the transistor 4300 is connected to the wiring 4007. The other electrode of the capacitor 4600 is connected to the wiring 4008. The other electrode of the capacitor 4500 is connected to the wiring 4009.

  The transistors 4200 to 4400 function as switches for controlling writing of data voltages and holding of electric charges. Note that as the transistors 4200 to 4400, transistors with low current (off-state current) flowing between the source and the drain in a non-conduction state are preferably used. The transistor with low off-state current is preferably a transistor having an oxide semiconductor in a channel formation region (OS transistor). An OS transistor has advantages such as low off-state current and that it can be formed over a transistor including silicon. In FIG. 67, the conductivity types of the transistors 4200 to 4400 are shown as n-channel types, but may be p-channel types.

  The transistor 4200, the transistor 4300, and the transistor 4400 are preferably provided in different layers even when a transistor including an oxide semiconductor is used. That is, the semiconductor device illustrated in FIG. 67 is preferably provided by stacking the transistor 4100, the transistor 4200, the transistor 4300, and the transistor 4400. A layer including a transistor may be provided by stacking. That is, by integrating transistors, the circuit area can be reduced and the semiconductor device can be downsized.

  Next, an operation of writing information to the semiconductor device illustrated in FIG. 67 is described.

First, a data voltage write operation (hereinafter referred to as a write operation 1) to the data holding portion connected to the node FG1 will be described. Note that in the following description, the data voltage written to the data holding portion connected to the node FG1 is V _D1, and the threshold voltage of the transistor 4100 is Vth.

In the writing operation 1, after the wiring 4003 is set to V _D1 and the wiring 4001 is set to the ground potential, the wiring 4001 is electrically floated. In addition, the wirings 4005 and 4006 are set to a high level. In addition, the wirings 4007 to 4009 are set to a low level. Then, the potential of the node FG2 which is in an electrically floating state is increased, and a current flows through the transistor 4100. When the current flows, the potential of the wiring 4001 increases. In addition, the transistors 4400 and 4200 are turned on. Therefore, the potentials of the nodes FG1 and FG2 increase as the potential of the wiring 4001 increases. When the potential of the node FG2 rises and the voltage (Vgs) between the gate and the source in the transistor 4100 becomes the threshold voltage Vth of the transistor 4100, the current flowing through the transistor 4100 decreases. Therefore, the potential increase of the wiring 4001 and the nodes FG1 and FG2 stops and becomes constant at “V _D1 −Vth” which is lower than V _D1 by Vth.

That is, V _{D1 applied} to the wiring 4003 is supplied to the wiring 4001 when current flows through the transistor 4100, so that the potentials of the nodes FG1 and FG2 are increased. When the potential of the node FG2 becomes “V _D1 −Vth” due to the rise in potential, Vgs of the transistor 4100 becomes Vth, so that the current stops.

Next, a data voltage writing operation (hereinafter referred to as writing operation 2) to the data holding portion connected to the node FG2 will be described. Incidentally, illustrating a data voltage to be written to the data holding unit connected to the node FG2 as V _D2.

In the write operation 2, after the wiring 4001 is set to V _D2 and the wiring 4003 is set to the ground potential, the wiring 4001 is electrically floated. Further, the wiring 4007 is set to a high level. In addition, the wirings 4005, 4006, 4008, and 4009 are set to a low level. The transistor 4300 is turned on and the wiring 4003 is set to a low level. Therefore, the potential of the node FG2 also decreases to a low level, and a current flows through the transistor 4100. When the current flows, the potential of the wiring 4003 increases. In addition, the transistor 4300 is turned on. Therefore, the potential of the node FG2 increases as the potential of the wiring 4003 increases. When the potential of the node FG2 rises and Vgs becomes Vth of the transistor 4100 in the transistor 4100, the current flowing through the transistor 4100 decreases. Therefore, the increase in the potentials of the wirings 4003 and FG2 stops and becomes constant at “V _D2 −Vth”, which is lower than V _D2 by Vth.

That is, V _{D2 applied} to the wiring 4001 is supplied to the wiring 4003 when a current flows through the transistor 4100, so that the potential of the node FG2 increases. When the potential of the node FG2 becomes “V _D2 −Vth” due to the rise in potential, Vgs of the transistor 4100 becomes Vth, so that the current stops. At this time, the potential of the node FG1 is non-conductive in the transistors 4200 and 4400, and “V _D1 −Vth” written in the writing operation 1 is held.

  In the semiconductor device illustrated in FIG. 67, after data voltages are written to a plurality of data holding portions, the wiring 4009 is set to a high level and the potentials of the nodes FG1 and FG2 are increased. Then, each transistor is brought into a non-conducting state to eliminate the movement of electric charges and to hold the written data voltage.

By the data voltage writing operation to the nodes FG1 and FG2 described above, the data voltages can be held in the plurality of data holding units. Note that although “V _D1 −Vth” and “V _D2 −Vth” have been described as examples of potentials to be written, these are data voltages corresponding to multi-value data. Therefore, when 4-bit data is held in each data holding unit, 16 values of “V _D1 −Vth” and “V _D2 −Vth” can be taken.

  Next, an operation of reading information from the semiconductor device illustrated in FIG. 67 is described.

  First, a data voltage read operation (hereinafter referred to as a read operation 1) to a data holding portion connected to the node FG2 will be described.

In the reading operation 1, the wiring 4003 that has been electrically floated after precharging is discharged. The wirings 4005 to 4008 are set to a low level. Further, the wiring 4009 is set to a low level, and the potential of the node FG2 in an electrically floating state is set to “V _D2 −Vth”. A current flows through the transistor 4100 when the potential of the node FG2 is decreased. When the current flows, the potential of the electrically floating wiring 4003 is decreased. As the potential of the wiring 4003 decreases, Vgs of the transistor 4100 decreases. When Vgs of the transistor 4100 becomes Vth of the transistor 4100, a current flowing through the transistor 4100 is reduced. That is, the potential of the wiring 4003 becomes “V _D2 ” that is a value larger by Vth than the potential “V _D2 −Vth” of the node FG2. The potential of the wiring 4003 corresponds to the data voltage of the data holding portion connected to the node FG2. The read data voltage of the analog value is subjected to A / D conversion, and data of a data holding unit connected to the node FG2 is acquired.

In other words, a current flows through the transistor 4100 when the wiring 4003 after precharging is in a floating state and the potential of the wiring 4009 is switched from a high level to a low level. When the current flows, the potential of the wiring 4003 in the floating state is decreased to “V _D2 ”. In the transistor 4100, Vgs between “V _D2 −Vth” of the node FG2 becomes Vth, so that the current stops. Then, “V _D2 ” written in the writing operation 2 is read out to the wiring 4003.

When data in the data holding portion connected to the node FG2 is acquired, the transistor 4300 is turned on to discharge “V _D2 −Vth” of the node FG2.

  Next, the charge held in the node FG1 is distributed to the node FG2, and the data voltage of the data holding unit connected to the node FG1 is transferred to the data holding unit connected to the node FG2. Here, the wirings 4001 and 4003 are set to a low level. The wiring 4006 is set to a high level. In addition, the wiring 4005 and the wirings 4007 to 4009 are set to a low level. When the transistor 4200 is turned on, the charge of the node FG1 is distributed to and from the node FG2.

Here, the potential after the charge distribution is lowered from the written potential “V _D1 −Vth”. Therefore, the capacitance value of the capacitor 4600 is preferably larger than the capacitance value of the capacitor 4500. Alternatively, the potential “V _D1 −Vth” written to the node FG1 is preferably higher than the potential “V _D2 −Vth” representing the same data. In this way, by changing the ratio of the capacitance values and increasing the potential to be written in advance, it is possible to suppress a decrease in potential after the charge is distributed. The fluctuation of the potential due to the charge distribution will be described later.

  Next, a data voltage read operation (hereinafter referred to as read operation 2) to the data holding portion connected to the node FG1 will be described.

In the reading operation 2, the wiring 4003 that has been electrically floated after precharging is discharged. The wirings 4005 to 4008 are set to a low level. Further, the wiring 4009 is set to a high level at the time of precharge and then to a low level. By setting the wiring 4009 to a low level, the node FG2 in an electrically floating state is set to a potential “V _D1 −Vth”. A current flows through the transistor 4100 when the potential of the node FG2 is decreased. When the current flows, the potential of the electrically floating wiring 4003 is decreased. As the potential of the wiring 4003 decreases, Vgs of the transistor 4100 decreases. When Vgs of the transistor 4100 becomes Vth of the transistor 4100, a current flowing through the transistor 4100 is reduced. That is, the potential of the wiring 4003 becomes “V _D1 ” that is a value larger by Vth than the potential “V _D1 −Vth” of the node FG2. The potential of the wiring 4003 corresponds to the data voltage of the data holding portion connected to the node FG1. The read data voltage of the analog value performs A / D conversion, and acquires data of the data holding unit connected to the node FG1. The above is the data voltage reading operation to the data holding portion connected to the node FG1.

In other words, a current flows through the transistor 4100 when the wiring 4003 after precharging is in a floating state and the potential of the wiring 4009 is switched from a high level to a low level. When the current flows, the potential of the wiring 4003 in the floating state is decreased to “V _D1 ”. In the transistor 4100, the current stops because Vgs between the node FG2 and “V _D1 −Vth” becomes Vth. Then, “V _D1 ” written in the writing operation 1 is read out to the wiring 4003.

  The data voltage can be read from the plurality of data holding units by the data voltage reading operation from the nodes FG1 and FG2 described above. For example, a total of 8 bits (256 values) of data can be held by holding 4 bits (16 values) of data in the nodes FG1 and FG2, respectively. In FIG. 67, the first layer 4021 to the third layer 4023 are used. However, by forming further layers, the storage capacity can be increased without increasing the area of the semiconductor device. .

Note that the read potential can be read as a voltage higher than the written data voltage by Vth. Therefore, it is possible to adopt a configuration in which Vth of “V _D1 −Vth” or “V _D2 −Vth” written by the write operation is canceled and read. As a result, the storage capacity per memory cell can be improved and the read data can be brought close to the correct data, so that the data reliability can be improved.

  The structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments.

(Embodiment 4)
In this embodiment, an example of a circuit configuration to which the OS transistor described in the above embodiment can be applied will be described with reference to FIGS.

FIG. 68A shows a circuit diagram of the inverter. The inverter 800 outputs a signal obtained by inverting the logic of the signal applied to the input terminal IN from the output terminal OUT. The inverter 800 includes a plurality of OS transistors. The signal _SBG is a signal that can switch the electrical characteristics of the OS transistor.

  FIG. 68B illustrates an example of the inverter 800. The inverter 800 includes an OS transistor 810 and an OS transistor 820. Since the inverter 800 can be manufactured using an n-channel transistor, the inverter 800 can be manufactured at a lower cost compared to a case where an inverter (CMOS inverter) is manufactured using a complementary metal oxide semiconductor (CMOS).

  Note that the inverter 800 having an OS transistor can also be disposed on a CMOS formed of Si transistors. Since the inverter 800 can be arranged so as to overlap with a CMOS circuit, an increase in circuit area corresponding to the addition of the inverter 800 can be suppressed.

  The OS transistors 810 and 820 include a first gate that functions as a front gate, a second gate that functions as a back gate, a first terminal that functions as one of a source and a drain, and a second gate that functions as the other of a source and a drain. It has a terminal.

The first gate of the OS transistor 810 is connected to the second terminal. A second gate of the OS transistor 810 is connected to a wiring for supplying the signal _SBG . A first terminal of the OS transistor 810 is connected to a wiring that supplies the voltage VDD. The second terminal of the OS transistor 810 is connected to the output terminal OUT.

  A first gate of the OS transistor 820 is connected to the input terminal IN. A second gate of the OS transistor 820 is connected to the input terminal IN. The first terminal of the OS transistor 820 is connected to the output terminal OUT. A second terminal of the OS transistor 820 is connected to a wiring that supplies the voltage VSS.

FIG. 68C is a timing chart for explaining the operation of the inverter 800. In the timing chart of FIG. 68 (C), it shows the signal waveform of the input terminal IN, the signal waveform of the output terminal OUT, and the change in the threshold voltage of the signal waveform of the signal _{S BG} and OS transistor 810, (FET810).

By _{supplying the} signal SBG to the second gate of the OS transistor 810, the threshold voltage of the OS transistor 810 can be controlled.

Signal _{S BG} has a voltage _V BG _{_ B} for voltage _V BG _{_ A} for causing negative shift of the threshold voltage, the threshold voltage is positive shift. By applying the voltage V _{BG — A} to the second gate, the OS transistor 810 can be negatively shifted to the threshold voltage V _{TH — A.} In addition, by applying the voltage V _{BG — B} to the second gate, the OS transistor 810 can be positively shifted to the threshold voltage V _{TH — B.}

  In order to visualize the above description, FIG. 69A shows a Vg-Id curve which is one of the electrical characteristics of the transistor.

The above-described electrical characteristics of the OS transistor 810 can be shifted to a curve represented by a broken line 840 in FIG. 69A by increasing the voltage of the second gate like the voltage V _{BG — A.} Further, the above-described electrical characteristics of the OS transistor 810 can be shifted to a curve represented by a solid line 841 in FIG. 69A by reducing the voltage of the second gate as the voltage V _{BG — B.} it can. As shown in FIG. 69 (A), OS transistor 810, by switching the signal _{S BG} and so the voltage _V BG _{_ A} or the voltage _V BG _{_ B,} can be shifted in the positive or negative shift of the threshold voltage.

By positively shifting the threshold voltage to the threshold voltage V _{TH — B} , the OS transistor 810 can be in a state in which current does not easily flow. FIG. 69 (B) visualizes this state. As shown in FIG. 69 (B), it can be extremely small current _{I B} flowing through the OS transistor 810. Therefore, when the signal applied to the input terminal IN is at a high level and the OS transistor 820 is in an on state (ON), the voltage at the output terminal OUT can be sharply decreased.

  As shown in FIG. 69B, since the current flowing through the OS transistor 810 can be made difficult to flow, the signal waveform 831 at the output terminal in the timing chart shown in FIG. 68C is changed abruptly. Can do. Since the through current flowing between the wiring for applying the voltage VDD and the wiring for supplying the voltage VSS can be reduced, an operation with low power consumption can be performed.

Further, by shifting the threshold voltage to the threshold voltage V _{TH — A} minus, the OS transistor 810 can be in a state in which current easily flows. FIG. 69C visualizes this state. As shown in FIG. 69 (C), it can be larger than at least the current I _B of the current I _A flowing at this time. Therefore, when the signal supplied to the input terminal IN is at a low level and the OS transistor 820 is in an off state (OFF), the voltage of the output terminal OUT can be rapidly increased.

  As illustrated in FIG. 69C, the current flowing through the OS transistor 810 can easily flow, and thus the signal waveform 832 of the output terminal in the timing chart illustrated in FIG. Can do.

The control of the threshold voltage of the OS transistor 810 by the signal _{S BG} previously the state of the OS transistor 820 is switched, i.e. it is preferably performed before time T1 and T2. For example, as shown in FIG. 68 (C), before the time T1 when the signal applied to the input terminal IN is switched to the high level, the threshold of the OS transistor 810 from the threshold voltage _V TH _{_ A} threshold voltage _V TH _{_ B} It is preferable to switch the voltage. Further, as illustrated in FIG. 68 (C), prior to the time T2 when the signal applied to the input terminal IN is switched to the low level, the threshold of the OS transistor 810 from the threshold voltage _V TH _{_ B} to the threshold voltage _V TH _{_ A} It is preferable to switch the voltage.

Note that although the structure in which the signal _SBG is switched in accordance with the signal applied to the input terminal IN is illustrated in the timing chart in FIG. 68C, another structure may be employed. For example, the voltage for controlling the threshold voltage may be held in the second gate of the OS transistor 810 in a floating state. FIG. 70A illustrates an example of a circuit configuration that can realize this configuration.

FIG. 70A includes an OS transistor 850 in addition to the circuit configuration illustrated in FIG. The first terminal of the OS transistor 850 is connected to the second gate of the OS transistor 810. The second terminal of the OS transistor 850 is connected to a wiring to provide a voltage _V BG _{_ B} (or voltage _V BG _{_ A).} The first gate of the OS transistor 850 is connected to a wiring for providing signal _{S F.} The second gate of the OS transistor 850 is connected to a wiring to provide a voltage _V BG _{_ B} (or voltage _V BG _{_ A).}

  The operation in FIG. 70A is described with reference to a timing chart in FIG.

The voltage for controlling the threshold voltage of the OS transistor 810 is applied to the second gate of the OS transistor 810 before time T3 when the signal applied to the input terminal IN switches to the high level. The OS transistor 850 is turned on the signal _{S F} to the high level, providing a voltage _V BG _{_ B} for controlling a threshold voltage in the node _{N BG.}

After the node N _BG becomes the voltage V _{BG — B} , the OS transistor 850 is turned off. OS transistor 850, an off-state current is extremely small, by continuing to the OFF state, the node in the state close to N _BG very floating state to hold the voltage V _BG _ _B obtained by temporarily held in the node N _BG Can do. Therefore, the number of operations for applying the voltage V _{BG — B} to the second gate of the OS transistor 850 is reduced, so that power consumption required for rewriting the voltage V _{BG — B} can be reduced.

  Note that in the circuit configurations in FIGS. 68B and 70A, the voltage supplied to the second gate of the OS transistor 810 is given by external control; however, another configuration may be used. For example, a voltage for controlling the threshold voltage may be generated based on a signal supplied to the input terminal IN and supplied to the second gate of the OS transistor 810. An example of a circuit configuration that can realize this configuration is illustrated in FIG.

  In FIG. 71A, in the circuit configuration shown in FIG. 68B, a CMOS inverter 860 is provided between the input terminal IN and the second gate of the OS transistor 810. The input terminal of the CMOS inverter 860 is connected to the input terminal IN. The output terminal of the CMOS inverter 860 is connected to the second gate of the OS transistor 810.

  The operation in FIG. 71A is described with reference to a timing chart in FIG. The timing chart in FIG. 71B shows changes in the signal waveform of the input terminal IN, the signal waveform of the output terminal OUT, the output waveform IN_B of the CMOS inverter 860, and the threshold voltage of the OS transistor 810 (FET 810).

  An output waveform IN_B that is a signal obtained by inverting the logic of a signal applied to the input terminal IN can be a signal for controlling the threshold voltage of the OS transistor 810. Therefore, as described in FIGS. 68A to 68C, the threshold voltage of the OS transistor 810 can be controlled. For example, at time T4 in FIG. 71B, a signal supplied to the input terminal IN is high and the OS transistor 820 is turned on. At this time, the output waveform IN_B is at a low level. Therefore, the OS transistor 810 can be in a state in which current does not easily flow, and the voltage of the output terminal OUT can be sharply decreased.

  At time T5 in FIG. 71B, the signal applied to the input terminal IN is low and the OS transistor 820 is turned off. At this time, the output waveform IN_B is at a high level. Therefore, the OS transistor 810 can be in a state in which current easily flows, and the voltage of the output terminal OUT can be rapidly increased.

  As described above, in the configuration of this embodiment, the voltage of the back gate in the inverter having the OS transistor is switched according to the logic of the signal at the input terminal IN. With this structure, the threshold voltage of the OS transistor can be controlled. By controlling the threshold voltage of the OS transistor by a signal applied to the input terminal IN, the voltage of the output terminal OUT can be changed abruptly. In addition, the through current between the wirings supplying the power supply voltage can be reduced. Therefore, low power consumption can be achieved.

  The structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments.

(Embodiment 5)
In this embodiment, an example of a semiconductor device including a plurality of circuits each including the OS transistor described in the above embodiment will be described with reference to FIGS.

  FIG. 72A is a block diagram of the semiconductor device 900. FIG. The semiconductor device 900 includes a power supply circuit 901, a circuit 902, a voltage generation circuit 903, a circuit 904, a voltage generation circuit 905, and a circuit 906.

The power supply circuit 901 is a circuit that generates a reference voltage V _ORG . The voltage V _ORG may be a plurality of voltages instead of a single voltage. The voltage V _ORG can be generated based on the voltage V ₀ given from the outside of the semiconductor device 900. The semiconductor device 900 can generate the voltage V _ORG based on a single power supply voltage given from the outside. Therefore, the semiconductor device 900 can operate without applying a plurality of power supply voltages from the outside.

The circuits 902, 904, and 906 are circuits that operate with different power supply voltages. For example, the power supply voltage of the circuit 902 is a voltage applied by the voltage V _ORG and the voltage V _SS (V _ORG > V _SS ). For example, the power supply voltage of the circuit 904 is a voltage applied by the voltage V _POG and the voltage V _SS (V _POG > V _ORG ). For example, the power supply voltage of the circuit 906 is a voltage applied by the voltage V _ORG and the voltage V _NEG (V _ORG > V _SS > V _NEG ). Note that if the voltage _VSS is set to the same potential as the ground (GND), the types of voltages generated by the power supply circuit 901 can be reduced.

The voltage generation circuit 903 is a circuit that generates the voltage V _POG . The voltage generation circuit 903 can generate the voltage V _POG based on the voltage V _{ORG supplied} from the power supply circuit 901. Therefore, the semiconductor device 900 including the circuit 904 can operate based on a single power supply voltage supplied from the outside.

The voltage generation circuit 905 is a circuit that generates a voltage V _NEG . The voltage generation circuit 905 can generate the voltage V _NEG based on the voltage V _{ORG supplied} from the power supply circuit 901. Therefore, the semiconductor device 900 including the circuit 906 can operate based on a single power supply voltage given from the outside.

FIG. 72B illustrates an example of a circuit 904 that operates at the voltage V _POG , and FIG. 72C illustrates an example of a waveform of a signal for operating the circuit 904.

In FIG. 72B, the transistor 911 is illustrated. Signal applied to the gate of the transistor 911 is generated, for example, based on the voltage _{V POG} and voltage _{V SS.} The signal is a voltage V _SS during operation of the conductive state of transistor 911 voltage V _POG, during operation of the non-conductive state. The voltage V _POG is higher than the voltage V _ORG as illustrated in FIG. Therefore, the transistor 911 can more reliably perform an operation of bringing the source (S) and the drain (D) into conduction. As a result, the circuit 904 can be a circuit in which malfunctions are reduced.

_72D illustrates an example of a circuit 906 that operates at the voltage V _NEG , and FIG. 72E illustrates an example of a waveform of a signal for operating the circuit 906.

FIG. 72D illustrates a transistor 912 having a back gate. Signal applied to the gate of the transistor 912, for example, generated based on the voltage _{V ORG} and the voltage _{V SS.} The signal voltage V _ORG during operation of the conductive state of transistor _911, a voltage V _SS during operation of a non-conductive state. Further, the voltage applied to the back gate of the transistor 912 is generated based on the voltage V _NEG . The voltage V _NEG is smaller than the voltage V _SS (GND) as illustrated in FIG. Therefore, the threshold voltage of the transistor 912 can be controlled to shift positively. Therefore, the transistor 912 can be more reliably turned off, and the current flowing between the source (S) and the drain (D) can be reduced. As a result, the circuit 906 can be a circuit in which malfunctions are reduced and power consumption is reduced.

Note that the voltage V _NEG may be directly applied to the back gate of the transistor 912. Alternatively, a signal to be _supplied to the gate of the transistor 912 may be generated based on the voltage V _ORG and the voltage V _NEG and the signal may be supplied to the back gate of the transistor 912.

  73 (A) and 73 (B) show modified examples of FIGS. 72 (D) and 72 (E).

In the circuit diagram illustrated in FIG. 73A, a transistor 922 whose conduction state can be controlled by the control circuit 921 is illustrated between the voltage generation circuit 905 and the circuit 906. The transistor 922 is an n-channel OS transistor. Control signal _{S BG} control circuit 921 is output a signal for controlling the conduction state of the transistor 922. In addition, transistors 912A and 912B included in the circuit 906 are OS transistors which are the same as the transistor 922.

The timing chart of FIG. 73 (B) includes a control signal _{S BG,} transistor 912A, indicated by a change in the potential of the state nodes _{N BG} back gate potential of 912B. Control signal _{S BG} is transistor 922 in a conducting state at the high level, the node _{N BG} becomes voltage _{V NEG.} Thereafter, when the control signal _SBG is at a low level, the node _NBG becomes electrically floating. Since the transistor 922 is an OS transistor, the off-state current is small. Therefore, even if the node _NBG is electrically floating, the voltage V _NEG once applied can be held.

FIG. 74A shows an example of a circuit configuration applicable to the voltage generation circuit 903 described above. A voltage generation circuit 903 illustrated in FIG. 74A is a five-stage charge pump including diodes D1 to D5, capacitors C1 to C5, and an inverter INV. The clock signal CLK is supplied to the capacitors C1 to C5 directly or via the inverter INV. When the power supply voltage of the inverter INV is a voltage applied by the voltage V _ORG and the voltage V _SS , a voltage V _POG that is boosted to a positive voltage five times the voltage V _ORG can be obtained by the clock signal CLK. The forward voltage of the diodes D1 to D5 is 0V. In addition, a desired voltage V _POG can be obtained by changing the number of stages of the charge pump.

FIG. 74B shows an example of a circuit configuration applicable to the voltage generation circuit 905 described above. A voltage generation circuit 905 illustrated in FIG. 74B is a four-stage charge pump including diodes D1 to D5, capacitors C1 to C5, and an inverter INV. The clock signal CLK is supplied to the capacitors C1 to C5 directly or via the inverter INV. The power supply voltage of the inverter INV, when the voltage applied by the voltage _{V ORG} and the voltage Vss, the clock signal CLK, the ground, that is, the voltage _{V NEG} stepped down from the voltage _{V SS} to four times the negative voltage of the voltage _{V ORG} Can be obtained. The forward voltage of the diodes D1 to D5 is 0V. Further, the desired voltage V _NEG can be obtained by changing the number of stages of the charge pump.

  Note that the circuit configuration of the voltage generation circuit 903 described above is not limited to the configuration of the circuit diagram illustrated in FIG. Modification examples of the voltage generation circuit 903 are illustrated in FIGS. 75A to 75C and FIGS. 76A and 76B.

A voltage generation circuit 903A illustrated in FIG. 75A includes transistors M1 to M10, capacitors C11 to C14, and an inverter INV1. The clock signal CLK is supplied directly to the gates of the transistors M1 to M10 or via the inverter INV1. A voltage V _POG that is boosted to a positive voltage four times the voltage V _ORG can be obtained by the clock signal CLK. Note that a desired voltage V _POG can be obtained by changing the number of stages. A voltage generation circuit 903A illustrated in FIG. 75A can reduce off-state current by using the transistors M1 to M10 as OS transistors, and can suppress leakage of charges held in the capacitors C11 to C14. Therefore, the voltage V _ORG can be efficiently boosted from the voltage V _POG . Further, since the OS transistor has a large on-current and a small subthreshold swing value, the operation speed can be improved.

A voltage generation circuit 903B illustrated in FIG. 75B includes transistors M11 to M14, capacitors C15 and C16, and an inverter INV2. The clock signal CLK is supplied directly to the gates of the transistors M11 to M14 or via the inverter INV2. With the clock signal CLK, it is possible to obtain a voltage V _POG that is boosted to a positive voltage that is twice the voltage V _ORG . A voltage generation circuit 903B illustrated in FIG. 75B can reduce off-state current by using the transistors M11 to M14 as OS transistors, and can suppress leakage of charges held in the capacitors C15 and C16. Therefore, the voltage V _ORG can be efficiently boosted from the voltage V _POG . Further, since the OS transistor has a large on-current and a small subthreshold swing value, the operation speed can be improved.

A voltage generation circuit 903C illustrated in FIG. 75C includes an inductor I11, a transistor M15, a diode D6, and a capacitor C17. The conduction state of the transistor M15 is controlled by the control signal EN. A voltage V _POG obtained by boosting the voltage V _ORG can be obtained by the control signal EN. Since the voltage generation circuit 903C illustrated in FIG. 75C uses the inductor I11 to increase the voltage, the voltage generation circuit 903C can increase the voltage with high conversion efficiency.

A voltage generation circuit 903D illustrated in FIG. 76A corresponds to a structure in which the diodes D1 to D5 of the voltage generation circuit 903 illustrated in FIG. 74A are replaced with diode-connected transistors M16 to M20. A voltage generation circuit 903D illustrated in FIG. 76A can reduce off-state current by using the transistors M16 to M20 as OS transistors and suppress leakage of charges held in the capacitors C1 to C5. Therefore, the voltage V _ORG can be efficiently boosted from the voltage V _POG . Further, since the OS transistor has a large on-current and a small subthreshold swing value, the operation speed can be improved.

A voltage generation circuit 903E illustrated in FIG. 76B corresponds to a structure in which the transistors M16 to M20 of the voltage generation circuit 903D illustrated in FIG. 76A are replaced with transistors M21 to M25 having back gates. Since the voltage generation circuit 903E illustrated in FIG. 76B can supply the same voltage as the gate to the back gate, the amount of current flowing through the transistor can be increased. Therefore, the voltage V _ORG can be efficiently boosted from the voltage V _POG .

Note that a modification of the voltage generation circuit 903 can also be applied to the voltage generation circuit 905 illustrated in FIG. A circuit diagram configuration in this case is shown in FIGS. 77A to 77C and FIGS. 78A and 78B. Voltage generating circuit 905A shown in FIG. 77 (A) is the clock signal CLK, and it is possible to obtain a voltage _{V NEG} stepped down from the voltage _{V SS} to 3 times the negative voltage of the voltage _{V ORG.} The voltage generating circuit 905A shown in FIG. 77 (B) is the clock signal CLK, and it is possible to obtain a voltage _{V NEG} stepped down from the voltage _{V SS} to twice the negative voltage of the voltage _{V ORG.}

The voltage generation circuits 905A to 905E shown in FIGS. 77A to 77C, 78A and 78B are shown in FIGS. 75A to 75C, 76A and 76B, respectively. In the voltage generation circuits 903A to 903E, the voltage applied to each wiring is changed or the arrangement of elements is changed. 77A to 77C, 78A, and 78B, as with the voltage generation circuits 905A to 905E, can efficiently reduce the voltage V _ORG to the voltage V _NEG .

  As described above, in the structure of this embodiment mode, a voltage necessary for a circuit included in the semiconductor device can be generated internally. Therefore, the semiconductor device can reduce the type of power supply voltage applied from the outside.

  The structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments.

(Embodiment 6)
In this embodiment, an example of a CPU including a transistor according to one embodiment of the present invention and a semiconductor device such as the memory device described above will be described.

<Configuration of CPU>
A semiconductor device 400 illustrated in FIG. 79 includes a CPU core 401, a power management unit 421, and a peripheral circuit 422. The power management unit 421 includes a power controller 402 and a power switch 403. The peripheral circuit 422 includes a cache 404 having a cache memory, a bus interface (BUS I / F) 405, and a debug interface (Debug I / F) 406. The CPU core 401 includes a data bus 423, a control device 407, a PC (program counter) 408, a pipeline register 409, a pipeline register 410, an ALU (Arithmic logic unit) 411, and a register file 412. Data exchange between the CPU core 401 and the peripheral circuit 422 such as the cache 404 is performed via the data bus 423.

  The semiconductor device (cell) can be applied to many logic circuits including the power controller 402 and the control device 407. In particular, the present invention can be applied to all logic circuits that can be configured using standard cells. As a result, a small semiconductor device 400 can be provided. In addition, the semiconductor device 400 capable of reducing power consumption can be provided. Further, the semiconductor device 400 capable of improving the operation speed can be provided. In addition, it is possible to provide the semiconductor device 400 capable of reducing fluctuations in the power supply voltage.

  In the semiconductor device (cell), a p-channel Si transistor and a transistor including the oxide semiconductor described in the above embodiment (preferably an oxide containing In, Ga, and Zn) in a channel formation region are used. By applying the semiconductor device (cell) to the semiconductor device 400, a small semiconductor device 400 can be provided. In addition, the semiconductor device 400 capable of reducing power consumption can be provided. Further, the semiconductor device 400 capable of improving the operation speed can be provided. In particular, manufacturing costs can be kept low by using only p-channel Si transistors.

  The control device 407 controls the operations of the PC 408, pipeline register 409, pipeline register 410, ALU 411, register file 412, cache 404, bus interface 405, debug interface 406, and power controller 402, thereby providing an input. A function of decoding and executing an instruction included in a program such as an executed application.

  The ALU 411 has a function of performing various arithmetic processes such as four arithmetic operations and logical operations.

  The cache 404 has a function of temporarily storing frequently used data. The PC 408 is a register having a function of storing an address of an instruction to be executed next. Although not shown in FIG. 79, the cache 404 is provided with a cache controller that controls the operation of the cache memory.

  The pipeline register 409 is a register having a function of temporarily storing instruction data.

  The register file 412 includes a plurality of registers including general-purpose registers, and can store data read from the main memory, data obtained as a result of arithmetic processing of the ALU 411, and the like.

  The pipeline register 410 is a register having a function of temporarily storing data used for the arithmetic processing of the ALU 411 or data obtained as a result of the arithmetic processing of the ALU 411.

  The bus interface 405 functions as a data path between the semiconductor device 400 and various devices outside the semiconductor device 400. The debug interface 406 has a function as a signal path for inputting an instruction for controlling debugging to the semiconductor device 400.

  The power switch 403 has a function of controlling power supply voltage supply to various circuits of the semiconductor device 400 other than the power controller 402. The various circuits belong to several power domains, and the power switches 403 control whether the various circuits belonging to the same power domain are supplied with a power supply voltage. The power controller 402 has a function of controlling the operation of the power switch 403.

  The semiconductor device 400 having the above structure can perform power gating. The flow of power gating operation will be described with an example.

  First, the CPU core 401 sets the timing at which the supply of the power supply voltage is stopped in the register of the power controller 402. Next, a command to start power gating is sent from the CPU core 401 to the power controller 402. Next, the various registers and the cache 404 included in the semiconductor device 400 start saving data. Next, supply of power supply voltage to various circuits other than the power controller 402 included in the semiconductor device 400 is stopped by the power switch 403. Next, when an interrupt signal is input to the power controller 402, supply of power supply voltage to various circuits included in the semiconductor device 400 is started. Note that a counter may be provided in the power controller 402 and the timing at which the supply of the power supply voltage is started may be determined using the counter without depending on the input of the interrupt signal. Next, the various registers and the cache 404 start data restoration. Next, the execution of the instruction in the control device 407 is resumed.

  Such power gating can be performed in the entire processor or in one or a plurality of logic circuits constituting the processor. Further, power supply can be stopped even in a short time. For this reason, power consumption can be reduced with fine granularity spatially or temporally.

  When power gating is performed, it is preferable that information held by the CPU core 401 and the peripheral circuit 422 can be saved in a short time. By doing so, the power can be turned on and off in a short time, and the power saving effect is increased.

  In order to save the information held by the CPU core 401 and the peripheral circuit 422 in a short time, it is preferable that the flip-flop circuit can save data in the circuit (referred to as a flip-flop circuit that can be backed up). In addition, it is preferable that the SRAM cell can save data in the cell (referred to as a backupable SRAM cell). A flip-flop circuit or SRAM cell that can be backed up preferably includes a transistor including an oxide semiconductor (preferably an oxide containing In, Ga, and Zn) in a channel formation region. As a result, when the transistor has a low off-state current, the flip-flop circuit and the SRAM cell that can be backed up can hold information without supplying power for a long time. In addition, when a transistor has a high switching speed, a backupable flip-flop circuit or an SRAM cell may be able to save and restore data in a short time.

  An example of a flip-flop circuit that can be backed up will be described with reference to FIG.

  A semiconductor device 500 illustrated in FIG. 80 is an example of a flip-flop circuit that can be backed up. The semiconductor device 500 includes a first memory circuit 501, a second memory circuit 502, a third memory circuit 503, and a reading circuit 504. A potential difference between the potential V1 and the potential V2 is supplied to the semiconductor device 500 as a power supply voltage. One of the potential V1 and the potential V2 is at a high level, and the other is at a low level. Hereinafter, a configuration example of the semiconductor device 500 will be described using a case where the potential V1 is at a low level and the potential V2 is at a high level as an example.

  The first memory circuit 501 has a function of holding data when a signal D including data is input in a period in which the power supply voltage is supplied to the semiconductor device 500. Then, in a period in which the power supply voltage is supplied to the semiconductor device 500, the first memory circuit 501 outputs a signal Q including retained data. On the other hand, the first memory circuit 501 cannot hold data during a period in which the power supply voltage is not supplied to the semiconductor device 500. That is, the first memory circuit 501 can be called a volatile memory circuit.

  The second memory circuit 502 has a function of reading and storing (or saving) data held in the first memory circuit 501. The third memory circuit 503 has a function of reading and storing (or saving) data held in the second memory circuit 502. The reading circuit 504 has a function of reading data stored in the second memory circuit 502 or the third memory circuit 503 and storing (or returning) the data in the first memory circuit 501.

  In particular, the third memory circuit 503 has a function of reading and storing (or saving) data held in the second memory circuit 502 even during a period in which the power supply voltage is not supplied to the semiconductor device 500. .

  As illustrated in FIG. 80, the second memory circuit 502 includes a transistor 512 and a capacitor 519. The third memory circuit 503 includes a transistor 513, a transistor 515, and a capacitor 520. The reading circuit 504 includes a transistor 510, a transistor 518, a transistor 509, and a transistor 517.

  The transistor 512 has a function of charging and discharging the capacitor 519 with charges corresponding to data held in the first memory circuit 501. The transistor 512 is preferably capable of charging / discharging the capacitor 519 at high speed according to data stored in the first memory circuit 501. Specifically, the transistor 512 desirably includes crystalline silicon (preferably polycrystalline silicon, more preferably single crystal silicon) in a channel formation region.

  The transistor 513 is selected to be conductive or nonconductive according to the charge held in the capacitor 519. The transistor 515 has a function of charging and discharging the capacitor 520 with a charge corresponding to the potential of the wiring 544 when the transistor 513 is in a conductive state. The transistor 515 preferably has extremely low off-state current. Specifically, the transistor 515 desirably includes an oxide semiconductor (preferably an oxide containing In, Ga, and Zn) in a channel formation region.

  Specifically, the connection relation of each element is described. One of a source and a drain of the transistor 512 is connected to the first memory circuit 501. The other of the source and the drain of the transistor 512 is connected to one electrode of the capacitor 519, the gate of the transistor 513, and the gate of the transistor 518. The other electrode of the capacitor 519 is connected to the wiring 542. One of a source and a drain of the transistor 513 is connected to the wiring 544. The other of the source and the drain of the transistor 513 is connected to one of the source and the drain of the transistor 515. The other of the source and the drain of the transistor 515 is connected to one electrode of the capacitor 520 and the gate of the transistor 510. The other electrode of the capacitor 520 is connected to the wiring 543. One of a source and a drain of the transistor 510 is connected to the wiring 541. The other of the source and the drain of the transistor 510 is connected to one of the source and the drain of the transistor 518. The other of the source and the drain of the transistor 518 is connected to one of the source and the drain of the transistor 509. The other of the source and the drain of the transistor 509 is connected to one of the source and the drain of the transistor 517 and the first memory circuit 501. The other of the source and the drain of the transistor 517 is connected to the wiring 540. In FIG. 80, the gate of the transistor 509 is connected to the gate of the transistor 517; however, the gate of the transistor 509 is not necessarily connected to the gate of the transistor 517.

  The transistor illustrated in the above embodiment can be used as the transistor 515. Since the off-state current of the transistor 515 is small, the semiconductor device 500 can hold information without supplying power for a long time. Since the switching characteristics of the transistor 515 are favorable, the semiconductor device 500 can perform high-speed backup and recovery.

  The structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments.

(Embodiment 7)
In this embodiment, an example of an imaging device using a transistor or the like according to one embodiment of the present invention will be described.

<Imaging device>
The imaging device according to one embodiment of the present invention is described below.

  FIG. 81A is a plan view illustrating an example of an imaging device 2200 according to one embodiment of the present invention. The imaging device 2200 includes a pixel portion 2210, a peripheral circuit 2260 for driving the pixel portion 2210, a peripheral circuit 2270, a peripheral circuit 2280, and a peripheral circuit 2290. The pixel portion 2210 includes a plurality of pixels 2211 arranged in a matrix of p rows and q columns (p and q are integers of 2 or more). The peripheral circuit 2260, the peripheral circuit 2270, the peripheral circuit 2280, and the peripheral circuit 2290 are each connected to the plurality of pixels 2211 and have a function of supplying a signal for driving the plurality of pixels 2211. Note that in this specification and the like, the peripheral circuit 2260, the peripheral circuit 2270, the peripheral circuit 2280, the peripheral circuit 2290, and the like are all referred to as “peripheral circuits” or “drive circuits” in some cases. For example, the peripheral circuit 2260 can be said to be part of the peripheral circuit.

  In addition, the imaging device 2200 preferably includes a light source 2291. The light source 2291 can emit the detection light P1.

  The peripheral circuit includes at least one of a logic circuit, a switch, a buffer, an amplifier circuit, and a conversion circuit. The peripheral circuit may be formed over a substrate over which the pixel portion 2210 is formed. Further, a semiconductor device such as an IC chip may be used for part or all of the peripheral circuit. Note that one or more of the peripheral circuit 2260, the peripheral circuit 2270, the peripheral circuit 2280, and the peripheral circuit 2290 may be omitted from the peripheral circuit.

  In addition, as illustrated in FIG. 81B, in the pixel portion 2210 included in the imaging device 2200, the pixel 2211 may be inclined. By arranging the pixels 2211 to be inclined, the pixel interval (pitch) in the row direction and the column direction can be shortened. Thereby, the imaging quality in the imaging device 2200 can be further improved.

<Pixel Configuration Example 1>
One pixel 2211 included in the imaging device 2200 is configured by a plurality of sub-pixels 2212, and a color image display is realized by combining each sub-pixel 2212 with a filter (color filter) that transmits light in a specific wavelength range. Information can be acquired.

  FIG. 82A is a plan view illustrating an example of a pixel 2211 for acquiring a color image. A pixel 2211 illustrated in FIG. 82A includes a sub-pixel 2212 (hereinafter, also referred to as “sub-pixel 2212R”) provided with a color filter that transmits light in the red (R) wavelength region, and a green (G) wavelength. A sub-pixel 2212 (hereinafter also referred to as “sub-pixel 2212G”) provided with a color filter that transmits light in the region and a sub-pixel 2212 (hereinafter referred to as “color filter” that transmits light in the blue (B) wavelength region). , Also referred to as “sub-pixel 2212B”. The sub-pixel 2212 can function as a photosensor.

  The sub-pixel 2212 (the sub-pixel 2212R, the sub-pixel 2212G, and the sub-pixel 2212B) is electrically connected to the wiring 2231, the wiring 2247, the wiring 2248, the wiring 2249, and the wiring 2250. Further, the sub-pixel 2212R, the sub-pixel 2212G, and the sub-pixel 2212B are each connected to an independent wiring 2253. Further, in this specification and the like, for example, the wiring 2248 and the wiring 2249 connected to the pixel 2211 in the n-th row are referred to as a wiring 2248 [n] and a wiring 2249 [n], respectively. For example, the wiring 2253 connected to the pixel 2211 in the m-th column is referred to as a wiring 2253 [m]. Note that in FIG. 82A, the wiring 2253 connected to the subpixel 2212R included in the pixel 2211 in the m-th column is the wiring 2253 [m] R, the wiring 2253 connected to the subpixel 2212G is the wiring 2253 [m] G, and A wiring 2253 connected to the subpixel 2212B is referred to as a wiring 2253 [m] B. The sub-pixel 2212 is electrically connected to the peripheral circuit through the wiring.

  In addition, the imaging device 2200 has a configuration in which subpixels 2212 provided with color filters that transmit light in the same wavelength region of adjacent pixels 2211 are electrically connected to each other via a switch. 82B, the sub-pixel 2212 included in the pixel 2211 arranged in n rows (n is an integer of 1 to p) and m columns (m is an integer of 1 to q) is adjacent to the pixel 2211. A connection example of the sub-pixel 2212 included in the pixel 2211 arranged in n + 1 rows and m columns is shown. 82B, a subpixel 2212R arranged in n rows and m columns and a subpixel 2212R arranged in n + 1 rows and m columns are connected through a switch 2201. Further, a subpixel 2212G arranged in n rows and m columns and a subpixel 2212G arranged in n + 1 rows and m columns are connected via a switch 2202. Further, a subpixel 2212B arranged in n rows and m columns and a subpixel 2212B arranged in n + 1 rows and m columns are connected via a switch 2203.

  Note that the color filter used for the sub-pixel 2212 is not limited to red (R), green (G), and blue (B), and transmits cyan (C), yellow (Y), and magenta (M) light, respectively. A color filter may be used. A full-color image can be acquired by providing the sub-pixel 2212 that detects light of three different wavelength ranges in one pixel 2211.

  Alternatively, in addition to the sub-pixel 2212 provided with a color filter that transmits red (R), green (G), and blue (B) light, a color filter that transmits yellow (Y) light is provided. A pixel 2211 including a sub-pixel 2212 may be used. Alternatively, in addition to the sub-pixel 2212 provided with a color filter that transmits cyan (C), yellow (Y), and magenta (M) light, a color filter that transmits blue (B) light is provided. A pixel 2211 including a sub-pixel 2212 may be used. By providing the sub-pixel 2212 for detecting light of four types of different wavelength ranges in one pixel 2211, the color reproducibility of the acquired image can be further improved.

  For example, in FIG. 82A, the sub-pixel 2212 that detects light in the red wavelength region, the sub-pixel 2212 that detects light in the green wavelength region, and the sub-pixel 2212 that detects light in the blue wavelength region. The pixel number ratio (or the light receiving area ratio) may not be 1: 1: 1. For example, a Bayer array in which the pixel number ratio (light receiving area ratio) is red: green: blue = 1: 2: 1 may be used. Alternatively, the pixel number ratio (light receiving area ratio) may be red: green: blue = 1: 6: 1.

  Note that the number of subpixels 2212 provided in the pixel 2211 may be one, but two or more are preferable. For example, by providing two or more subpixels 2212 that detect light in the same wavelength region, redundancy can be increased and the reliability of the imaging device 2200 can be increased.

  In addition, by using an IR (IR: Infrared) filter that absorbs or reflects visible light and transmits infrared light, an imaging device 2200 that detects infrared light can be realized.

  Further, by using an ND (ND: Neutral Density) filter (a neutral density filter), it is possible to prevent output saturation that occurs when a large amount of light enters the photoelectric conversion element (light receiving element). By using a combination of ND filters having different light reduction amounts, the dynamic range of the imaging apparatus can be increased.

  In addition to the above-described filter, a lens may be provided in the pixel 2211. Here, an arrangement example of the pixel 2211, the filter 2254, and the lens 2255 will be described with reference to the cross-sectional view of FIG. By providing the lens 2255, the photoelectric conversion element can efficiently receive incident light. Specifically, as illustrated in FIG. 83A, light 2256 is input to the photoelectric conversion element 2220 through the lens 2255, the filter 2254 (the filter 2254R, the filter 2254G, and the filter 2254B) formed in the pixel 2211, the pixel circuit 2230, and the like. It can be set as the structure made to enter.

  However, part of the light 2256 indicated by the arrow may be blocked by part of the wiring 2257 as shown in the region surrounded by the alternate long and short dash line. Therefore, a structure in which a lens 2255 and a filter 2254 are provided on the photoelectric conversion element 2220 side so that the photoelectric conversion element 2220 efficiently receives light 2256 as illustrated in FIG. 83B is preferable. By making the light 2256 enter the photoelectric conversion element 2220 from the photoelectric conversion element 2220 side, the imaging device 2200 with high detection sensitivity can be provided.

  As the photoelectric conversion element 2220 illustrated in FIG. 83, a photoelectric conversion element in which a pn-type junction or a pin-type junction is formed may be used.

  Alternatively, the photoelectric conversion element 2220 may be formed using a substance that has a function of generating charge by absorbing radiation. Examples of the substance having a function of absorbing radiation and generating a charge include selenium, lead iodide, mercury iodide, gallium arsenide, cadmium telluride, and cadmium zinc alloy.

  For example, when selenium is used for the photoelectric conversion element 2220, a photoelectric conversion element 2220 having a light absorption coefficient over a wide wavelength range such as X-rays and gamma rays in addition to visible light, ultraviolet light, and infrared light can be realized.

  Here, one pixel 2211 included in the imaging device 2200 may include a sub-pixel 2212 including a first filter in addition to the sub-pixel 2212 illustrated in FIG.

<Pixel Configuration Example 2>
Hereinafter, an example in which a pixel is formed using a transistor including silicon and a transistor including an oxide semiconductor will be described. As each transistor, a transistor similar to that described in the above embodiment can be used.

  FIG. 84 is a cross-sectional view of elements constituting the imaging device. The imaging device illustrated in FIG. 84 is provided on a transistor 2351 using silicon provided on a silicon substrate 2300, a transistor 2352 and a transistor 2353 using oxide semiconductor layers stacked over the transistor 2351, and a silicon substrate 2300. Photo diode 2360. Each transistor and photodiode 2360 is electrically connected to various plugs 2370 and wirings 2371. The anode 2361 of the photodiode 2360 is electrically connected to the plug 2370 through the low resistance region 2363.

  In addition, the imaging device is provided in contact with the layer 2310 including the transistor 2351 and the photodiode 2360 provided over the silicon substrate 2300, the layer 2320 including the wiring 2371, the layer 2320 including the wiring 2371, and the transistor 2352. A layer 2330 including a transistor 2353 and a layer 2340 provided in contact with the layer 2330 and including a wiring 2372 and a wiring 2373.

  Note that in the example of the cross-sectional view of FIG. 84, the silicon substrate 2300 has a light receiving surface of the photodiode 2360 on the surface opposite to the surface on which the transistor 2351 is formed. With this configuration, an optical path can be secured without being affected by various transistors and wirings. Therefore, a pixel with a high aperture ratio can be formed. Note that the light-receiving surface of the photodiode 2360 can be the same as the surface over which the transistor 2351 is formed.

  Note that in the case where a pixel is formed using only a transistor including an oxide semiconductor, the layer 2310 may be a layer including a transistor including an oxide semiconductor. Alternatively, the layer 2310 may be omitted, and the pixel may be formed using only a transistor including an oxide semiconductor.

  Note that the silicon substrate 2300 may be an SOI substrate. Further, instead of the silicon substrate 2300, germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, or an organic semiconductor substrate can be used.

  Here, an insulator 2380 is provided between the layer 2310 including the transistor 2351 and the photodiode 2360 and the layer 2330 including the transistor 2352 and the transistor 2353. However, the position of the insulator 2380 is not limited. An insulator 2379 is provided below the insulator 2380, and an insulator 2381 is provided on the insulator 2380.

  Conductors 2390a to 2390e are provided in openings provided in the insulators 2379 to 2380. The conductor 2390a, the conductor 2390b, and the conductor 2390e function as a plug and a wiring. The conductor 2390c functions as a back gate of the transistor 2353. The conductor 2390d functions as a back gate of the transistor 2352.

  Hydrogen in the insulator provided in the vicinity of the channel formation region of the transistor 2351 has an effect of terminating dangling bonds of silicon and improving the reliability of the transistor 2351. On the other hand, hydrogen in the insulator provided in the vicinity of the transistor 2352, the transistor 2353, and the like is one of the factors that generate carriers in the oxide semiconductor. Therefore, the reliability of the transistor 2352, the transistor 2353, and the like may be reduced. Therefore, in the case where a transistor including an oxide semiconductor is stacked over a transistor including a silicon-based semiconductor, an insulator 2380 having a function of blocking hydrogen is preferably provided therebetween. By confining hydrogen below the insulator 2380, the reliability of the transistor 2351 can be improved. Further, since hydrogen can be prevented from diffusing from the lower layer than the insulator 2380 to the upper layer from the insulator 2380, reliability of the transistor 2352, the transistor 2353, and the like can be improved. Further, since the conductor 2390a, the conductor 2390b, and the conductor 2390e are formed, hydrogen can be prevented from diffusing into an upper layer through the via hole formed in the insulator 2380, so that the reliability of the transistor 2352, the transistor 2353, and the like can be reduced. Can be improved.

  In the cross-sectional view in FIG. 84, the photodiode 2360 provided in the layer 2310 and the transistor provided in the layer 2330 can be formed to overlap with each other. Then, the integration degree of pixels can be increased. That is, the resolution of the imaging device can be increased.

  Further, a part or all of the imaging device may be curved. By curving the imaging device, field curvature and astigmatism can be reduced. Therefore, optical design of a lens or the like used in combination with the imaging device can be facilitated. For example, since the number of lenses for aberration correction can be reduced, it is possible to reduce the size and weight of an electronic device using an imaging device. In addition, the quality of the captured image can be improved.

  The structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments.

(Embodiment 8)
In this embodiment, a semiconductor wafer, a chip, and an electronic component according to one embodiment of the present invention will be described.

<Semiconductor wafer, chip>
FIG. 85A shows a top view of the substrate 711 before the dicing process is performed. As the substrate 711, for example, a semiconductor substrate (also referred to as a “semiconductor wafer”) can be used. A plurality of circuit regions 712 are provided on the substrate 711. In the circuit region 712, a semiconductor device according to one embodiment of the present invention, a CPU, an RF tag, an image sensor, or the like can be provided.

  Each of the plurality of circuit regions 712 is surrounded by the isolation region 713. A separation line (also referred to as “dicing line”) 714 is set at a position overlapping with the separation region 713. By cutting the substrate 711 along the separation line 714, the chip 715 including the circuit region 712 can be cut out from the substrate 711. FIG. 85B shows an enlarged view of the chip 715.

  Further, a conductive layer, a semiconductor layer, or the like may be provided in the separation region 713. By providing a conductive layer, a semiconductor layer, or the like in the separation region 713, ESD that may occur in the dicing process can be reduced, and a reduction in yield due to the dicing process can be prevented. In general, the dicing step is performed while supplying pure water having a specific resistance lowered by dissolving carbon dioxide gas or the like for the purpose of cooling the substrate, removing shavings, and preventing charging. By providing a conductive layer, a semiconductor layer, or the like in the separation region 713, the amount of pure water used can be reduced. Thus, the production cost of the semiconductor device can be reduced. In addition, the productivity of the semiconductor device can be increased.

<Electronic parts>
An example of an electronic component using the chip 715 will be described with reference to FIG. Note that the electronic component is also referred to as a semiconductor package or an IC package. Electronic parts have a plurality of standards, names, and the like depending on the terminal take-out direction, the terminal shape, and the like.

  Electronic components are completed by combining the semiconductor device described in the above embodiment and components other than the semiconductor device in an assembly process (post-process).

  The post-process will be described with reference to the flowchart shown in FIG. After the semiconductor device or the like according to one embodiment of the present invention is formed over the substrate 711 in the previous step, a “back surface grinding step” of grinding the back surface (the surface where the semiconductor device or the like is not formed) of the substrate 711 is performed (step S721). . By reducing the thickness of the substrate 711 by grinding, the electronic component can be downsized.

  Next, a “dicing step” for separating the substrate 711 into a plurality of chips (chips 715) is performed (step S722). Then, a “die bonding step” is performed in which the separated chip 715 is bonded onto each lead frame (step S723). For the bonding of the chip 715 and the lead frame in the die bonding step, a suitable method is appropriately selected according to the product, such as bonding with a resin or bonding with a tape. Note that the chip 715 may be bonded on the interposer substrate instead of the lead frame.

  Next, a “wire bonding process” is performed in which the lead of the lead frame and the electrode on the chip 715 are electrically connected with a thin metal wire (step S724). A silver wire, a gold wire, etc. can be used for a metal fine wire. For wire bonding, for example, ball bonding or wedge bonding can be used.

  The chip 715 that has been wire bonded is subjected to a “sealing process (molding process)” that is sealed with an epoxy resin or the like (step S725). By performing the sealing process, the inside of the electronic component is filled with resin, the wire connecting the chip 715 and the lead can be protected from mechanical external force, and deterioration of characteristics due to moisture, dust, etc. (reliability Reduction) can be reduced.

  Next, a “lead plating process” for plating the leads of the lead frame is performed (step S726). The plating process prevents rusting of the lead, and soldering when mounted on a printed circuit board later can be performed more reliably. Next, a “molding process” for cutting and molding the lead is performed (step S727).

  Next, a “marking process” is performed in which a printing process (marking) is performed on the surface of the package (step S728). An electronic component is completed through an “inspection process” (step S729) for checking whether the external shape is good or not, and whether there is a malfunction.

  FIG. 86B is a schematic perspective view of the completed electronic component. FIG. 86B shows a schematic perspective view of a QFP (Quad Flat Package) as an example of an electronic component. An electronic component 750 illustrated in FIG. 86B includes a lead 755 and a chip 715. The electronic component 750 may have a plurality of chips 715.

  An electronic component 750 illustrated in FIG. 86B is mounted on a printed board 752, for example. A plurality of such electronic components 750 are combined and each is electrically connected on the printed circuit board 752 to complete a substrate (mounting substrate 754) on which the electronic components are mounted. The completed mounting board 754 is used for an electronic device or the like.

  The structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments.

(Embodiment 9)
In this embodiment, electronic devices using a transistor or the like according to one embodiment of the present invention will be described.

<Electronic equipment>
A semiconductor device according to one embodiment of the present invention includes a display device, a personal computer, and an image reproducing device including a recording medium (typically a display that can reproduce a recording medium such as a DVD: Digital Versatile Disc and display the image) Device). In addition, as an electronic device in which the semiconductor device according to one embodiment of the present invention can be used, a mobile phone, a game machine including a portable type, a portable data terminal, an electronic book terminal, a video camera, a digital still camera, or the like, goggles Type displays (head-mounted displays), navigation systems, sound playback devices (car audio, digital audio players, etc.), copiers, facsimiles, printers, multifunction printers, automated teller machines (ATMs), vending machines, etc. It is done. Specific examples of these electronic devices are shown in FIGS.

  FIG. 87A illustrates a portable game machine including a housing 1901, a display portion 1903, a microphone 1905, a speaker 1906, operation keys 1907, and the like. Note that although the portable game machine illustrated in FIG. 87A includes one display portion 1903, the number of display portions included in the portable game machine is not limited thereto. For example, a configuration having a plurality of display units may be employed. Further, a stylus for operating the display portion 1903 may be attached.

  FIG. 87B illustrates a portable data terminal, which includes a first housing 1911, a second housing 1912, a first display portion 1913, a second display portion 1914, a connection portion 1915, operation keys 1916, and the like. The first display portion 1913 is provided in the first housing 1911, and the second display portion 1914 is provided in the second housing 1912. The first casing 1911 and the second casing 1912 are connected by a connection portion 1915, and the angle between the first casing 1911 and the second casing 1912 can be changed by the connecting portion 1915. is there. It is good also as a structure which switches the image | video in the 1st display part 1913 according to the angle between the 1st housing | casing 1911 and the 2nd housing | casing 1912 in the connection part 1915. FIG. Further, a display device in which a function as a position input device is added to at least one of the first display portion 1913 and the second display portion 1914 may be used. Note that the function as a position input device can be added by providing a touch panel on the display device. Alternatively, the function as a position input device can be added by providing a photoelectric conversion element called a photosensor in a pixel portion of a display device.

  FIG. 87C illustrates a laptop personal computer, which includes a housing 1921, a display portion 1922, a keyboard 1923, a pointing device 1924, and the like.

  FIG. 87D illustrates an electric refrigerator-freezer, which includes a housing 1931, a refrigerator door 1932, a refrigerator door 1933, and the like.

  FIG. 87E illustrates a video camera, which includes a first housing 1941, a second housing 1942, a display portion 1943, operation keys 1944, a lens 1945, a connection portion 1946, and the like. The operation key 1944 and the lens 1945 are provided in the first housing 1941, and the display portion 1943 is provided in the second housing 1942. The first housing 1941 and the second housing 1942 are connected to each other by a connection portion 1946. The angle between the first housing 1941 and the second housing 1942 can be changed by the connection portion 1946. is there. The video on the display portion 1943 may be switched according to the angle between the first housing 1941 and the second housing 1942 in the connection portion 1946.

  FIG. 87F illustrates an automobile, which includes a vehicle body 1951, wheels 1952, a dashboard 1953, lights 1954, and the like.

  Note that one embodiment of the present invention is described in this embodiment. Note that one embodiment of the present invention is not limited thereto. In other words, in the present embodiment and the like, various aspects of the invention are described, and thus one embodiment of the present invention is not limited to a particular embodiment. For example, although an example in which a channel formation region, a source / drain region, and the like of a transistor include an oxide semiconductor is described as one embodiment of the present invention, one embodiment of the present invention is not limited thereto. In some cases or depending on circumstances, various transistors in one embodiment of the present invention, a channel formation region of the transistor, a source / drain region of the transistor, or the like may include various semiconductors. Depending on circumstances or circumstances, various transistors in one embodiment of the present invention, a channel formation region of the transistor, a source / drain region of the transistor, and the like can be formed using, for example, silicon, germanium, silicon germanium, silicon carbide, or gallium. At least one of arsenic, aluminum gallium arsenide, indium phosphide, gallium nitride, or an organic semiconductor may be included. Alternatively, for example, depending on circumstances or circumstances, a variety of transistors, channel formation regions of the transistors, source and drain regions of the transistors, and the like of the transistor may not include an oxide semiconductor. Good.

  The structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments.

  In this example, the results of observation of an In—Ga—Zn oxide film (hereinafter sometimes referred to as an IGZO film) formed using the film formation method described in the above embodiment will be described.

  In this example, as a sample 1, an IGZO film is formed on an yttria-stabilized zirconia (YSZ) substrate using an In—Ga—Zn oxide (atomic ratio In: Ga: Zn = 1: 1: 1) target. Filmed. The surface orientation of the surface of the YSZ substrate used for sample 1 is (111). The IGZO film was formed by controlling the pressure to 0.4 Pa in an atmosphere containing oxygen gas 30 sccm, applying a substrate temperature of 300 ° C., and applying 1000 W output to the target from a DC power source.

  About the produced sample 1, the HAADF-STEM (High-angle annular Dark Field Scanning TEM) image of the interface vicinity of the IGZO film | membrane was observed. A HAADF-STEM image of Sample 1 is shown in FIG.

  As shown in FIG. 88, sample 1 shows an IGZO film in which layered crystals are formed on a YSZ substrate. Further, the plane orientation (111) of the YSZ substrate of Sample 1 matches the lattice constant of the IGZO film, and the CAAC-OS is formed from directly above the YSZ substrate.

  As described above, an In—Ga—Zn oxide crystal is formed from the initial stage of film formation by forming the IGZO film over the YSZ substrate by using the film formation method described in the above embodiment. Indicated. This is in good agreement with the CAAC-OS film formation model described in the above embodiment.

  In this example, the results of evaluation of crystallinity using XRD for an IGZO film formed using the film formation method described in the above embodiment will be described.

In this embodiment, as a sample 2A to a sample 2D, an In—Ga—Zn oxide film is formed over a quartz substrate, and an In—Ga—Zn oxide (atomic ratio In: Ga: Zn = 1: 1: 1.2) A target was used to form a film with a thickness of 100 nm. The IGZO film was formed by controlling the pressure to 0.4 Pa, applying a substrate temperature of 200 ° C., and applying an output of 200 W to the target from a DC power source. The film forming gas flow rate is 30 sccm for O ₂ gas for sample 2A, 30 sccm for O ₂ gas and 0.5 sccm for H ₂ O gas for sample 2B, 30 sccm for O ₂ gas and 1.5 sccm for H ₂ O gas for sample 2C, 2D was O ₂ gas 30 sccm and H ₂ O gas 3.0 sccm. Here, the ratio of the H ₂ O gas in the film formation gas is 0% by volume for sample 2A, 1.67% by volume for sample 2B, 5.0% by volume for sample 2C, and 10.0% by volume for sample 2D. Become.

  The produced samples 2A to 2D were subjected to XRD measurement by an out-of-plane method. FIG. 89 shows the XRD spectra of Sample 2A to Sample 2D. Here, the horizontal axis of FIG. 89 represents the diffraction angle 2θ [degree], and the vertical axis represents the X-ray diffraction intensity (arbitrary unit).

As shown in FIG. 89, the sample 2A has a peak in the vicinity of 2θ = 30 °, but the samples 2B to 2D have no peak in the vicinity of 2θ = 30 °. The peak around 2θ = 30 ° is attributed to the (009) plane of the InGaZnO ₄ crystal. Thus, it can be seen that Sample 2A is a CAAC-OS having c-axis alignment. Note that the peak observed in the vicinity of 2θ = 20 ° in samples 2A to 2D is attributed to the quartz substrate.

As described above, the CAAC-OS is formed in the sample 2A in which the film formation gas does not contain H ₂ O, and the CAAC-OS is formed in the samples 2B to 2D in which the film formation gas contains H ₂ O of 0.5 sccm or more. Not formed. From this, it is predicted that H ₂ O contained in the deposition gas inhibits formation of the CAAC-OS.

Therefore, it is preferable that impurities such as H ₂ O are not included in the gas for forming the IGZO film. For example, H ₂ O contained in the film forming gas is preferably less than 0.5 sccm.

  In this example, results of various measurements performed on the IGZO film formed using the film formation method described in the above embodiment will be described.

In this example, as the samples 3A to 3H, an In—Ga—Zn oxide film was formed over a quartz substrate with a thickness of 100 nm. The IGZO film was formed by controlling the pressure of the film forming gas to 0.4 Pa, applying a substrate temperature of 300 ° C., and applying 200 W output to the target from a DC power source. Samples 3A to 3D have a film formation gas flow rate of O ₂ gas 30 sccm (oxygen 100%), and samples 3E to 3H have film formation gas flow rates of O ₂ gas 10 sccm and Ar gas 20 sccm (oxygen 33%). It was. In this example, deposition was performed using a target in which SiO ₂ was included in an In—Ga—Zn oxide (atomic ratio In: Ga: Zn = 1: 1: 1) as a target. Target sample 3A and Sample 3E is free of SiO _2, the target sample 3B and sample. 3F containing SiO ₂ 0.02 wt%, the target sample 3C and sample 3G, including an SiO ₂ 0.2 wt%, and Sample 3D Sample 3H was formed using a target containing 2% by weight of SiO ₂ .

  XRD measurement by the out-of-plane method was performed on the manufactured samples 3A to 3H. FIG. 90A shows the XRD spectra of Samples 3A to 3D, and FIG. 90B shows the XRD spectra of Samples 3E to 3H. 90A and 90B, the horizontal axis represents the diffraction angle 2θ [degree], and the vertical axis represents the X-ray diffraction intensity (arbitrary unit).

As shown in FIG. 90A, the sample 3A to sample 3C have a peak near 2θ = 30 °, but the sample 3D has no peak near 2θ = 30 °. The peak around 2θ = 30 ° is attributed to the (009) plane of the InGaZnO ₄ crystal. Thus, it can be seen that Samples 3A to 3C are CAAC-OS having c-axis alignment. As shown in FIG. 90B, the sample 3E has a peak in the vicinity of 2θ = 30 °, but the samples 3F to 3H have no peak in the vicinity of 2θ = 30 °. Thus, when the oxygen flow rate during film formation is small, formation of the CAAC-OS is more likely to be hindered. In the samples 3A to 3H, the peak observed near 2θ = 20 ° is attributed to the quartz substrate.

  A cross-sectional TEM image of Sample 3D was taken. FIG. 91 shows a cross-sectional TEM image of Sample 3D. As shown in FIG. 91, the layered crystal is not formed in the sample 3D, and the CAAC-OS is not formed.

Thus, the CAAC-OS is formed in the samples 3A to 3C in which the SiO ₂ contained in the target is 0.2% by weight or less, and the CAAC-OS is formed in the sample 3D in which the SiO ₂ contained in the target is 2% by weight. Was not formed. From this, it is predicted that SiO ₂ contained in the target inhibits formation of CAAC-OS.

Therefore, it is preferable that the target used for forming the IGZO film does not include impurities such as SiO ₂ . For example, SiO ₂ contained in the target may be less than 2% by weight, preferably 0.2% by weight or less, more preferably less than 0.02% by weight.

  In this example, Hall effect measurement was performed on samples 3A to 3D. In addition, the Hall effect measurement was performed using Toyo Technica Co., Ltd. ResiTest8400 series.

FIG. 92 shows Hall mobility obtained by Hall effect measurement of Samples 3A to 3D. In FIG. 92, the vertical axis represents the hole mobility [cm ² / V · s].

As shown in FIG. 92, Sample 3A to Sample 3C have the same hole mobility, but Sample 3D has a lower hole mobility than the others. Here, the hole mobility is 17.90 [cm ² / V · s] for the sample 3A, 18.09 [cm ² / V · s] for the sample 3B, and 18.67 [cm ² / V · s] for the sample 3C. Sample 3D was 12.50 [cm ² / V · s].

In this manner, hole mobility can be improved by preventing the IGZO film from containing SiO ₂ and using the IGZO film as a CAAC-OS.

  In this example, the results of observation of an In—Ga—Zn oxide film (hereinafter referred to as a sample 4) formed over an amorphous silicon oxide film using a TEM or the like will be described.

  Sample 4 is formed using an opposed target sputtering apparatus using an In—Ga—Zn oxide film on a silicon substrate and an In—Ga—Zn oxide (atomic ratio In: Ga: Zn = 1: 1: 1) target. Formed. Note that an amorphous silicon oxide film is formed over the surface of the silicon substrate, and an In—Ga—Zn oxide film is formed thereover. The In—Ga—Zn oxide film was formed by controlling the pressure to 0.4 Pa in an atmosphere containing argon gas 20 sccm and oxygen gas 10 sccm, applying a substrate temperature of 300 ° C., and applying 1000 W output to the target from a DC power source. went.

  A cross-sectional TEM image of the In—Ga—Zn oxide film was observed on the manufactured sample 4. A cross-sectional TEM image of Sample 4 is shown in FIG. In FIG. 93A, IGZO represents an In—Ga—Zn oxide film, and SiO x represents a silicon oxide film.

  As shown in FIG. 93A, a layered crystal region is observed in the In—Ga—Zn oxide film of Sample 4, which indicates that the above-described CAAC-OS is formed. Note that a layered crystal region cannot be observed in the vicinity of an interface between an amorphous silicon oxide film and an In—Ga—Zn oxide film (hereinafter referred to as a region 5000).

  Further, Si and O are detected in the vicinity of the interface of the silicon substrate, the silicon oxide film, and the In—Ga—Zn oxide film of Sample 4 using energy dispersive X-ray spectroscopy (EDX). did. FIG. 93B shows a photograph in which the cross-sectional TEM image shown in FIG. 93A is reduced and the range is expanded, and the Si and O profiles by EDX are aligned with the film thickness of the sample 4. The profile of EDX shown in FIG. 93B has the measurement depth [nm] on the vertical axis and the signal intensity [count] on the horizontal axis.

  As shown in FIG. 93 (B), in the region 5000, as it approaches the Si substrate side, Si increases while O decreases. That is, a mixed layer of silicon oxide and In—Ga—Zn oxide is formed in the region 5000. Accordingly, since a mixed layer of In—Ga—Zn oxide and amorphous silicon is formed at the initial stage of film formation of the In—Ga—Zn oxide, it is assumed that a layered crystal region is not observed in the region 5000. Is done.

  In this example, the results of observation using a TEM or the like of a sample in which an In—Ga—Zn oxide film is formed over a convex portion (hereinafter referred to as a sample 5) will be described.

  FIG. 94A shows an outline of the structure of Sample 5. As illustrated in FIG. 94A, the sample 5 includes a silicon oxynitride film 5010 formed over a silicon substrate and an In—Ga—Zn oxide film 5011 formed over the silicon oxynitride film 5010. And an In—Ga—Zn oxide film 5012 formed over the silicon oxynitride film 5010 and the In—Ga—Zn oxide film 5011. Here, the In—Ga—Zn oxide film 5011 is patterned to form island-shaped protrusions. Hereinafter, a method for manufacturing Sample 5 will be described.

  First, a silicon oxynitride film 5010 was formed on a silicon substrate by a PECVD method with a film thickness of 300 nm. Next, CMP treatment was performed on the silicon oxynitride film 5010.

  Next, an In—Ga—Zn oxide film was formed over the silicon oxynitride film 5010 by a sputtering method. The In—Ga—Zn oxide film includes an oxide film formed with a target of an atomic ratio of In: Ga: Zn = 1: 3: 4 and a thickness of 20 nm, and an atomic ratio on the oxide film. This is a stacked film of oxide films formed to a thickness of 15 nm using a target of In: Ga: Zn = 1: 1: 1. In forming an oxide film using a target having an atomic ratio of In: Ga: Zn = 1: 3: 4, the pressure is controlled to 0.7 Pa in an atmosphere containing argon gas 40 sccm and oxygen gas 5 sccm, and the substrate temperature Was performed by applying an output of 500 W to the target from a DC power source. In addition, in the formation of the oxide film using the target having the atomic ratio In: Ga: Zn = 1: 1: 1, the pressure is controlled to 0.7 Pa in an atmosphere containing 30 sccm of argon gas and 15 sccm of oxygen gas, The substrate temperature was 300 ° C., and an output of 500 W was applied to the target from a DC power source.

  Next, a metal mask made of tungsten was formed over the stacked film of In—Ga—Zn oxide, and an island-shaped In—Ga—Zn oxide film 5011 was formed using a dry etching method.

  Next, an In—Ga—Zn oxide film 5012 was formed over the silicon oxynitride film 5010 and the In—Ga—Zn oxide film 5011 by a sputtering method. The In—Ga—Zn oxide film 5012 was formed using an In—Ga—Zn oxide (atomic ratio In: Ga: Zn = 4: 2: 4.1) target with a thickness of 50 nm. . The In—Ga—Zn oxide film 5012 is formed by controlling the pressure to 0.7 Pa in an atmosphere containing an argon gas of 30 sccm and an oxygen gas of 15 sccm, applying a substrate temperature of 200 ° C. and an output of 500 W to the target from a DC power source. I went.

  With respect to the manufactured sample 5, observation of a cross-sectional TEM image of the In—Ga—Zn oxide film and observation of an electron diffraction pattern were performed. A cross-sectional TEM image of Sample 5 is shown in FIG. Further, enlarged views of regions B1 to B6 in FIG. 94B are shown in FIGS. 94B1 to 94B6. In addition, an enlarged view of a cross-sectional TEM image of Sample 5 is shown in FIG. Further, electron diffraction patterns at points A1 to A4 in FIG. 95A are shown in FIGS. 95A1 to 95A4.

  As shown in FIGS. 94B1 to 94B6, layered crystal regions are observed in the regions B1 to B6 of the In—Ga—Zn oxide film 5011 and the In—Ga—Zn oxide film 5012. Here, the In—Ga—Zn oxide film 5012 is formed using a protruding In—Ga—Zn oxide film 5011 as a base. The regions B4 and B6 are based on the side surface portion of the In—Ga—Zn oxide film 5011, the regions B1 and B3 are based on the curved surface portion of the In—Ga—Zn oxide film 5011, and the region B2 is In—Ga—Zn. The upper surface portion of the oxide film 5011 is used as a base. The layered crystal region of the In—Ga—Zn oxide film 5012 includes the In—Ga—Zn oxide film 5011 and the In—Ga—Zn oxide film 5012 in any of the regions B1, B2, B3, B4, and B6. It is substantially parallel to the surface.

  Therefore, as shown in FIG. 6B of the above-described embodiment, it was shown that the nanoclusters formed on the convex portion were arranged substantially parallel to the convex surface.

  As shown in FIGS. 95A1 to 95A4, clear spot-like patterns appear at points A1 to A4, and spots belonging to the (009) plane were also observed. In addition, at points A1 to A3 of the In—Ga—Zn oxide film 5012, straight lines connecting spots belonging to the (009) plane are In—Ga—Zn oxide film 5011 and In—Ga—Zn oxide. It is substantially perpendicular to the surface of the film 5012.

  From the above, it is estimated that the layered crystal region of the In—Ga—Zn oxide film 5012 is oriented so that the c-axis of the crystal is substantially perpendicular to the surface of the In—Ga—Zn oxide film 5011. The As a result, as shown in the above embodiment, nanoclusters whose c-axis is substantially perpendicular to the base surface are formed on the base film, and the nanoclusters grow laterally and have a layered crystal region. A model in which a physical semiconductor film is formed can be considered.

  In this example, a result of performing polarization XANES (X-ray Absorption Near Edge Structure) measurement on the IGZO film formed by using the film formation method described in the above embodiment mode will be described.

  In this example, as samples 6A to 6C, an IGZO film was formed on an n-type single crystal silicon substrate. In sample 6A, the film thickness of IGZO was aimed at 50 nm, and in sample 6B and sample 6C, the film thickness of IGZO was aimed at 100 nm. In Sample 6A and Sample 6B, a CAAC-OS was formed as an IGZO film, and in Sample 6C, an nc-OS was formed as an IGZO film. Note that the sample 6A was a CAAC-OS having higher crystallinity than the sample 6B.

  The IGZO film used in this example was formed by controlling the pressure of the deposition gas to 0.4 Pa and applying an output of 200 W to the target from a DC power source. In addition, an In—Ga—Zn oxide (atomic ratio: In: Ga: Zn = 1: 1: 1) was used as a target. However, in the sample 6A, in order to form the CAAC-OS film, the film formation gas was set to oxygen gas 30 sccm, and the substrate temperature was set to 300 ° C. In Sample 6B, in order to form a CAAC-OS film, deposition was performed with an argon gas of 20 sccm and an oxygen gas of 10 sccm and a substrate temperature of 300 ° C. In Sample 6C, in order to form an nc-OS film, deposition was performed with a deposition gas of 20 sccm of argon gas and 10 sccm of oxygen gas, and a substrate temperature of room temperature.

  For the produced samples 6A to 6C (hereinafter sometimes abbreviated as samples), polarized XANES measurement, which is a kind of XAS (X-ray Absorption Spectroscopy), was performed, and X-ray absorbance was measured. In the X-ray absorption spectrum obtained by XAS, a steep rise called an absorption edge appears. In the polarization XANES measurement, polarized X-rays in the energy range corresponding to the vicinity of the absorption edge are irradiated, the absorbance at each energy of the X-ray is calculated, and an X-ray absorption spectrum near the absorption edge is obtained.

  The polarized XANES measurement of this example was performed by irradiating synchrotron X-rays with BL-11 at the Ritsumeikan University SR Center. In general, synchrotron radiation provides linearly polarized light whose electric field vector is oriented in the direction of bending electrons. For this reason, the synchrotron X-ray used in this embodiment is linearly polarized light. The energy range of the synchrotron radiation X-ray was set in the vicinity of the K absorption edge of oxygen atoms, specifically 510 eV to 650 eV.

  In this example, XANES measurement was performed by changing the angle of the sample with respect to the electric field vector of the incident X-ray. 96A to 96C show the arrangement of the sample with respect to the incident X-ray. In FIGS. 96A to 96C, the traveling direction of incident X-rays is indicated by a broken line, and the electric field vector of polarized incident X-rays is indicated by a solid line. Further, a normal vector perpendicular to the substrate surface of the sample is shown. In FIG. 96A, the sample is arranged so that the angle formed by the electric field vector of the incident X-ray and the normal vector of the sample (hereinafter sometimes referred to as angle θ) is 90 °. In FIG. 96B, the sample is arranged so that the angle θ = 55 °. In FIG. 96C, the sample is arranged so that the angle θ = 15 °.

  Here, as the angle θ increases, the component of the electric field vector parallel to the IGZO film surface increases, and as the angle θ decreases, the component of the electric field vector perpendicular to the IGZO film surface increases. Therefore, when the IGZO film has c-axis orientation, if the angle θ is large as shown in FIG. 96A, the absorption in response to the electric field oscillating in the ab plane direction is emphasized, as shown in FIG. 96C. If the angle θ is small, the absorption in response to the electric field oscillating in the c-axis direction is emphasized.

  The sample was irradiated with X-rays in the arrangement shown in FIGS. 96A to 96C, and the absorbance of X-rays was calculated using the total electron yield method.

  97A to 97C show X-ray absorption spectra obtained by polarized XANES measurement in samples 6A to 6C. In the X-ray absorption spectra shown in FIGS. 97A to 97C, the horizontal axis represents X-ray energy [eV], and the vertical axis represents normalized absorbance. Note that the energy range of the X-rays illustrated in FIGS. 97A to 97C is 525 eV to 560 eV. Absorbance was normalized by taking 1.0 as an area where the energy of incident X-rays was sufficiently large and no peak near the K absorption edge was observed, excluding background contribution.

  As shown in FIGS. 97A and 97B, in samples 6A and 6B, the absorbance in the vicinity of 530 eV to 540 eV increases as the angle θ increases. On the other hand, in the sample 6C shown in FIG. 97C, the correlation between the angle θ and the absorbance was not observed as much as in the samples 6A and 6B.

  Here, with respect to the absorbance of the peak in the vicinity of 534 eV (hereinafter referred to as the 1st peak) of the X-ray absorption spectra shown in FIGS. 97A to 97C, a relative value where the value of the angle θ = 55 ° is 1.0. 98 (hereinafter referred to as the relative value of the 1st peak absorbance) is shown in FIG. In FIG. 98, the horizontal axis represents the sample angle θ [deg], and the vertical axis represents the relative value of the 1st peak absorbance.

  As shown in FIG. 98, regarding the relative value of the 1st peak absorbance, the sample 6A and the sample 6B showed a clear correlation with the angle θ. On the other hand, in Sample 6C, no clear correlation was found between the angle θ and the relative value of the 1st peak absorbance as in Sample 6A and Sample 6B.

  Thus, in the samples 6A and 6B in which the CAAC-OS is formed, the absorbance near the K absorption edge is large when the angle θ = 90 °, and the absorbance near the K absorption edge is when the angle θ = 15 °. It was small. That is, in the CAAC-OS, it can be said that the absorption in response to the electric field oscillating in the ab plane direction appears stronger than the absorption in response to the electric field oscillating in the c-axis direction. Thus, in CAAC-OS, the possibility that the electronic structure has anisotropy corresponding to the anisotropy of the crystal structure was shown.

  Further, immediately above the K absorption edge of the oxygen atom corresponds to an electron transition from the 1s orbit to the 2p orbit. In general, IGZO is said to be an ionic crystal, and in the ionic crystal, the 2p orbit of oxygen ions should be occupied by electrons. However, in this practical example, an X-ray absorption spectrum corresponding to the electron transition from the 1s orbit to the 2p orbit of the oxygen atom was observed. This suggests that the 2p orbit of the oxygen atom is not completely occupied by electrons, and that a part of the 2p orbit of the oxygen atom is higher than the Fermi level, that is, included in the conduction band. .

  Next, a simulation was performed on the crystal model of the IGZO film, a spectrum corresponding to the polarization XANES measurement was calculated, and compared with the sample according to this example. In order to compare with the crystal model of the IGZO film, a sample 6D obtained by polycrystallizing the IGZO film of the sample 6B and a sample 6E obtained by polycrystallizing the IGZO film of the sample 6C were manufactured.

  Sample 6D was manufactured by forming an IGZO film under the same conditions as Sample 6B and performing heat treatment. Sample 6E was manufactured by forming an IGZO film under the same conditions as Sample 6C and performing heat treatment. Note that the heat treatment of Sample 6D and Sample 6E was performed for 1 hour in an atmosphere of nitrogen 16 L / min and oxygen 4 L / min at a substrate temperature of 800 ° C.

  Sample 6D and sample 6E were subjected to XRD measurement by the out-of-plane method. The XRD spectra of Sample 6D and Sample 6E are shown in FIGS. 99 (A) and 99 (B). Here, the horizontal axis of FIG. 99 represents the diffraction angle 2θ [degree], and the vertical axis represents the X-ray diffraction intensity (arbitrary unit). Furthermore, the diffraction pattern of InGaZnO 4 (ICSD Code 90003) in the inorganic crystal structure database (ICSD) is shown below FIG. 99 (A) and FIG. 99 (B).

  As shown in FIG. 99 (A), in sample 6D, only the peak attributed to the diffraction pattern of the (001) plane (for example, (009) plane) is seen with respect to the intensity ratio of the diffraction pattern of ICSD InGaZnO 4. The peaks of diffraction patterns attributed to other crystal planes are not observed. In sample 6E, the intensity ratio of the diffraction pattern of ICSD InGaZnO4 is different from that of the diffraction pattern of the (001) plane, and the peak attributed to the diffraction pattern of the (001) plane is emphasized. Many are also seen. This suggests that although the sample 6D has higher c-axis orientation than the sample 6E, both are polycrystalline with c-axis orientation.

  Polarized XANES measurement was performed on Sample 6D and Sample 6E under the same conditions as Sample 6A to Sample 6C. 100A and 100B show X-ray absorption spectra obtained by polarized XANES measurement in Sample 6D and Sample 6E. In the X-ray absorption spectra shown in FIGS. 100A and 100B, the horizontal axis represents X-ray energy [eV], and the vertical axis represents normalized absorbance. Note that the energy range of X-rays illustrated in FIGS. 100A and 100B is 525 eV to 545 eV.

  As shown in FIGS. 100A and 100B, in sample 6D and sample 6E, the absorbance at the 1st peak increases as angle θ increases. Thus, also in Sample 6D and Sample 6E, as in Sample 6A and Sample 6B, a correlation was found between angle θ and absorbance at the 1st peak.

  However, under the conditions measured at θ = 15 °, a clear difference was observed in the absorbance and peak position of the peak in the vicinity of 537 to 539 eV (hereinafter referred to as 2nd peak) between Sample 6D and Sample 6E.

Next, the XANES spectrum was calculated using the crystal model of InGaZnO ₄ shown in FIG. The XANES spectrum corresponds to the absorption spectrum when the inner-shell electrons transition to the conduction band.

  Here, the transition probability of the inner shell electron can be regarded as being proportional to the magnitude of the transition dipole moment under the dipole approximation.

The crystal model shown in FIG. 101 is a 112-atom 1nGaZnO ₄ supercell model created for the purpose of reducing the interaction between the inner shell vacancies. For each supercell, an inner shell vacancy (indicated as core hole in FIG. 101) is introduced into the 1s orbit of one oxygen atom. Thus, a spectrum corresponding to the X-ray absorption spectrum shown in FIG. 97 or 100 was calculated by the calculation using the crystal model.

  In the first principle calculation, a density functional program (CASTEP) using a pseudopotential and a plane wave basis was used. The Vanderbuit type ultrasoft pseudopotential is used for the pseudopotential of the atom, but in order to incorporate the effect of the inner vacancies, the pseudopotential obtained by removing electrons from the oxygen 1s orbital was used. In addition, when the pseudopotential method is used, the transition energy cannot be obtained directly. Therefore, isolated atoms were calculated with potentials that reflected the presence or absence of electrons in the 1s orbital of oxygen, and the transition energy was calculated from the difference in total energy. Moreover, PBEsol (Perdew-Burke-Ernzerhof revised for solid) type generalized gradient approximation (GGA) was used for the exchange correlation potential. The cut-off energy was 800 eV. The number of sample k points was 4 × 3 × 3.

  Similarly to the polarization XANES measurement, in this calculation, the lattice vector of the crystal model was set so as to correspond to the incident X-ray angle θ = 0 °, 15 °, 55 °, or 90 °.

  A spectrum obtained by the calculation of the crystal model is shown in FIG. In the spectrum illustrated in FIG. 102A, the horizontal axis represents transition energy [eV], and the vertical axis represents normalized absorbance. Note that the transition energy range illustrated in FIG. 102A is 525 eV to 545 eV. Further, the absorbance is normalized by a value around 545 eV.

  In the spectrum shown in FIG. 102A, there is a correlation between the relative value of the absorbance of the first peak and the angle θ, and the X-ray absorption spectrum of the sample 6D (FIG. 100A) can be reproduced well. As shown in FIG. 101, there is structural anisotropy in the c-axis direction and ab-plane direction of the crystal model. Therefore, the fact that the spectrum shown in FIG. 102A is obtained means that the c-axis orientation is high. The spectrum shown in FIG. 102A can reproduce well the polarization XANES spectrum of the sample 6D. Therefore, it was confirmed that Sample 6D has c-axis orientation.

  In addition, it was confirmed whether the X-ray absorption spectrum of the sample 6E having low c-axis orientation can be reproduced by correcting the spectrum of the crystal model in consideration of the orientation distribution. In the calculation of the spectrum shown in FIG. 102 (A), the spectrum was calculated at each incident X-ray angle with respect to a completely oriented crystal model. On the other hand, the calculation result of the crystal model was corrected by giving a distribution in the c-axis direction of the crystal. Here, the distribution in the c-axis direction was set so as to follow a Gaussian distribution with an average inclination of 0 ° (equal to the case of complete orientation).

  A spectrum obtained by calculation corrected in consideration of the orientation distribution is shown in FIG. The spectrum illustrated in FIG. 102B has transition energy [eV] on the horizontal axis and normalized absorbance on the vertical axis. Note that the transition energy range illustrated in FIG. 102B is 525 eV to 545 eV. Further, the absorbance is normalized by a value around 545 eV.

  In the spectrum shown in FIG. 102B, the absorbance of the 2nd peak at θ = 15 ° is smaller than the spectrum shown in FIG. 102A, and the X-ray absorption spectrum of the sample 6E (FIG. 100B) is obtained. Qualitatively reproduced. Thus, by the calculation corrected in consideration of the orientation distribution, the spectrum of the crystal model could be made closer to the X-ray absorption spectrum of the sample 6E.

  In addition, in the X-ray absorption spectra of the samples 6A and 6B, that is, the CAAC-OS, a correlation is observed between the absorbance of the first peak and the angle θ, similarly to the X-ray absorption spectra of the samples 6D and 6E. From this, it was suggested that Sample 6A and Sample 6B also have c-axis orientation.

  In this example, the results of measuring the Hall effect by forming an In—Ga—Zn oxide film using PESP or VDSP described in the above embodiment and changing the carrier density by heat treatment will be described. To do.

  First, a method for manufacturing Samples 7A, 7B, 7C, 7D, 7E, 7F, 7G, 7H, and 7J used in this example will be described. Samples 7A, 7B, 7C, 7D, and 7E are samples in which an In—Ga—Zn oxide film is formed using PESP, and Samples 7F, 7G, 7H, and 7J are In—Ga— using VDSP. This is a sample in which a Zn oxide film is formed.

  In samples 7A, 7B, 7C, 7D, and 7E, a film was formed on a quartz substrate by a parallel plate sputtering apparatus using an In—Ga—Zn oxide (atomic ratio In: Ga: Zn = 1: 1: 1) target. An In—Ga—Zn oxide film with a thickness of about 100 nm was formed. The In—Ga—Zn oxide film was formed by controlling the pressure to 0.4 Pa in an atmosphere containing argon gas 20 sccm and oxygen gas 10 sccm, applying a substrate temperature of 300 ° C. and an output of 200 W from the DC power source to the target. went.

  In Samples 7F, 7G, 7H, and 7J, a quartz substrate was formed with a film thickness of 100 nm by an opposed target sputtering apparatus using an In—Ga—Zn oxide (atomic ratio In: Ga: Zn = 1: 1: 1) target. About In-Ga-Zn oxide film was formed. The In—Ga—Zn oxide film was formed by controlling the pressure to 0.4 Pa in an atmosphere containing argon gas 20 sccm and oxygen gas 10 sccm, applying a substrate temperature of 200 ° C., and applying 1000 W output to the target from a DC power source. went.

  Next, the samples 7A, 7B, 7C, 7D, 7E, 7F, 7G, 7H, and 7J were heat-treated under different conditions. Samples 7A and 7F were heat-treated in a nitrogen atmosphere for 1 hour at a substrate temperature of 450 ° C. Samples 7B, 7C, 7D, 7E, 7G, 7H, and 7J were heat-treated in a nitrogen atmosphere for 1 hour at a substrate temperature of 450 ° C., and further heat-treated in an oxygen atmosphere for 1 hour.

Further, Samples 7C, 7D, 7E, 7H, and 7J were heat-treated for 1 hour at a pressure of 133 Pa in a hydrogen atmosphere (H ₂ gas flow rate 500 sccm) using a CVD apparatus. The heat treatment temperatures were 200 ° C. for sample 7C, 250 ° C. for sample 7D, 350 ° C. for sample 7E, 150 ° C. for sample 7H, and 300 ° C. for sample 7J.

  As described above, by performing heat treatment in a nitrogen atmosphere and then performing heat treatment in an oxygen atmosphere, oxygen was supplied to the In—Ga—Zn oxide in the sample, and oxygen vacancies were reduced to reduce the carrier density. . Further, by performing heat treatment in a hydrogen atmosphere, hydrogen was supplied to the In—Ga—Zn oxide in the sample, and the defect level density was increased to increase the carrier density.

  Hall effect measurement was performed on the manufactured samples 7A, 7B, 7C, 7D, 7E, 7F, 7G, 7H, and 7J, and the carrier density and the hole mobility were evaluated. In addition, the Hall effect measurement was performed using Toyo Technica Co., Ltd. ResiTest8400 series.

Table 6 shows the carrier density and the Hall mobility of each sample obtained by the Hall effect measurement. Further, FIG. 103 shows the correlation between the hole mobility and the carrier density of each sample. In FIG. 103, the vertical axis represents the hole mobility [cm ² / V · s], and the horizontal axis represents the carrier density [1 / cm ³ ]. Further, FIG. 103 shows approximate curves for a sample manufactured by PESP and a sample manufactured by VDSP, respectively.

  As shown in FIG. 103, the carrier density and the hole mobility showed a positive correlation in both the sample manufactured by PESP and the sample manufactured by VDSP. A sample manufactured by PESP has a high carrier density dependence on hole mobility. When the carrier density is high, the hole mobility is also high, but the hole mobility is also reduced as the carrier density is reduced.

  On the other hand, the sample produced with VDSP has a low carrier density dependence on the hole mobility, and is higher than the sample with the same carrier density produced with PESP in the range where the carrier density is low. Has hole mobility.

  As described in the above embodiment, the CAAC-OS is an oxide semiconductor with few impurities and oxygen vacancies and low carrier density. From the above results, it is suggested that when a CAAC-OS film is formed using a VDSP, a transistor using the CAAC-OS with a low carrier density also has a relatively high mobility. Thus, by forming a CAAC-OS film using VDSP, the transistor using the CAAC-OS film as an active layer can improve the S value and the on-state current.

20 Nanocluster 21 Ion 22 Horizontal growth portion 23 Particle 25 Cleaved surface 26 Region 27 Connection portion 32 Substrate 33 Target 34 Plasma 35a Flat portion 35b Convex portion 100 Capacitance element 101 Capacitance element 102 Capacitance element 105 Capacitance element 110 Insulator 112 Insulator 112 Conductor 112a Conductor 112b Conductor 114 Insulator 116 Conductor 122 Conductor 124 Conductor 130 Insulator 132 Insulator 134 Insulator 150 Insulator 200 Transistor 201 Transistor 202 Transistor 205 Conductor 205a Conductor 205A Conductor 205b Conductor 205B Conductor 210 Insulator 212 Insulator 213 Insulator 214 Insulator 216 Insulator 218 Conductor 220 Insulator 222 Insulator 224 Insulator 230 Oxide 230a Oxide 230A Oxide 230b Oxide 230B Oxidation 230c oxide 230d oxide 240a conductor 240A conductive film 240b conductor 240B conductive layer 241a conductor 241b conductor 244 conductor 245 barrier layer 250 insulator 260 conductor 260a conductor 260A conductor 260A conductor 260c conductor 270 insulator Body 280 insulator 282 insulator 283 insulator 284 insulator 285 insulator 286 insulator 290 resist mask 292 resist mask 294 resist mask 296 resist mask 300 transistor 301 transistor 302 transistor 311 substrate 312 semiconductor region 314 insulator 316 conductor 318a low Resistance region 318b Low resistance region 320 Insulator 322 Insulator 324 Insulator 326 Insulator 328 Conductor 330 Conductor 350 Insulator 352 Insulator 354 Insulator 356 Conductor 358 Insulator 400 Semiconductor device 401 CPU core 402 Power controller 403 Power switch 404 Cache 405 Bus interface 406 Debug interface 407 Controller 408 PC
409 Pipeline register 410 Pipeline register 411 ALU
412 register file 421 power management unit 422 peripheral circuit 423 data bus 500 semiconductor device 501 memory circuit 502 memory circuit 503 memory circuit 504 circuit 509 transistor 510 transistor 512 transistor 513 transistor 515 transistor 517 transistor 518 transistor 519 capacitor element 520 capacitor element 540 wiring 541 Wiring 542 Wiring 543 Wiring 544 Wiring 600 Target 600a Target 600b Target 601 Film forming chamber 610 Backing plate 610a Backing plate 610b Backing plate 620 Target holder 620a Target holder 620b Target holder 622 Target shield 623 Target shield 630 Magnet unit 6 0a Magnet unit 630b Magnet unit 630N Magnet 630N1 Magnet 630N2 Magnet 630S Magnet 632 Magnet holder 640 Plasma 642 Member 660 Substrate 670 Substrate holder 680a Magnetic field line 680b Magnetic field line 690 Power supply 691 Power source 711 Substrate 712 Circuit area 713 Separation area 714 Separation line 715 752 Printed circuit board 754 Mounting board 755 Lead 800 Inverter 810 OS transistor 820 OS transistor 831 Signal waveform 832 Signal waveform 840 Broken line 841 Solid line 850 OS transistor 860 CMOS inverter 900 Semiconductor device 901 Power supply circuit 902 Circuit 903 Voltage generation circuit 903A Voltage generation circuit 903B Voltage Generation circuit 903C Voltage generation circuit 9 3D voltage generation circuit 903E voltage generation circuit 904 circuit 905 voltage generation circuit 905A voltage generation circuit 905E voltage generation circuit 906 circuit 911 transistor 912 transistor 912A transistor 912B transistor 921 control circuit 922 transistor 1901 casing 1902 casing 1903 display section 1904 display section 1905 Microphone 1906 Speaker 1907 Operation key 1908 Stylus 1911 Case 1912 Case 1913 Display unit 1914 Display unit 1915 Connection unit 1916 Operation key 1921 Case 1922 Display unit 1923 Keyboard 1924 Pointing device 1931 Case 1932 Refrigeration room door 1933 Freezer compartment door 1941 Case 1942 Case 1943 Display unit 1944 Operation key 1945 Lens 1946 Connection unit 19 1 Car body 1952 Wheel 1953 Dashboard 1954 Light 2200 Imaging device 2201 Switch 2202 Switch 2203 Switch 2210 Pixel unit 2211 Pixel 2212 Subpixel 2212B Subpixel 2212G Subpixel 2212R Subpixel 2220 Photoelectric conversion element 2230 Pixel circuit 2231 Wiring 2247 Wiring 2248 Wiring 2249 Wiring 2250 wiring 2253 wiring 2254 filter 2254B filter 2254G filter 2254R filter 2255 lens 2256 light 2257 wiring 2260 peripheral circuit 2270 peripheral circuit 2280 peripheral circuit 2291 light source 2300 silicon substrate 2310 layer 2320 layer 2330 layer 2340 layer 2351 transistor 2352 transistor 2353 transistor 2360 Photodio 2361 Anode 2363 Low resistance region 2370 Plug 2371 Wiring 2372 Wiring 2373 Wiring 2379 Insulator 2380 Insulator 2390 Insulator 2390a Conductor 2390b Conductor 2390c Conductor 2390d Conductor 2390e Conductor 2700 Film formation apparatus 2701 Atmosphere side substrate supply chamber 2702 Atmosphere side substrate transfer chamber 2703a Load lock chamber 2703b Unload lock chamber 2704 Transfer chamber 2705 Substrate heating chamber 2706a Film formation chamber 2706b Film formation chamber 2706c Film formation chamber 2751 Cryo trap 2752 Stage 2761 Cassette port 2762 Alignment port 2863 Transfer robot 2764 Gate valve 2765 Heating stage 2766 Target 2766a Target 2766b Target 2767 Target shield 276 7a Target shield 2767b Target shield 2768 Substrate holder 2769 Substrate 2770 Vacuum pump 2771 Cryo pump 2772 Turbo molecular pump 2780 Mass flow controller 2781 Refiner 2784 Gas heating mechanism 2784 Variable member 2790a Magnet unit 2790b Magnet unit 2791 Power supply 3001 Wiring 3002 Wiring 3003 Wiring 3004 Wiring 3005 wiring 3006 wiring 3200 transistor 3500 transistor 4001 wiring 4003 wiring 4005 wiring 4006 wiring 4007 wiring 4008 wiring 4009 wiring 4021 layer 4023 layer 4100 transistor 4200 transistor 4300 transistor 4400 transistor 4500 capacitor element 4600 capacitor element 5000 region 5010 Silicon nitride film 5011 In-Ga-Zn oxide film 5012 In-Ga-Zn oxide film

Claims (9)

A method of forming an oxide by sputtering using a film formation chamber, a target disposed in the film formation chamber, and a substrate,
Heating the substrate;
After supplying a film formation gas containing oxygen or / and a rare gas to the film formation chamber, a plasma having ions of the film formation gas in the vicinity of the target by applying a potential difference between the target and the substrate. Produces
The ions of the deposition gas are accelerated toward the target by the potential difference,
The accelerated ions of the deposition gas bombard the target, so that the atoms constituting the target and the aggregate of atoms constituting the target are separated from the target,
The atoms and the aggregates of the atoms are deposited on the substrate, cause migration by heating the substrate, and form a plurality of plate-like clusters,
In the region between one of the plurality of plate-like clusters and another one of the plurality of plate-like clusters, the atoms and the aggregate of the atoms enter,
The atoms and the aggregates of the atoms grow laterally in a region between the plate-like clusters, so that one of the plurality of plate-like clusters and another of the plurality of plate-like clusters are separated. A connecting portion is formed between
A manufacturing method of an oxide, wherein a crystal structure having a strain is formed in the connecting portion. In claim 1,
A method for producing an oxide, characterized in that the flat clusters are stacked to form a thin film structure. In claim 1,
The method for producing an oxide, wherein silicon oxide contained in the target is less than 2% by weight. In claim 1,
The method for producing an oxide, wherein water molecules contained in the deposition gas is 0.5 sccm or less. In claim 1,
A method for producing an oxide, characterized in that no other flat cluster is formed in a region between one of the plurality of flat clusters and another one of the plurality of flat clusters. . In claim 1,
The target includes indium, zinc, an element M (the element M is aluminum, gallium, yttrium, or tin) and oxygen, and a method for manufacturing an oxide. In claim 6,
The method for producing an oxide, wherein the target is a target of a mixture including indium oxide, an oxide of element M, and zinc oxide. In claim 6,
The flat cluster has a layer formed of the element M, the zinc, and the oxygen formed on a surface thereof. In claim 1,
The method for producing an oxide, wherein the flat cluster has a surface perpendicular to the c-axis.

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