JPWO2017110495A1 - Thin film transistor manufacturing method - Google Patents

Abstract

It is an object of the present invention to provide a TFT manufacturing method that provides a TFT in which element isolation is realized by a simpler method, a TFT manufactured by the manufacturing method, and an electronic device including the TFT. The ink containing a solvent capable of dissolving or dispersing the semiconductor material forming the semiconductor layer as an essential component is printed using an elastomer blanket or an elastomer plate, and the channel region is a non-image area. The problem is solved by printing on the semiconductor layer so that the boundary of the image portion forms a closed curve surrounding the outer periphery of the channel region.

Description

The present invention relates to a method for manufacturing a thin film transistor (TFT).

Thin film transistors (TFTs) using amorphous silicon or polycrystalline silicon as a semiconductor material are widely used as switching elements in liquid crystal display devices and organic EL display devices. However, since TFTs using such silicon have a high temperature heat treatment process in their production, they cannot be developed for next-generation flexible display devices that use plastic substrates due to heat resistance problems. In order to solve this problem, an organic thin film transistor (organic TFT) in which an organic semiconductor material is used for a semiconductor layer instead of silicon has been proposed.

Organic semiconductor materials can be formed into ink at a low temperature, so it can be applied to plastic substrates with poor heat resistance, can be applied to flexible display devices, and flexible electronics (lightweight electronic tags and sensors) Application to flexible electronic devices) is expected.

In addition, as for the organic semiconductor material, in terms of semiconductor characteristics, the development of a new material makes it possible to provide a semiconductor that surpasses the mobility of amorphous silicon.

For example, Patent Document 1 discloses that a compound having a dinaphtho [2,3-b: 2 ′, 3′-f] thieno [3,2-b] thiophene skeleton is 4.0 cm ² / Vs in a vacuum-deposited thin film. Patent Document 2 shows that a V-shaped compound compound having various substituents has a high mobility of 11 cm ² / Vs in a single crystal thin film formed by an edge casting method. However, in Non-Patent Document 1, 2,7-dioctyl [1] benzothieno [3,2-b] [1] benzothiophene (hereinafter sometimes abbreviated as 2,7-dioctyl BTBT) is double. Single crystal thin film produced by ink jet printing method with large variation in characteristics and high mobility of 30 cm ² / Vs at maximum. Patent Document 3 discloses naphthodithiol having a phenyl group as a substituent. It is disclosed that the phenoxy compound exhibits a mobility of 0.7 cm ² / Vs. As described above, there are a number of reports on organic semiconductor materials exhibiting semiconductor characteristics exceeding the mobility (0.5 cm ² / Vs) of amorphous silicon.

On the other hand, for practical use of organic TFTs, not only the improvement of mobility, but also element isolation (the semiconductor layer of any one TFT is sometimes referred to as electrical wiring around the TFT (hereinafter abbreviated as wiring)), It is necessary to establish a technology that is electrically separated (insulated) from the electrodes around the TFT, the semiconductor layers of other TFTs adjacent to the TFT, and the electrodes of other TFTs adjacent to the TFT. is there. Electronic devices using TFTs are usually composed of two or more TFTs, other electronic elements, wiring, electrodes, and other various conductor parts. And leakage current flows between adjacent TFTs, between the semiconductor layer and the gate electrode, between the semiconductor layer and the wiring, and as a result, the ON / OFF ratio etc. deteriorates. For example, when applied to a display device, the image display quality is impaired. It will be.

As a method for element separation, there is a method of patterning a semiconductor layer by an ink jet printing method (Patent Document 4), a dispensing method, or a drop casting method. However, these printing methods require extra steps such as forming a hydrophilic / hydrophobic pattern on the lower layer surface and forming partition walls before printing in order to suppress spreading of the ink after landing. . In addition, it has been pointed out that the characteristics of low molecular organic semiconductors vary when formed by these printing methods.
Another method is to apply a semiconductor layer once wider than the channel region, and then inactivate the semiconductor layer outside the channel region using light, heat, oxidant, plasma, resin, solvent, etc. (Patent Documents 5 to 12). However, these methods usually require that the protective layer be formed wider than the semiconductor layer before the deactivation step, which complicates the process and increases costs.

International Publication No. 2012/115236 International Publication No. 2013/125599 International Publication No. 2010/058692 JP 2012-043926 A Special table 2008-519445 Japanese Patent Laid-Open No. 08-018125 JP 2014-013912 A JP 2012-222203 A JP 2008-277381 A JP 2008-270494 A JP 2006-179855 A JP 2012-256784 A

Nature, 2011, 475, 364

The present invention has been made in view of the above problems, and aims to provide a TFT in which element isolation is realized by a simpler manufacturing method.

In order to achieve the above object, the present inventor has made extensive studies and uses an ink containing an essential component of a solvent that can dissolve or disperse a semiconductor material forming a semiconductor layer. An overcoat layer formed by using a printing method using a plate of the above, and the overcoat layer was isolated in an element configuration having a contact portion in contact with the semiconductor layer around the outer periphery of the channel region The present inventors have found that a TFT can be easily provided and have completed the present invention.

That is, in the present invention,
1. A gate electrode, a gate insulating layer, a source electrode and a drain electrode;
A semiconductor layer formed in a range wider than the channel region;
An overcoat layer formed after the semiconductor layer is formed, and a method for producing a thin film transistor,
The overcoat layer is formed so as to surround the periphery of the outer periphery of the channel region, and has a contact portion that contacts the semiconductor layer,
In the contact portion, the semiconductor layer is laminated as a lower layer and the overcoat layer is an upper layer,
The overcoat layer is formed by a printing method using an ink whose essential component is a solvent capable of dissolving or dispersing the semiconductor material forming the semiconductor layer,
The printing method is a printing method using an elastomeric blanket or an elastomeric plate, and has a step of transferring ink on the elastomeric blanket or the elastomeric plate onto a substrate. is there,
A method of manufacturing a thin film transistor,
2. 1. The semiconductor layer is a semiconductor layer made of an organic semiconductor material. A method for producing the thin film transistor according to claim 1,
3. 1. The method for forming the semiconductor layer is a vacuum deposition method. Or 2. A method for producing the thin film transistor according to claim 1,
4). 1. The method for forming the semiconductor layer is a wet film formation method. Or 2. A method for producing the thin film transistor according to claim 1,
5. The printing method is a letterpress reverse printing method. To 4. A method for producing the thin film transistor according to any one of the above,
6). The method for producing a thin film transistor according to any one of 1 to 4, wherein the printing method is a microcontact printing method,
7). The printing method is a gravure offset printing method. To 4. A method for producing the thin film transistor according to any one of the above,
I will provide a.

By using the manufacturing method according to the present invention, a device-isolated TFT can be easily provided. As a result, a TFT having a high ON / OFF ratio can be easily provided.

It is a conceptual sectional view of a bottom gate bottom contact (BGBC) type TFT. It is a conceptual sectional view of a bottom gate top contact (BGTC) type TFT. It is a conceptual sectional view of a top gate bottom contact (TGBC) type TFT. It is a conceptual sectional view of a top gate top contact (TGTC) type TFT. It is a schematic plan view which shows an example of a source electrode shape, a drain electrode shape, and a channel region shape. It is the schematic which shows an example of the positional relationship of a channel area | region and a "contact part." It is the schematic of BGBC type TFT manufactured by applying the manufacturing method of the present invention. The upper figure is a plan view. The lower figure is a sectional view taken along the line ab in the upper figure. It is the schematic of the BGTC type TFT manufactured by applying the manufacturing method of the present invention. The upper figure is a plan view. The lower figure is a sectional view taken along the line ab in the upper figure. It is the schematic of the BGTC type TFT manufactured by applying the manufacturing method of the present invention. The upper figure is a plan view. The lower figure is a sectional view taken along the line ab in the upper figure. It is the schematic of the BGTC type TFT manufactured by applying the manufacturing method of the present invention. The upper figure is a plan view. The lower figure is a sectional view taken along the line ab in the upper figure. It is the schematic of BGBC type TFT manufactured by applying the manufacturing method of the present invention. The upper figure is a plan view. The lower figure is a sectional view taken along the line ab in the upper figure. FIG. 6 is a schematic diagram illustrating an example of a positional relationship between a channel region and a “contact part” and a shape of a “contact part” in an electronic device including four TFTs. FIG. 6 is a schematic diagram illustrating an example of a positional relationship between a channel region and a “contact part” and a shape of a “contact part” in an electronic device including four TFTs. It is the schematic of BGBC type TFT manufactured by applying the manufacturing method of the present invention. The upper figure is a plan view. The lower figure is a sectional view taken along the line ab in the upper figure. It is the schematic of the BGTC type TFT manufactured by applying the manufacturing method of the present invention. The upper figure is a plan view. The lower figure is a sectional view taken along the line ab in the upper figure. It is the schematic of BGBC type TFT manufactured by applying the manufacturing method of the present invention. The upper figure is a plan view. The lower figure is a sectional view taken along the line ab in the upper figure.

Hereinafter, the present invention will be described in detail with reference to the drawings. In addition, this invention is not limited to the form mentioned later. The postscript form is an exemplification, and the present invention has any configuration substantially the same as the technical idea described in the claims of the present invention and exhibits the same function and effect. Is included in the technical scope.
(Configuration of TFT)
First, a basic configuration of a TFT that is an object of the manufacturing method of the present invention will be described.
A TFT is an electronic element having a gate electrode, a gate insulating layer, a source electrode, a drain electrode, and a semiconductor layer as essential elements, and various element configurations are possible depending on the arrangement of each electrode and each layer (for example, “ The configuration of the TFT manufactured by the manufacturing method of the present invention is not particularly limited as long as it is a known and conventional configuration, such as the configuration described in “Basics of Material Science No. 6 Basics of Organic Transistors (Aldrich)”. For example, bottom gate bottom contact (BGBC) type (FIG. 1), bottom gate top contact (BGTC) type (FIG. 2), top gate bottom contact (TGBC) type (FIG. 3), top gate top contact (TGTC) type (FIG. 4) etc. can be mentioned. In the figure, 1 is a substrate, 2 is a gate electrode, 3 is a gate insulating layer, 4 is a semiconductor layer, 5 is a source electrode, and 6 is a drain electrode.
The constituent elements of the TFT manufactured by the TFT manufacturing method of the present invention need only have at least a substrate, a gate electrode, a gate insulating layer, a semiconductor layer, a source electrode, and a drain electrode. As other components, a semiconductor protective layer, a sealing layer, a light shielding layer, a primary layer, a planarization layer, and the like may be included.

(substrate)
The substrate material is not particularly limited as long as it can be processed into a plate shape, a sheet shape, a film shape, etc.
silicon;
Inorganic glass such as quartz glass, soda glass, borosilicate glass, alkali-free glass;
Cellulose acetate propionate (CAP), cellulose triacetate (TAC), polyarylate, polyimide, polyethylene, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyetherimide, polyetheretherketone, polyethersulfone (PES) And resins and polymer compounds such as polycarbonate (PC), polycycloolefin, polystyrene, polypropylene, polyphenylene sulfide, and polymethyl methacrylate (PMMA).
Among them, from the viewpoint of improving the productivity of TFT, an inorganic substrate such as a glass plate or a silicon wafer is preferable, and from the viewpoint of obtaining a flexible TFT, a glass sheet, a resin sheet, a plastic film, or the like is preferable. In addition to flexibility, a resin sheet or a plastic film is preferable from the viewpoint of reducing weight and improving portability and impact resistance.

(electrode)
The material for the gate electrode, the source electrode, and the drain electrode is not particularly limited as long as it is a conductive material, and examples thereof include inorganic conductive materials and organic conductive materials. Examples of inorganic conductive materials include lithium, beryllium, carbon, sodium, magnesium, aluminum, silicon, potassium, calcium, scandium, titanium, chromium, manganese, iron, nickel, copper, zinc, gallium, zirconium, niobium, Molybdenum, silver, tin, antimony, hafnium, tungsten, platinum, gold, graphite, glassy carbon, tin oxide, tin-doped indium oxide (ITO), fluorine-doped zinc oxide, sodium-potassium alloy, molybdenum-tantalum alloy, magnesium-copper mixture , Magnesium-silver mixture, magnesium-aluminum mixture, magnesium-indium mixture, lithium-aluminum mixture, silver-silver oxide mixture, aluminum-aluminum oxide mixture, doped silicon It can include a carbon paste, silver paste, silver ink, nanosilver, copper paste, a copper ink, nano copper. On the other hand, examples of the organic conductive material include conductive polyaniline, conductive polyaniline derivative, conductive polypyrrole, conductive polypyrrole derivative, conductive polythiophene, conductive polythiophene derivative, polyethylenedioxythiophene and polystyrenesulfonic acid complex ( PEDOT-PSS) and other known and commonly used conductive polymers whose electrical conductivity has been improved by doping;
Charge transfer complexes such as tetrathiafulvalene-tetracyanoquinodimethane complex; and the like.

Each electrode may be made of one type of conductive material or may be made of two or more types of conductive material. In the case of two or more types, they may be mixed and used. Further, the same conductive material may be used for the gate electrode, the source electrode, and the drain electrode, and different conductive materials may be used for the respective electrodes.

The thickness of the electrode is appropriately determined within a range in which a desired electrical conductivity can be achieved, depending on the type of conductive material used to form the electrode, and is usually in the range of 1 nm to 1 μm. Preferably, it is in the range of 10 nm to 200 nm, more preferably in the range of 20 nm to 100 nm.

The shapes of the source electrode and the drain electrode are not particularly limited as long as they are formed so as to oppose each other with a substantially constant interval (corresponding to a channel length (L) described later). FIG. 5 shows an example of an embodiment of the shape pattern. In FIG. 5, reference numeral 8 denotes a portion corresponding to the “fixed interval”, and the length of this portion corresponds to the channel length (L).

The length between the source electrode and the drain electrode (the length of the “constant interval” portion = the channel length (L)) is usually preferably in the range of 0.1 μm to 1 mm, preferably 0.5 μm to 200 μm. The range is more preferable, and the range of 1 μm to 100 μm is more preferable.

Here, the channel region will be described. As described above, the source electrode and the drain electrode are formed so as to oppose each other with a substantially constant interval, and a region provided between the two electrodes separated by this constant interval is a channel. It becomes an area. Therefore, the channel region has a shape corresponding to the shape of the source electrode and the drain electrode, and can be formed in various shapes as long as the channel region is sandwiched between the source electrode and the drain electrode at a constant interval. In FIG. 5, a region where a vertical line pattern is drawn corresponds to this (region indicated by reference numeral 7 in the drawing), and FIG. 5 shows an example of the embodiment. 5 (a) and 5 (b) show a channel region (simple rectangular shape) surrounded by a straight line, and FIG. 5 (c) shows that the source electrode and the drain electrode are arranged in a comb shape and are separated on a plane. A plurality of “unit channel regions” are combined to form one channel region, and FIG. 5D illustrates a channel region surrounded by a curve.

As a method for forming the electrode, a known and conventional method as described in “Basics of Material Science No. 6 Basics of Organic Transistors (Aldrich)” can be given, and a desired pattern shape and a desired thickness can be used. As long as it is a method capable of forming an electrode, it is not particularly limited. For example,
First, using a wet film formation method or a dry film formation method, a conductive film is once formed over a wide range (or a conductive film is formed over the entire surface), and then a resist is formed on the conductive film. A method of patterning a film by photolithography or printing, and then etching using the resist film pattern as a mask;
A method of patterning a resist by photolithography or printing, and then forming a conductive film over a wide area and removing the resist film (lift-off method);
Using a wet film formation method or a dry film formation method, a conductive film is once formed over a wide range (or a conductive film is formed over the entire surface), and then the conductive film is not passed through a mask. Patterning by laser ablation (dry etching);
A direct patterning method using a dry film formation method through a mask;
Examples thereof include a method of directly patterning using a printing method using a conductive film forming ink as a material.

Examples of the dry film forming method include chemical vapor deposition (CVD) methods such as plasma CVD, thermal CVD, and laser CVD; physical vapor deposition (PVD) methods such as vacuum deposition, sputtering, and ion plating; Etc.
Examples of the wet film forming method include an electrolytic plating method, an immersion plating method, an electroless plating method, a sol-gel method, an organometallic decomposition (MOD) method, a coating method, and a printing method.
Examples of the coating method include an ESD (Electro Spray Deposition) method, an ESDUS (Evaporative Spray Deposition from Ultra-dilution Solution) method, an air doctor coat method, an air knife coat method, an edge cast method, an impregnation coat method, a kiss coat method, , Squeeze coating method, spin coating method, slit coating method, electrostatic coating method, electrostatic spray coating method, die coating method, ultrasonic spray coating method, supercritical spray method, dispensing method, dip coating method, doctor blade coating method, Transfer roll coat method, drop cast method, bar coat method, blade coat method, reverse coat method, roll coat method, wire bar coat method, etc.
Examples of the printing method include an inkjet printing method, an offset printing method, a gravure printing method, a gravure offset printing method, a screen printing method, a dispensing method, a letterpress printing method, a letterpress reverse printing method, a drop cast method, a flexographic printing method, and a planographic printing method. And a microcontact printing method.

Among these, from the viewpoint of reducing the manufacturing cost, a method using a wet film forming method that eliminates the need for a vacuum environment is preferable, and among the wet film forming methods, a method using a printing method with a small number of steps is more preferable.

(Gate insulation layer)
The gate insulating layer has a function of electrically insulating the gate electrode and the source electrode, the gate electrode and the drain electrode, and the gate electrode and the semiconductor layer. Accordingly, the material of the gate insulating layer is not particularly limited as long as it is an electrically insulating material. For example, cyanoethyl pullulan, cellulose acetate propionate (CAP), cellulose triacetate (TAC), Teflon (registered trademark) ), Polyarylate, polyimide, polyester, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyetherimide, polyetheretherketone, polyethersulfone (PES), polyvinylidene chloride, polyvinyl chloride, polycarbonate (PC) ), Polycycloolefin, polystyrene and polystyrene derivatives, polyparaxylylene derivatives (for example, Parylene series manufactured by Japan Parylene), polyvinyl alcohol, polyvinylphenol, polypheny Sulfide, polymethyl methacrylate (PMMA), acrylic resin, amorphous fluororesin (for example, Cyto series made by Asahi Glass), alkyd resin, urethane resin, epoxy resin, electron beam curable resin (for example, electron beam curable acrylic resin) And electron beam curable methacrylic resins), phenoxy resins, phenol resins, fluororesins, unsaturated polyester resins, polyimide resins, polyvinylphenol resins, melamine resins, UV curable resins (for example, UV curable acrylic resins and UV curable resins). Polymer compounds such as methacrylic resin);
Inorganic compounds such as Al ₂ O ₃ , SiO ₂ , Ba _x Sr _(1-x) TiO ₃ , BaTi _x Zr _(1-x) O ₃ ;

Note that the gate insulating layer may be made of one type of insulating material or may be made of two or more types of insulating material. Further, it may contain a reaction (polymerization) initiator, a crosslinking agent, a crosslinking auxiliary agent and the like.
When it consists of two or more types of insulating materials, each insulating material may be simply mixed and the covalent bond may be formed between insulating materials. Furthermore, when a reaction (polymerization) initiator, a crosslinking agent, and a crosslinking auxiliary agent are included, these materials and the insulating material may be simply mixed, and a covalent bond is formed between these materials. Also good.
The thickness of the gate insulating layer is appropriately determined within a range in which a desired insulating property can be achieved, depending on the type of insulating material used to form the gate insulating layer, and is usually 10 nm to 5 μm. It is preferable that it is the range of these.

A method for forming the gate insulating layer is not particularly limited as long as a film or a layer that can electrically insulate between the gate electrode and the source electrode, between the gate electrode and the drain electrode, and between the gate electrode and the semiconductor layer can be formed. For example, known dry film forming methods and wet film forming methods can be used.

Examples of the dry film forming method include chemical vapor deposition (CVD) methods such as plasma CVD, thermal CVD, and laser CVD; physical vapor deposition (PVD) such as vacuum deposition, sputtering, and ion plating; The
Examples of the wet film forming method include an electrolytic plating method, an immersion plating method, an electroless plating method, a sol-gel method, an organometallic decomposition (MOD) method, a coating method, and a printing method.
Examples of the coating method include an ESD (Electro Spray Deposition) method, an ESDUS (Evaporative Spray Deposition from Ultra-dilution Solution) method, an air doctor coat method, an air knife coat method, an edge cast method, an impregnation coat method, a kiss coat method, , Squeeze coating method, spin coating method, slit coating method, electrostatic coating method, electrostatic spray coating method, die coating method, ultrasonic spray coating method, supercritical spray method, dispensing method, dip coating method, doctor blade coating method, Transfer roll coat method, drop cast method, bar coat method, blade coat method, reverse coat method, roll coat method, wire bar coat method, etc.
Examples of the printing method include an inkjet printing method, an offset printing method, a gravure printing method, a gravure offset printing method, a screen printing method, a dispensing method, a letterpress printing method, a letterpress reverse printing method, a drop cast method, a flexographic printing method, and a planographic printing method. And a microcontact printing method.

Among these, from the viewpoint of reducing manufacturing costs, a method using a wet film forming method that eliminates the need for a vacuum environment is preferable.
If patterning is required, patterning can be performed by the same method as described in the section “Electrodes”.

(Semiconductor layer)
The material for the semiconductor layer is not particularly limited as long as it is a material capable of forming a semiconductor layer having semiconductor characteristics, and a known and commonly used semiconductor material can be used. Examples of such semiconductor materials include π-conjugated organic low molecular compounds, π-conjugated organic polymer compounds, organic silicon compounds, organic dye materials, organic pigment materials, and organic dye materials.

Specifically, “Basics of Materials Science No. 1 Basics of Organic EL Element and its Manufacturing Technology (Aldrich)”, “Basics of Materials Science No. 6 Basics of Organic Transistors (Aldrich)”, “Material Materials” Organic semiconductor materials described in “No. 2 Organic Electronics (Aldrich)”, “Material Maters No. 4 Organic and Molecular Electronics (Aldrich)”, etc. For example, tetracene and its derivatives, rubrene, chrysene and chrysene derivatives, pyrene and pyrene derivatives, triphenylene and triphenylene derivatives, pentacene and pentacene derivatives (for example, 6,13-bis (triisopropylsilylethynyl) pentacene, etc. Realkylsilylethynyl substituted pentacene), picene and picene derivatives, coronene and coronene derivatives, benzodithiophene derivatives, naphthodithiophene derivatives, anthradithiophene derivatives, benzothienobenzothiophene derivatives, dinaphthothiophene derivatives, dithienobenzodithiophene derivatives , Dinaphthothienothiophene derivatives, phthalocyanine derivatives, porphyrazine derivatives, oligothiophenes (eg 4T, 5T, 6T) and oligothiophene derivatives, perylenetetracarboxylic diimide and perylenetetracarboxylic diimide derivatives, perylenetetracarboxylic acid anhydride and Perylenetetracarboxylic acid anhydride derivatives, naphthalenetetracarboxylic acid diimide and naphthalenetetracarboxylic acid diimide Examples of π-conjugated organic polymer compounds such as polypyrrole and poly (N-substituted pyrrole) include amide derivatives, naphthalenetetracarboxylic acid anhydride, naphthalenetetracarboxylic acid anhydride derivatives, benzobis (thiadiazole) derivatives, fullerene derivatives, and the like. Polypyrrole derivatives such as poly (3-substituted pyrrole) and poly (3,4-disubstituted pyrrole); polythiophene, poly (3-substituted thiophene), poly (3,4-disubstituted thiophene), polybenzothiophene and the like Polythiophene derivatives; polyisothianaphthene derivatives such as polyisothianaphthene; polythienylene vinylene derivatives such as polythienylene vinylene; poly (p-phenylene vinylene) derivatives such as poly (p-phenylene vinylene); polyaniline, poly (N -Place Polyaniline derivatives such as aniline; polyacetylene derivatives such as polyacetylene and polydiacetylene; polyazulene derivatives such as polyazulene; thiophene, thiophene derivatives, thienothiophene, thienothiophene derivatives, diketopyrrolopyrrole, diketopyrrolopyrrole derivatives, indico And the like. Note that the semiconductor layer may be made of one kind of semiconductor material or may be made of two or more kinds of semiconductor materials. Moreover, the well-known and usual high molecular compound may be included. Such a polymer compound is not particularly limited as long as it does not significantly reduce the semiconductor characteristics of the semiconductor layer by mixing. For example, polystyrene, polystyrene derivatives (for example, poly-α-methylstyrene) , Polymethyl methacrylate, polyvinyl carbazole, polytriallylamine, and the like.

The thickness of the semiconductor layer is appropriately determined within a range in which desired semiconductor characteristics can be achieved, depending on the type of semiconductor material used for forming the semiconductor layer, and is usually in the range of 0.5 nm to 1 μm. Preferably, the range is from 5 nm to 500 nm, and more preferably from 10 nm to 300 nm.

As a method for forming the semiconductor layer, a method in which the semiconductor layer can be formed so as to cover the channel region (that is, a method in which the semiconductor layer can be formed in a range including the channel region and wider than the channel region). There is no particular limitation as long as it is present, and examples thereof include publicly known dry film forming methods and wet film forming methods.

Examples of the dry film forming method include chemical vapor deposition (CVD) methods such as plasma CVD, thermal CVD, and laser CVD; physical vapor deposition (PVD) such as vacuum deposition, sputtering, and ion plating; The
Examples of the wet film forming method include an electrolytic plating method, an immersion plating method, an electroless plating method, a sol-gel method, an organometallic decomposition (MOD) method, a coating method, and a printing method.
Examples of the coating method include an ESD (Electro Spray Deposition) method, an ESDUS (Evaporative Spray Deposition from Ultra-dilution Solution) method, an air doctor coat method, an air knife coat method, an edge cast method, an impregnation coat method, a kiss coat method, , Squeeze coating method, spin coating method, slit coating method, electrostatic coating method, electrostatic spray coating method, die coating method, ultrasonic spray coating method, supercritical spray method, dispensing method, dip coating method, doctor blade coating method, Transfer roll coat method, drop cast method, bar coat method, blade coat method, reverse coat method, roll coat method, wire bar coat method, etc.
Examples of the printing method include an inkjet printing method, an offset printing method, a gravure printing method, a gravure offset printing method, a screen printing method, a dispensing method, a letterpress printing method, a letterpress reverse printing method, a drop cast method, a flexographic printing method, and a planographic printing method. And a microcontact printing method.

Among these, from the viewpoint of reducing manufacturing costs, a method using a wet film forming method that eliminates the need for a vacuum environment is preferable. On the other hand, from the viewpoint of obtaining a homogeneous film or layer, a dry film forming method or a method using a coating method is preferable. Among them, a vacuum evaporation method, a spin coating method, which can easily form a homogeneous film over a wide range. A method using an edge casting method, a blade coating method, or a dip coating method is more preferable.

In forming the semiconductor layer, annealing may be performed after the film is formed as described above for the purpose of increasing the crystallinity of the semiconductor material and improving the semiconductor characteristics. The annealing temperature is preferably in the range of 50 ° C. to 200 ° C., more preferably in the range of 70 ° C. to 200 ° C., and the annealing time is preferably in the range of 10 minutes to 12 hours. More preferably, it is in the range of 10 hours, more preferably in the range of 30 minutes to 10 hours.

(Overcoat layer)
The TFT using the manufacturing method of the present invention has an overcoat layer, and the overcoat layer is formed around the outer peripheral edge of the channel region so as to surround the channel region and is in contact with the semiconductor layer. It has a contact portion, and the contact layer is laminated so that the semiconductor layer is the lower layer and the overcoat layer is the upper layer. Further, the overcoat layer is formed by a process subsequent to the semiconductor layer forming process.
First, the contact portion will be described with reference to a plan view (FIG. 6). The contact portion is a portion where the overcoat layer contacts the semiconductor layer around the outer periphery of the channel region. The “outer periphery of the channel region” corresponds to reference numeral 12 (dotted line) in FIG. 6, and “around the outer periphery of the channel region” refers to a portion surrounding the channel region (reference numeral 7), that is, reference numeral 12 (dotted line). It corresponds to the area outside. Specifically, as shown in FIGS. 6 (a) to 6 (d), the contact portion (symbol 10) may surround the outer periphery of the outer peripheral edge of the channel region, or FIG. 6 (e). As shown in FIG. 6, the channel region may be surrounded by the outer periphery.
Since the edge (reference numeral 11) on the channel region side of the contact portion is a shape surrounding the channel region, it is a closed straight line or curve, for example, as shown in FIGS. 6 (a), (c) to (e) Moreover, the rectangular shape comprised by a straight line may be sufficient and it may be comprised by the curve as shown in FIG.6 (b). The form of the contact portion on the plan view is not particularly limited as long as it surrounds the outer periphery of the outer peripheral edge (reference numeral 12) of the channel region (reference numeral 7). For example, FIG. It may be surrounded by a straight line (a dashed-dotted line of reference numeral 11) as shown in (c) to (e), or may be surrounded by a curved line (a dashed-dotted line of reference numeral 11) as shown in FIG. 6 (b).
Note that the channel regions in FIGS. 6A, 6B, and 6E correspond to FIGS. 5A and 5B, and the channel region in FIG. The channel region in FIG. 6D corresponds to the channel region in FIG. 5D.
As described above, an electronic device using TFTs is usually composed of two or more TFTs. 12 and 13 are schematic views showing an example of the positional relationship between the channel region and the “contact portion” and the shape of the “contact portion” in an electronic device composed of four TFTs. Symbols 7a, 7b, 7c and 7d in the figure indicate the channel regions of the four TFTs. As shown in FIGS. 12 and 13, the contact portion (reference numeral 10) only needs to be formed so as to surround the outer peripheral edge (reference numeral 12) of each channel region of each TFT, and is formed in a linear shape having a width. It may be formed (FIG. 13 (a)), and may be formed in the entire region outside the channel region with respect to the edge (reference numeral 11) of the contact portion (FIG. 12 (a), FIG. 13 (b). )), A region where no contact portion is formed may be formed in the contact portion region (FIG. 12B).

Next, the overcoat layer will be described. The overcoat layer is formed by a method described later in a step after the semiconductor layer forming step, and has the contact portion that contacts the semiconductor layer around the outer peripheral edge of the channel region. In the contact portion, the semiconductor layer is The layer is not particularly limited as long as it is a lower layer and is laminated so that the overcoat layer is an upper layer. Next, specific examples thereof will be described with reference to FIGS. 7 to 11. However, these forms are merely examples and do not limit the overcoat layer of the present invention.
7A and 7B are diagrams in which the manufacturing method of the present invention is applied to a BGBC type TFT. The upper diagram is a plan view, and the lower diagram is a cross-sectional view taken along the line ab in FIG. The overcoat layer (symbol 15) is in contact with the semiconductor layer (symbol 4) via the contact portion (symbol 10) around the outer periphery (symbol 12) of the channel region, and the overcoat layer is a semiconductor layer at the contact portion. It is an upper layer.
FIG. 8 is a diagram in which the manufacturing method of the present invention is applied to a BGTC type TFT, with the upper diagram being a plan view and the lower diagram being a cross-sectional view taken along the line ab of FIG. The overcoat layer (symbol 15) is in contact with the semiconductor layer (symbol 4) via the contact portion (symbol 10) around the outer periphery (symbol 12) of the channel region, and the overcoat layer is a semiconductor layer at the contact portion. It is an upper layer.
FIG. 9 is a diagram in which the manufacturing method of the present invention is applied to a BGTC type TFT. The overcoat layer (symbol 15) is in contact with the semiconductor layer (symbol 4) via the contact portion (symbol 10) around the outer periphery (symbol 12) of the channel region, and the overcoat layer is a semiconductor layer at the contact portion. It is an upper layer. A difference from the TFT of FIG. 8 is that the overcoat layer is formed after the formation of the source electrode and the drain electrode and has a portion that becomes an upper layer of the source electrode and the drain electrode.
10A and 10B are diagrams in which the manufacturing method of the present invention is applied to a BGTC type TFT. The upper diagram is a plan view, and the lower diagram is a cross-sectional view taken along the line ab in the upper diagram. The overcoat layer (symbol 15) is in contact with the semiconductor layer (symbol 4) via the contact portion (symbol 10) around the outer periphery (symbol 12) of the channel region, and the overcoat layer is a semiconductor layer at the contact portion. It is an upper layer. The difference from the TFT of FIG. 9 is that the overcoat layer is formed before the source electrode and the drain electrode are formed, and the source electrode and the drain electrode have a portion that is an upper layer of the overcoat layer.
FIG. 11 is a diagram in which the manufacturing method of the present invention is applied to a BGBC type TFT. The overcoat layer (symbol 15) is in contact with the semiconductor layer (symbol 4) via the contact portion (symbol 10) around the outer periphery of the channel region, and the overcoat layer is overlaid on the semiconductor layer at the contact portion. ing. A difference from the TFT of FIG. 7 is that the overcoat layer is formed after the formation of the semiconductor protective layer formed after the formation of the semiconductor layer, and therefore, a part thereof has a portion to be an upper layer of the semiconductor protective layer.
Next, a method for forming the overcoat layer will be described. The overcoat layer is formed by a printing method using an elastomer blanket or an elastomer plate, using an ink whose essential component is a solvent capable of dissolving or dispersing the semiconductor material forming the semiconductor layer. Is.

First, the ink will be described (hereinafter abbreviated as the present ink). This ink is an ink containing, as an essential component, a solvent capable of dissolving or dispersing the semiconductor material forming the semiconductor layer.
Here, the solvent that can dissolve or disperse the semiconductor material will be described. The solvent is “a mixture of a semiconductor material forming a semiconductor layer and a concentration of 10 ⁻⁸ mol / L or more in an approximate solvent to prepare a mixed solution of the approximate solvent and the semiconductor material, Using this mixed solution as a sample, a commercially available ultraviolet-visible absorption spectrum spectrophotometer (for example, Hitachi High-Tech Science spectrophotometer U-3900, JASCO V-700 series, Shimadzu UV-2600 / 2700, etc.) The solvent can detect the absorption spectrum of the semiconductor material.

Such a solvent is appropriately selected according to the type of the semiconductor material. For example, ethoxyethyl propionate (EEP), isopropyl acetate, ethyl acetate, normal propyl acetate, propylene carbonate, propylene glycol monomethyl Ester solvents such as ether acetate (PGMAc) and 3-methoxy-3-methyl-butyl acetate;
Methanol, ethanol, 1-propanol, 2-propanol, 1-butanol, 2-methyl-1-butanol, 3-methoxy-3-methyl-1-butanol, 1,3-butanediol, 1-pentanol, 4- Alcohol-based solvents such as methyl-2-pentanol, 1-hexanol, cyclohexanol, industrial higher alcohols (for example, Diadol series manufactured by Mitsubishi Chemical);
Hydrocarbon solvents such as pentane, n-hexane, hexane, cyclohexane, methylcyclohexane, n-octane, n-decane, toluene, xylene;
Benzene, toluene, cumene, n-propylbenzene, n-butylbenzene, n-pentylbenzene, o-xylene, m-xylene, p-xylene, p-cymene, 1,4-diethylbenzene, mesitylene, 1,3,5 -Triethylbenzene, anisole, 2-methylanisole, 3-methylanisole, 4-methylanisole, 2,5-dimethylanisole, 1,3-dimethoxybenzene, 3,5-dimethoxytoluene, 2,4-dimethylanisole, phenetole , Methyl benzoate, ethyl benzoate, propyl benzoate, butyl benzoate, chlorobenzene, o-dichlorobenzene, trichlorobenzene, tetralin, 1,5-dimethyltetralin, 1-methylnaphthalene, industrial aromatic solvents (for example, ExxonMobil Solvesso 10 , Aromatic solvents such as such as Solvesso 150);

Tetrahydrofuran, 2-methyltetrahydrofuran, dioxane, ethylene glycol diethyl ether (monoglyme), diglyme, triglyme, ethylene glycol monomethyl ether (cellosolve), ethyl cellosolve, propiocellosolve, butyrocellosolve, phenylcellosolve, diethylene glycol methyl ether, diethylene glycol ethyl ether , Diethylene glycol propyl ether, diethylene glycol butyl ether, benzyl ethyl ether, ethyl phenyl ether, diphenyl ether, methyl-t-butyl ether, cyclopentyl methyl ether, cyclohexyl methyl ether benzonitryl propylene glycol monomethyl ether, propylene glycol monoethyl ether, pro Glycol monopropyl ether, propylene glycol tertiary butyl ether, dipropylene glycol monomethyl ether, ethylene glycol butyl ether, ethylene glycol ethyl ether, ethylene glycol methyl ether, diethylene glycol butyl ether, ether solvents such as diethylene glycol ethyl ether;
Ketone solvents such as acetone, methyl ethyl ketone, cyclohexanone, 2-hexanone, 2-heptanone, 3-heptanone, acetophenone, propiophenone, butyrophenone, cyclohexanone;
And aprotic polar solvents such as N, N-dimethylformamide, dimethyl sulfoxide, diethylformamide, N-methyl-2-pyrrolidone, and the like.

In addition, the solvent used for this ink may be one type, and may be two or more types. In addition, the ink may contain a solvent that does not satisfy this requirement as long as it contains the “solvent capable of dissolving or dispersing the semiconductor material”.

The concentration of the “solvent capable of dissolving or dispersing the semiconductor material” in the ink is not particularly limited as long as it is within the range in which the above “effect of the invention” can be achieved. A range of 00% by mass is preferred.

The ink may contain, as other components, a polymer compound, a resin, a constitutional component, a surfactant, a release agent, and the like. These components are added as necessary to impart printability and film-forming properties (film-forming ability) to the ink.

The polymer compound or resin is not particularly limited as long as it is a known and commonly used insulating polymer compound or insulating resin. For example, cyanoethyl pullulan, cellulose acetate propionate (CAP), cellulose triacetate (TAC) , Teflon (registered trademark), polyarylate, polyimide, polyester, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyetherimide, polyetheretherketone, polyethersulfone (PES), polyvinylidene chloride, polyvinyl chloride , Polycarbonate (PC), polycycloolefin, polystyrene and polystyrene derivatives, polyparaxylylene derivatives (for example, Parylene series manufactured by Japan Parylene), polyvinyl alcohol, polyvinylphenol Polyphenylene sulfide, polymethyl methacrylate (PMMA), acrylic resin, amorphous fluororesin (for example, Cytop series manufactured by Asahi Glass), alkyd resin, urethane resin, epoxy resin, electron beam curable resin (for example, electron beam curable acrylic resin) And electron beam curable methacrylic resins), phenoxy resins, phenol resins, fluororesins, unsaturated polyester resins, polyimide resins, polyvinylphenol resins, melamine resins, UV curable resins (for example, UV curable acrylic resins and UV curable resins). High molecular compounds such as methacrylic resin).
In addition, the polymer compound and resin used for this ink may be one type, and may be two or more types.
The concentration of the polymer compound or resin in the ink is not particularly limited as long as it is within a range where the above-mentioned “effect of the invention” can be achieved, and it is usually preferably in the range of 1 to 10% by mass. Is more preferably in the range of 7 to 7% by mass.

The constitutional component is not particularly limited as long as it is a well-known and commonly used electrically insulating inorganic fine particle or a well-known and commonly used electrically insulating pigment. For example, Evonik Japan Aerosil series, Fuji Silysia Chemical silica Materials (Silicia, Silo Hobic, Silo Pute, Silopage, Silo Pure, Syrosphere, Silo Mask, Silwell, Fuji Balloon, etc.), Nissan Chemical Industries colloidal materials (PMA-ST, IPA-ST, etc.), BIC Chemie colloidal materials Inorganic fine particles such as (NANOBIC3600 series, NANOBIC3800 series, etc.);
And pigments such as pigment materials made by DIC (EXCEDIC BLUE0565, EXCEDIC RED0759, EXCEDIC YELLOW 0599, EXCEDIC GREEN0358, EXCEDIC YELLOW0648, etc.). The constitutional component used in the ink may be one type or two or more types.
The concentration of the constitutional component in the ink is not particularly limited as long as it is within the range in which the above-mentioned “effect of the invention” can be achieved.

The surfactant is not particularly limited as long as it is a known and commonly used electrically insulating surfactant. For example, a hydrocarbon surfactant, a silicone surfactant, a fluorine surfactant, and the like are used. I can give you. Among these, fluorine-based surfactants having a linear perfluoroalkyl group and a chain length of C6 or more (for example, DIC MegaFuck series) are preferable. The surfactant used in the ink may be one type or two or more types.
The concentration of the surfactant in the ink is not particularly limited as long as it is within the range in which the above-mentioned “effect of the invention” can be achieved, and is usually in the range of 0.01 to 5.00% by mass of the active ingredient. Preferably, the active ingredient is in the range of 0.05 to 1.0% by mass.

The release agent is not particularly limited as long as it is a known and commonly used electrically insulating silicone compound. For example, dimethyl silicone oil, dimethyl silicone rubber, silicone resin, organically modified silicone oil, methyl phenyl silicone oil Long chain alkyl-modified silicone oils, mixtures of fluorine compounds and silicone polymers, fluorine-modified silicones, and the like. Among these, Kyoeisha Chemical's granol series and Shin-Etsu Chemical KF-96L series are preferable from the viewpoint of releasability and compatibility with the resin. In addition, the release agent used for this ink may be one type, and may be two or more types. Further, the concentration of the release agent in the ink is not particularly limited as long as it is within the range in which the above-mentioned “effect of the invention” can be achieved, and is usually in the range of 0.0 to 5.0% by mass as an active ingredient. The active ingredient is preferably in the range of 0.0 to 3.0% by mass.

In addition, the present ink can appropriately contain a leveling agent, a dispersant, an antifoaming agent and the like as optional components.

The ink may contain at least a “solvent capable of dissolving or dispersing a semiconductor material”. From the viewpoint of improving printability and film-forming properties, “the solvent capable of dissolving or dispersing a semiconductor material”. “, A resin and a surfactant, and more preferably“ a solvent capable of dissolving or dispersing a semiconductor material ”, a resin, a surfactant, a release agent, and a constitutional component. The mixing ratio of the constituent components in the ink is appropriately determined within a range in which the “effect of the invention” can be achieved.

The method of mixing the constituent components in producing the present ink is not particularly limited as long as a homogeneous ink can be provided. For example, heat treatment, stirring treatment, dispersion stirring treatment, dispersion homogenizing treatment, Known and commonly used dispersion methods such as sonication treatment, ultrasonic stirring treatment, ultrasonic homogenization treatment, ultrasonic dispersion treatment, and laser irradiation treatment, a mixing method, and a stirring method can be used.

Next, a printing method (hereinafter abbreviated as the present printing method) for forming the overcoat layer will be described. This printing method is a printing method using the present ink and using an elastomeric blanket or an elastomeric plate, and transferring ink on the elastomeric blanket or the elastomeric plate onto the substrate. There is a printing method having a step of:

This printing method is a printing method using an elastomeric blanket or an elastomeric plate, and has a step of transferring ink on the elastomeric blanket or the elastomeric plate onto a substrate. If it is, it will not specifically limit.
Among these, as a printing method using an elastomeric blanket, a letterpress reverse printing method, a gravure offset printing method, and the like are exemplified, and as a printing method using an elastomer plate, a micro contact printing (μCP) method is exemplified. Can do.
The letterpress reversal printing method (for example, “Advanced Electronic Materials, 2015, Vol. 1, page 1001435”) describes that an ink is applied to a blanket having a smooth release surface made of an elastomer, By pressing the relief printing plate on the ink application surface, removing the ink portion in contact with the relief printing plate from the blanket surface, and pressing the ink on the remaining blanket against the printed material such as a substrate, the remaining pattern (said This is a method of transferring a negative pattern of a relief pattern.
The gravure offset printing method is to transfer an intaglio pattern by filling an intaglio with ink, transferring the filled ink to a blanket made of an elastomer, and then pressing the ink on the blanket against a printed material such as a substrate. Is the method.
The microcontact printing method (for example, “Details are described in“ Journal of the Japan Printing Society, 2009, Vol. 46, page 2 ”) means that an ink is applied to a relief printing plate made of an elastomer, and the relief printing plate made of this elastomer. Is a method of transferring ink on a relief printing plate (pressing pattern) by pressing the substrate onto a printed material such as a substrate.
Examples of the elastomer include acrylonitrile butadiene rubber, ethylene propylene copolymer rubber, epichlorohydrin ethylene oxide copolymer rubber, chloroprene rubber, silicone rubber, polyurethane, polyester, polyepichlorohydrin rubber, butadiene rubber, and the like. Is preferred.
Examples of the silicone rubber material include polydimethylsiloxane and copolymers thereof, fluorine group-containing polydimethylsiloxane and copolymers thereof, polyvinylmethylsiloxane, and polyphenylmethylsiloxane.
Among the printing methods, when a fine shape is required for printing the overcoat layer, a relief printing method and a micro contact printing method, which are excellent in fine printing, are preferable.

  The overcoat layer forming step may be a step subsequent to the formation of the semiconductor layer so as to form the contact portion in time series, and may be a step subsequent to the formation of the semiconductor layer (see FIG. 7). After forming the layer, it may be a step after forming the electrode (see FIG. 9), or after forming the semiconductor layer and after forming the semiconductor protective layer (see FIG. 11), the semiconductor layer was formed. It may be a step after the electrode is formed and the semiconductor protective layer is further formed.

Next, the element isolation mechanism in the present invention will be described with reference to FIGS.
7 to 11, the upper diagram is a plan view, and the lower diagram is a cross-sectional view taken along the line ab of the upper diagram. The overcoat layer (symbol 15) is in contact with the semiconductor layer (symbol 4) via the contact portion (symbol 10) around the outer periphery (symbol 12) of the channel region, and the overcoat layer is a semiconductor layer at the contact portion. It is an upper layer.

Therefore, the region (reference numeral 14) in the semiconductor layer immediately below the contact portion (reference numeral 10) is penetrated (acted) by the solvent that dissolves or disperses the semiconductor material contained in the ink from the upper overcoat layer. As a result, the semiconductor characteristics of the region indicated by reference numeral 14 in the semiconductor layer are deteriorated. The mechanism of the deterioration is not necessarily clear, but the crystal size of the semiconductor material constituting the semiconductor layer is altered by the action of the solvent in the region indicated by reference numeral 14. This is considered to be caused by phenomena such as a decrease in the thickness of the semiconductor layer, a change in the morphology of the semiconductor layer, and a discontinuity in the semiconductor layer.

The region in which the semiconductor characteristics thus deteriorated is a region immediately below the contact portion, and is generated so as to surround the channel region as shown in the upper diagrams of FIGS. Therefore, the channel region is in a state of being substantially electrically insulated from other regions, and an element isolation effect can be obtained.

Here, the difference between the case where the overcoat layer is printed by a publicly known printing method and the case where the overcoat layer is printed by the printing method “via an elastomeric blanket or an elastomeric plate” of the present invention will be described.
When the overcoat layer is printed by a known and commonly used printing method, the solvent in the overcoat layer may permeate to the channel region through the contact portion and may deteriorate the semiconductor characteristics of the channel region (for example, comparison described later). Example 4).
On the other hand, according to the present invention, in the process in which the present ink is transferred and printed through an elastomer blanket or an elastomer plate, the ink is once transferred onto the elastomer blanket or the elastomer plate. At this time, the solvent in the ink liquid film is partially absorbed by the elastomer, so that the ink liquid film is semi-dried and then transferred and printed. Therefore, the use of the printing method “through an elastomeric blanket or an elastomeric plate”, which is a feature of the present invention, uses other known printing methods in which the amount of solvent in the overcoat layer immediately after printing is known. It is extremely small compared to the case. For this reason, as described above, the semiconductor characteristics of the channel region are not deteriorated by printing the overcoat layer in the present invention.

In order to more efficiently form the “region where the semiconductor characteristics are deteriorated” represented by reference numeral 14 in the semiconductor layer, heat treatment may be performed after performing this step. The heating temperature is not particularly limited as long as it does not impair the effect of element isolation, and is preferably in the range of 30 to 200 ° C, and more preferably in the range of 40 to 150 ° C.

(Semiconductor protective layer)
The TFT manufactured by the manufacturing method of the present invention may have a semiconductor protective layer so as to cover the semiconductor layer channel region in order to prevent deterioration of the semiconductor layer (for example, FIG. 11 and FIG. 16). ).
The material of the semiconductor protective layer is not particularly limited as long as it does not significantly reduce the electrical properties of the semiconductor layer. For example, cyanoethyl pullulan, cellulose acetate propionate (CAP), cellulose triacetate (TAC), Teflon (Registered trademark), polyarylate, polyimide, polyester, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyetherimide, polyetheretherketone, polyethersulfone (PES), polyvinylidene chloride, polyvinyl chloride, polyvinyl chloride Carbonate (PC), polycycloolefin, polystyrene and polystyrene derivatives, polyparaxylylene derivatives (for example, Parylene series manufactured by Japan Parylene), polyvinyl alcohol, polyvinyl phenol , Polyphenylene sulfide, polymethylmethacrylate (PMMA), acrylic resin, amorphous fluororesin (for example, Cytop series made by Asahi Glass), alkyd resin, urethane resin, epoxy resin, electron beam curable resin (for example, electron beam curable acrylic) Resin, electron beam curable methacrylic resin), phenoxy resin, phenol resin, fluororesin, unsaturated polyester resin, polyimide resin, polyvinylphenol resin, melamine resin, UV curable resin (for example, UV curable acrylic resin, UV Polymer compounds such as curable methacrylic resins;
Inorganic compounds such as Al ₂ O ₃ , SiO ₂ , Ba _x Sr _(1-x) TiO ₃ , BaTi _x Zr _(1-x) O ₃ ;
Among these, Teflon (registered trademark), polyparaxylylene derivative, polyvinyl alcohol, amorphous fluororesin, fluororesin, polyimide having a substituent having a fluorine atom, and acrylic resin having a substituent having a fluorine atom are preferable.

The semiconductor protective layer may be made of one kind of material or may be made of two or more kinds of materials. Further, it may contain a reaction (polymerization) initiator, a crosslinking agent, a crosslinking auxiliary agent and the like.
When it consists of two or more types of materials, each material may be simply mixed and the covalent bond may be formed between materials. Furthermore, when a reaction (polymerization) initiator, a crosslinking agent, and a crosslinking auxiliary agent are included, these materials and the material may be simply mixed, or a covalent bond may be formed between these materials. Good.
The thickness of the semiconductor protective layer is appropriately determined within a range where desired performance can be achieved, depending on the type of insulating material used, and is usually preferably in the range of 10 nm to 5 μm.

The method for forming the semiconductor protective layer is not particularly limited as long as the desired performance can be achieved, and examples thereof include known and commonly used dry film forming methods and wet film forming methods.

Examples of the dry film forming method include chemical vapor deposition (CVD) methods such as plasma CVD, thermal CVD, and laser CVD; physical vapor deposition (PVD) such as vacuum deposition, sputtering, and ion plating; The
Examples of the wet film forming method include an electrolytic plating method, an immersion plating method, an electroless plating method, a sol-gel method, an organometallic decomposition (MOD) method, a coating method, and a printing method.
Examples of the coating method include an ESD (Electro Spray Deposition) method, an ESDUS (Evaporative Spray Deposition from Ultra-dilution Solution) method, an air doctor coat method, an air knife coat method, an edge cast method, an impregnation coat method, a kiss coat method, , Squeeze coating method, spin coating method, slit coating method, electrostatic coating method, electrostatic spray coating method, die coating method, ultrasonic spray coating method, supercritical spray method, dispensing method, dip coating method, doctor blade coating method, Transfer roll coat method, drop cast method, bar coat method, blade coat method, reverse coat method, roll coat method, wire bar coat method, etc.
Examples of the printing method include an inkjet printing method, an offset printing method, a gravure printing method, a gravure offset printing method, a screen printing method, a dispensing method, a letterpress printing method, a letterpress reverse printing method, a drop cast method, a flexographic printing method, and a planographic printing method. And a microcontact printing method.

If patterning is required, patterning can be performed by the same method as described in the section “Electrodes”.

Hereinafter, the present invention will be described in detail with reference to examples. In addition, this invention is not limited to the Example mentioned later. The examples described later are merely examples, and the present invention has the same configuration as that of the technical idea described in the claims of the present invention, and has the same functions and effects as those described above. It is included in the technical scope of the invention.

Example 1
A case where the manufacturing method of the present invention is applied to manufacturing an integrated TFT (electronic device) in which 10 BGBC type TFTs are arranged in a grid pattern in a substrate will be described with reference to FIG. FIG. 14 is a schematic view of four TFTs that are adjacent to each other, out of 10 TFTs arranged in a grid pattern.

<Gate electrode, gate insulating layer, and source and drain electrode formation process>
On the glass substrate (symbol 1), aluminum was formed to a thickness of 30 nm by a vacuum deposition method using a metal mask to form a gate electrode (symbol 2). Here, using a parylene vapor deposition apparatus (Nippon Parylene Lab Coater PDS2010), dichloro-diparaxylylene (Japan Parylene DPX-C) is used as a raw material, and the gate insulating layer made of polyparachloroxylylene (Parylene C) is thick. A film was formed with a thickness of 500 nm (reference 3), and a source and drain electrode made of a gold thin film was patterned with a thickness of 40 nm by a vacuum deposition method using a metal mask (reference 5 and reference 6). Note that the distance between the source electrode and the drain electrode (channel length (L)) (symbol 8) was 75 μm, and the channel width (W) was 5 mm. Next, the substrate thus obtained was immersed in a 0.1% by mass ethanol solution of pentafluorothiophenol for 1 hour and then dried by nitrogen blowing.

<Semiconductor layer formation process>
On the gate insulating layer so as to cover the source and drain electrodes, pentacene obtained by repeating sublimation purification three times is used as a raw material, and a semiconductor layer made of pentacene is formed to a thickness of 30 nm by vacuum deposition. A solid (entire) film was formed (reference 4).

<Overcoat layer formation process>
The ink used in this process is p-xylene (0.32 g) as a “solvent capable of dissolving or dispersing a semiconductor material”, Maruka Linker M (0.23 g) manufactured by Maruzen Petrochemical as a resin, and Nissan Chemical as a constitutional component. Industrial PMA-ST (3.76 g), Shin-Etsu Chemical silicone oil KF96L-1cs (0.23 g) as a release agent, DIC TF-1303 (0.12 g) as a surfactant, and propylene as another solvent Prepared by mixing carbonate (0.60 g), propylene glycol monomethyl ether (2.41 g) as the other solvent, and isopropyl acetate (1.97 g) as the other solvent. Next, the ink thus adjusted is printed on the semiconductor layer by a reverse printing method so that the channel region becomes a non-image portion (portion where the overcoat layer is not printed) (reference numeral 15). An overcoat layer (reference numeral 15) was formed to a thickness of 500 nm. In addition, regarding the pattern shape of the overcoat layer, the non-image portion (the portion where the overcoat layer is not printed) is a rectangular shape having a side length of 10 mm (that is, the image portion (the portion where the overcoat layer is printed) The periphery of the outer periphery of the channel region is surrounded by a rectangular shape having a side length (reference numeral 17) of 10 mm, while the interval between the non-image portions (reference numeral 18) is 10 mm.

<Semiconductor characteristics (mobility and ON / OFF ratio) and mobility variation evaluation>
With respect to the TFT obtained in this manner, the mobility was measured by applying a voltage (V _g ) to the gate electrode using a digital multimeter (SMU237 manufactured by Keithley) with -80 V applied to the drain electrode and grounding. ) Was swept (0 to −80 V), the current (I _d ) flowing through the drain electrode was measured, and the value was obtained from the slope of √I _d −V _g using Equation 1. The unit is cm ² / Vs.

I _d = (W / 2L) · C · μ · (V _g −V _T ) ² (Equation 1)
(Wherein, W is the channel width, L is the channel length, μ is the mobility, C is the capacitance per unit area of the gate insulating layer, and V _T is the threshold voltage.)

On the other hand, ON / OFF ratio for the measured _{I d,} was determined by the maximum value / minimum value.

The variation in mobility was evaluated by calculating the coefficient of variation (CV value) using Equation 2 from the average value and standard deviation of the mobility of the 10 TFTs.

(C.V. value) = (standard deviation of mobility of 10 manufactured TFTs) / (average value of mobility of 10 manufactured TFTs) (Equation 2)

The results are shown in Table 1.

(Example 2)
After an integrated TFT composed of 10 TFTs was manufactured in the same manner as in Example 1, the integrated TFT was heated at 100 ° C. for 10 minutes in a nitrogen atmosphere. Evaluation of variation in semiconductor characteristics and mobility was performed in the same manner as in Example 1. The results are shown in Table 1.

(Example 3)
<Gate electrode, gate insulating layer, and source and drain electrode formation process>
In the same manner as in Example 1, a gate electrode, a gate insulating layer, and source and drain electrodes were formed.

<Semiconductor layer formation process>
On the gate insulating layer so as to cover the source and drain electrodes, a 0.5 mass% solution of 2,7-dioctyl [1] benzothieno [3,2-b] [1] benzothiophene in p-xylene is used. The semiconductor layer made of 2,7-dioctyl [1] benzothieno [3,2-b] [1] benzothiophene was solidified to a thickness of 30 nm by spin coating (1000 rpm, 30 seconds) (entire surface) A film was formed.

<Overcoat layer formation process>
This step was performed in the same manner as in Example 1.
<Semiconductor characteristics (mobility and ON / OFF ratio) and mobility variation evaluation>
Evaluation was performed in the same manner as in Example 1. The results are shown in Table 1.

Example 4
A case where the manufacturing method of the present invention is applied to manufacturing an integrated TFT (electronic device) in which 10 BGTC TFTs are arranged in a grid pattern in a substrate will be described with reference to FIG. FIG. 15 is a schematic diagram of two adjacent TFTs extracted from 10 TFTs arranged in a grid pattern.

<Gate electrode and gate insulating layer formation process>
A gate electrode was formed by depositing aluminum with a thickness of about 30 nm on a glass substrate (symbol 1) by a vacuum deposition method using a metal mask (symbol 2). Here, using a parylene vapor deposition apparatus (Nippon Parylene Lab Coater PDS2010), dichloro-diparaxylylene (Japan Parylene DPX-C) is used as a raw material, and the gate insulating layer made of polyparachloroxylylene (Parylene C) is thick. A film was formed at 500 nm (reference 3).

<Semiconductor layer and source and drain electrode formation process>
On the gate insulating layer, a spin coating method (1000 rpm, 30 seconds) was performed using a 0.5 mass% solution of 2,7-dioctyl [1] benzothieno [3,2-b] [1] benzothiophene in p-xylene. ), A solid (overall) semiconductor layer made of 2,7-dioctyl [1] benzothieno [3,2-b] [1] benzothiophene was formed to a thickness of 30 nm (reference 4). Next, the source and drain electrodes made of a gold thin film were patterned with a thickness of 40 nm by a vacuum deposition method using a metal mask (reference numerals 5 and 6). Here, the distance between the source electrode and the drain electrode (channel length (L)) (symbol 8) was 75 μm, and the channel width (W) (symbol 9) was 5 mm.

<Overcoat layer formation process>
This step was performed in the same manner as in Example 1.
<Semiconductor characteristics (mobility and ON / OFF ratio) and mobility variation evaluation>
Evaluation was performed in the same manner as in Example 1. The results are shown in Table 1.
(Example 5)
In Example 3, a TFT was produced in the same manner as in Example 3 except that the overcoat layer was formed by the gravure offset printing method. The results are shown in Table 1.
(Example 6)
In Example 3, a TFT was produced in the same manner as in Example 3 except that the overcoat layer was formed by the microcontact printing method. The results are shown in Table 1.
(Example 7)
In Example 1, 5.0 mass% of p-xylene is added to the ink for forming the overcoat layer with respect to the insulating ink (F-1) described in Example 6 of International Publication No. 2014/125990. A TFT was produced in the same manner as in Example 1 except that the ink prepared in Step 1 was used. The results are shown in Table 1.
(Example 8)
FIG. 16 shows a case where the manufacturing method of the present invention is applied to the manufacture of an integrated TFT (electronic device) having 10 “BGBC type TFTs having a semiconductor protective layer” in the same arrangement as in Example 1 in the substrate. It will be explained using. FIG. 16 is a schematic diagram of two adjacent TFTs extracted from the ten TFTs.
<Gate electrode, gate insulating layer, and source and drain electrode formation process>
In the same manner as in Example 1, a gate electrode, a gate insulating layer, and source and drain electrodes were formed.

<Semiconductor layer and semiconductor protective layer forming step>
A 0.5 mass% toluene solution of 6,13-bis (triisopropylsilylethynyl) pentacene (hereinafter sometimes abbreviated as TIPS-pentacene) on the gate insulating layer so as to cover the source and drain electrodes. The semiconductor layer made of TIPS-pentacene was formed into a solid (entire surface) film having a thickness of 30 nm by spin coating (2500 rpm, 30 seconds) (reference 4). After that, amorphous fluorine resin (Asahi Glass Cytop Series CTL809M) (5.00 g) and a fluorine-based solvent (Asahi Glass CT-SOLV180) (0.50 g) was used to produce amorphous fluorine by an inkjet printing method. A semiconductor protective layer made of resin was formed into a pattern so as to cover the channel region (reference numeral 16).

<Overcoat layer formation process>
This step was performed in the same manner as in Example 1.
<Semiconductor characteristics (mobility and ON / OFF ratio) and mobility variation evaluation>
Evaluation was performed in the same manner as in Example 1. The results are shown in Table 1.

(Comparative Example 1)
Except that no overcoat layer was formed, the semiconductor characteristics (mobility and ON / OFF ratio) and mobility variation were evaluated in the same manner as in Example 1.
(Comparative Example 2)
Except that no overcoat layer was formed, the semiconductor characteristics (mobility and ON / OFF ratio) and mobility variation were evaluated in the same manner as in Example 3.
(Comparative Example 3)
<Gate electrode, gate insulating layer, and source and drain electrode formation process>
In the same manner as in Example 1, a gate electrode, a gate insulating layer, and source and drain electrodes were formed.
<Semiconductor layer formation process>
2,7-dioctyl [1] benzothieno [3,2-b] is formed on the gate insulating layer so as to cover each of the 10 pairs of the source and drain electrodes (that is, to cover each of the 10 channel regions). ] [1] A 0.5 mass% solution of benzothiophene in p-xylene was 0.05 μL drop cast for each channel region.

<Semiconductor characteristics (mobility and ON / OFF ratio) and mobility variation evaluation>
Evaluation was performed in the same manner as in Example 1. The results are shown in Table 1.
(Comparative Example 4)
<Gate electrode, gate insulating layer, source and drain electrodes, semiconductor layer, and semiconductor protective layer forming step>
In the same manner as in Example 8, a gate electrode, a gate insulating layer, a source and drain electrode, a semiconductor layer, and a semiconductor protective layer were formed.
<Overcoat layer formation process>
Using the overcoat layer forming ink produced in Example 1, an overcoat layer was formed by spin coating (2500 rpm, 30 seconds).
<Semiconductor characteristics (mobility and ON / OFF ratio) and mobility variation evaluation>
Evaluation was performed in the same manner as in Example 1. The results are shown in Table 1.

(Table 1)

As shown in Table 1, the TFT manufactured by the manufacturing method of the present invention has a large ON / OFF ratio and a small variation in mobility. On the other hand, Comparative Example 1 and Comparative Example 2 in which the overcoat layer was not formed have a small ON / OFF ratio. This is because element isolation is not performed. In Comparative Example 3 in which the semiconductor layer is formed by drop casting, since the semiconductor layer is patterned (because element isolation is performed), the ON / OFF ratio is high, but the semiconductor characteristics (mobility) are high. Variation is large. As described above, this large variation is a general tendency seen in low molecular weight semiconductors formed by a drop cast method or an ink jet printing method. Furthermore, when an overcoat layer was formed using a spin coat method, which is a film formation method outside the present invention, the semiconductor layer was destroyed in spite of the formation of a protective film on the semiconductor layer. It is presumed that the ink was washed out by the ink for forming the coat layer.) The TFT characteristics were not shown. This is because the film forming method outside the present invention has a large amount of solvent on the printing liquid film, so that the lower layer is affected by the solvent.
As described above, by using the manufacturing method according to the present invention, a TFT with element isolation can be easily obtained, and a TFT with a high ON / OFF ratio can be easily obtained.

A TFT manufactured by the manufacturing method of the present invention and an electronic device including the TFT have a high ON / OFF ratio and can be used for flexible electronics.

1: Substrate 2: Gate electrode 3: Gate insulating layer 4: Semiconductor layer 5: Source electrode 6: Drain electrode 7: Channel region 7 ': Semiconductor layers 7a to 7b on the channel region: On an electronic device comprising a plurality of TFTs Channel region 8: channel length (L)
9: Channel width (W)
10: Contact portion between overcoat layer and semiconductor layer 11: Edge of contact portion 12: Outer peripheral edge of channel region 14: Region immediately below contact portion of semiconductor layer 15: Overcoat layer 16: Semiconductor protective layer 17: Overcoat layer Among the pattern shapes, the length 18 of one side of the non-image portion: the interval (length) between the non-image portions of the overcoat layer pattern shape

Claims (7)

A gate electrode, a gate insulating layer, a source electrode and a drain electrode;
A semiconductor layer formed in a range wider than the channel region;
An overcoat layer formed after the semiconductor layer is formed, and a method for producing a thin film transistor,
The overcoat layer is formed so as to surround the periphery of the outer periphery of the channel region, and has a contact portion that contacts the semiconductor layer,
In the contact portion, the semiconductor layer is laminated as a lower layer and the overcoat layer is an upper layer,
The overcoat layer is formed by a printing method using an ink whose essential component is a solvent capable of dissolving or dispersing the semiconductor material forming the semiconductor layer,
The printing method is a printing method using an elastomeric blanket or an elastomeric plate, and has a step of transferring ink on the elastomeric blanket or the elastomeric plate onto a substrate. is there,
A method for manufacturing a thin film transistor. The method for manufacturing a thin film transistor according to claim 1, wherein the semiconductor layer is a semiconductor layer made of an organic semiconductor material. The method for producing a thin film transistor according to claim 1 or 2, wherein a method for forming the semiconductor layer is a vacuum deposition method. The method for producing a thin film transistor according to claim 1, wherein the method for forming the semiconductor layer is a wet film formation method. The method for producing a thin film transistor according to any one of claims 1 to 4, wherein the printing method is a letterpress reverse printing method. The method for producing a thin film transistor according to any one of claims 1 to 4, wherein the printing method is a microcontact printing method. The method for producing a thin film transistor according to any one of claims 1 to 4, wherein the printing method is a gravure offset printing method.

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