JPWO2017056427A1 - Program rewriting device, method and storage medium - Google Patents

Abstract

The present invention provides a technique for rewriting a program to be efficiently supplied to an accelerator in a program to be executed by a computer system including a processor and an accelerator. The program analysis unit 11 specifies an offload target process in a program to be executed by a computer system including a processor and an accelerator. The high-level synthesis unit 12 generates design content information of the arithmetic device that implements the offload target process on the accelerator and generates structure information of the arithmetic device. Based on the structure information, the program code fragment generation unit 13 describes a process of placing a set of input data to be simultaneously supplied to the arithmetic device in a continuous area on the memory and calling the offload target process using the continuous area. Generate a piece of program code. The program rewriting unit 14 embeds a piece of program code at the location where the offload target process is called in the program.

Description

  The present invention relates to a technique for rewriting a program to be executed by a computer system including a processor and an accelerator.

  Computer systems that include a processor and an accelerator are known. When describing a program to be executed by such a computer system, it is necessary to decide a process to be assigned to an accelerator. For example, Patent Document 1 describes a technique for dynamically determining a function to be assigned to an accelerator at the time of execution. Hereinafter, allocating processing to an accelerator is also referred to as offloading.

JP 2012-133778 A

  Here, it is required that the input data is efficiently supplied to the accelerator in which the offloaded processing is mounted. For example, when an offloaded process is implemented as a pipeline computing unit, it is desirable to supply input data for each cycle to the pipeline computing unit. In this case, input data required in each stage of the pipeline operation needs to be simultaneously supplied to the pipeline operation unit. That is, it is necessary to supply the same set of input data groups to the pipeline arithmetic unit at different timings according to the structure of the pipeline arithmetic unit. Therefore, it is conceivable to delay input data by adding a multi-stage pipeline register. However, multistage pipeline registers are not acceptable because they consume a large circuit area.

  As described above, an accelerator in which offloaded processing is implemented requires a plurality of different sets of input data in a certain cycle. However, in a normal memory system, one type of address can be requested in a certain cycle. If the memory bus width is wide, it is possible to read a plurality of input data arranged in the continuous area at a time. However, a plurality of input data arranged in non-contiguous areas cannot be read at a time. Therefore, in order for an accelerator equipped with an offloaded process to efficiently read a plurality of input data required in a certain cycle, the input data needs to be arranged in a continuous area.

  As described above, in order to efficiently supply input data to an accelerator in which processing to be offloaded is implemented, a plurality of different sets of input data are considered in consideration of the necessary timing of each input data. It is necessary to write a program to be placed in a continuous area. However, writing such a program is difficult and inefficient for programmers.

  Japanese Patent Application Laid-Open No. 2004-228867 describes that the process of offloading to an accelerator is dynamically determined at the time of execution, but does not describe efficiently supplying input data to the accelerator.

  The present invention has been made to solve the above-described problems. That is, an object of the present invention is to provide a technique for rewriting a program to efficiently supply data to an accelerator in a program executed by a computer system including a processor and an accelerator.

  In order to achieve the above object, a program rewriting apparatus according to the present invention includes a program analysis unit for specifying a process (offload target process) to be offloaded to an accelerator in a program to be executed by a computer system including a processor and an accelerator. High-level synthesis that generates design content information representing the design content of an arithmetic device that implements the offload target process on the accelerator, and generates structure information that represents the structure of the arithmetic device based on the generated design content information And a process of reading a set of input data to be simultaneously supplied to the arithmetic unit based on the structure information and placing the set in a continuous area on a memory and calling the offload target process using the continuous area Program code fragment generator that generates the described program code fragment If, on the call point of the offload target process in the program, and a program rewrite means for embedding the program code fragment.

  Further, the method of the present invention specifies a process (offload target process) to be offloaded to the accelerator in a program that is executed by a computer system including a processor and an accelerator. Generates design content information representing the design content of the arithmetic device mounted on the accelerator, generates structure information representing the structure of the arithmetic device based on the generated design content information, and performs the computation based on the structure information. A program code fragment describing a process for reading a set of input data to be simultaneously supplied to the apparatus and arranging the read data in a continuous area on the memory and calling the offload target process using the continuous area is generated in the program. The program at the location where the offload target process is called Embed the over-de-piece.

  The storage medium of the present invention includes a program analysis step for specifying a process (offload target process) to be offloaded to the accelerator in a program executed by a computer system including a processor and an accelerator, and the offload target process. A high-level synthesis step for generating design content information representing the design content of the arithmetic device mounted on the accelerator, and generating structure information representing the structure of the arithmetic device based on the generated design content information, Based on this, a set of input data to be simultaneously supplied to the arithmetic device is read and arranged in a continuous area on the memory, and a program code fragment describing a process for calling the offload target process using the continuous area is generated. A program code fragment generation step, and the program Wherein the call point offload target process, and stores a program to be executed and the program rewriting step of embedding the program code fragments, to the computer system in.

  The present invention can provide a technique for rewriting a program to be efficiently supplied to an accelerator in a program executed by a computer system including a processor and an accelerator.

It is a block diagram which shows the structure of the program rewriting apparatus as embodiment of this invention. It is a figure which shows an example of the hardware constitutions of the program rewriting apparatus as embodiment of this invention. It is a flowchart explaining operation | movement of the program rewriting apparatus as embodiment of this invention. It is a figure which shows an example of the program input in the specific example of embodiment of this invention, and an offload object process and an offload non-object process among them. It is a flowchart explaining an example of operation | movement of the program analysis part in the specific example of embodiment of this invention. It is a flowchart explaining an example of operation | movement of the high level synthetic | combination part in the specific example of embodiment of this invention. It is a figure which shows an example of a structure of the pipeline arithmetic unit determined in the specific example of embodiment of this invention. It is a figure which shows an example of the design content information produced | generated in the specific example of embodiment of this invention. It is a figure which shows an example of the structure information produced | generated in the specific example of embodiment of this invention. It is a flowchart explaining an example of operation | movement of the program code piece production | generation part in the specific example of embodiment of this invention. It is a figure which shows an example of the program code piece produced | generated in the specific example of embodiment of this invention. It is a figure explaining an example of the set of input data supplied simultaneously to a pipeline calculator in the specific example of embodiment of this invention. It is a figure which shows an example of the program code piece of a prologue and an epilogue in the specific example of embodiment of this invention. It is a figure which shows an example of the program output in the specific example of embodiment of this invention.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 shows a functional block configuration of a program rewriting device 1 as an embodiment of the present invention. In FIG. 1, the program rewriting device 1 includes a program analysis unit 11, a high-level synthesis unit 12, a program code fragment generation unit 13, and a program rewriting unit 14.

  Here, the program rewriting device 1 can be configured by hardware elements as shown in FIG. In FIG. 2, the program rewriting device 1 includes a CPU (Central Processing Unit) 1001 and a memory 1002. The memory 1002 includes a RAM (Random Access Memory), a ROM (Read Only Memory), an auxiliary storage device (such as a hard disk), and the like. In this case, each functional block of the program rewriting device 1 is configured by a CPU 1001 that reads and executes a computer program stored in the memory 1002 and controls other units. Note that the hardware configuration of the program rewriting device 1 and each functional block thereof is not limited to the above-described configuration.

  The program analysis unit 11 specifies a process (offload target process) to be offloaded to the accelerator in a program to be executed by a computer system including a processor and an accelerator. For example, the program analysis unit 11 may specify an offload target process by acquiring information representing a program and information designating the offload target process as input. In addition, for example, the program analysis unit 11 may acquire information representing a program as an input, and may specify the offload target process using a known technique for determining the offload target process.

  The high-level synthesis unit 12 generates design content information representing the design content of the arithmetic device that mounts the offload target process on the accelerator. The design content information may be, for example, RTL (Register Transfer Level) description. In addition, the high-level synthesis unit 12 generates structure information representing the structure of the arithmetic device based on the generated design content information. The structure information may include, for example, information regarding the delay of each input terminal.

  The program code fragment generation unit 13 generates a program code fragment based on the structure information of the arithmetic device. The program code fragment is a description of a process for arranging a set of input data to be simultaneously supplied to an arithmetic device mounted on an accelerator in a continuous area on the memory 1002, and an offload target process is called using the continuous area. Process description. For example, when the structure information includes information regarding the delay of each input terminal, the program code fragment generation unit 13 reads a set of input data to be supplied simultaneously by considering the delay for each input terminal, and the read input data Describes the process of placing a set in a continuous area. In addition, the program code fragment generation unit 13 describes a call statement having information indicating the above-described continuous area as an argument as a call statement for the offload target process.

  The program rewriting unit 14 embeds the above-described program code fragment at the location where the offload target process is called in the program. Specifically, the program rewriting unit 14 may output a program in which a part other than the offload target process in the program is replaced with the above-described program code fragment in the part including the call statement of the offload target process. .

  The operation of the program rewriting device 1 configured as described above is shown in FIG.

  In FIG. 3, first, the program analysis unit 11 obtains a program to be executed by a computer system including a processor and an accelerator. And the program analysis part 11 specifies an offload object process in the acquired program (step S1).

  For example, as described above, the program analysis unit 11 may acquire information specifying the offload target process as an input together with the program.

  Next, the high-level synthesis unit 12 generates design content information regarding the arithmetic device that mounts the offload target process on the accelerator (step S2).

  Next, the high-level synthesis unit 12 generates structure information representing the structure of the arithmetic device based on the design content information (step S3).

  Next, the program code fragment generation unit 13 generates a program code fragment based on the structure information (step S4).

  As described above, the program code fragment is a description of a process for arranging a set of input data to be simultaneously supplied to the arithmetic device in a continuous area on the memory 1002 and a process for calling an offload target process using the continuous area. And a description.

  Next, the program rewriting unit 14 embeds the above-described program code fragment at the location where the offload target process is called in the program (step S5).

  As described above, the program rewriting unit 14 may output a program in which a portion other than the offload target process in the program is replaced with the above-described program code fragment in the part including the call statement of the offload target process. .

  Thus, the program rewriting device 1 finishes the operation.

  In this way, the program rewriting device 1 outputs the design content information generated in step S2 and the program other than the offload target process rewritten in step S5 with respect to the program acquired in step S1.

  Next, the operation of the program rewriting device 1 will be shown as a specific example. In this example, it is assumed that the offload target process is implemented as a pipeline arithmetic unit on the accelerator.

  First, in step S1, the program analysis unit 11 acquires information representing the input program shown in FIG. 4 and information specifying an offload target process. In this example, the input program includes two functions “funcA” and “main”. Further, it is assumed that the program analysis unit 11 acquires the function name “funcA” as information for designating the offload target process.

  In this specific example, in this step, the program analysis unit 11 outputs the acquired input program separately to an offload target program and an offload non-target program that is not an offload target.

  FIG. 5 shows details of the operation of the program analysis unit 11 at step S1 in the specific example.

  In FIG. 5, the program analysis unit 11 analyzes the structure of the input program and extracts function name symbols (step S11). Here, “funcA” and “main” are extracted.

  Next, the program analysis unit 11 searches for a function name symbol that matches information specifying the offload target process from among the extracted function name symbols (step S12). Here, “funcA” is detected.

  Next, the program analysis unit 11 outputs a program in a range corresponding to the detected function name symbol as an offload target program (step S13).

  Next, the program analysis unit 11 outputs a program in a range corresponding to the function name symbol that does not match the information “funcA” designating the offload target process as an offload non-target program (step S14).

  Above, detailed description of operation | movement of step S1 in a specific example is complete | finished.

  As a result, as shown in FIG. 4, the contents of the function funcA are output as the offload target program. The contents of the function main are output as the offload non-target program.

  Next, in steps S2 to S3, the high-level synthesis unit 12 outputs the RTL description of the pipeline arithmetic unit based on the offload target program. Further, the high-level synthesis unit 12 generates, as structure information, information indicating the number of cycles (the number of delays) from the previous input terminal for each input terminal of the pipeline arithmetic unit.

  Details of the operation of the high-level synthesis unit 12 in steps S2 to S3 in the specific example are shown in FIG.

  In FIG. 6, the high-level synthesis unit 12 performs high-level synthesis of the offload target program and generates a pipeline arithmetic unit structure (step S21).

  In this example, as shown in FIG. 4, the offload target program calculates (((a * b) + c) * d) for the four inputs a, b, c, and d, and the calculation result Is a program that outputs Therefore, the high-level synthesis unit 12 generates the structure shown in FIG. 7 as the structure of the pipeline arithmetic unit that implements such an offload target program. This pipeline operator performs multiplication of inputs a and b in the first pipeline stage (stage 1). If the multiplication delay is two cycles, the multiplication result is output in stage 3. The pipeline computing unit adds the multiplication result of stage 1 and the input c at stage 3. If the delay of addition is 2 cycles, the addition result is output at stage 5. The pipeline arithmetic unit multiplies the addition result of stage 3 and the input d at stage 5. The multiplication result is output at stage 7.

  Next, the high-level synthesis unit 12 converts the generated structure into an RTL description and outputs it (step S22).

  Here, it is assumed that a Verilog-RTL description as shown in FIG. 8 is output to the structure of the pipeline arithmetic unit shown in FIG. In FIG. 8, MULTIPLIER represents a multiplier. ADDER represents an adder.

  Next, for each input terminal in the generated structure, the high-level synthesis unit 12 obtains the number of cycles (the number of delays) from the previous input terminal and outputs it as structure information (step S23).

  Here, structure information as shown in FIG. 9 is output for the structure of the pipeline arithmetic unit shown in FIG. In the example of FIG. 9, the structure information is represented by a set of input data and a delay number. For example, input a is input at stage 1. Since the delay number of the input a is the difference from the first stage, which is the first stage, 1-1 = 0. The delay number of the input b is 0 as in the case of the input a. Input c is input at stage 3. Therefore, the delay number of the input c is 3-1 = 2. The input d is input at the stage 5. Therefore, the delay number of the input d is 5-1 = 4.

  Above, detailed description of operation | movement of step S2-S3 in a specific example is complete | finished.

  Next, in step S4, the program code fragment generation unit 13 refers to the structure information of the pipeline arithmetic unit, and sets a description in which each input data corresponding to the number of delays is arranged in a continuous area and a continuous area. Is used to describe the process of calling the offload target process.

  Details of the operation of the program code fragment generation unit 13 in step S4 in the specific example are shown in FIG.

  In FIG. 10, the program code fragment generation unit 13 executes the following steps S31 to S32 for each argument in the call statement of the offload target process. Here, each argument is assumed to be argj (j = 0 to M, M is an integer of 0 or more). In this example, arg0 corresponds to “A + i”, arg1 corresponds to “B + i”, arg2 corresponds to “C + i”, and arg3 corresponds to “D + i”. In this example, M = 3.

  Here, first, the program code fragment generation unit 13 searches the delay number dj corresponding to argj by referring to the structure information (step S31).

  For example, referring to FIG. 9, 0 is retrieved as the delay number d0 corresponding to arg0.

  Next, the program code fragment generation unit 13 generates a sentence “pack [j] = * (argj + Z−dj);” as a description in which an argument corresponding to the number of delays is arranged in the continuous area (step S32). .

  Here, Z represents the number of delays from the input to the output of the pipeline arithmetic unit. Referring to FIG. 7, in this specific example, Z = 6. For example, the code fragment corresponding to arg0 is “pack [0] = * (A + i + 6);”. Then, the program code fragment generation unit 13 sets the description generated for the argument as a program code fragment. If there is a program code fragment generated for another argument so far, the program code fragment generation unit 13 adds the description generated for this argument to the previous program code fragment.

  When steps S31 to S32 are completed for all the arguments, as shown in FIG. 11, a program code piece 901 that arranges a set of arguments corresponding to the number of delays in a continuous area is generated.

  Next, the program code fragment generation unit 13 generates a description for calling the offload target process using “pack” representing a continuous area (step S33). As a result, as shown in FIG. 11, a program code fragment 902 serving as a call statement for the offload target process is output.

  Next, the program code fragment generation unit 13 generates a program code fragment that becomes a prologue and an epilogue of a process for placing an argument set corresponding to the number of delays in a continuous area and calling an offload target process (step S34).

  Here, a program code fragment that becomes a prologue and an epilogue will be described. For this purpose, first, a description will be given of combinations of arguments supplied simultaneously to the pipeline arithmetic unit shown in FIG. The combination of arguments supplied at the same time is as shown in FIG. 12 in consideration of the delay number of each argument. In FIG. 12, each row represents a combination of arguments supplied simultaneously. In FIG. 12, the column “output” represents information output from the pipeline computing unit in the cycle in which the argument of the combination of each row is input. At this time, in the period 801 from the first input to the pipeline calculator until the Z-th cycle, part of the arguments are unnecessary or there is no output from the pipeline calculator, so the above-described program code pieces 901 and 902 Is not applicable. In addition, the program code pieces 901 and 902 described above cannot be applied to the Z cycle period 803 from the pipeline arithmetic unit until the last output is present, because some or all of the arguments are unnecessary. That is, the period during which the above-described program code pieces 901 and 902 can be applied is a period 802 from the Z + 1th cycle to the Nth cycle. Therefore, as shown in FIG. 13, the program code fragment generation unit 13 generates a program code fragment 903 serving as a prolog for the period 801. Further, the program code fragment generation unit 13 generates a program code fragment 904 that becomes an epilogue for the period 803. Note that the program code fragment generation unit 13 adds a description declaring the continuous area to the program code fragment as necessary. In the examples of FIGS. 11 and 13, the declaration statement of the continuous area pack is added to the head of the program code piece 903 that becomes the prologue.

  Above, detailed description of operation | movement of step S4 in a specific example is complete | finished.

  Next, in step S5, the program rewriting unit 14 embeds and outputs the above-described program code pieces 901 to 904 at the offload target process call location in the offload non-target program. The output program is as shown in FIG. In this specific example, the program rewriting unit 14 performs the program shown in FIG. 11 immediately before the call statement “R [i] = funcA (A + i, B + i, C + i, D + i)” in the offload target program shown in FIG. A cord piece 901 is inserted. Further, the program rewriting unit 14 replaces the calling statement “R [i] = funcA (A + i, B + i, C + i, D + i)” in the offload target program shown in FIG. 4 with the program code fragment 902 shown in FIG. doing. Further, the number of repetitions of the program code pieces 901 and 902 is changed to NZ times. The program rewriting unit 14 inserts the program code pieces 903 and 904 before and after the repetitive processing of the program code pieces 901 and 902, respectively. In FIG. 14, details of the program code pieces 903 and 904 are omitted.

  In this way, in this specific example, the program rewriting device 1 outputs the RTL description of FIG. 8 and the output program of FIG. 14 to the input program of FIG.

  This is the end of the description of the specific example.

  Next, effects of the embodiment of the present invention will be described.

  The program rewriting apparatus according to the present embodiment can rewrite a program to efficiently supply data to an accelerator in a program executed by a computer system including a processor and an accelerator.

  The reason will be described. In the present embodiment, the program analysis unit specifies an offload target process in a program to be executed by a computer system including a processor and an accelerator. Then, the high-level synthesis unit generates design content information representing the design content of the arithmetic device that mounts the offload target process on the accelerator. Further, the high-level synthesis unit generates structure information representing the structure of the arithmetic device based on the generated design content information. Then, the program code fragment generation unit generates a program code fragment based on the structure information of the arithmetic device. The program code fragment includes a description of a process for arranging a set of input data to be simultaneously supplied to the arithmetic device in a continuous area on the memory and a description of a process for calling an offload target process using the continuous area. . This is because the program rewriting unit embeds a piece of program code in the calling location of the offload target process in the program.

  As a result, when the computer system including the processor and the accelerator is executed with the program rewritten using the present embodiment, different sets of input data arranged in non-contiguous areas are sent to the accelerator at the same time. It can be supplied efficiently.

  Here, the effect that the program rewritten according to the present embodiment reduces the input data reading speed by the accelerator as compared with the original program will be described using a specific example.

  For example, in the offload non-target process in the program, when calling the offload target process, consider passing four 4-byte data arranged in a non-contiguous area as an argument. Here, the offload target process is Suppose that it is implemented as a pipeline computing unit.

  First, consider the speed difference between the processor and the pipeline computing unit on the accelerator. If the processor operates at 3 GHz and the pipeline calculator on the accelerator operates at 100 MHz, the speed difference is about 30 times. Further, it is assumed that the processor can load one 4-byte data in one cycle. Further, it is assumed that the accelerator can load one 4-byte data in one cycle.

  The original program before rewriting supplies different sets of four input data required at the same time to the accelerator without arranging them in the continuous area. In this case, sending an address from the processor to the accelerator requires 4 cycles (1 cycle × 4). Since the sent addresses are non-consecutive, loading of data corresponding to each address by the accelerator requires 4 cycles (1 cycle × 4). Here, the four cycles of the accelerator correspond to 120 cycles in terms of the processor cycle in consideration of a speed difference of 30 times from the processor. In other words, in this case, reading of four sets of input data from different sets requires a total of 4 + 120 = 124 cycles in terms of processor cycles.

  On the other hand, the program rewritten in accordance with the present embodiment supplies different sets of four input data required at the same time to the accelerator after arranging them in the continuous area. In this case, the collection of input data by the processor requires 4 cycles (1 cycle × 4). Next, the writing of the collected input data to the continuous area requires 4 cycles (1 cycle × 4). The address transmission from the processor to the accelerator requires one cycle (1 cycle × 1). In addition, since four pieces of data are arranged in the continuous area indicated by the sent address, loading of data corresponding to the address by the accelerator is completed in one cycle (1 cycle × 1). Here, one cycle of the accelerator corresponds to 30 cycles in terms of the processor cycle in consideration of a speed difference of 30 times from the processor. That is, in the present embodiment, reading of four different sets of input data requires a total of 4 + 4 + 1 + 30 = 39 cycles in terms of processor cycles.

  Thus, the program rewritten according to the present embodiment can cause the accelerator to read input data at 124 ÷ 39 = about 3.2 times faster than the original program.

  In the embodiment of the present invention, for example, a field-programmable gate array (FPGA) or a graphics processing unit (GPU) is applicable as an accelerator, but is not limited thereto.

  In the embodiment of the present invention, the example in which the offloaded process is implemented as a pipeline arithmetic unit on the accelerator has been described. However, the arithmetic unit that implements the offloaded process is included in the pipeline arithmetic unit. Not exclusively.

  In the embodiment of the present invention, the design content information generated by the high-level synthesis unit has been mainly described as an example of Verilog RTL description. However, the present invention is not limited to this. The design content information may be described in another hardware description language.

  Further, in the embodiment of the present invention, the example in which each functional block of the program rewriting device is realized by a CPU that executes a computer program stored in a storage device or ROM has been described. However, the present invention is not limited to this, and some, all, or a combination of each functional block may be realized by dedicated hardware.

  In each of the above-described embodiments of the present invention, the functional block of the program rewriting device may be distributed and implemented in a plurality of devices.

  In the embodiment of the present invention, the operation of the program rewriting device described with reference to each flowchart may be stored in a storage device (storage medium) of the computer device as the computer program of the present invention. Then, the computer program may be read and executed by the CPU. In such a case, the present invention is constituted by the code of the computer program or a storage medium.

  The present invention has been described above using the above-described embodiment as an exemplary example. However, the present invention is not limited to the above-described embodiment. That is, the present invention can apply various modes that can be understood by those skilled in the art within the scope of the present invention.

  This application claims the priority on the basis of Japanese application Japanese Patent Application No. 2015-193106 for which it applied on September 30, 2015, and takes in those the indications of all here.

DESCRIPTION OF SYMBOLS 1 Program rewriting apparatus 11 Program analysis part 12 High-level synthesis part 13 Program code piece generation part 14 Program rewriting part 1001 CPU
1002 memory

Claims (5)

In a program to be executed by a computer system including a processor and an accelerator, program analysis means for specifying a process (offload target process) to be offloaded to the accelerator;
High-level synthesis means for generating design content information representing the design content of an arithmetic device for mounting the offload target process on the accelerator, and generating structure information representing the structure of the arithmetic device based on the generated design content information When,
A program describing a process of reading a set of input data to be simultaneously supplied to the arithmetic unit based on the structure information, placing the input data in a continuous area on a memory, and calling the offload target process using the continuous area Program code fragment generating means for generating a code fragment;
Program rewriting means for embedding the program code fragment in the call location of the offload target process in the program,
A program rewriting device comprising: The high-level synthesis means generates, as the structure information, information including the number of cycles (the number of delays) from the input terminal in the previous stage for each input terminal of the arithmetic device,
2. The program code fragment generation unit according to claim 1, wherein the program code fragment includes a description of processing for arranging the input data according to the number of delays as a set and arranging the input data in the continuous area. Program rewriting device.   The program rewriting apparatus according to claim 1, wherein the high-level synthesis unit generates design content information of a pipeline arithmetic unit as the arithmetic unit. Computer equipment
In a program to be executed by a computer system including a processor and an accelerator, a process to be offloaded to the accelerator (offload target process) is specified,
Generate design content information representing the design content of a computing device that implements the offload target process on the accelerator, and generate structure information representing the structure of the computing device based on the generated design content information.
A program describing a process of reading a set of input data to be simultaneously supplied to the arithmetic unit based on the structure information, placing the input data in a continuous area on a memory, and calling the offload target process using the continuous area Generate a piece of code
A method of embedding the program code fragment at a call location of the offload target process in the program. In a program to be executed by a computer system including a processor and an accelerator, a program analysis step for specifying a process (offload target process) to be offloaded to the accelerator;
A high-level synthesis step of generating design content information representing the design content of an arithmetic device that implements the offload target process on the accelerator, and generating structure information representing the structure of the arithmetic device based on the generated design content information When,
A program describing a process of reading a set of input data to be simultaneously supplied to the arithmetic unit based on the structure information, placing the input data in a continuous area on a memory, and calling the offload target process using the continuous area A program code fragment generation step for generating a code fragment;
A program rewriting step of embedding the program code fragment at a call location of the offload target process in the program;
A storage medium storing a program for causing a computer device to execute the program.

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