JPWO2016181625A1 - Semiconductor light emitting device and manufacturing method thereof - Google Patents

Abstract

An object of the present invention is to provide a semiconductor light emitting device capable of improving reliability and a method for manufacturing the same. The n-type nitride semiconductor layer (3) has at least an n-type AlGaN layer (31). The passivation film (11) is a silicon nitride film containing hydrogen. The first peel prevention layer (12a) and the second peel prevention layer (12b) are formed on the passivation film (11) and the end of the surface (8a) of the positive electrode (8) and the surface (9a) of the negative electrode (9). Each is interposed between the end portions. Each of the first peeling prevention layer (12a) and the second peeling prevention layer (12b) includes a lower layer (121) and an upper layer (122) formed on the lower layer (121). The lower layer (121) is formed of one material selected from the group consisting of Ti, Zr, Si, Al, Ni, and Sn. The upper layer (122) is formed of an oxide of the material of the lower layer (121).

Description

  The present invention relates to a semiconductor light emitting device and a method for manufacturing the same, and more particularly to a semiconductor light emitting device that emits ultraviolet light and a method for manufacturing the same.

  Conventionally, as a semiconductor light emitting device, a laminated film of an n-type layer, a light-emitting layer, and a p-type layer on one surface side of a substrate has a mesa structure, an n electrode provided on an exposed surface of the n-type layer, p An ultraviolet semiconductor light emitting device including a p-electrode provided on the surface side of a mold layer is known (Patent Document 1).

The n-type layer in the ultraviolet semiconductor light emitting device described in Patent Document 1 is composed of an n-type Al _z Ga _{1 -z} N layer (0 <z ≦ 1).

  The semiconductor light emitting device includes a substrate, an n-type gallium nitride semiconductor layer, a light emitting layer, a p-type gallium nitride semiconductor layer, an insulating protective film, a negative electrode, a positive electrode, a negative electrode, and a positive electrode. A light-emitting element including an adhesion reinforcing layer between each electrode and an insulating protective film is known (Patent Document 2).

The n-type gallium nitride-based semiconductor layer and the light emitting layer in the light emitting element described in Patent Document 2 are made of AlInGaN and InGaN doped with Si, respectively. Moreover, the insulating protective film in the light emitting element described in Patent Document 2 is formed of, for example, Si ₃ N ₄ . In Patent Document 2, when the insulating protective film is formed of Si ₃ N ₄ , the adhesion reinforcing layer is formed of any one of Cr, Ni, Cu, and Al, or an oxide thereof. It is described that it is preferable.

  In a semiconductor light emitting device including an n-type AlGaN layer that transmits ultraviolet rays radiated from the light emitting layer, it is desired to improve reliability by improving moisture resistance.

JP 2014-96460 A JP-A-11-150301

  An object of the present invention is to provide a semiconductor light emitting device capable of improving reliability and a method for manufacturing the same.

  A semiconductor light emitting device according to an aspect of the present invention includes an n-type nitride semiconductor layer having at least an n-type AlGaN layer, a light-emitting layer that is formed on the n-type AlGaN layer and emits ultraviolet light, and a light-emitting layer on the light-emitting layer. Supporting the formed p-type nitride semiconductor layer, the n-type nitride semiconductor layer, the light emitting layer, and the p-type nitride semiconductor layer, and emitting ultraviolet rays emitted from the light emitting layer A substrate which is a transparent single crystal substrate, a positive electrode formed on the surface of the p-type nitride semiconductor layer, and a portion of the n-type nitride semiconductor layer which is not covered with the light emitting layer. A negative electrode and a passivation film are provided. The n-type nitride semiconductor layer, the light emitting layer, and the p-type nitride semiconductor layer are arranged in this order from the substrate side. The n-type AlGaN layer has a first region that overlaps the light emitting layer and a second region that does not overlap the light emitting layer, and the surface of the second region recedes toward the substrate rather than the surface of the first region. A step to be formed is formed. The light emitting layer is formed on the surface of the first region of the n-type AlGaN layer. The negative electrode is formed on the surface of the second region of the n-type AlGaN layer. The passivation film is a silicon nitride film containing hydrogen. The semiconductor light emitting device includes a first delamination preventing layer interposed between the passivation film and the end of the surface of the positive electrode, and a second interposed between the passivation film and the end of the surface of the negative electrode. A peeling prevention layer. Each of the first peeling prevention layer and the second peeling prevention layer includes a lower layer and an upper layer formed on the lower layer. The lower layer is formed of one material selected from the group consisting of Ti, Zr, Si, Al, Ni, and Sn. The upper layer is formed of an oxide of the lower layer material.

  The method for manufacturing a semiconductor light emitting device according to the present invention is the above-described method for manufacturing a semiconductor light emitting device, wherein the first step of forming the first peeling prevention layer and the second peeling prevention layer, and after the first step. And a second step of forming the passivation film. In the first step, after forming a layer made of one material selected from the group consisting of Ti, Zr, Si, Al, Ni and Sn, the surface side of the layer is oxidized, or in an oxidizing atmosphere By forming an oxide layer of one material selected from the group consisting of Ti, Zr, Si, Al, Ni and Sn by reactive sputtering or ion beam deposition in an oxidizing atmosphere, the first peeling is performed. The same laminated structure as each of the prevention layer and the second peeling prevention layer is formed, and then, the first peeling prevention layer and the second peeling prevention layer are formed by patterning the lamination structure.

FIG. 1 is a schematic cross-sectional view of a semiconductor light emitting device according to an embodiment of the present invention. FIG. 2 is a schematic plan view of the above semiconductor light emitting device.

  Each drawing described in the following embodiment is a schematic diagram, and the ratio of the size and thickness of each component in the drawing does not necessarily reflect the actual dimensional ratio.

(Embodiment)
Hereinafter, the semiconductor light emitting device 100 of the present embodiment (hereinafter sometimes abbreviated as “light emitting device 100”) will be described with reference to FIGS. 1 is a cross-sectional view taken along line XX of FIG.

  The light-emitting element 100 includes a substrate 1, an n-type nitride semiconductor layer 3, a light-emitting layer 4 that emits ultraviolet light having an emission peak wavelength in the ultraviolet wavelength region, a p-type nitride semiconductor layer 5, a positive electrode 8, The negative electrode 9, the passivation film 11, the 1st peeling prevention layer 12a, and the 2nd peeling prevention layer 12b are provided. The substrate 1 has a first surface 1a and a second surface 1b. The substrate 1 is a single crystal substrate that transmits ultraviolet rays emitted from the light emitting layer 4. The n-type nitride semiconductor layer 3 is formed on the first surface 1 a of the substrate 1 and has at least an n-type AlGaN layer 31. The n-type AlGaN layer 31 has a first region 311 that overlaps the light emitting layer 4 and a second region 312 that does not overlap the light emitting layer 4, and the surface 312 a of the second region 312 is more substrate than the surface 311 a of the first region 311. A step is formed to recede toward the first surface 1a. The light emitting layer 4 is formed on the surface 311 a of the first region 311 of the n-type AlGaN layer 31. The p-type nitride semiconductor layer 5 is formed on the light emitting layer 4. The positive electrode 8 is formed on the surface 5 a of the p-type nitride semiconductor layer 5. The negative electrode 9 is formed on the surface 312 a of the second region 312 of the n-type AlGaN layer 31. The passivation film 11 is a silicon nitride film containing hydrogen. The first peeling prevention layer 12 a is interposed between the passivation film 11 and the end portion of the surface 8 a of the positive electrode 8. The second peeling preventing layer 12b is interposed between the passivation film 11 and the end portion of the surface 9a of the negative electrode 9. Each of the first peeling prevention layer 12 a and the second peeling prevention layer 12 b includes a lower layer 121 and an upper layer 122 formed on the lower layer 121. The lower layer 121 is made of Ti. The upper layer 122 is made of an oxide of Ti. The lower layer 121 in the first peeling prevention layer 12 a is a layer formed directly on the end portion of the surface 8 a of the positive electrode 8. The lower layer 121 in the second peeling preventing layer 12b is a layer formed directly on the end portion of the surface 9a of the negative electrode 9.

  The light emitting element 100 having the above-described configuration can improve reliability. More specifically, in the light emitting device 100, each of the first peeling prevention layer 12a and the second peeling prevention layer 12b includes the lower layer 121 and the upper layer 122, so that the passivation film 11 and the first peeling layer are separated. It becomes possible to improve adhesiveness with each of the prevention layer 12a and the second peeling prevention layer 12b. Therefore, in the light emitting element 100, it is possible to suppress the passivation film 11 from being peeled off from each of the first peel preventing layer 12a and the second peel preventing layer 12b. Thereby, the light emitting element 100 can improve the reliability. In the light emitting element 100, the second surface 1b of the substrate 1 constitutes a light extraction surface.

  The light emitting element 100 is an ultraviolet LED chip (Light Emitting Diode Chip) that emits ultraviolet rays. The chip size of the light emitting element 100 is, for example, 400 μm □ (400 μm × 400 μm).

  In the light emitting element 100, it is preferable that the surface 8a side of the positive electrode 8 is formed of Au and the surface 9a side of the negative electrode 9 is formed of Au. Thereby, in the light emitting element 100, it becomes possible to easily join the Au wire or the Au bump to each of the positive electrode 8 and the negative electrode 9. “The surface 8a side of the positive electrode 8 is formed of Au” means that at least the surface 8a side of the positive electrode 8 is formed of Au. “The surface 9a side of the negative electrode 9 is formed of Au” means that at least the surface 9a side of the negative electrode 9 is formed of Au.

  The positive electrode 8 preferably includes a first contact electrode 81 in ohmic contact with the p-type nitride semiconductor layer 5 and a first pad electrode 82 formed so as to cover the first contact electrode 81. The negative electrode 9 preferably includes a second contact electrode 91 in ohmic contact with the n-type AlGaN layer 31 and a second pad electrode 92 formed so as to cover the second contact electrode 91. The light emitting element 100 preferably further includes an electrical insulating film 10 made of a silicon oxide film. The electrical insulating film 10 includes a part of the surface 5a and the side surface 5c of the p-type nitride semiconductor layer 5, the side surface 4c of the light emitting layer 4, the side surface 311c of the first region 311 of the n-type AlGaN layer 31, and the n-type AlGaN. It is preferable to cover a part of the surface 312 a of the second region 312 of the layer 31. The electrical insulating film 10 includes a first contact hole 101 in which the first contact electrode 81 is disposed inside, and a second contact hole 102 in which the second contact electrode 91 is disposed inside. The passivation film 11 is preferably formed so as to cover at least the end of the surface 8 a of the positive electrode 8 and the end of the surface 9 a of the negative electrode 9. Thereby, the light emitting element 100 can further improve the reliability.

  Each component of the light emitting element 100 will be described in detail below.

  The light emitting element 100 is, for example, an ultraviolet LED chip that emits ultraviolet light having an emission peak wavelength in a wavelength range of 210 nm to 360 nm. Thereby, the light emitting element 100 can be used in fields such as high-efficiency white illumination, sterilization, medical treatment, and uses for treating environmental pollutants at high speed. The “emission peak wavelength” is an emission peak wavelength at room temperature (27 ° C.).

  When the light emitting element 100 is used in the field of sterilization, for example, it is preferable that the light emitting element 100 has an emission peak wavelength in a wavelength range of 260 nm to 285 nm. As a result, the light emitting element 100 can emit ultraviolet light in the 260 nm to 285 nm band that is easily absorbed by DNA of viruses and bacteria, and can be sterilized efficiently. The light emitting element 100 preferably has a light emission peak wavelength in the UV-C wavelength region. The wavelength range of UV-C is, for example, 100 nm to 280 nm according to the classification by the wavelength of ultraviolet rays in the International Commission on Illumination (CIE).

  The single crystal substrate constituting the substrate 1 is preferably a sapphire substrate. The first surface 1a of the substrate 1 preferably has an off angle from the (0001) plane of 0 ° to 0.5 °, more preferably 0.05 ° to 0.4 °. More preferably, the angle is 1 ° to 0.31 °.

  N-type nitride semiconductor layer 3 is formed on first surface 1 a of substrate 1. Here, the n-type nitride semiconductor layer 3 is preferably formed on the substrate 1 via the first buffer layer 2a and the second buffer layer 2b. In short, the light emitting device 100 preferably includes the first buffer layer 2a and the second buffer layer 2b between the substrate 1 and the n-type nitride semiconductor layer 3. In this case, in the light emitting device 100, the first buffer layer 2a is formed directly on the first surface 1a of the substrate 1, and the n-type nitride semiconductor layer 3 is formed on the second buffer layer 2b on the first buffer layer 2a. Is formed directly. In this specification, “formed on the first surface 1 a of the substrate 1” may be formed directly on the first surface 1 a of the substrate 1, or may be formed on the first surface 1 a of the substrate 1. It may be formed via the buffer layer 2a and the second buffer layer 2b, or may be formed on the first surface 1a of the substrate 1 via only the first buffer layer 2a.

The first buffer layer 2a is composed of an Al _x Ga _1-x N layer (0 <x ≦ 1). The first buffer layer 2a is preferably composed of an AlN layer.

The first buffer layer 2 a is a layer provided for the purpose of improving the crystallinity of the n-type nitride semiconductor layer 3, the light emitting layer 4, and the p-type nitride semiconductor layer 5. Since the light emitting element 100 includes the first buffer layer 2a, the dislocation density can be reduced, and the crystallinity of the n-type nitride semiconductor layer 3, the light emitting layer 4, and the p-type nitride semiconductor layer 5 can be improved. It becomes possible to plan. Therefore, the light emitting element 100 can improve the light emission efficiency. In the light emitting element 100, if the first buffer layer 2a is too thin, the reduction of threading dislocation tends to be insufficient. The dislocation density of the first buffer layer 2a is preferably 5 × 10 ⁹ cm ⁻³ or less. Further, in the light emitting element 100, if the first buffer layer 2a is too thick, cracks due to lattice mismatch with the substrate 1, peeling of the first buffer layer 2a from the substrate 1, and a plurality of light emissions. There is a concern that warping of a wafer forming the device 100 becomes a factor that becomes too large. For this reason, the thickness of the first buffer layer 2a is, for example, preferably about 500 nm to 10 μm, and more preferably 1 μm to 5 μm. As an example, the thickness of the first buffer layer 2a is set to 4 μm.

Second buffer layer 2 b is interposed between first buffer layer 2 a and n-type nitride semiconductor layer 3. The second buffer layer 2 b is a layer provided to further reduce threading dislocations in the light emitting layer 4 and reduce residual strain in the light emitting layer 4. The second buffer layer 2b is a small lattice constant difference between the first buffer layer 2a than the n-type nitride semiconductor layer 3 larger composition ratio of Al than the n-type nitride semiconductor layer 3 Al _y Ga _1-y N It is composed of layers (0 <y <1, y <x). The composition ratio of the Al _y Ga _1-y N layer (0 <y <1, y <x) constituting the second buffer layer 2b is set so that the ultraviolet light emitted from the light emitting layer 4 can be efficiently emitted. preferable. The second buffer layer 2b is, for example, an Al _0.95 Ga _0.05 N layer. The thickness of the second buffer layer 2b is preferably 0.03 μm to 1 μm, for example. As an example, the thickness of the second buffer layer 2b is set to 0.5 μm.

In the light emitting device 100, the n-type nitride semiconductor layer 3 is a layer for transporting electrons to the light emitting layer 4. The n-type nitride semiconductor layer 3 can be composed of, for example, an n-type AlGaN layer 31. The n-type AlGaN layer 31 is an n-type Al _z Ga _1-z N layer (0 <z <1). The n-type Al _z Ga _{1 -z} N layer (0 <z <1) preferably has an Al composition ratio z so that ultraviolet rays emitted from the light emitting layer 4 can be efficiently emitted. For example, when the light emitting layer 4 has a quantum well structure composed of a barrier layer and a well layer, the well layer is composed of an Al _0.45 Ga _0.55 N layer, and the barrier layer is composed of an Al _0.55 Ga _0.45 N layer The Al composition ratio z can be set to 0.55, which is the same as the Al composition ratio of the barrier layer. That is, the n-type AlGaN layer 31 can be an n-type Al _0.55 Ga _0.45 N layer. The Al composition ratio z of the n-type Al _z Ga _{1 -z} N layer (0 <z <1) is not limited to the same as the Al composition ratio of the barrier layer, and may be different. As an example, the thickness of the n-type nitride semiconductor layer 3 is set to 2 μm. As the donor impurity of the n-type nitride semiconductor layer 3, for example, Si is preferable. Moreover, it is preferable that the electron concentration of the n-type nitride semiconductor layer 3 is about 1 × 10 ¹⁸ to 1 × 10 ¹⁹ cm ⁻³ , for example.

  The n-type nitride semiconductor layer 3 only needs to include at least an n-type AlGaN layer 31, and includes an n-type AlGaN layer having an Al composition ratio different from that of the n-type AlGaN layer 31 in addition to the n-type AlGaN layer 31. It may be. In the light emitting device 100, the n-type AlGaN layer 31 also serves as an n-type contact layer. In other words, the n-type AlGaN layer 31 has a function of an n-type contact layer.

The light emitting layer 4 is between the n-type nitride semiconductor layer 3 and the p-type nitride semiconductor layer 5. The light emitting layer 4 is a layer for converting injected carriers (here, electrons and holes) into light. In other words, the light emitting layer 4 is a layer that emits ultraviolet rays by recombination of electrons injected from the n-type nitride semiconductor layer 3 and holes injected from the p-type nitride semiconductor layer 5. The light emitting layer 4 preferably has a quantum well structure. In the light emitting layer 4, the well layer of the quantum well structure is configured by an Al _a Ga _1-a N layer (0 <a <1), and the barrier layer of the quantum well structure is an Al _b Ga _1-b N layer (0 <B ≦ 1, b> a) is preferable. In the light emitting device 100, the emission wavelength can be set to an arbitrary emission wavelength in the range of 210 nm to 360 nm by changing the Al composition ratio a in the Al _a Ga _1-a N layer (0 <a <1). Is possible. For example, in the light emitting element 100, when the desired emission wavelength is around 275 nm, the Al composition ratio a may be set to 0.45. In the light emitting layer 4, the well layer of the quantum well structure may be composed of an InAlGaN layer.

  The quantum well structure may be a multiple quantum well structure or a single quantum well structure. In the light emitting device 100, if the well layer in the light emitting layer 4 is too thick, electrons and holes injected into the well layer are caused by a piezo electric field caused by lattice mismatch in the quantum well structure. It is presumed that the recombination efficiency decreases and the light emission efficiency decreases. “Electron and hole are spatially separated” means that electrons and holes are separated at both ends of the well layer (p-type nitride semiconductor layer 5 side and n-type nitride semiconductor layer 3 side). To do. Further, in the light emitting layer 4, when the thickness of the well layer is too thin, it is presumed that the carrier confinement effect is lowered and the light emission efficiency is lowered. For this reason, it is preferable that the thickness of a well layer is about 1 nm-5 nm, for example, and it is more preferable that it is about 1.3 nm-3 nm. Moreover, it is preferable that the thickness of a barrier layer is about 5 nm-15 nm, for example. In the light emitting device 100, as an example, the thickness of the well layer is set to 2 nm, and the thickness of the barrier layer is set to 10 nm. The light-emitting element 100 is not limited to the configuration in which the light-emitting layer 4 has a quantum well structure. For example, the light-emitting element 100 may have a double hetero structure in which the light-emitting layer 4 is sandwiched between the n-type nitride semiconductor layer 3 and the p-type nitride semiconductor layer 5. Good.

  The light emitting element 100 preferably includes a cap layer 6 between the light emitting layer 4 and the p-type nitride semiconductor layer 5. The cap layer 6 is a diffusion preventing layer for suppressing impurities in the p-type nitride semiconductor layer 5 from diffusing into the light emitting layer 4. Examples of the impurities in the p-type nitride semiconductor layer 5 include acceptor impurities in the p-type nitride semiconductor layer 5.

The cap layer 6 is an Al _w Ga _1-w N layer (0 <w <1). The Al composition ratio w of the Al _w Ga _1-w N layer (0 <w <1) is, for example, 0.55. The Al composition ratio w in the Al _w Ga _1-w N layer (0 <w <1) is not limited to 0.55, but is larger than the Al composition ratio in the well layer, and the Al content in the electron block layer 51 described later. What is necessary is just to be smaller than a composition ratio. The thickness of the cap layer 6 is 5 nm, for example.

  The p-type nitride semiconductor layer 5 includes at least a p-type AlGaN layer 52. The p-type nitride semiconductor layer 5 preferably includes, for example, an electron block layer 51 and a p-type contact layer 53 in addition to the p-type AlGaN layer 52.

The electron blocking layer 51 is preferably provided between the light emitting layer 4 and the p-type AlGaN layer 52. In the electron block layer 51, among the electrons injected from the n-type nitride semiconductor layer 3 into the light emitting layer 4, electrons not recombined with holes in the light emitting layer 4 leak to the p-type AlGaN layer 52 side (overflow). ) Is a layer for suppressing. The electron block layer 51 can be composed of a p-type Al _c Ga _1-c N layer (0 <c <1). The Al composition ratio c of the p-type Al _c Ga _1-c N layer (0 <c <1) is, for example, 0.9. The composition ratio of the p-type Al _c Ga _1-c N layer (0 <c <1) is such that the band gap energy of the electron block layer 51 is higher than the band gap energy of the p-type AlGaN layer 52 or the barrier layer. Preferably it is set. The thickness of the electron block layer 51 is 30 nm as an example. In the light emitting device 100, if the electron blocking layer 51 is too thin, the effect of suppressing the overflow of electrons is reduced, and if the electron blocking layer 51 is too thick, the resistance of the light emitting device 100 may increase. The thickness of the electron blocking layer 51 varies depending on the Al composition ratio c, the hole concentration, and the like, so it cannot be generally stated, but it is preferably 1 nm to 50 nm, for example. It is more preferable that the thickness is 5 nm to 25 nm. As the acceptor impurity of the electron block layer 51, for example, Mg is preferable.

The p-type AlGaN layer 52 is a layer for transporting holes to the light emitting layer 4. The p-type AlGaN layer 52 is preferably composed of a p-type Al _d Ga _1-d N layer (0 <d <1). p-type Al _d Ga _1-d N layer composition ratio of (0 <d <1) is the ultraviolet radiation emitted from the light emitting layer 4, p-type Al _d Ga _1-d N layer (0 <d <1) in It is preferable to set so that absorption can be suppressed. For example, when the Al composition ratio of the well layer in the light emitting layer 4 is 0.5 and the Al composition ratio b of the barrier layer is 0.7, a p-type Al _d Ga _1-d N layer (0 <d <1) The Al composition ratio d can be set to 0.55, for example, which is the same as the Al composition ratio b of the barrier layer. That is, when the well layer of the light emitting layer 4 is composed of an Al _0.45 Ga _0.55 N layer, the p-type AlGaN layer 52 can be constituted by, for example, a p-type Al _0.55 Ga _0.45 N layer. The Al composition ratio of the p-type AlGaN layer 52 is not limited to the same as the Al composition ratio b of the barrier layer, and may be different. As the acceptor impurity of the p-type AlGaN layer 52, for example, Mg is preferable.

  The hole concentration of the p-type AlGaN layer 52 is preferably higher in the hole concentration range where the film quality of the p-type AlGaN layer 52 does not deteriorate. However, since the hole concentration of the p-type AlGaN layer 52 is lower than the electron concentration of the n-type nitride semiconductor layer 3 in the light-emitting element 100, if the thickness of the p-type AlGaN layer 52 is too thick, the resistance of the light-emitting element 100 is reduced. Is too big. For this reason, the thickness of the p-type AlGaN layer 52 is preferably 200 nm or less, and more preferably 100 nm or less. In the light emitting device 100, as an example, the thickness of the p-type AlGaN layer 52 is set to 50 nm.

  The p-type nitride semiconductor layer 5 can be configured to suitably include a p-type contact layer 53 on the p-type AlGaN layer 52.

The p-type contact layer 53 is provided in order to reduce the contact resistance of the positive electrode 8 with the first contact electrode 81 and obtain good ohmic contact with the first contact electrode 81. The p-type contact layer 53 is preferably composed of, for example, a p-type GaN layer. The hole concentration of the p-type GaN layer constituting the p-type contact layer 53 is preferably higher than that of the p-type AlGaN layer 52. In the p-type contact layer 53 composed of the p-type GaN layer, for example, by setting the hole concentration to about 7 × 10 ¹⁷ cm ⁻³ , good ohmic contact with the first contact electrode 81 can be obtained. It is. However, the hole concentration of the p-type GaN layer may be changed as appropriate within the range of the hole concentration at which good ohmic contact with the positive electrode 8 is obtained. The thickness of the p-type contact layer 53 is preferably 50 nm to 300 nm, for example. As an example, the thickness of the p-type contact layer 53 is set to 200 μm.

  As can be seen from the above description, the light emitting element 100 includes the substrate 1 that supports the nitride semiconductor layer 20 that is a stacked body including the n-type nitride semiconductor layer 3, the light emitting layer 4, and the p-type nitride semiconductor layer 5. Prepare. The substrate 1 is a single crystal substrate. The substrate 1 transmits ultraviolet rays emitted from the light emitting layer 4. The nitride semiconductor layer 20 includes, for example, a configuration including a first buffer layer 2a, a second buffer layer 2b, an n-type nitride semiconductor layer 3, a light emitting layer 4, a cap layer 6, and a p-type nitride semiconductor layer 5. can do. In the nitride semiconductor layer 20, the first buffer layer 2a, the second buffer layer 2b, the cap layer 6, the electron block layer 51, and the p-type contact layer 53 may be provided as appropriate. The nitride semiconductor layer 20 is provided on the first surface 1 a that is one surface of the substrate 1. The n-type nitride semiconductor layer 3, the light emitting layer 4, and the p-type nitride semiconductor layer 5 are arranged in this order from the first surface 1a of the substrate 1. The nitride semiconductor layer 20 can be formed by an epitaxial growth method. The epitaxial growth method is, for example, a MOVPE (metal organic vapor phase epitaxy) method. The nitride semiconductor layer 20 may contain impurities such as H, C, O, Si, and Fe that are inevitably mixed when the nitride semiconductor layer 20 is formed. The epitaxial growth method is not limited to the MOVPE method, and may be, for example, an HVPE (hydride vapor phase epitaxy) method, an MBE (molecular beam epitaxy) method, or the like.

  The light emitting device 100 has a mesa structure 22. The mesa structure 22 is formed by etching a part of the nitride semiconductor layer 20 from the surface 20 a side of the nitride semiconductor layer 20 to the middle of the n-type nitride semiconductor layer 3. Thus, the light emitting device 100 forms a step in the n-type AlGaN layer 31 to expose the surface 312a of the second region 312 of the n-type AlGaN layer 31. The distance from the surface 312 a of the second region 312 to the first surface 1 a of the substrate 1 is shorter than the distance from the surface 311 a of the first region 311 to the first surface 1 a of the substrate 1.

The electrical insulating film 10 includes a part of the upper surface 22 a of the mesa structure 22 (the surface 20 a of the nitride semiconductor layer 20), the side surface 22 c of the mesa structure 22, and the surface 312 a of the second region 312 in the n-type AlGaN layer 31. It is preferable that it is formed across the part. As a result, in the light emitting element 100, the side surface 6 c of the cap layer 6 is also covered with the electrical insulating film 10 in the mesa structure 22. The electrical insulating film 10 is a film having electrical insulation properties. The electrical insulating film 10 is a silicon oxide film. The silicon oxide film is preferably a SiO ₂ film. For example, the thickness of the electrical insulating film 10 is 800 nm.

  The first contact electrode 81 of the positive electrode 8 is an ohmic contact electrode formed on the surface 5 a of the p-type nitride semiconductor layer 5. For example, the first contact electrode 81 is formed by forming a stacked film of an Ni film and an Au film (hereinafter also referred to as “first stacked film”) on the surface 5 a of the p-type nitride semiconductor layer 5. It is formed by performing an annealing process. Therefore, the first contact electrode 81 includes Ni and Au as constituent elements. The first laminated film is composed of a Ni film directly formed on the surface 5a of the p-type nitride semiconductor layer 5 and an Au film directly formed on the Ni film. For example, in the first laminated film, the thickness of the Ni film is set to 30 nm, and the thickness of the Au film is set to 200 nm.

  The first pad electrode 82 of the positive electrode 8 is an external connection electrode. In other words, the first pad electrode 82 is a mounting electrode. More specifically, in the light emitting device 100, a conductive wire, a conductive bump, or the like is bonded to the first pad electrode 82 when mounted on a package, a wiring board, or the like. For example, an Au wire or the like is employed as the conductive wire. As the conductive bump, for example, an Au bump or the like is employed.

  The first pad electrode 82 is formed across the first contact electrode 81 and the electrical insulating film 10 in plan view. In short, the first pad electrode 82 is formed so as to include the first contact hole 101 and the periphery of the first contact hole 101 on the surface of the electrical insulating film 10 in plan view. In other words, in the light emitting element 100, the first contact hole 101 and the electric insulating film 10 are formed in the vertical projection region of the first pad electrode 82 along the projection direction in the thickness direction of the p-type nitride semiconductor layer 5. And a peripheral edge of the first contact hole 101 on the surface.

  The first pad electrode 82 preferably has a structure in which a plurality of (for example, four) metal layers are stacked. Hereinafter, the four metal layers in the first pad electrode 82 are also referred to as a first metal layer, a second metal layer, a third metal layer, and a fourth metal layer in order from the side closer to the p-type nitride semiconductor layer 5.

  In the first pad electrode 82, the first metal layer, the second metal layer, the third metal layer, and the fourth metal layer are constituted by a Ti layer, an Al layer, a Ti layer, and an Au layer, respectively. The thicknesses of the first metal layer, the second metal layer, the third metal layer, and the fourth metal layer in the first pad electrode 82 are, for example, 100 nm, 250 nm, 100 nm, and 1300 nm, respectively. The material of the first metal layer in the first pad electrode 82 is preferably one selected from the group of Ti, Mo, Cr and W. Accordingly, in the light emitting element 100, it is possible to improve the adhesion between the first metal layer and the first contact electrode 81 in the first pad electrode 82.

  The second contact electrode 91 of the negative electrode 9 is formed on the surface 312 a of the second region 312 in the n-type AlGaN layer 31.

  The second contact electrode 91 is an ohmic contact electrode formed on the surface 312 a of the second region 312 of the n-type AlGaN layer 31. As an example, the second contact electrode 91 is a laminated film of an Al film, a Ni film, an Al film, a Ni film, and an Au film (hereinafter also referred to as a “second laminated film”) of the n-type AlGaN layer 31. It is formed by forming on the surface 312a of the region 312 and then performing annealing treatment and slow cooling. Therefore, the second contact electrode 91 includes Al, Ni, and Au as constituent elements. In the second stacked film, an Al film, a Ni film, an Al film, a Ni film, and an Au film are formed in this order from the side closer to the surface 312 a of the second region 312 of the n-type AlGaN layer 31. The thicknesses of the Al film, Ni film, Al film, Ni film, and Au film in the second stacked film are, for example, 200 nm, 30 nm, 200 nm, 30 nm, and 200 nm, respectively.

  The second contact electrode 91 is composed of a solidified structure mainly composed of Ni and Al. Thereby, in the light emitting device 100, it is possible to reduce the contact resistance between the n-type AlGaN layer 31 and the second contact electrode 91. The “solidified structure” means a crystal structure formed as a result of transformation of a molten metal into a solid. In other words, the solidified structure is a molten solidified structure formed by solidification of a molten metal containing Ni and Al. The solidified structure mainly composed of Ni and Al may contain, for example, Au and N as impurities.

  In the light emitting device 100, by reducing the contact resistance between the n-type AlGaN layer 31 and the second contact electrode 91, the operating voltage of the light emitting device 100 can be reduced, and the light emission luminance can be improved. Is possible.

  The second contact electrode 91 is not limited to the configuration mainly composed of Ni and Al, but may be composed of another material including Ti or the like.

  In the light emitting element 100, the contact between the n-type AlGaN layer 31 and the second contact electrode 91 in the negative electrode 9 is an ohmic contact. Here, the “ohmic contact” means a contact having no current rectification caused by the direction of the applied voltage among the contact between the n-type AlGaN layer 31 and the second contact electrode 91. The ohmic contact is preferably substantially linear in current-voltage characteristics, and more preferably linear. Moreover, it is preferable that ohmic contact has a smaller contact resistance. In the contact between the n-type AlGaN layer 31 and the second contact electrode 91, the current passing through the interface between the n-type AlGaN layer 31 and the second contact electrode 91 causes a thermionic emission current to overcome the Schottky barrier. This is thought to be the sum of the tunnel current passing through the Schottky barrier. For this reason, in the contact between the n-type AlGaN layer 31 and the second contact electrode 91, it is considered that an ohmic contact is approximately realized when the tunnel current is dominant.

  The second pad electrode 92 of the negative electrode 9 is an external connection electrode. In other words, the second pad electrode 92 is a mounting electrode. More specifically, in the light emitting device 100, a conductive wire, a conductive bump, or the like is bonded to the second pad electrode 92 when mounted on a package, a wiring board, or the like.

  The second pad electrode 92 is formed across the second contact electrode 91 and the electrical insulating film 10 in plan view. In short, the second pad electrode 92 is formed so as to include the second contact hole 102 and the periphery of the second contact hole 102 on the surface of the electrical insulating film 10 in plan view. In other words, in the light emitting element 100, the second contact hole 102 and the surface of the electrical insulating film 10 are in the vertical projection region of the second pad electrode 92 along the projection direction in the thickness direction of the n-type AlGaN layer 31. And a peripheral edge of the second contact hole 102.

  The second pad electrode 92 has a structure in which a plurality of (for example, four) metal layers are stacked. Hereinafter, the four metal layers in the second pad electrode 92 are arranged in order from the side closer to the surface 312a of the second region 312 in the n-type AlGaN layer 31, in order from the first metal layer, the second metal layer, the third metal layer, and the second metal layer. Also referred to as 4 metal layers.

  In the second pad electrode 92, the first metal layer, the second metal layer, the third metal layer, and the fourth metal layer are constituted by a Ti layer, an Al layer, a Ti layer, and an Au layer, respectively. The thicknesses of the first metal layer, the second metal layer, the third metal layer, and the fourth metal layer in the second pad electrode 92 are set to 100 nm, 250 nm, 100 nm, and 1300 nm, respectively. The material of the first metal layer in the second pad electrode 92 is preferably one selected from the group of Ti, Mo, Cr and W. As a result, in the light emitting element 100, the adhesion between the first metal layer and the second contact electrode 91 in the second pad electrode 92 can be improved.

  In the light emitting element 100, it is preferable that the first pad electrode 82 and the second pad electrode 92 have the same stacked structure and are formed of the same material. Thereby, when manufacturing the light emitting element 100, it becomes possible to form the 1st pad electrode 82 and the 2nd pad electrode 92 simultaneously.

  The passivation film 11 is a protective insulating film for ensuring the moisture resistance of the light emitting element 100 and has a function of blocking moisture and sodium ions. The passivation film 11 is formed on the end of the surface 8a of the positive electrode 8 (surface of the first pad electrode 82), the side surface of the first pad electrode 82, and the surface 9a of the negative electrode 9 (surface of the second pad electrode 92). It is formed so as to cover the end portion, the side surface of the second pad electrode 92, and the electrical insulating film 10. As a result, in the light emitting element 100, the end portion of the first pad electrode 82, the end portion of the second pad electrode 92, and the electrical insulating film 10 are covered with the passivation film 11. The passivation film 11 includes an opening 111 that exposes the central portion of the surface 8 a of the positive electrode 8 (hereinafter also referred to as “first opening 111”) and an opening that exposes the central portion of the surface 9 a of the negative electrode 9. 112 (hereinafter also referred to as “second opening 112”). Therefore, “the end portion of the surface 8 a of the positive electrode 8” is a portion of the surface 8 a of the positive electrode 8 that overlaps with the peripheral portion of the first opening 111 in the passivation film 11. Similarly, “the end portion of the surface 9 a of the negative electrode 9” is a portion of the surface 9 a of the negative electrode 9 that overlaps with the peripheral portion of the second opening 112 in the passivation film 11.

  The first opening 111 is preferably formed in a shape in which the opening area gradually increases as the distance from the p-type nitride semiconductor layer 5 increases in the thickness direction of the p-type nitride semiconductor layer 5. The inner surface of the first opening 111 in the passivation film 11 is preferably formed in a tapered shape.

  Since the inner surface of the second opening 112 is tapered, the opening area gradually increases as the distance from the surface 312a of the second region 312 of the n-type AlGaN layer 31 increases in the thickness direction of the n-type AlGaN layer 31. It is preferable to form in a large shape. The inner surface of the second opening 112 in the passivation film 11 is preferably formed in a tapered shape.

The passivation film 11 has electrical insulation. For example, the thickness of the passivation film 11 is 700 nm. The passivation film 11 is formed by patterning a silicon nitride film formed by a plasma CVD apparatus (plasma-enhanced chemical vapor deposition system). Thereby, the passivation film 11 can make moisture permeability smaller than that of the silicon oxide film. Therefore, in the light emitting element 100, moisture resistance can be improved. When a silicon nitride film is formed by a plasma CVD apparatus, it is preferable to employ SiH ₄ as the Si source gas and NH ₃ as the N source gas.

The composition of the silicon nitride film is preferably a Si ₃ N _4, may be shifted from the Si ₃ N _4. However, the passivation film 11 is a silicon nitride film containing hydrogen, and includes Si—H bonds and H—N bonds in addition to Si—N bonds. Whether or not the passivation film 11 contains Si—H bonds and H—N bonds can be known by analysis using Fourier transform infrared spectroscopy, for example. In other words, the criterion for determining whether or not the passivation film 11 includes Si—H bonds and H—N bonds depends on the detection limit of analysis by Fourier transform infrared spectroscopy. The concentration of hydrogen in the passivation film 11 is, for example, about 2 to 3 × 10 ²² cm ⁻³ . The concentration of hydrogen in the passivation film 11 can be known, for example, by analysis using Fourier transform infrared spectroscopy. In addition, in the silicon nitride film | membrane formed into a film by the ECR sputtering apparatus (electron cyclotron resonance sputtering system), as a result of the analysis by a Fourier transform infrared spectroscopy, all of content of Si-H bond, HN bond, and hydrogen It was below the respective detection limit.

Each of the first peeling prevention layer 12a and the second peeling prevention layer 12b is a functional layer for preventing the passivation film 11 from peeling. As an example, the thickness of each of the first peeling prevention layer 12a and the second peeling prevention layer 12b is 20 nm. For example, each of the first peeling prevention layer 12a and the second peeling prevention layer 12b includes a lower layer 121 made of Ti and an upper layer 122 made of an oxide of Ti. The oxide of Ti is TiO _x1 (x1 = 1, 2). The upper layer 122 is preferably made of TiO ₂ . As a method of forming each of the first peeling prevention layer 12a and the second peeling prevention layer 12b, for example, a Ti layer that forms the basis of the lower layer 121 and the upper layer 122 is formed, and then the surface side of the Ti layer is oxidized. There is a way to do it. Here, in each of the first peeling prevention layer 12a and the second peeling prevention layer 12b, the oxidized portion of the Ti layer constitutes the upper layer 122, and the unoxidized portion of the Ti layer constitutes the lower layer 121. . As an oxidation treatment for oxidizing the surface side of the Ti layer, for example, there is an O ₂ plasma treatment under reduced pressure. Each formation method of the 1st peeling prevention layer 12a and the 2nd peeling prevention layer 12b is not restricted to the above-mentioned example. For example, in the formation method of each of the first peeling prevention layer 12a and the second peeling prevention layer 12b, after forming the Ti layer, a TiO _x1 layer (with a target material of TiO _x1 (x1 = 1, 2)) ( x1 = 1, 2) to form the same laminated structure as each of the first peeling prevention layer 12a and the second peeling prevention layer 12b, and then patterning the laminated structure to form the first peeling prevention layer 12a and The second peeling prevention layer 12b may be formed. Further, in each of the forming methods of the first peeling preventing layer 12a and the second peeling preventing layer 12b, after forming the Ti layer, a TiO _x1 layer (x1 = 1) is formed by sputtering in an oxidizing atmosphere using Ti as a target material. 2) is formed to form the same laminated structure as each of the first peeling prevention layer 12a and the second peeling prevention layer 12b, and then the first peeling prevention layer 12a and the second peeling layer are patterned by patterning the lamination structure. The prevention layer 12b may be formed. Further, in each of the forming methods of the first peeling preventing layer 12a and the second peeling preventing layer 12b, after forming the Ti layer, a TiO _x1 layer (x1) is formed by ion beam evaporation in an oxidizing atmosphere using Ti as an evaporation source. = 1, 2) to form the same laminated structure as each of the first peeling prevention layer 12a and the second peeling prevention layer 12b, and then patterning the laminated structure to form the first peeling prevention layer 12a and the first peeling prevention layer 12a. 2 You may form the peeling prevention layer 12b. “Oxidizing atmosphere” means an atmosphere containing oxidizing species. Examples of the oxidizing species include atomic oxygen, oxygen molecules, ozone, oxygen radicals, and oxygen ions. The oxidizing atmosphere can be realized, for example, by introducing oxygen gas into the chamber of the sputtering apparatus.

  Incidentally, the inventors of the present application produced a semiconductor light emitting device of Comparative Example 1 (hereinafter, abbreviated as “light emitting device”) and evaluated its moisture resistance at the research stage of developing the light emitting device 100. The light emitting element of Comparative Example 1 has substantially the same basic configuration as that of the light emitting element 100, and each of the first pad electrode 82 and the second pad electrode 92 in the light emitting element 100 is composed of only an Au layer, and the first peeling prevention layer 12a. And the point which is not providing the 2nd peeling prevention layer 12b is different. About the light emitting element of the comparative example 1, the same code | symbol is attached | subjected and demonstrated to the component similar to the light emitting element 100, and is demonstrated.

In order to evaluate the moisture resistance of the light emitting device of Comparative Example 1, the inventors of the present application conducted a high-temperature and high-humidity energization test, an electrical property evaluation, an optical microscope, and an appearance inspection using a scanning electron microscope (SEM). It was. The high-temperature and high-humidity current test is THB (Temperature Humidity Bias test). In the high-temperature and high-humidity energization test, the temperature was 60 ° C., the relative humidity was 80 RH%, the energization current was 20 mA, and the continuous energization time was 2000 hours. The inventors of the present application have found that the light emitting device of Comparative Example 1 needs further improvement in moisture resistance. More specifically, the inventors of the present application have found that a defect may occur in the light-emitting element of Comparative Example 1 during the high-temperature and high-humidity current test. Problems include open defects, corrosion of the region immediately below the negative electrode 9 in the n-type AlGaN layer 31, damage to the end of the second pad electrode 92, and a site on the damaged portion of the end of the second pad electrode 92 in the passivation film 11. Breakage, etc. The corrosion of the region immediately below the negative electrode 9 in the n-type AlGaN layer 31 means the oxidation of the region immediately below the second contact electrode 91 in the n-type AlGaN layer 31 and means that Al ₂ O ₃ is formed. In addition, in the light emitting device of Comparative Example 1, the present inventors have found that the p-type contact layer 53 made of the p-type GaN layer does not corrode or the end portion of the first pad electrode 82 is damaged even when the above-described problem occurs. The knowledge that it does not occur was obtained.

  The inventors of the present application have considered the following estimation mechanism for the mechanism by which the above-described problems occur in the light emitting element of Comparative Example 1.

Moisture that has entered from the outside through defects such as pinholes and cracks in the passivation film 11 passes through n-type AlGaN through the grain boundaries of the Au layer constituting the second pad electrode 92 of the negative electrode 9 and defects such as pinholes and cracks. The surface 312a of the second region 312 of the layer 31 is reached. At this time, in the light emitting element of Comparative Example 1, if a current flows from the positive electrode 8 to the negative electrode 9 and holes (h ⁺ ) are generated in the n-type AlGaN layer 31, the AlN in the n-type AlGaN layer 31 is generated. Due to this, the following electrochemical reaction takes place near the surface 312a of the second region 312.

2AlN + 6h ⁺ → 2Al ³⁺ + N ₂
2Al ³⁺ + 6OH ⁻ → Al ₂ O ₃ + 3H ₂ O
In short, in the light emitting device of Comparative Example 1, N ₂ is generated in the vicinity of the surface 312a of the second region 312 of the n-type AlGaN layer 31, and Al ₂ O ₃ is formed by the oxidation reaction, resulting in electrical insulation and volume expansion. Arise. Thereby, in the light emitting device of Comparative Example 1, corrosion of the region immediately below the negative electrode 9 in the n-type AlGaN layer 31, breakage of the end of the second pad electrode 92, end of the second pad electrode 92 in the passivation film 11 The part of the damaged part of the part is damaged. Further, in the light emitting device of Comparative Example 1, when Al ₂ O ₃ is formed, the current path in the second region 312 changes, so that the region to be electrically insulated is expanded, and just below the negative electrode 9 in the second region 312. An open defect occurs in which the part becomes electrically insulated and no current flows.

  Therefore, the inventors of the present application considered that it is important to improve the adhesion of the passivation film 11 in order to improve the moisture resistance of the light emitting element of Comparative Example 1.

  In the light emitting element 100, by providing the first peeling prevention layer 12a and the second peeling prevention layer 12b, it is possible to improve the adhesion of the passivation film 11 and improve the moisture resistance as compared with Comparative Example 1. Is possible. The inventors of the present application conducted extensive research and development on the underlayer of a silicon nitride film containing hydrogen, and evaluated the adhesion between the silicon nitride film and the underlayer. For evaluation of adhesion, an evaluation sample was prepared and evaluated by a scratch test defined in JIS H0211-1992. The evaluation sample is a sample in which a base layer is formed on a silicon wafer and a silicon nitride film is formed on the base layer by a plasma CVD apparatus. In the evaluation of adhesion, the fracture energy (load at the time of peeling) of the silicon nitride film measured in the scratch test was regarded as the adhesion. As a result, the inventors of the present application made the silicon nitride film as compared with the case where the underlayer is formed of only the Ti layer by making the underlayer the same structure as the first exfoliation prevention layer 12a and the second exfoliation prevention layer 12b. Experimental results have been obtained that the fracture energy (load when the silicon nitride film peels) increases and adhesion improves. The inventors of the present application have found that the adhesion is improved by making the underlayer the same structure as the first anti-peeling layer 12a and the second anti-peeling layer 12b, so that N is formed in the vicinity of the interface between the silicon nitride film and the underlayer. It is presumed that this is because the —H bond H or the Si—H bond H and the O—Ti bond O are bonded to form an O—H bond having a relatively large bond energy.

In the light emitting device 100, Comparative Example 2 that does not include the first peeling prevention layer 12a and the second peeling prevention layer 12b, and a comparison that includes a Ti layer instead of each of the first peeling prevention layer 12a and the second peeling prevention layer 12b. Compared to Comparative Example 4 in which Example 3 is replaced with each of the first peeling prevention layer 12a and the second peeling prevention layer 12b and a TiO ₂ layer is provided, it is possible to improve moisture resistance and improve reliability. Is possible. For the evaluation of moisture resistance, a high-temperature and high-humidity energization test was performed, and electrical characteristics were evaluated, an optical microscope, an appearance inspection using an SEM, and the like were performed. In Comparative Example 4, an experimental result was obtained that the laminated structure of the passivation film 11 and the TiO ₂ layer peeled off from the positive electrode 8 and the negative electrode 9 during the high-temperature and high-humidity energization test.

  Below, the manufacturing method of the light emitting element 100 is demonstrated.

(1) Preparation of wafer The wafer is a disk-shaped substrate. When the substrate 1 in the light emitting element 100 is a sapphire substrate, a sapphire wafer can be adopted as the wafer. The first surface of the sapphire wafer corresponds to the first surface 1 a of the substrate 1. Therefore, the first surface of the sapphire wafer preferably has an off angle from the (0001) plane of 0 ° to 0.5 °.

(2) Step of laminating nitride semiconductor layer 20 on the first surface of the wafer In this step, the nitride semiconductor layer 20 is formed by an epitaxial growth apparatus. The epitaxial growth apparatus preferably employs a reduced pressure MOVPE apparatus.

Trimethylaluminum (TMAl) is preferably employed as the Al source gas. Trimethylgallium (TMGa) is preferably employed as the Ga source gas. As the N source gas, NH ₃ is preferably employed. It is preferable to employ tetraethylsilane (TESi) as a source gas of Si that is an impurity imparting n-type conductivity. It is preferable to employ biscyclopentadienyl magnesium (Cp ₂ Mg) as a source gas for Mg, which is an impurity contributing to p-type conductivity. For example, H ₂ gas is preferably used as the carrier gas of each source gas.

  The growth conditions of the nitride semiconductor layer 20 may be set as appropriate such as the substrate temperature, the V / III ratio, the supply amount of each source gas, the growth pressure, and the like. “V / III ratio” means the molar supply of the source gas of N which is a group V element to the total molar supply amount [μmol / min] of the source gas of group III element (Al source gas, Ga source gas) It is a ratio to the amount [μmol / min]. The “growth pressure” is the pressure in the reaction furnace in a state where each source gas and each carrier gas are supplied into the reaction furnace of the MOVPE apparatus.

  The epitaxial growth method of the nitride semiconductor layer 20 is not limited to the MOVPE apparatus, and may be, for example, an MBE apparatus, an HVPE apparatus, or the like.

(3) Step of performing annealing for activating the p-type impurity This step is a step of activating the p-type impurity of the p-type nitride semiconductor layer 5 in the annealing furnace of the annealing apparatus. More specifically, in this step, the p-type impurities in the electron block layer 51, the p-type AlGaN layer 52, and the p-type contact layer 53 in the p-type nitride semiconductor layer 5 are activated. The annealing conditions are set such that the annealing temperature is 600 to 800 ° C. and the annealing time is 10 to 50 minutes. As the annealing apparatus, for example, a lamp annealing apparatus, an electric furnace annealing apparatus, or the like can be employed.

(4) Step of forming mesa structure 22 In this step, a first resist layer is formed on the surface 20a of the nitride semiconductor layer 20 on a region corresponding to the upper surface 22a of the mesa structure 22 by using a photolithography technique. Form. In this step, the mesa structure 22 is formed by etching a part of the nitride semiconductor layer 20 from the surface 20a side to the middle of the n-type nitride semiconductor layer 3 using the first resist layer as a mask. Thereafter, the first resist layer is removed. The nitride semiconductor layer 20 is preferably etched using, for example, a dry etching apparatus. As the dry etching apparatus, for example, an inductively coupled plasma etching system is preferable.

(5) Step of Forming Electrical Insulating Film 10 In this step, a silicon oxide film that forms the basis of the electrical insulating film 10 is formed on the entire surface on the first surface side of the wafer by, for example, an atmospheric pressure CVD apparatus. In this step, the first contact hole 101 and the second contact hole 102 are opened in the silicon oxide film on the first surface side of the wafer. In short, in this step, the electrical insulating film 10 is formed by patterning the silicon oxide film. The patterning of the silicon oxide film is performed using, for example, a photolithography technique and an etching technique.

(6) Step of Forming Second Contact Electrode 91 in Negative Electrode 9 In this step, first, only the region where negative electrode 9 is to be formed (that is, the second region in n-type AlGaN layer 31) on the first surface side of the wafer. A first step of forming a second resist layer patterned so that a part of the surface 312a of the 312 is exposed is performed. In this step, a second layer in which an Al film, a Ni film, an Al film, a Ni film, and an Au film are sequentially stacked on the surface 312a of the second region 312 in the n-type AlGaN layer 31 from the side close to the surface 312a. A second step of forming a laminated film with an electron beam evaporation apparatus is performed. In this step, the thicknesses of the Al film, Ni film, Al film, Ni film, and Au film in the second stacked film are set to 200 nm, 30 nm, 200 nm, 30 nm, and 200 nm, respectively. In this process, after the second laminated film is formed, a third step of removing the unnecessary film on the second resist layer and the second resist layer is performed by performing lift-off. Further, in this step, a fourth step of forming the second contact electrode 91 by performing an annealing process and performing slow cooling is performed. The annealing treatment is preferably RTA (Rapid Thermal Annealing) in an N ₂ gas atmosphere. In this step, it is preferable to perform an annealing process using an infrared annealing apparatus.

  The RTA treatment conditions may be, for example, an annealing temperature of 650 ° C. and an annealing time of 1 minute. The annealing temperature is preferably a temperature equal to or higher than the eutectic point (about 640 ° C.) of AlNi, and preferably 700 ° C. or lower. The annealing temperature may be changed as appropriate based on the Al composition ratio of the n-type AlGaN layer 31. The annealing time is preferably set in the range of about 30 seconds to 3 minutes, for example. “Eutectic point” means the temperature at which a liquid eutectic mixture solidifies when it produces a solid phase of the same composition.

  “Slow cooling” means gradually cooling. The cooling rate when performing slow cooling may be, for example, 30 ° C./min. The cooling rate is not limited to 30 ° C./min, and is preferably set as appropriate in the range of 20 to 60 ° C./min, for example.

(7) Step of Forming First Contact Electrode 81 in Positive Electrode 8 In this step, first contact electrode 81 is formed on surface 5a of p-type nitride semiconductor layer 5.

More specifically, in this step, first, a third pattern patterned so that only a region where the positive electrode 8 is to be formed on the first surface side of the wafer (a part of the surface 53a of the p-type contact layer 53) is exposed. A resist layer is formed. In this step, for example, a first laminated film of a Ni film having a thickness of 30 nm and an Au film having a thickness of 200 nm is formed by an electron beam evaporation apparatus, and lift-off is performed, whereby the third resist layer and the third film are formed. The unnecessary film on the resist layer is removed. Furthermore, in this step, RTA treatment is performed in an N ₂ gas atmosphere so that the contact between the first contact electrode 81 and the p-type nitride semiconductor layer 5 is an ohmic contact. The RTA treatment conditions may be, for example, an annealing temperature of 500 ° C. and an annealing time of 15 minutes.

(8) Step of Forming First Pad Electrode 82 of Positive Electrode 8 and Second Pad Electrode 92 of Negative Electrode 9 In this step, first, first pad electrode 82 and second pad electrode 92 on the first surface side of the wafer. A fourth resist layer patterned so as to expose only the respective formation planned regions is formed. In this step, for example, a stacked film of a 100 nm thick Ti layer, a 250 nm thick Al layer, a 100 nm thick Ti layer, and a 1300 nm thick Au layer is formed by an electron beam evaporation apparatus. A first pad electrode 82 and a second pad electrode 92 are formed. Thereafter, in this step, lift-off is performed to remove the fourth resist layer and the unnecessary film on the fourth resist layer.

(9) Step of forming first peeling prevention layer 12a and second peeling prevention layer 12b In this step, first, a Ti layer having a thickness of 20 nm, for example (hereinafter referred to as “first Ti layer”) is formed on the entire first surface side of the wafer. Is also formed by an electron beam evaporation apparatus. In this step, a laminated structure of the _second Ti layer and the TiO ₂ layer is formed on the entire surface on the first surface side of the wafer by oxidizing the surface side of the first Ti layer by oxidation treatment. The second Ti layer is thinner than the first Ti layer. The oxidation treatment is preferably O ₂ plasma treatment under reduced pressure. In short, in the oxidation treatment, it is preferable to perform plasma oxidation from the viewpoint of reducing the manufacturing cost. In this step, after the oxidation treatment, the first peeling prevention layer 12a and the second peeling prevention layer 12b are formed by patterning the laminated structure of the _second Ti layer and the TiO ₂ layer. Patterning of the laminated structure of the _second Ti layer and the TiO ₂ layer is performed using a photolithography technique and an etching technique. Etching of the laminated structure of the _second Ti layer and the TiO ₂ layer is preferably performed using a dry etching apparatus. As the dry etching apparatus, for example, a reactive ion etching system is preferable. As the etching gas, a fluorine-based gas may be used. The fluorine-based gas is, for example, CF ₄ .

(10) Step of Forming Passivation Film 11 In this step, a silicon nitride film containing hydrogen serving as a basis for the passivation film 11 is formed on the entire first surface side of the wafer by, for example, a plasma CVD apparatus. The film formation temperature when forming the silicon nitride film containing hydrogen is preferably 350 ° C. or lower. In this step, the silicon nitride film containing hydrogen is patterned so that the first opening 111 and the second opening 112 are opened in the silicon nitride film containing hydrogen on the first surface side of the wafer. Thus, the passivation film 11 is formed. The patterning of the silicon nitride film containing hydrogen is performed using, for example, a photolithography technique and an etching technique.

(11) Step of forming a split groove In this step, a split groove reaching from the surface side of the passivation film 11 of the wafer to the middle of the thickness direction of the wafer is formed. In this step, it is preferable to form the split groove by ablation processing using a laser processing machine. Ablation processing means laser processing under irradiation conditions that cause ablation.

(12) Step of polishing wafer In this step, the wafer is polished from the second surface side opposite to the first surface, so that the wafer is thinned to a thickness corresponding to the predetermined thickness of the substrate 1. In polishing the wafer, it is preferable to sequentially perform a grinding process and a lapping process.

  In the method for manufacturing the light emitting element 100, the wafer on which a plurality of the light emitting elements 100 are formed is completed by completing the step of polishing the wafer. In short, in the method for manufacturing the light emitting element 100, a wafer on which a plurality of the light emitting elements 100 are formed is completed by sequentially performing the steps (1) to (12) described above.

(13) Step of dividing the light emitting element 100 from the wafer (dividing step)
The dividing step is a step of dividing a wafer on which a plurality of light emitting elements 100 are formed into individual light emitting elements 100. In the dividing step, the wafer is divided along the dividing grooves after the lapping step described above. More specifically, in the dividing step, a braking step and an expanding step are performed. After the expanding process, the individual light emitting elements 100 may be picked up with an appropriate pickup tool or the like and the light emitting elements 100 may be stored in a chip tray, for example.

  In the breaking process, for example, the wafer is divided into individual light emitting elements 100 using a blade. In the breaking process, the wafer is sandwiched by two wafer tapes from both sides in the thickness direction. The wafer tape is an adhesive resin tape. After the wafer is divided into the individual light emitting elements 100, the wafer tape disposed on the nitride semiconductor layer 20 side of the wafer is removed from the two wafer tapes.

  In the expanding step, the distance between the adjacent light emitting elements 100 is increased by stretching the wafer tape on the second surface 1b side of the substrate 1 in each light emitting element 100 by, for example, an expanding apparatus.

  In the manufacturing method of the light emitting element 100, by performing the dividing step, a part of the first surface of the sapphire wafer after the lapping step constitutes the first surface 1a of the substrate 1, and a part of the second surface of the sapphire wafer is formed. The second surface 1b of the substrate 1 is configured.

  In the dividing step, a wafer on which a plurality of light emitting elements 100 are formed may be divided into individual light emitting elements 100 by cutting with a dicing saw or the like.

  By the way, the lower layer 121 in each of the first peeling prevention layer 12a and the second peeling prevention layer 12b is not limited to Ti but is formed of one material selected from the group of Ti, Zr, Si, Al, Ni, and Sn. It only has to be done. The upper layer 122 only needs to be formed of an oxide of the material of the lower layer 121.

In short, in each of the first peeling prevention layer 12a and the second peeling prevention layer 12b, the lower layer 121 may be made of Zr and the upper layer 122 may be made of an oxide of Zr. The oxide of Zr is ZrO _x2 (x2 = 1, 2).

In each of the first peeling prevention layer 12a and the second peeling prevention layer 12b, the lower layer 121 may be formed of Si, and the upper layer 122 may be formed of an Si oxide. The oxide of Si is SiO _x3 (x3 = 1, 2).

In each of the first peeling prevention layer 12a and the second peeling prevention layer 12b, the lower layer 121 may be made of Al, and the upper layer 122 may be made of an oxide of Al. The oxide of Al is Al _x4 O _y (x4 = 1, 2, y = 1, 3).

In each of the first peeling prevention layer 12a and the second peeling prevention layer 12b, the lower layer 121 may be formed of Ni, and the upper layer 122 may be formed of an oxide of Ni. The oxide of Ni is NiO _x5 (x5 = 1, 2).

In each of the first peeling prevention layer 12a and the second peeling prevention layer 12b, the lower layer 121 may be formed of Sn, and the upper layer 122 may be formed of Sn oxide. The oxide of Sn is SnO _x6 (x6 = 1, 2).

  The composition of the oxide of the upper layer 122 may deviate from the stoichiometry. In other words, the oxide of the upper layer 122 may have a non-stoichiometric composition.

  The light emitting device 100 of the present embodiment described above includes the n-type nitride semiconductor layer 3, the light emitting layer 4, the p-type nitride semiconductor layer 5, the substrate 1, the positive electrode 8, the negative electrode 9, and the passivation. A film 11. The n-type nitride semiconductor layer 3 has at least an n-type AlGaN layer 31. The light emitting layer 4 is formed on the n-type AlGaN layer 31 and emits ultraviolet rays. The p-type nitride semiconductor layer 5 is formed on the light emitting layer 4. The substrate 1 supports a nitride semiconductor layer 20 including an n-type nitride semiconductor layer 3, a light emitting layer 4, and a p-type nitride semiconductor layer 5. The substrate 1 is a single crystal substrate. The substrate 1 transmits ultraviolet rays emitted from the light emitting layer 4. The positive electrode 8 is formed on the surface 5 a of the p-type nitride semiconductor layer 5. The negative electrode 9 is provided in a portion of the n-type nitride semiconductor layer 3 that is not covered with the light emitting layer 4. The n-type nitride semiconductor layer 3, the light emitting layer 4, and the p-type nitride semiconductor layer 5 are arranged in this order from the substrate 1 side. The n-type AlGaN layer 31 has a first region 311 that overlaps the light emitting layer 4 and a second region 312 that does not overlap the light emitting layer 4, and the surface 312 a of the second region 312 is more substrate than the surface 311 a of the first region 311. A step for retreating to the 1 side is formed. The light emitting layer 4 is formed on the surface 311 a of the first region 311 of the n-type AlGaN layer 31. The negative electrode 9 is formed on the surface 312 a of the second region 312 of the n-type AlGaN layer 31. The passivation film 11 is a silicon nitride film containing hydrogen. The light emitting element 100 includes a first peeling prevention layer 12a interposed between the passivation film 11 and the end portion of the surface 8a of the positive electrode 8, and an intermediate portion between the passivation film 11 and the end portion of the surface 9a of the negative electrode 9. And a second peeling preventing layer 12b. Each of the first peeling prevention layer 12 a and the second peeling prevention layer 12 b includes a lower layer 121 and an upper layer 122 formed on the lower layer 121. The lower layer 121 is made of one material selected from the group consisting of Ti, Zr, Si, Al, Ni, and Sn. The upper layer 122 is formed of an oxide of the material of the lower layer 121. The light emitting element 100 having the above-described configuration can improve reliability. More specifically, in the light emitting device 100, each of the first peeling prevention layer 12a and the second peeling prevention layer 12b includes the lower layer 121 and the upper layer 122, so that the passivation film 11 and the first peeling layer are separated. It becomes possible to improve adhesiveness with each of the prevention layer 12a and the second peeling prevention layer 12b. Therefore, in the light emitting element 100, it is possible to suppress the passivation film 11 from being peeled off from each of the first peel preventing layer 12a and the second peel preventing layer 12b. Thereby, the light emitting element 100 can improve the reliability.

The method for manufacturing the light emitting element 100 includes a first step of forming the first peeling prevention layer 12a and the second peeling prevention layer 12b, and a second step of forming the passivation film 11 after the first step. In the first step, after forming a layer made of one material selected from the group consisting of Ti, Zr, Si, Al, Ni and Sn, the surface side of the layer is oxidized to thereby form the first peeling prevention layer 12a. And the same laminated structure as each of the 2nd peeling prevention layer 12b is formed, and the 1st peeling prevention layer 12a and the 2nd peeling prevention layer 12b are formed by patterning a laminated structure after that. Thereby, in the manufacturing method of the light emitting element 100, it becomes possible to manufacture the light emitting element 100 capable of improving the reliability. In the method for manufacturing the light emitting element 100, since each of the first peeling prevention layer 12a and the second peeling prevention layer 12b includes the lower layer 121 and the upper layer 122, the residue of the material of the upper layer 122 is positive when patterning. It is possible to suppress the remaining of the central portion of the surface 8 a of the electrode 8 and the central portion of the surface 9 a of the negative electrode 9. Thereby, in the manufacturing method of the light emitting element 100, it is possible to improve the manufacturing yield. In the method for manufacturing the light emitting element 100, O ₂ plasma treatment is preferable as the oxidation treatment for oxidizing the surface side of the layer made of one material selected from the group consisting of Ti, Zr, Si, Al, Ni, and Sn. In the method for manufacturing the light emitting element 100, ozone treatment may be employed instead of the O ₂ plasma treatment.

  In the first step, a layer made of one material selected from the group of Ti, Zr, Si, Al, Ni and Sn is formed, and then reactive sputtering or ion beam evaporation in an oxidizing atmosphere. By forming an oxide layer of one material selected from the group consisting of Ti, Zr, Si, Al, Ni and Sn by the same lamination as each of the first peeling prevention layer 12a and the second peeling prevention layer 12b You may make it form the 1st peeling prevention layer 12a and the 2nd peeling prevention layer 12b by forming a structure and then patterning a laminated structure. Also in this case, the manufacturing method of the light emitting element 100 makes it possible to manufacture the light emitting element 100 capable of improving the reliability.

  The materials, numerical values, and the like described in the embodiments are merely preferred examples and are not intended to be limiting. Furthermore, the present invention can be appropriately modified in configuration without departing from the scope of its technical idea.

  For example, the single crystal substrate constituting the substrate 1 is not limited to a sapphire substrate, and may be a group III nitride semiconductor crystal substrate, for example. The group III nitride semiconductor crystal substrate is, for example, an AlN substrate.

  Further, the first contact hole 101 of the electrical insulating film 10 may be larger than the first contact electrode 81 in plan view. In this case, the inner side surface of the first contact hole 101 of the electrical insulating film 10 is separated from the side surface of the first contact electrode 81. In this case, a part of the first pad electrode 82 covering the first contact electrode 81 may be in contact with the surface 5 a of the p-type nitride semiconductor layer 5.

  The first contact hole 101 of the electrical insulating film 10 has an inner surface formed in a tapered shape, so that the opening area gradually increases as the distance from the p-type nitride semiconductor layer 5 increases in the thickness direction of the p-type nitride semiconductor layer 5. It is preferable to be larger.

  Further, the second contact hole 102 of the electrical insulating film 10 may be larger than the second contact electrode 91 in plan view. In this case, the inner side surface of the second contact hole 102 is separated from the side surface of the second contact electrode 91. In this case, a part of the second pad electrode 92 covering the second contact electrode 91 may contact the surface 312 a of the second region 312 in the n-type AlGaN layer 31.

  The second contact hole 102 of the electrical insulating film 10 has an inner surface formed in a tapered shape, so that the second contact hole 102 is separated from the surface 312 a of the second region 312 of the n-type AlGaN layer 31 in the thickness direction of the n-type AlGaN layer 31. The opening area is preferably gradually increased.

  The side surface of the first pad electrode 82 is preferably tapered.

  The side surface of the second pad electrode 92 is preferably tapered.

  Each of the first peeling prevention layer 12 a and the second peeling prevention layer 12 b may be also between the electrical insulating film 10 and the passivation film 11. However, in this case, the first peeling prevention layer 12a and the second peeling prevention layer 12b need to be patterned so that the positive electrode 8 and the negative electrode 9 are not short-circuited.

1 substrate 3 n-type nitride semiconductor layer 31 n-type AlGaN layer 311 first region 311a surface 311c side surface 312 second region 312a surface 4 light emitting layer 5 p-type nitride semiconductor layer 5a surface 8 positive electrode 8a surface 81 first contact electrode 82 First pad electrode 9 Negative electrode 9a Surface 91 Second contact electrode 92 Second pad electrode 10 Electrical insulating film 101 First contact hole 102 Second contact hole 11 Passivation film 12a First peeling prevention layer 12b Second peeling prevention layer 121 Lower layer 122 Upper layer 100 Semiconductor light emitting device

Claims (4)

An n-type nitride semiconductor layer having at least an n-type AlGaN layer;
A light emitting layer that is formed on the n-type AlGaN layer and emits ultraviolet light;
A p-type nitride semiconductor layer formed on the light emitting layer;
A substrate that is a single crystal substrate that supports the nitride semiconductor layer including the n-type nitride semiconductor layer, the light-emitting layer, and the p-type nitride semiconductor layer and transmits ultraviolet rays emitted from the light-emitting layer;
A positive electrode formed on the surface of the p-type nitride semiconductor layer;
A negative electrode provided in a portion of the n-type nitride semiconductor layer not covered with the light emitting layer;
A passivation film,
The n-type nitride semiconductor layer, the light emitting layer, and the p-type nitride semiconductor layer are arranged in this order from the substrate side,
The n-type AlGaN layer has a first region that overlaps the light emitting layer and a second region that does not overlap the light emitting layer, and the surface of the second region recedes toward the substrate rather than the surface of the first region. Step to be formed,
The light emitting layer is formed on the surface of the first region of the n-type AlGaN layer,
The negative electrode is formed on the surface of the second region of the n-type AlGaN layer,
The passivation film is a silicon nitride film containing hydrogen,
A first peeling prevention layer interposed between the passivation film and an end of the surface of the positive electrode;
A second peeling prevention layer interposed between the passivation film and the end of the negative electrode surface;
Each of the first peeling prevention layer and the second peeling prevention layer includes a lower layer and an upper layer formed on the lower layer,
The lower layer is formed of one material selected from the group of Ti, Zr, Si, Al, Ni and Sn,
The upper layer is formed of an oxide of the lower layer material,
A semiconductor light emitting element characterized by the above. At least the surface side of the positive electrode is formed of Au,
At least the surface side of the negative electrode is formed of Au,
The semiconductor light-emitting device according to claim 1. The positive electrode includes a first contact electrode that is in ohmic contact with the p-type nitride semiconductor layer, and a first pad electrode formed to cover the first contact electrode,
The negative electrode includes a second contact electrode in ohmic contact with the n-type AlGaN layer, and a second pad electrode formed to cover the second contact electrode,
Further comprising an electrical insulating film made of a silicon oxide film,
The electrical insulating film includes a part and a side surface of the p-type nitride semiconductor layer, a side surface of the light emitting layer, a side surface of the first region of the n-type AlGaN layer, and the side surface of the n-type AlGaN layer. A first contact hole that covers a part of the surface of the second region and in which the first contact electrode is disposed inside, and a second contact hole in which the second contact electrode is disposed on the inside. And
The passivation film is formed so as to cover at least an end of the surface of the positive electrode and an end of the surface of the negative electrode.
The semiconductor light-emitting device according to claim 1 or 2. A method for manufacturing a semiconductor light emitting device according to any one of claims 1 to 3,
A first step of forming the first peel prevention layer and the second peel prevention layer;
A second step of forming the passivation film after the first step,
In the first step, after forming a layer made of one material selected from the group consisting of Ti, Zr, Si, Al, Ni and Sn, the surface side of the layer is oxidized, or in an oxidizing atmosphere By forming an oxide layer of one material selected from the group consisting of Ti, Zr, Si, Al, Ni and Sn by reactive sputtering or ion beam deposition in an oxidizing atmosphere, the first peeling is performed. Forming the same laminated structure as each of the prevention layer and the second peeling prevention layer, and then forming the first peeling prevention layer and the second peeling prevention layer by patterning the lamination structure;
A method for manufacturing a semiconductor light emitting device.

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