JP6323782B2 - Semiconductor light emitting device and method for manufacturing semiconductor light emitting device - Google Patents

Description

  The present invention relates to a semiconductor light emitting device and a method for manufacturing the semiconductor light emitting device.

  Conventionally, a gallium nitride compound semiconductor light emitting device (hereinafter referred to as “semiconductor light emitting device”) is known as a light emitting device (for example, Japanese Patent No. 3482955 (hereinafter referred to as “Document 1”).

  In the semiconductor light emitting device described in Document 1, an n-type gallium nitride compound semiconductor layer, an active layer, and a p-type gallium nitride compound semiconductor layer are sequentially stacked on an insulating substrate. Further, in this semiconductor light emitting device, a part of each of the p-type gallium nitride compound semiconductor layer and the active layer is removed by etching. As a result, the n-type gallium nitride compound semiconductor layer is exposed in the semiconductor light emitting device.

  In the semiconductor light emitting device, a negative electrode (n electrode) in contact with the n-type gallium nitride compound semiconductor layer is formed on the surface of the exposed n-type gallium nitride compound semiconductor layer.

  In Document 1, in forming a negative electrode, a multilayer film composed of a laminated film of a lowermost Ti film, an Al film, and an uppermost Au film is formed and then annealed at 400 ° C. or higher and 1200 ° C. or lower. Is described. Document 1 describes that a preferable ohmic contact between the negative electrode and the n-type gallium nitride compound semiconductor layer can be obtained by the above-described annealing.

  Further, Document 1 describes that the annealing temperature in the above-described annealing is 400 ° C. or higher, more preferably 500 ° C. or higher, and most preferably 600 ° C. or higher.

  The semiconductor light emitting device described above is directed from the positive electrode to the negative electrode by applying a forward bias voltage between the positive electrode (p electrode) and the negative electrode so that the positive electrode is at a higher potential side than the negative electrode. As a result, current flows and holes and electrons combine in the active layer to emit light of a predetermined wavelength.

In WO2012 / 039442 (hereinafter referred to as “Document 2”), an n-electrode (Ti / Al / Ti / Au) formed on an n _- type Al _x Ga _1-x N layer and an n-type Al _x Ga _1-x N The result of measuring the relationship between the contact resistance with the layer and the heat treatment temperature is shown. Reference 2 shows the result of measuring this relationship for four types of AlN molar fraction x of 0, 0.25, 0.4, and 0.6 of the n-type Al _x Ga _1-x N layer. ing.

Further, in Document 2, in the case of an ultraviolet light-emitting element having an emission wavelength shorter than 365 nm, in order to form an n-electrode on an n-type Al _x Ga _1-x N layer with a low contact resistance, approximately 600 ° C. or higher. It is described that the heat treatment is necessary. Further, Document 2 describes that when the emission wavelength is shortened, that is, when the AlN molar fraction x is increased, heat treatment at a higher temperature is required.

  In the semiconductor light emitting device described above, for example, when the emission wavelength is set to 300 nm or less, the n-type gallium nitride compound semiconductor layer having an Al composition ratio higher than 0.6 is used as the n-type gallium nitride compound semiconductor layer. Is required.

The inventors of the present application, for example, tried to obtain ohmic contact after forming a laminated film of the above-described Ti film, Al film, and Au film on the exposed surface of the n-type Al _0.7 Ga _0.3 N layer. In this case, it was found that it was necessary to perform annealing at an annealing temperature of 750 ° C. or higher. Further, the inventors of the present application have found that the surface roughness (surface irregularities) of the negative electrode becomes noticeable when annealing is performed at an annealing temperature of 750 ° C. or higher when forming the negative electrode during the manufacture of the semiconductor light emitting device. Got.

  Further, a light emitting device including a semiconductor light emitting element and a package containing the semiconductor light emitting element electrically connects a positive electrode and a negative electrode of the semiconductor light emitting element, and a first conductor portion and a second conductor portion of the package, respectively. Need to be connected. For this reason, in the light emitting device, it is necessary to perform wire bonding or flip chip bonding at the time of manufacture, and wires and bumps are bonded to the positive electrode and the negative electrode of the semiconductor light emitting element, respectively. In the light emitting device, when the surface roughness of the negative electrode of the semiconductor light emitting element is remarkable, the bonding strength between the negative electrode and the wire or the bump becomes insufficient, the temperature stress applied repeatedly, or the semiconductor light emitting element It has been found that the wire and bump may be peeled off from the negative electrode due to repeated turning on and off, etc., leading to open defects.

Further, according to the measurement results described in Document 2, when the AlN molar fraction x is 0.6, the contact resistance is the lowest value when the heat treatment temperature is about 950 ° C. The minimum value of this contact resistance is about 1 × 10 ⁻² Ω · cm ² . However, in the semiconductor light emitting device, it is desired to realize ohmic contact with a smaller contact resistance.

  An object of the present invention is to provide a semiconductor light-emitting device and a semiconductor capable of suppressing the surface roughness of the negative electrode and reducing the contact resistance between the n-type gallium nitride compound semiconductor layer and the negative electrode It is providing the manufacturing method of a light emitting element.

  The semiconductor light emitting device of the present invention includes a substrate and an n-type gallium nitride compound semiconductor layer, a light emitting layer, and a p-type gallium nitride compound semiconductor layer formed on the first surface side of the substrate in order from the first surface side. A nitride semiconductor layer; a positive electrode formed on a surface side of the p-type gallium nitride compound semiconductor layer; and a negative electrode formed on an exposed surface of the n-type gallium nitride compound semiconductor layer. The negative electrode does not contain Ti as a constituent element, the negative electrode includes a plurality of electrode layers overlapping in the thickness direction, and the uppermost electrode layer of the plurality of electrode layers is configured by an Au layer. The lowermost electrode layer of the plurality of electrode layers includes Al, N, and a metal capable of forming a compound with N as constituent elements.

  In this semiconductor light emitting device, the metal is preferably selected from the group of Ni, Cu, Fe, W, and Ta.

  In the semiconductor light emitting device, the plurality of electrode layers are a first electrode layer, a second electrode layer, and a third electrode layer that are composed of the lowermost electrode layers in order from the side closer to the n-type gallium nitride compound semiconductor layer. A fourth electrode layer comprising the uppermost electrode layer, wherein the second electrode layer is composed of Al and the metal, and the third electrode layer is composed of Al, Au, and the metal. Preferably there is.

  The method of manufacturing a semiconductor light emitting device according to the present invention includes a substrate, an n-type gallium nitride compound semiconductor layer, a light emitting layer, and a p-type gallium nitride compound semiconductor formed on the first surface side of the substrate in order from the first surface side. A nitride semiconductor layer having a layer; a positive electrode formed on a surface side of the p-type gallium nitride compound semiconductor layer; and the nitride semiconductor layer of the n-type gallium nitride compound semiconductor layer in a depth direction A negative electrode formed on an exposed surface that is removed halfway, wherein the negative electrode does not contain Ti as a constituent element, wherein the n-type gallium nitride-based compound semiconductor In forming the negative electrode on the surface of the layer, a first metal layer made of Al, N and a compound can be formed on the surface of the n-type gallium nitride compound semiconductor layer. A second metal layer made of a metal, a third metal layer made of Al, a fourth metal layer made of a second metal capable of forming a compound with N, and a fifth metal layer made of Au are sequentially laminated, and then annealed. The negative electrode is formed by performing a treatment.

  In this method for manufacturing a semiconductor light emitting device, the first metal and the second metal are preferably selected from the group of Ni, Cu, Fe, W, and Ta.

  In the semiconductor light emitting device of the present invention, it is possible to suppress the surface roughness of the negative electrode and to reduce the contact resistance between the n-type gallium nitride compound semiconductor layer and the negative electrode. effective.

  In the method for manufacturing a semiconductor light emitting device of the present invention, it is possible to suppress the surface roughness of the negative electrode and to reduce the contact resistance between the n-type gallium nitride compound semiconductor layer and the negative electrode. It becomes possible to manufacture a simple semiconductor light emitting device.

FIG. 1 is a schematic cross-sectional view of the semiconductor light emitting device of the embodiment. FIG. 2A is a schematic explanatory diagram of the distribution in the depth direction of the constituent elements of the negative electrode in the semiconductor light emitting device of the embodiment. FIG. 2B is a schematic explanatory diagram of a negative electrode in the semiconductor light emitting device of the embodiment. FIG. 3 is a main process sectional view for explaining the method for manufacturing the semiconductor light emitting device of the embodiment.

  Hereinafter, the semiconductor light emitting device B1 of the present embodiment will be described with reference to FIGS. 1, 2A, and 2B.

The semiconductor light emitting device B1 is formed on the first surface 1a side of the substrate 1 and the n-type gallium nitride compound semiconductor layer 3, the light emitting layer 4, and the p-type gallium nitride compound semiconductor layer in order from the first surface 1a side. And a nitride semiconductor layer 20 having 6. Further, the semiconductor light emitting device B1 includes a positive electrode 8 formed on the surface 6a side of the p-type gallium nitride compound semiconductor layer 6 and a negative electrode formed on the exposed surface 3a of the n-type gallium nitride compound semiconductor layer 3. And an electrode 9. In the semiconductor light emitting device B1, the negative electrode 9 does not contain Ti as a constituent element. As shown in FIG. 2B, the negative electrode 9 includes a plurality of electrode layers 9 _i (i = 1 to n, n = 4 in the example of FIG. 2B) overlapping in the thickness direction. Negative electrode 9, the uppermost electrode layer 9 _n among the plurality of electrode layers 9 _i is composed of Au layer, the lowest layer of the electrode layer 9 _one of the plurality of electrode layers 9 _i, as an element, Al And N and a metal capable of forming a compound with N. Thereby, the semiconductor light emitting element B1 can suppress the surface roughness of the negative electrode 9, and can reduce the contact resistance between the n-type gallium nitride compound semiconductor layer 3 and the negative electrode 9. It becomes. In the example of FIG. 2B, n = 4, but it is sufficient if n ≧ 3.

  Each component of the semiconductor light emitting device B1 will be described in detail below.

  The semiconductor light emitting element B1 can be an ultraviolet light emitting diode having an emission wavelength (emission peak wavelength) in an ultraviolet wavelength region of 210 nm to 280 nm, for example. Thereby, the semiconductor light-emitting element B1 can be used in fields such as high-efficiency white illumination, sterilization, medical treatment, and uses for treating environmental pollutants at high speed. In the case of an ultraviolet light emitting element such as an ultraviolet light emitting diode, the semiconductor light emitting element B1 preferably has an emission wavelength in the UV-C wavelength region. The wavelength range of UV-C is, for example, 100 nm to 280 nm according to the classification by the wavelength of ultraviolet rays in the International Commission on Illumination (CIE).

The substrate 1 can be constituted by, for example, a sapphire substrate whose first surface 1a is a (0001) surface. That is, the substrate 1 can be configured by a c-plane sapphire substrate (α-Al ₂ O ₃ substrate). The sapphire substrate preferably has an off angle from the (0001) plane of 0 to 0.3 °.

The semiconductor light emitting device B1 preferably includes a buffer layer 2 between the substrate 1 and the n-type gallium nitride compound semiconductor layer 3 (hereinafter also referred to as “n-type semiconductor layer 3”). In short, in the semiconductor light emitting element B1, it is preferable that the buffer layer 2 is formed on the first surface 1a of the substrate 1 and the n-type semiconductor layer 3 is formed on the buffer layer 2. The buffer layer 2 is configured by an Al _y Ga _1-y N (0 ≦ y ≦ 1) layer. The buffer layer 2 is preferably composed of an AlN layer.

  The buffer layer 2 is a layer provided for the purpose of reducing threading dislocations. If the buffer layer 2 is too thin, the threading dislocations are likely to be insufficiently reduced. If the buffer layer 2 is too thick, cracks may occur due to lattice mismatch or a wafer on which a plurality of semiconductor light emitting elements B1 are formed. There is a concern that the warpage will be too large. For this reason, the thickness of the buffer layer 2 is preferably set, for example, in the range of about 500 nm to 10 μm, and more preferably set in the range of 1 μm to 5 μm. The thickness of the buffer layer 2 is set to 4 μm, but it is an example and is not particularly limited.

The n-type semiconductor layer 3 is a layer for transporting electrons to the light emitting layer 4. The n-type semiconductor layer 3 can be constituted by, for example, an n-type Al _z Ga _{1 -z} N (0 <z <1) layer. The composition ratio of the n-type Al _z Ga _1-z N (0 <z <1) layer constituting the n-type gallium nitride compound semiconductor layer 3 is set so that the ultraviolet light emitted from the light emitting layer 4 can be efficiently emitted. Is preferred. For example, when the light emitting layer 4 has a quantum well structure composed of a barrier layer and a well layer, the Al composition ratio of the well layer is 0.5, and the Al composition ratio of the barrier layer is 0.7. The Al composition ratio z of the type Al _z Ga _1-z N (0 <z <1) can be set to 0.7, which is the same as the Al composition ratio of the barrier layer. That is, when the well layer of the light emitting layer 4 is composed of an Al _0.5 Ga _0.5 N layer and the barrier layer is composed of an Al _0.7 Ga _0.3 N layer, the n-type semiconductor layer 3 is, for example, an n-type Al _0.7 Ga _0.3 N It can be composed of layers. The Al composition ratio of the n-type semiconductor layer 3 is not limited to being the same as the Al composition ratio of the barrier layer, and may be different. In addition, the n-type semiconductor layer 3 is not limited to a single layer film, and may be formed of, for example, a multilayer film in which a plurality of n-type AlGaN layers having different Al composition ratios are stacked. The thickness of the n-type semiconductor layer 3 is set to 2 μm as an example, but is not particularly limited. In addition, as a donor impurity of the n-type semiconductor layer 3, Si is preferable, for example. Moreover, what is necessary is just to set the electron concentration of the n-type semiconductor layer 3 in the range of about 1 * 10 < ¹⁸ > -1 * 10 < ¹⁹ > cm < ^-3 >, for example.

The light emitting layer 4 is a layer for converting injected carriers (here, electrons and holes) into light. In other words, the light emitting layer 4 is a layer that emits ultraviolet rays by recombination of two types of injected carriers (electrons and holes). The light emitting layer 4 preferably has a quantum well structure. In the light-emitting layer 4, the well layer of the quantum well structure is composed of Al _a Ga _1-a N (0 <a <1) layer, and the barrier layer of the quantum well structure is Al _b Ga _1-b N (0 < It is preferable that b ≦ 1 and b> a) layers. The light emitting layer 4 having a well layer composed of Al _a Ga _1-a N (0 <a <1) layer has an emission wavelength in the range of 210 nm to 360 nm by changing the Al composition ratio a of the well layer. It is possible to set an arbitrary emission wavelength. For example, when the desired emission wavelength is around 265 nm, the Al composition ratio a may be set to 0.50. In the light emitting layer 4, the well layer of the quantum well structure may be composed of an InAlGaN layer.

  The quantum well structure may be a multiple quantum well structure or a single quantum well structure. Moreover, each thickness of a well layer and a barrier layer is not specifically limited. However, if the thickness of the well layer is too large, the light-emitting layer 4 spatially separates electrons and holes injected into the well layer due to piezoelectric fields due to lattice mismatch in the quantum well structure. Therefore, it is assumed that the light emission efficiency is lowered. Further, in the light emitting layer 4, when the thickness of the well layer is too thin, it is presumed that the carrier confinement effect is lowered and the light emission efficiency is lowered. For this reason, the thickness of the well layer is, for example, preferably about 1 nm to 5 nm, and more preferably about 1.3 nm to 3 nm. Moreover, it is preferable to set the thickness of a barrier layer in the range of about 5 nm-15 nm, for example. In the semiconductor light emitting device B1, as an example, the thickness of the well layer is set to 2 nm and the thickness of the barrier layer is set to 10 nm. However, the thickness is not limited to these. The semiconductor light emitting device B1 is not limited to the configuration in which the light emitting layer 4 has a quantum well structure. For example, the light emitting layer 4 includes an n type semiconductor layer 3 and a p type gallium nitride compound semiconductor layer 6 (hereinafter referred to as “p type semiconductor layer”). It may also be a double heterostructure sandwiched between.

  The semiconductor light emitting element B1 preferably includes an electron blocking layer 5 between the light emitting layer 4 and the p-type semiconductor layer 6.

The electron blocking layer 5 suppresses that electrons out of the electrons injected into the light emitting layer 4 that are not recombined with holes in the light emitting layer 4 leak (overflow) to the p-type semiconductor layer 6 side. Further, it can be suitably provided between the light emitting layer 4 and the p-type semiconductor layer 6. The electron block layer 5 is composed of a p-type Al _c Ga _1-c N (0 <c <1) layer. The Al composition ratio c of the p-type Al _c Ga _1-c N (0 <c <1) layer can be set to 0.9, for example. The composition ratio of the p-type Al _c Ga _1-c N (0 <c <1) layer is not particularly limited, but the band gap energy of the electron blocking layer 5 is the band of the p-type semiconductor layer 6 or the barrier layer. It is preferable to set so as to be higher than the gap energy. Moreover, the hole density | concentration of the electronic block layer 5 is not specifically limited. Moreover, the thickness of the electron block layer 5 is set to 30 nm as an example. The thickness of the electron blocking layer 5 is not particularly limited, but if the thickness is too thin, the effect of suppressing overflow is reduced, and if the thickness is too thick, the resistance of the semiconductor light emitting element B1 is increased. The thickness of the electron blocking layer 5 varies depending on values such as the Al composition ratio c and the hole concentration, and therefore cannot be generally specified, but is preferably set in the range of 1 nm to 50 nm. It is more preferable to set in the range of 5 nm to 25 nm.

The p-type semiconductor layer 6 is a layer for transporting holes to the light emitting layer 4. The p-type semiconductor layer 6 is preferably composed of a p-type Al _d Ga _1-d N (0 <d <1) layer. The composition ratio of the p-type Al _d Ga _1-d N (0 <d <1) layer is preferably set so that absorption of ultraviolet rays emitted from the light emitting layer 4 can be suppressed. For example, when the Al composition ratio of the well layer in the light emitting layer 4 is 0.5 and the Al composition ratio of the barrier layer is 0.7 as described above, p-type Al _d Ga _1-d N (0 <d < 1) The Al composition ratio d of the layer can be set to 0.7, for example, the same as the Al composition ratio a of the barrier layer. That is, when the well layer of the light emitting layer 4 is composed of an Al _0.5 Ga _0.5 N layer, the p-type semiconductor layer 6 can be constituted by, for example, a p-type Al _0.7 Ga _0.3 N layer. The Al composition ratio of the p-type semiconductor layer 6 is not limited to the same as the Al composition ratio of the barrier layer, and may be different. As the acceptor impurity of the p-type semiconductor layer 6, for example, Mg is preferable.

The hole concentration of the p-type semiconductor layer 6 is not particularly limited, and a higher concentration is preferable in the hole concentration range in which the film quality of the p-type semiconductor layer 6 does not deteriorate. However, in the semiconductor light emitting device B1, the hole concentration of the p-type Al _d Ga _1-d N (0 <d <1) layer is the electron concentration of the n-type Al _z Ga _1-z N (0 <z ≦ 1) layer. Therefore, if the thickness of the p-type semiconductor layer 6 is too thick, the resistance of the semiconductor light emitting element B1 becomes too large. For this reason, the thickness of the p-type semiconductor layer 6 is preferably 200 nm or less, and more preferably 100 nm or less. In the semiconductor light emitting device B1, as an example, the thickness of the p-type semiconductor layer 6 is set to 50 nm.

  The semiconductor light emitting element B <b> 1 can be configured to suitably include the p-type contact layer 7 on the surface 6 a of the p-type semiconductor layer 6.

The p-type contact layer 7 is provided in order to reduce the contact resistance with the positive electrode 8 and obtain good ohmic contact with the positive electrode 8. The p-type contact layer 7 is preferably composed of a p-type GaN layer. The hole concentration of the p-type GaN layer constituting the p-type contact layer 7 is preferably higher than that of the p-type semiconductor layer 6. For example, by setting the hole concentration to about 7 × 10 ¹⁷ cm ⁻³ , the positive electrode Good ohmic contact with 8 can be obtained. However, the hole concentration of the p-type GaN layer is not particularly limited, and may be appropriately changed within the range of the hole concentration at which good ohmic contact with the positive electrode 8 is obtained. The thickness of the p-type contact layer 7 is set to 200 nm. However, the thickness is not limited to this, and may be set in the range of 50 nm to 300 nm, for example.

  In the semiconductor light emitting element B1, as described above, the nitride semiconductor layer 20 includes the buffer layer 2, the n-type semiconductor layer 3, the light emitting layer 4, the electron block layer 5, the p-type semiconductor layer 6, and the p-type contact layer 7. Can be configured. The nitride semiconductor layer 20 may be provided as appropriate except for the n-type semiconductor layer 3, the light emitting layer 4, and the p-type semiconductor layer 6. The nitride semiconductor layer 20 can be formed by an epitaxial growth method. Epitaxial growth methods employ, for example, metal organic vapor phase epitaxy (MOVPE) method, hydride vapor phase epitaxy (HVPE) method, molecular beam epitaxy (MBE) method, etc. it can. The nitride semiconductor layer 20 may contain impurities such as H, C, O, Si, and Fe that are inevitably mixed when the nitride semiconductor layer 20 is formed.

  The semiconductor light emitting element B1 is removed by etching a part of the nitride semiconductor layer 20 from the surface 20a side of the nitride semiconductor layer 20 to the middle of the n-type semiconductor layer 3. Thus, the surface 3a of the n-type semiconductor layer 3 is exposed in the semiconductor light emitting element B1. In short, the semiconductor light emitting device B1 has a mesa structure 22 formed by etching a part of the nitride semiconductor layer 20. In the semiconductor light emitting device B1, a positive electrode (also referred to as “p electrode”) 8 is formed on the surface 20a of the nitride semiconductor layer 20, and a negative electrode (on the surface 3a of the n-type semiconductor layer 3). Also called “n-electrode”.) 9 is formed. In the semiconductor light emitting element B1, when the nitride semiconductor layer 20 includes the p-type contact layer 7, the surface 7a of the p-type contact layer 7 constitutes the surface 20a of the nitride semiconductor layer 20.

The semiconductor light emitting device B1 includes an insulating film straddling a part of the upper surface 22a of the mesa structure 22 (the surface 20a of the nitride semiconductor layer 20), a side surface 22c of the mesa structure 22, and a part of the surface 3a of the n-type semiconductor layer 3. (Not shown) is preferably formed. As the material of the insulating film, for example, SiO ₂ can be employed.

  In the semiconductor light emitting device B1, the nitride semiconductor layer 20 is formed on the first surface 1a side of the substrate 1 as described above. In the semiconductor light emitting device B1, the second surface 1b opposite to the first surface 1a of the substrate 1 preferably constitutes a light extraction surface.

  The positive electrode 8 is preferably electrically connected to the p-type semiconductor layer 6 through the p-type contact layer 7. The positive electrode 8 is formed by forming a laminated film (hereinafter referred to as “first laminated film”) of a Ni film having a thickness of 30 nm and an Au film having a thickness of 200 nm on the surface 7 a of the p-type contact layer 7. Then, it is formed by performing an annealing process. The configuration, thickness, and the like of the first laminated film are not particularly limited.

  The semiconductor light emitting element B1 preferably includes, for example, a first pad electrode (not shown) and a second pad electrode (not shown) on the positive electrode 8 and the negative electrode 9. The first pad electrode and the second pad electrode can be constituted by a laminated film of a Ti film and an Au film, for example.

  The negative electrode 9 is electrically connected to the n-type semiconductor layer 3. The negative electrode 9 is formed on the surface 3 a of the n-type semiconductor layer 3. The negative electrode 9 is a constituent element as described above and does not contain Ti.

Negative electrode 9, the uppermost electrode layer 9 _n among the plurality of electrode layers 9 _{i (9 4)} is constituted by an Au layer, is lowermost electrode layer 9 _one of the plurality of electrode layers 9 _i, constituent elements And Al, N, and a metal capable of forming a compound with N. The uppermost electrode layer 9 _n means an electrode layer farthest from the surface 3 a of the n-type semiconductor layer 3 among the plurality of electrode layers 9 _i . The electrode layer 9 ₁ the lowermost, meaning closest to the electrode layer on the surface 3a of the n-type semiconductor layer 3. In other words, the electrode layer 9 _first bottom layer in contact with the surface 3a of the n-type semiconductor layer 3. Au layer constituting the uppermost electrode layer 9 _n, the metal may be present as an impurity. The impurity means an element other than the constituent element (Au) constituting the uppermost electrode layer 9 _n . Being able to form a compound with N means that it can be nitrided.

The semiconductor light-emitting element B1, as described above, the uppermost electrode layer 9 _n among the plurality of electrode layers 9 _i is composed of Au layer, the lowest layer of the electrode layer 9 _one of the plurality of electrode layers 9 _i As a constituent element, Al, N, and a metal capable of forming a compound with N are included. Thereby, the semiconductor light emitting element B1 can suppress the surface roughness of the negative electrode 9, and can reduce the contact resistance between the n-type gallium nitride compound semiconductor layer 3 and the negative electrode 9. It becomes. Suppressing the surface roughness of the negative electrode 9 means that the negative electrode 9 has surface flatness suitable for bonding wires, bumps and the like. The surface roughness of the negative electrode 9 can be evaluated by, for example, observing the surface morphology of the negative electrode 9 with a differential interference microscope. The surface roughness of the negative electrode 9 is not limited to the differential interference microscope, and for example, the surface roughness calculated by measuring the surface shape of the negative electrode 9 may be evaluated. As the surface roughness, for example, an arithmetic average roughness Ra defined in JIS B 0601-2001 (ISO 4287-1997) can be employed. The surface shape can be measured by, for example, a three-dimensional shape measuring apparatus such as an AFM (atomic force microscope). The contact resistance is, for example, a value measured by a TLM (Transmission Line Model) method.

In the semiconductor light emitting element B1, by suppressing the surface roughness of the negative electrode 9, it is possible to improve the bonding strength when a wire, a bump, or the like is bonded to the negative electrode 9. Thereby, for example, in the light emitting device including the semiconductor light emitting element B1 and the package containing the semiconductor light emitting element B1, long-term reliability can be improved. Also, the semiconductor light-emitting element B1, since the uppermost electrode layer 9 _n are constituted by an Au layer in the negative electrode 9, compared to the comparative example the uppermost electrode layer 9 _n are constituted by the Al layer, The oxidation resistance of the negative electrode 9 can be improved.

  In addition, the semiconductor light emitting device B1 can reduce the operating voltage of the semiconductor light emitting device B1 by reducing the contact resistance between the n-type gallium nitride compound semiconductor layer 3 and the negative electrode 9, and can emit light. The luminance can be improved.

  In the semiconductor light emitting device B1, the contact between the n-type gallium nitride compound semiconductor layer 3 and the negative electrode 9 is preferably ohmic contact. The ohmic contact means a contact having no current rectifying property caused by the direction of the applied voltage among the contact between the n-type gallium nitride compound semiconductor layer 3 and the negative electrode 9. The ohmic contact is preferably substantially linear in current-voltage characteristics, and more preferably linear. Moreover, it is preferable that ohmic contact has a smaller contact resistance. At the contact between the n-type gallium nitride compound semiconductor layer 3 and the negative electrode 9, the current passing through the interface between the n-type gallium nitride compound semiconductor layer 3 and the negative electrode 9 is This is thought to be the sum of the tunnel current that passes through the Schottky barrier. For this reason, when the tunnel current is dominant in the contact between the n-type gallium nitride compound semiconductor layer 3 and the negative electrode 9, it is considered that an ohmic contact is approximately realized.

  Ni is adopted as the metal, but is not limited thereto. The metal is preferably selected from the group of Ni, Cu, Fe, W, Ta. Thereby, the semiconductor light emitting element B1 can easily realize a reduction in contact resistance between the negative electrode 9 and the n-type gallium nitride compound semiconductor layer 3.

The plurality of electrode layers 9 _i, for example, in order from a side close to the n-type gallium nitride-based compound semiconductor layer 3, a first electrode layer made of the electrode layer 9 ₁ the lowermost, second electrode layer 9 _2, the third electrode layer 9 _3, it may be configured such that a fourth electrode layer formed of the uppermost electrode layer 9 _4. The second electrode layer 9 _2, constituent elements is Al and the metal, the third electrode layer 9 _3, constituent elements Al, is preferably Au and the metal. Thus, the semiconductor light-emitting element B1, it becomes possible to obtain an ohmic contact with the n-type gallium nitride-based compound semiconductor layer 3 by the electrode layer 9 ₁ the lowermost, the uppermost electrode layer 9 _4, wires or bumps It is possible to ensure good bondability. Further, as shown in FIG. 3, the semiconductor light emitting device B1 includes a first metal layer 9a made of Al, a second metal layer 9b made of the metal, and a third metal made of Al on the surface 3a of the n-type semiconductor layer 3. By sequentially laminating the layer 9c, the fourth metal layer 9d made of the metal, and the fifth metal layer 9e made of Au, the negative electrode 9 can be formed by performing an annealing process. The annealing temperature in the annealing process at the time of forming the negative electrode 9 is set to 700 ° C. as an example. The annealing temperature in the annealing process at the time of forming the negative electrode 9 is preferably a temperature at which Al diffusion easily occurs. Specifically, for example, a specified temperature (for example, 650 ° C.) slightly lower than the melting point of Al (about 660 ° C.). ) The above temperature is preferable, and a temperature of less than 750 ° C. is preferable.

  In forming the negative electrode 9, the thicknesses of the first metal layer 9a, the second metal layer 9b, the third metal layer 9c, the fourth metal layer 9d, and the fifth metal layer 9e are set to 50 nm, 20 nm, 100 nm, Although it is set to 20 nm and 100 nm, it is not limited to these thicknesses. In addition, about these thickness, it demonstrates with the manufacturing method of below-mentioned semiconductor light-emitting device B1.

  FIG. 2A is a schematic explanatory diagram of the distribution in the depth direction of the constituent elements of the negative electrode 9 in the semiconductor light emitting device B1. More specifically, FIG. 2A schematically shows the depth direction distribution of constituent elements other than N among the constituent elements Al, Ni, N and Au in the negative electrode 9 when the metal is Ni. It is. The depth direction distribution is a content distribution of constituent elements at each position in the depth direction with respect to the surface of the negative electrode 9. FIG. 2A shows the distribution in the depth direction from the surface of the negative electrode 9 in FIG. 2B to the vicinity of the interface between the negative electrode 9 and the n-type semiconductor layer 3. In short, FIG. 2A and FIG. 2B correspond to the position of the surface of the negative electrode 9 and the position in the depth direction.

By the way, in the measurement results described in Document 2, when the AlN molar fraction x is 0.6, the contact resistance becomes the lowest value when the heat treatment temperature is about 950 ° C., and the minimum value of the contact resistance is 1 × 10 ⁻² Ω · cm ² On the other hand, the semiconductor light emitting device B1 has a contact resistance between the negative electrode 9 and the n-type gallium nitride compound semiconductor layer 3 constituted by the n-type Al _0.7 Ga _0.3 N layer having a higher Al composition ratio of 5 ×. It can be about 10 ⁻³ Ωcm ² . In the semiconductor light emitting device B1, the contact resistance tends to increase as the Al composition ratio increases. For this reason, the negative electrode 9 is not limited to an n-type AlGaN layer having a low Al composition ratio as long as an ohmic contact is obtained with respect to an n-type AlGaN layer having a higher Al composition ratio, but Al _x1 Ga _y1 In _{1− The present} invention can be applied to the n-type semiconductor layer 3 represented by a composition of _x1-y1 N (0 ≦ x1, 0 ≦ y1, x1 + y1 ≦ 1).

  The chip size of the semiconductor light emitting element B1 is set to 400 μm □ (400 μm × 400 μm), but is not limited thereto. The chip size can be appropriately set within a range of, for example, about 200 μm □ (200 μm × 200 μm) to 1 mm □ (1 mm × 1 mm). Further, the planar shape of the semiconductor light emitting element B1 is not limited to a square shape, and may be, for example, a rectangular shape. When the planar shape of the semiconductor light emitting element B1 is rectangular, the chip size of the semiconductor light emitting element B1 can be set to, for example, 500 μm × 240 μm.

  A method for manufacturing the semiconductor light emitting device B1 will be described with reference to FIGS.

  The semiconductor light emitting device B1 is formed on the first surface 1a side of the substrate 1 and the n-type gallium nitride compound semiconductor layer 3, the light emitting layer 4, and the p-type gallium nitride compound semiconductor layer in order from the first surface 1a side. And a nitride semiconductor layer 20 having 6. The semiconductor light emitting device B1 includes a positive electrode 8 formed on the surface 6a side of the p-type gallium nitride compound semiconductor layer 6 and a negative electrode formed on the exposed surface 3a of the n-type gallium nitride compound semiconductor layer 3. 9. In the semiconductor light emitting device B1, the negative electrode 9 does not contain Ti as a constituent element.

  In forming the negative electrode 9 on the surface 3a of the n-type gallium nitride compound semiconductor layer 3 in the method for manufacturing the semiconductor light emitting device B1, the first electrode made of Al is formed on the surface 3a of the n-type gallium nitride compound semiconductor layer 3. 1 metal layer 9a, second metal layer 9b made of a first metal capable of forming a compound with N, third metal layer 9c made of Al, made of a second metal capable of forming a compound with N After the fourth metal layer 9d and the fifth metal layer 9e made of Au are sequentially stacked, the negative electrode 9 is formed by performing an annealing process. Thereby, in the manufacturing method of the semiconductor light emitting element B1, the surface roughness of the negative electrode 9 can be suppressed, and the contact resistance between the n-type gallium nitride compound semiconductor layer 3 and the negative electrode 9 is reduced. It becomes possible to manufacture the semiconductor light emitting element B1 that can be used.

  Below, the manufacturing method of semiconductor light-emitting device B1 is explained in full detail.

(1) Preparation of wafer The wafer is a disk-shaped substrate. When the substrate 1 in the semiconductor light emitting element B1 is a sapphire substrate, a sapphire wafer can be adopted as the wafer. The wafer is preferably formed with an orientation flat (OF). The thickness of the wafer is preferably, for example, several hundred μm to several mm, and more preferably 200 μm to 1 mm. The diameter of the wafer is preferably 50.8 mm to 150 mm, for example.

  The wafer preferably satisfies or conforms to standards such as Japan Electronics Industry Promotion Association (JEIDA) and SEMI (Semiconductor Equipment and Materials International). As for the sapphire wafer, it is preferable that the specification of the sapphire substrate used for the compound semiconductor epitaxial wafer standardized by SEMI M65-0306 is satisfied. The first surface of the sapphire wafer corresponds to the first surface 1 a of the substrate 1. As the first surface of the sapphire wafer, for example, a c-plane, m-plane, a-plane, R-plane, etc. can be adopted, and the (0001) plane that is the c-plane is preferable. The first surface of the sapphire wafer preferably has an off angle from the (0001) plane of 0 to 0.3 °.

(2) Step of Laminating a Nitride Semiconductor Layer on the First Surface of the Wafer The nitride semiconductor layer includes a n-type gallium nitride compound semiconductor layer 3, a light emitting layer 4, and a p-type gallium nitride compound semiconductor layer 6. It is a membrane. The nitride semiconductor layer is an epitaxial layer having a multilayer structure. The nitride semiconductor layer does not particularly limit the laminated structure of the laminated film. The nitride semiconductor layer includes a buffer layer 2, an electron block layer 5, and a p-type contact layer 7 in addition to the n-type gallium nitride compound semiconductor layer 3, the light emitting layer 4 and the p-type gallium nitride compound semiconductor layer 6. It is preferable. The buffer layer 2, the electron block layer 5, and the p-type contact layer 7 may be provided as appropriate.

  In this step, the MOVPE method is adopted as an epitaxial growth method of the nitride semiconductor layer. In this step, it is preferable to employ the reduced pressure MOVPE method as the MOVPE method.

Trimethylaluminum (TMAl) is preferably employed as the Al source gas. Further, it is preferable to employ trimethyl gallium (TMGa) as the Ga source gas. As the N source gas, NH ₃ is preferably employed. It is preferable to employ tetraethylsilane (TESi) as a source gas of Si that is an impurity imparting n-type conductivity. It is preferable to employ biscyclopentadienyl magnesium (Cp ₂ Mg) as a source gas for Mg, which is an impurity contributing to p-type conductivity. For example, H ₂ gas is preferably used as the carrier gas of each source gas.

Each source gas is not particularly limited. For example, triethylgallium (TEGa) may be used as a Ga source gas, a hydrazine derivative may be used as a N source gas, and monosilane (SiH ₄ ) may be used as a Si source gas.

  The growth conditions for the nitride semiconductor layer may be appropriately set such as the substrate temperature, the V / III ratio, the supply amount of each source gas, the growth pressure, and the like.

  The epitaxial growth method of the nitride semiconductor layer is not limited to the MOVPE method, and for example, an MBE method, an HVPE method, or the like may be used.

(3) Step of performing annealing for activating the p-type impurity In this step, the electron blocking layer 5 and the p-type nitriding are maintained by holding at a predetermined annealing temperature for a predetermined annealing time in an annealing furnace of the annealing apparatus. This is a step of activating p-type impurities in the gallium compound semiconductor layer 6 and the p-type contact layer 7. The annealing conditions are set such that the annealing temperature is set to 750 ° C. and the annealing time is set to 10 minutes, but these values are merely examples and are not particularly limited. As the annealing apparatus, for example, a lamp annealing apparatus, an electric furnace annealing apparatus, or the like can be employed.

(4) Step of forming mesa structure 22 In this step, photolithography is performed on a region of the nitride semiconductor layer corresponding to the upper surface 22a of the mesa structure 22 of the nitride semiconductor layer 20 (the surface 20a of the nitride semiconductor layer 20). A first resist layer is formed using a technique. In this step, the mesa structure 22 is formed by etching a part of the nitride semiconductor layer 20 from the surface 20a side to the middle of the n-type gallium nitride compound semiconductor layer 3 using the first resist layer as a mask. To do. Further, in this step, the first resist layer is removed. Etching of the nitride semiconductor layer 20 can be performed by, for example, reactive ion etching.

(5) Step of Forming Insulating Film In this step, a SiO ₂ film serving as a base of the insulating film is formed on the entire first surface side of the wafer by, for example, PECVD (plasma-enhanced chemical vapor deposition). In this step, on the first surface side of the wafer, the SiO ₂ film is opened so that the portions of the nitride semiconductor layer 20 that overlap with the respective regions where the positive electrode 8 and the negative electrode 9 are to be formed are opened. By patterning the _two films, a patterned insulating film is formed. Note that the method of forming the SiO ₂ film is not limited to the PECVD method, and may be another CVD method, for example. The patterning of the SiO ₂ film is performed using a photolithography technique and an etching technique.

(6) Step of Forming Negative Electrode 9 In this step, first, only the region where negative electrode 9 is to be formed (that is, the thickness of n-type gallium nitride compound semiconductor layer 3 is reduced) on the first surface side of the wafer. Then, a second resist layer patterned so as to expose a part of the surface 3a of the exposed portion is formed. In this step, for example, a first metal layer 9a, N made of Al, a second metal layer 9b made of a first metal capable of forming a compound with N, a third metal layer 9c, N made of Al, and a compound A laminated film of the fourth metal layer 9d made of the second metal and the fifth metal layer 9e made of Au can be formed by vapor deposition. The vapor deposition method is preferably an electron beam vapor deposition method. The method for forming the laminated film is not limited to the vapor deposition method, and may be a sputtering method, for example. The first metal and the second metal are preferably selected from the group of Ni, Cu, Fe, W, and Ta. For example, in this step, Ni is adopted as the first metal and the second metal, but Cu may be adopted, Ni is adopted as the first metal, and Cu is adopted as the second metal. May be adopted. In this step, the second resist layer and the unnecessary film on the second resist layer are removed by performing lift-off. Further, in this step, an annealing process is performed. The annealing process is a process for making the contact between the negative electrode 9 and the n-type gallium nitride compound semiconductor layer 3 ohmic contact. The annealing treatment is preferably RTA (Rapid Thermal Annealing) in an N ₂ gas atmosphere. The structure and thickness of the laminated film are examples and are not particularly limited. The RTA treatment conditions may be, for example, an annealing temperature of 700 ° C. and an annealing time of 1 minute, but these values are merely examples and are not particularly limited. The annealing temperature is preferably a temperature at which Al diffusion is likely to occur. Specifically, for example, a temperature slightly higher than a specified temperature (for example, 650 ° C.) slightly lower than the melting point of Al (about 660 ° C.) is preferable, and less than 750 ° C. Is preferred. The annealing temperature is preferably about 700 ° C. when the n-type gallium nitride compound semiconductor layer 3 is an n-type Al _0.7 Ga _0.3 N layer. The annealing temperature may be appropriately changed based on the Al composition ratio of the n-type gallium nitride compound semiconductor layer 3. The annealing time may be set in the range of about 30 seconds to 3 minutes, for example.

  The inventors of the present application considered as follows an estimated mechanism for forming the negative electrode 9 by performing the annealing process in this step. Note that the manufacturing method of the semiconductor light emitting element B1 is within the scope of the present invention even if the estimation mechanism is different.

In this step, by annealing, the first metal of the second metal layer 9b diffuses into the first metal layer 9a to form an alloy of Al and the first metal, and the first metal layer 9a is n-type gallium nitride. It is assumed that ohmic contact between the n-type gallium nitride compound semiconductor layer 3 and the negative electrode 9 can be realized by extracting a part of nitrogen from the system compound semiconductor layer 3. Further, in this step, the second metal of the fourth metal layer 9d suppresses the reaction between Al, which is a constituent element of the third metal layer 9c, and Au, which is a constituent element of the fifth metal layer, by the uppermost electrode layer 9 ₄ made of Au layer on the outermost surface side of the metal layer 9e is left, the flatness of the surface of the negative electrode 9, than the flatness of the surface of the laminated film be inhibited from reduction It is thought that it can do.

  However, if the thickness of the first metal layer 9a is too large, the second metal, which is a constituent element of the second metal layer 9b, goes to the interface between the first metal layer 9a and the n-type gallium nitride compound semiconductor layer 3. Therefore, it is desirable to set it to 200 nm or less. The thickness of each of the second metal layer 9b and the fourth metal layer 9d is preferably set to 5 nm or more because a desired effect cannot be obtained if the thickness is too thin.

(7) Step of Forming Positive Electrode 8 In this step, only the region where positive electrode 8 is to be formed on the first surface side of the wafer (here, part of surface 7a of p-type contact layer 7) is exposed. A patterned third resist layer is formed. In this step, for example, a laminated film of a Ni film having a thickness of 30 nm and an Au film having a thickness of 200 nm is formed by electron beam evaporation, and lift-off is performed, whereby the third resist layer and the third film are formed. The unnecessary film on the resist layer is removed. Further, in this step, RTA treatment is performed in an N ₂ gas atmosphere so that the contact between the positive electrode 8 and the p-type contact layer 7 is ohmic contact. The structure and thickness of the laminated film are examples and are not particularly limited. The RTA treatment conditions may be, for example, an annealing temperature of 500 ° C. and an annealing time of 15 minutes, but these values are merely examples and are not particularly limited.

(8) Step of forming the first pad electrode and the second pad electrode In this step, the first pad electrode and the second pad electrode are respectively formed on the positive electrode 8 and the negative electrode 9 using the photolithography technique and the thin film forming technique. A pad electrode is formed. As the thin film formation technique, for example, a vapor deposition method or the like can be employed. The vapor deposition method is preferably an electron beam vapor deposition method. The first pad electrode and the second pad electrode are electrically connected to the positive electrode 8 and the negative electrode 9, respectively. The first pad electrode is preferably formed so as to cover the positive electrode 8. The second pad electrode is preferably formed so as to cover the negative electrode 9.

  In the method for manufacturing the semiconductor light emitting element B1, by completing this process, a wafer on which a plurality of semiconductor light emitting elements B1 are formed is completed. In short, in the method for manufacturing the semiconductor light emitting element B1, the above-described steps (1) to (8) are sequentially performed to complete a wafer on which a plurality of semiconductor light emitting elements B1 are formed.

(9) Process of Dividing from Wafer into Individual Semiconductor Light Emitting Elements B1 This process is a dicing process, and the wafer is cut into pieces by dividing the wafer with a dicing saw or the like. Thereby, a plurality of semiconductor light emitting elements B1 can be obtained from one wafer.

  In the manufacturing method of the semiconductor light emitting device B1 of the present embodiment described above, the surface roughness of the negative electrode 9 can be suppressed, and the contact resistance between the n-type gallium nitride compound semiconductor layer 3 and the negative electrode 9 can be suppressed. It is possible to manufacture the semiconductor light emitting device B1 capable of reducing the above. In the method for manufacturing the semiconductor light emitting element B1, the first metal and the second metal are preferably selected from the group of Ni, Cu, Fe, W, and Ta. Thereby, in the manufacturing method of semiconductor light emitting element B1, it becomes possible to implement | achieve reduction of the contact resistance of the negative electrode 9 and the n-type gallium nitride type compound semiconductor layer 3 easily.

  The semiconductor light emitting element B1 is not limited to the ultraviolet light emitting diode but may be an ultraviolet laser diode.

  Each figure explained in the above-mentioned embodiment is a typical figure, and the ratio of each size and thickness of each component does not necessarily reflect an actual dimensional ratio. In addition, the materials, numerical values, and the like described in the embodiments are merely preferred examples and are not limited thereto. Furthermore, the present invention can be appropriately modified in configuration without departing from the scope of its technical idea.

Claims (5)

A substrate, a nitride semiconductor layer formed on the first surface side of the substrate and having an n-type gallium nitride compound semiconductor layer, a light emitting layer, and a p-type gallium nitride compound semiconductor layer in that order from the first surface side; A positive electrode formed on the surface side of the n-type gallium nitride compound semiconductor layer, and a negative electrode formed on the exposed surface of the n-type gallium nitride compound semiconductor layer,
The negative electrode does not contain Ti as a constituent element,
The negative electrode includes a plurality of electrode layers overlapping in the thickness direction, the uppermost electrode layer of the plurality of electrode layers is composed of an Au layer, the lowermost electrode layer of the plurality of electrode layers, A semiconductor light emitting device comprising Al, N, and a metal capable of forming a compound with N as constituent elements.   2. The semiconductor light emitting device according to claim 1, wherein the metal is selected from the group of Ni, Cu, Fe, W, and Ta.   The plurality of electrode layers are, in order from the side closer to the n-type gallium nitride compound semiconductor layer, a first electrode layer, a second electrode layer, a third electrode layer, and an uppermost electrode composed of the lowermost electrode layer. A fourth electrode layer comprising layers, wherein the second electrode layer is composed of Al and the metal, and the third electrode layer is composed of Al, Au, and the metal. The semiconductor light-emitting device according to claim 1.   A substrate, a nitride semiconductor layer formed on the first surface side of the substrate and having an n-type gallium nitride compound semiconductor layer, a light emitting layer, and a p-type gallium nitride compound semiconductor layer in that order from the first surface side; A positive electrode formed on the surface side of the n-type gallium nitride compound semiconductor layer, and the n-type gallium nitride compound semiconductor layer formed on the surface exposed by removing the nitride semiconductor layer halfway in the depth direction. A negative electrode, wherein the negative electrode does not contain Ti as a constituent element, and the negative electrode is formed on the surface of the n-type gallium nitride compound semiconductor layer. In the process, a first metal layer made of Al, a second metal layer made of a first metal capable of forming a compound with N, and Al are formed on the surface of the n-type gallium nitride compound semiconductor layer. The negative electrode is formed by sequentially laminating three metal layers, a fourth metal layer made of a second metal capable of forming a compound with N, and a fifth metal layer made of Au, followed by annealing. A method for manufacturing a semiconductor light emitting device.   5. The method of manufacturing a semiconductor light emitting element according to claim 4, wherein the first metal and the second metal are selected from the group of Ni, Cu, Fe, W, and Ta.

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