JPWO2016157820A1 - Switching element, semiconductor device, and method of manufacturing switching element - Google Patents

Abstract

Provided is a switching element capable of improving on-state retention performance and reducing off-state leakage current. The switching element of the present invention includes a first electrode and a second electrode, and a resistance change layer provided between the first electrode and the second electrode, and the resistance change layer is in contact with the first electrode. And a second ion conductive layer in contact with the second electrode. The first electrode includes the same type of metal as the metal included in the first ion conductive layer, and the concentration of the metal is the first electrode and the first ion. It is the structure distributed so that it may become small in the direction in a 1st electrode from the interface with a conductive layer.

Description

  The present invention relates to a switching element, a semiconductor device, and a method for manufacturing a switching element using metal deposition.

  In order to diversify the functions of the programmable logic and promote the mounting to electronic devices, it is necessary to reduce the size of the switch for connecting the logic cells to each other and to reduce the on-resistance. There has been known a switching element having an ion conductive layer capable of conducting metal ions and utilizing precipitation of metal in the ion conductive layer. This switching element is known to have a smaller size and lower on-resistance than a semiconductor switch. The switching element includes a two-terminal switch and a three-terminal switch. An example of a two-terminal switch is disclosed in Patent Document 1, and an example of a three-terminal switch is disclosed in Patent Document 2.

  FIG. 1 is a schematic cross-sectional view showing a configuration example of a related two-terminal switch. As shown in FIG. 1, the two-terminal switch includes a first electrode 201 that supplies metal ions, a second electrode 202 that does not supply metal ions, and an ion conductive layer sandwiched between the first electrode 201 and the second electrode 202. 203. The two-terminal switch is switched by connecting / disconnecting two electrodes by forming / extinguishing a metal bridge in the ion conductive layer. Since the two-terminal switch has a simple structure, the manufacturing process is simple, and the element size can be reduced to the nanometer order. The three-terminal switch has a structure in which the second electrodes of two two-terminal switches are integrated, and high reliability is ensured.

  As the ion conductive layer, a porous polymer mainly composed of silicon, oxygen, and carbon is desirable. An ion conductive layer composed of a porous polymer is excellent in operation reliability because it can maintain a high breakdown voltage even if a metal bridge is formed in the layer (Patent Document 3).

  In order to mount this switch as a wiring switch for programmable logic, it is necessary to increase the density by miniaturizing the switch and to simplify the manufacturing process. The wiring material of the state-of-the-art semiconductor device is mainly composed of copper, and a technique for efficiently forming a resistance change element in the copper wiring is desired. Non-Patent Document 1 discloses a technique for integrating a switch element using an electrochemical reaction into a semiconductor device.

  Non-Patent Document 1 describes a technique that combines a copper wiring on a semiconductor substrate and a first electrode of a switching element. If this structure is used, the process for newly forming the first electrode can be reduced. Therefore, a mask for forming the first electrode is not necessary, and the number of photomasks (PR: Photoresist) to be added to manufacture the resistance change element is two. When the ion conductive layer is directly formed on the copper wiring, the surface of the copper wiring is oxidized and the leakage current increases. To deal with this problem, Non-Patent Document 1 sandwiches a metal thin film that functions as an oxidation sacrificial layer between a copper wiring and an ion conductive layer. The metal thin film is oxidized by oxygen contained in the ion conductive layer to prevent the copper wiring from being oxidized, and the oxide functions as a part of the ion conductive layer.

  On the other hand, Non-Patent Document 2 discloses a technique in which a part of a buffer metal formed on a copper wiring is alloyed with copper and the rest is oxidized. It is disclosed that the buffer metal diffuses into the metal bridge, thereby improving the thermal stability of the metal bridge and improving the retention resistance (retention). This is considered to be because Joule heat generation efficiency is improved by incorporating the buffer metal into the metal bridge, and a current required for the transition from the ON state to the OFF state does not increase.

Special Table 2002-536840 Publication International Publication No. 2012/043502 International Publication No. 2011/058947

Munehiro Tada, 5 others, “Nonvolatile Crossbar Switch TiOx / TaSiOy Solid Electrolyte”, IEEE TRANSACTIONS ON ELECTRON DEVICES, Vol. 8, 1987-1995, 2010 Munehiro Tada, 6 others, “Improved ON-State Reliability of Atom Switching Using Electrodes”, IEEE TRANSACTIONS ON ELECTRON DEVICES, Vol. 10, 3534 to 3540 pages, 2013

  The wiring changeover switch of the programmable logic desirably has a high on / off resistance ratio. Since the on-state current path of the switch using the metal bridge is a metal aggregate, the on-state resistance can be sufficiently low. On the other hand, the resistance value in the off state follows the initial resistance of the element.

  In the technique disclosed in Non-Patent Document 2, there is a problem in coexistence of alloying the buffer metal and the copper electrode and preventing the oxidation of the copper electrode. If alloying is insufficient, sufficient retention cannot be secured.

  If the copper electrode is oxidized, copper ions diffuse into the ion conductive layer, causing an increase in leakage current. If the thickness of the buffer metal is reduced, the entire buffer metal diffuses inside the copper electrode, making it difficult to prevent oxidation of the copper electrode. On the other hand, if the thickness of the buffer metal is increased, a metal that is not oxidized remains. If the metal oxide film is formed without using the sacrificial oxidation method, the diffusion of the buffer metal to the copper electrode does not proceed, and alloying becomes difficult.

  The present invention has been made to solve the above-described problems of the technology, and includes a switching element, a semiconductor device, and a switching device that can improve retention performance in an on state and reduce leakage current in an off state. An object is to provide a method for manufacturing an element.

In order to achieve the above object, a switching element according to one aspect of the present invention includes:
A first electrode and a second electrode;
A variable resistance layer provided between the first electrode and the second electrode,
The variable resistance layer includes a first ion conductive layer in contact with the first electrode and a second ion conductive layer in contact with the second electrode.
The first electrode includes the same kind of metal as the metal included in the first ion conductive layer,
The metal has a configuration in which the concentration of the metal is distributed so as to decrease from the interface between the first electrode and the first ion conductive layer in the direction within the first electrode.

A semiconductor device according to another aspect of the present invention is
A switching element according to one aspect of the invention as described above;
Multilayer wiring having wiring provided in at least two layers,
Of the two layers of wiring, one wiring is the first electrode,
Of the two layers of wiring, the other wiring is connected to the second electrode through a plug.

A method for manufacturing a switching element according to still another aspect of the present invention is
Forming a first electrode on a substrate;
Forming a metal film on the first electrode;
Forming the first ion conductive layer by oxidizing the metal film under reduced pressure without exposing to the atmosphere after forming the metal film; and
Forming a second ion conductive layer on the first ion conductive layer;
Forming a second electrode on the second ion conductive layer;
It is what has.

  According to the present invention, both the on-state retention performance can be improved and the off-state leakage current can be reduced.

It is a cross-sectional schematic diagram which shows one structural example of a related 2 terminal switching element. It is a cross-sectional schematic diagram which shows one structural example of the switching element of 1st Embodiment. It is the cross-sectional schematic diagram which showed the structure of the switching element shown to FIG. 2A by another expression method. It is a cross-sectional schematic diagram for demonstrating the drive method of the switching element shown to FIG. 2B. It is a cross-sectional schematic diagram which shows the manufacturing process of the switching element of 1st Embodiment. It is a cross-sectional schematic diagram which shows the manufacturing process of the switching element of 1st Embodiment. It is a cross-sectional schematic diagram which shows the manufacturing process of the switching element of 1st Embodiment. It is a cross-sectional schematic diagram which shows the manufacturing process of the switching element of 1st Embodiment. It is a cross-sectional schematic diagram which shows one structural example of the semiconductor device containing the switching element of 1st Embodiment. It is a graph which shows the measurement result of the ON current of the switching element of a comparative example, and an OFF current. It is a graph which shows the measurement result of the ON current of the switching element of 1st Embodiment, and an OFF current. It is a graph which shows the measurement result of the set voltage and off current of the switching element of a comparative example. It is a graph which shows the measurement result of the set voltage and off current of the switching element of 1st Embodiment. FIG. 6 is a schematic cross-sectional view showing a manufacturing step of the semiconductor device shown in FIG. 5. FIG. 6 is a schematic cross-sectional view showing a manufacturing step of the semiconductor device shown in FIG. 5. FIG. 6 is a schematic cross-sectional view showing a manufacturing step of the semiconductor device shown in FIG. 5. FIG. 6 is a schematic cross-sectional view showing a manufacturing step of the semiconductor device shown in FIG. 5. FIG. 6 is a schematic cross-sectional view showing a manufacturing step of the semiconductor device shown in FIG. 5. FIG. 6 is a schematic cross-sectional view showing a manufacturing step of the semiconductor device shown in FIG. 5. FIG. 6 is a schematic cross-sectional view showing a manufacturing step of the semiconductor device shown in FIG. 5. FIG. 6 is a schematic cross-sectional view showing a manufacturing step of the semiconductor device shown in FIG. 5. FIG. 6 is a schematic cross-sectional view showing a manufacturing step of the semiconductor device shown in FIG. 5. FIG. 6 is a schematic cross-sectional view showing a manufacturing step of the semiconductor device shown in FIG. 5. FIG. 6 is a schematic cross-sectional view showing a manufacturing step of the semiconductor device shown in FIG. 5. FIG. 6 is a schematic cross-sectional view showing a manufacturing step of the semiconductor device shown in FIG. 5. It is a cross-sectional schematic diagram which shows the example of 1 structure of the semiconductor device containing the switching element of 2nd Embodiment. FIG. 9 is a schematic cross-sectional view showing a manufacturing step of the semiconductor device shown in FIG. 8. FIG. 9 is a schematic cross-sectional view showing a manufacturing step of the semiconductor device shown in FIG. 8. FIG. 9 is a schematic cross-sectional view showing a manufacturing step of the semiconductor device shown in FIG. 8. FIG. 9 is a schematic cross-sectional view showing a manufacturing step of the semiconductor device shown in FIG. 8. FIG. 9 is a schematic cross-sectional view showing a manufacturing step of the semiconductor device shown in FIG. 8. FIG. 9 is a schematic cross-sectional view showing a manufacturing step of the semiconductor device shown in FIG. 8. FIG. 9 is a schematic cross-sectional view showing a manufacturing step of the semiconductor device shown in FIG. 8. FIG. 9 is a schematic cross-sectional view showing a manufacturing step of the semiconductor device shown in FIG. 8. FIG. 9 is a schematic cross-sectional view showing a manufacturing step of the semiconductor device shown in FIG. 8. FIG. 9 is a schematic cross-sectional view showing a manufacturing step of the semiconductor device shown in FIG. 8. FIG. 9 is a schematic cross-sectional view showing a manufacturing step of the semiconductor device shown in FIG. 8. FIG. 9 is a schematic cross-sectional view showing a manufacturing step of the semiconductor device shown in FIG. 8.

(First embodiment)
The configuration of the switching element of this embodiment will be described. The switching element of this embodiment is a two-terminal switch having two terminals.

  FIG. 2A is a cross-sectional view schematically illustrating a configuration example of the switching element of the present embodiment.

  The switching element includes a first electrode 21, an ion conductive layer corresponding to a resistance change layer, and a second electrode 22. The ion conductive layer is a laminated film of the first ion conductive layer 23 and the second ion conductive layer 24. The first ion conductive layer 23 is in contact with the first electrode 21 and the second ion conductive layer 24. The second ion conductive layer 24 is in contact with the first ion conductive layer 23 and the second electrode 22.

  The material of the first electrode 21 is a material that supplies metal ions into the ion conductive layer when a voltage is applied between the first electrode 21 and the second electrode 22. In contrast, the material of the second electrode 22 is desirably a material that does not supply metal ions into the ion conductive layer when a voltage is applied between the first electrode 21 and the second electrode 22. The first ion conductive layer 23 and the second ion conductive layer 24 serve as a medium for conducting metal ions.

  An alloy of the metal constituting the first electrode 21 and the metal contained in the first ion conductive layer 23 is formed at the interface between the first electrode 21 and the first ion conductive layer 23. Hereinafter, a metal contained in the first ion conductive layer 23 is referred to as a “first metal”, and a film containing the first metal as a main material is referred to as a “first metal film”.

  Although the details of the method of forming the alloy will be described later, when the first metal film is formed on the first electrode 21 and then the first metal film is oxidized to form the first ion conductive layer 23, the alloy It is formed at the interface between the electrode 21 and the first ion conductive layer 23. A part of the first metal film is consumed for alloying with the metal of the first electrode 21, and the rest is used as an oxide for forming the first ion conductive layer 23. In a state after the first ion conductive layer 23 is formed, the alloy can be seen as a part of the first electrode 21 integrally with the first electrode 21, or formed as a configuration different from the first electrode 21. It can also be seen as being done. FIG. 2B shows a diagram in which the alloy is expressed as the alloy layer 25 with a configuration different from that of the first electrode 21. Hereinafter, the case of the configuration shown in FIG. 2B will be described.

  The concentration of the first metal contained in the alloy layer 25 shown in FIG. 2B is attenuated in the direction away from the first ion conductive layer 23 from the interface between the first ion conductive layer 23 and the first electrode 21. That is, the first metal is distributed so that the concentration thereof decreases from the interface between the first electrode 21 and the first ion conductive layer 23 toward the first electrode 21.

  Next, the configuration of the switching element of the present embodiment will be described in detail with reference to FIG. 2B.

  In the present embodiment, the material of the first electrode 21 is copper. The method for forming copper may be any one of a physical vapor deposition method (PVD method: Physical Vapor Deposition), a chemical vapor deposition method (CVD method: Chemical Vapor Deposition), and an electroplating method.

  The first ion conductive layer 23 is composed of a metal oxide formed by oxidizing the first metal. Here, the formation method will be briefly described. After the first metal film is formed on the first electrode 21 in the chamber of the film forming apparatus, the first metal film is exposed to an oxygen-containing gas under reduced pressure in the chamber without being exposed to the atmosphere as it is, and is oxidized. Thus, the first ion conductive layer 23 of the metal oxide is formed. The first metal film is formed on the first electrode 21 after the first metal film is formed by such a method, or the first metal film is exposed to the atmosphere or placed under atmospheric pressure or increased pressure with a gas containing oxygen. This is because even the first electrode 21 may be oxidized.

  The first metal is formed by a PVD method, particularly a sputtering method. As materials candidates, elements used for high-k metal gate oxides such as zirconium (Zr), hafnium (Hf), aluminum (Al), titanium (Ti), and the like are desirable. These first metals are valve metals that have a low standard Gibbs energy for oxide generation and are likely to become oxides.

  Moreover, since these first metals have high thermal stability, they effectively function as oxygen getters during the formation of the ion conductive layer, and can prevent oxidation of the copper wiring surface.

  If the film thickness of the first metal film is too thick, there is a risk that a metal that is not oxidized remains, depending on the oxidation treatment after the film formation. Therefore, for example, when the first ion conductive layer 23 is formed with a first metal film having a thickness of more than 1 nm, after forming a part of the film, it is exposed to an oxidizing atmosphere under reduced pressure without being exposed to the atmosphere. A method of forming by the procedure of oxidizing and subsequently forming the remaining portion and exposing to an oxidizing atmosphere to oxidize is desirable.

  When the film thickness of the first metal film is large, the combination process of “film formation and oxidation” is not limited to two times, and may be three or more times. In addition, when oxidizing the first metal, it is desirable to heat-treat the first metal at 400 ° C. or less before or after the oxidation process. Alternatively, the first ion conductive layer 23 may be formed by exposing the first metal to an oxygen atmosphere while heating. The first ion conductive layer 23 may be formed by a method of forming a stacked structure of a plurality of types of first metals and oxidizing the stacked structure. An alloy in which a plurality of types of first metals are mixed is used. The oxidation method may be used.

  In this specification, “reduced pressure” means that the pressure in the chamber is lowered to a pressure lower than the atmospheric pressure by operating the vacuum pump. “Depressurization” in the film formation process is to maintain the atmospheric pressure in the chamber at a predetermined pressure lower than the atmospheric pressure while the chamber is filled with a gas necessary for the film formation process by controlling the vacuum pump. Means. Further, “vacuum” means a state in which the vacuum pump is operated to reduce the atmospheric pressure in the chamber as much as possible.

  The alloy layer 25 is formed by mixing copper and the first metal of the first electrode 21 at the interface between the first metal film and the first electrode 21 when the first ion conductive layer 23 is formed. . In addition, the heat treatment before and after the oxidation treatment of the first metal film increases the concentration of the first metal at the interface, and the diffusion of the first metal proceeds into the first electrode 21. Although it is conceivable that the entire first electrode 21 becomes the alloy layer 25, in that case, the resistivity of the electrode is increased, or the electrode is easily affected by electromigration. Connected. Therefore, the alloy layer 25 is desirably present at the interface between the first electrode 21 and the first ion conductive layer 23.

  Since the first metal diffuses from the first ion conductive layer 23 to the first electrode 21, the concentration of the first metal is determined based on the interface between the first electrode 21 and the first ion conductive layer 23. Attenuating in a direction away from 23 is confirmed. Further, since the concentration of the first metal is lower in the alloy layer 25 than in the first ion conductive layer 23, when a positive voltage is applied to the first electrode 21, the copper of the first electrode 21 is ionized, and the copper The electrochemical reaction in which ions are implanted into the first ion conductive layer 23 and the second ion conductive layer 24 is not inhibited.

  In the present embodiment, when the switching element transitions from the off state to the on state and a metal bridge including copper is formed in the first ion conductive layer 23 and the second ion conductive layer 24, the first included in the alloy layer 25 is included. One metal is mixed in the metal bridge. As a result, the temperature coefficient of resistance (TCR) decreases as compared with a metal bridge formed only of copper, so that thermal stability is improved and retention performance is improved. On the other hand, since the specific resistance of the metal bridge increases, the generation efficiency of Joule heat generated when a current flows through the metal bridge at the transition from the on state to the off state is improved. For this reason, the current required for the transition from the on state to the off state does not increase.

  The second ion conductive layer 24 is a SiOCH polymer film containing silicon, oxygen, carbon and hydrogen. The second ion conductive layer 24 is formed by plasma CVD. The formation method will be briefly described. The cyclic organosiloxane raw material and the carrier gas helium flow into the reaction chamber of the film deposition system. When the supply of both is stabilized and the pressure in the reaction chamber becomes constant, RF (Radio Frequency) power is applied. Start and stop when a predetermined film thickness is formed. The supply amount of the raw material is a flow rate of 10 to 200 sccm. Helium is supplied to the reaction chamber at a flow rate of 500 sccm via a raw material vaporizer, and is directly supplied to the reaction chamber at a flow rate of 500 sccm via a separate line.

  The plasma CVD method is, for example, a gas source or a liquid source that is continuously supplied to a reaction chamber under reduced pressure, and molecules are excited by plasma energy to cause a gas phase reaction or a substrate surface reaction. This is a method for forming a continuous film on a substrate.

  The second electrode 22 is preferably made of a conductive material and has a structure in which a metal and a metal nitride are laminated. In this embodiment, a metal film is formed on the second ion conductive layer 24, and a metal nitride film is laminated on the metal film. Therefore, hereinafter, the metal film in contact with the second ion conductive layer 24 is referred to as a “lower second electrode”, and the metal nitride film is referred to as an “upper second electrode”.

  As the metal of the lower second electrode, a ruthenium alloy (Ru alloy) to which titanium, tantalum, zirconium, hafnium, aluminum or the like is added is used. Hereinafter, the metal added to ruthenium is referred to as “second metal”. The content of the second metal in the ruthenium alloy is preferably 10 atm% or more and 40 atm% or less. According to the study by the inventors, the second metal in the lower second electrode is selected so that the standard generation Gibbs energy in the process of generating metal ions from the metal (oxidation process) is larger in the negative direction than ruthenium (Ru). Found it desirable.

  Titanium, tantalum, zirconium, hafnium, and aluminum have a chemical reaction (for example, oxidation reaction) compared to ruthenium because the standard generation Gibbs energy in the process of generating metal ions from metal (oxidation process) is larger in the negative direction than ruthenium. It is likely to happen spontaneously. Adhesion with metal bridge is improved by using a material in which the second metal is alloyed with ruthenium as a material for forming the lower second electrode. Two or more kinds of second metals may be added to ruthenium.

  It is desirable to use a sputtering method for forming the ruthenium alloy. There are at least three methods for depositing this alloy by sputtering. The first method uses an alloy target of ruthenium and a second metal. The second is a co-sputtering method in which a ruthenium target and a second metal target are simultaneously sputtered in the same chamber. The third is an intermixing method in which a thin film of a second metal is formed in advance, ruthenium is formed on the thin film using a sputtering method, and alloyed with the energy of collision atoms. Use of the co-sputtering method and the intermixing method has an advantage that the composition of the alloy can be changed. When adopting the intermixing method, it is preferable to heat-treat the second metal thin film and the ruthenium film at 400 ° C. or lower to complete the mixed state after the ruthenium film is formed.

  Furthermore, when copper, which is a metal cross-linking component, is mixed into the second electrode 22, the effect of adding a metal having a large standard Gibbs energy in the negative direction diminishes, so that the metal added to ruthenium has a barrier property against copper and copper ions. Some materials are preferred. Examples of the material include tantalum and titanium. In particular, when the second metal is titanium, the transition to the off state and the stability of the on state are excellent. Therefore, it is preferable that the material of the lower second electrode is an alloy of ruthenium and titanium, and the titanium content is in the range of 20 atm% to 30 atm%.

  The upper second electrode of the second electrode 22 serves to protect the ruthenium alloy corresponding to the lower second electrode from etching damage. The upper second electrode is formed when the second electrode 22 is processed to a specified element size, or when a contact hole for electrically connecting an external electrode to the lower second electrode is provided on the second electrode 22. Avoid direct exposure of ruthenium alloys related to switching performance. The upper second electrode also has a function as an etching stopper film when the contact hole is formed when the contact hole is formed. Therefore, it is preferable that the material of the upper second electrode has a low etching rate with respect to a plasma of a fluorocarbon gas used for etching an insulating film such as silicon oxide in which the contact hole is formed.

  The upper second electrode is made of a metal nitride. The material of the upper second electrode is particularly preferably a nitride of titanium, tantalum, zirconium, hafnium, or aluminum that functions as an etching stopper film and has conductivity. If a metal that is not a nitride is used for the upper second electrode, a part of the metal diffuses into the ruthenium alloy of the lower second electrode due to heating or plasma damage during the process, and these defects are the starting points. As a result, the dielectric breakdown voltage of the ion conductive layer may be reduced. Therefore, it is possible to prevent diffusion of metal to the ruthenium alloy of the lower second electrode by using a stable metal nitride which is a compound having electrical conductivity for the upper second electrode.

  In particular, it is preferable that the nitride metal constituting the upper second electrode and the ruthenium alloy second metal constituting the lower second electrode be the same metal. Thereby, the diffusion failure of the second metal can be prevented more efficiently. For example, when the lower second electrode is an alloy electrode of ruthenium and titanium, the upper second electrode is preferably a titanium nitride electrode. Alternatively, when the lower second electrode is an alloy of ruthenium and tantalum, the upper second electrode is a tantalum nitride electrode. By matching the metal components constituting the upper layer and the lower layer of the second electrode 22, it is difficult to form a defect even if the upper layer metal diffuses into the lower layer.

  A more preferable condition is to make the ratio of the metal to nitrogen of the nitride constituting the upper second electrode larger than the ratio of the second metal to ruthenium of the ruthenium alloy constituting the lower second electrode. In this case, it is possible to prevent the second metal contained in the lower second electrode from diffusing into the nitride constituting the upper second electrode and changing the composition of the lower second electrode. Specifically, when the upper second electrode is titanium nitride, the content of titanium is preferably 60 atm% or more and 80 atm% or less. If a composition outside this range is used, intermixing between the lower second electrode and the upper second electrode is likely to occur due to a thermal load during the process in a later step, and the switching characteristics are deteriorated.

  It is desirable to use a sputtering method for forming the second electrode 22. In the case of forming a metal nitride film using a sputtering method, it is preferable to use a reactive sputtering method in which a metal target is evaporated using plasma of a mixed gas of nitrogen and argon. In this method, the metal evaporated from the metal target reacts with nitrogen to form a metal nitride and is deposited on the substrate.

  Next, a method for driving the switching element of this embodiment will be described. FIG. 3 is a schematic cross-sectional view for explaining a method of driving the switching element shown in FIG. 2B.

  When the second electrode 22 is grounded and a positive voltage is applied to the first electrode 21, the metal of the alloy layer 25 becomes metal ions 35 via the first ion conductive layer 23 and dissolves in the second ion conductive layer 24. .

  Then, metal ions 35 in the first ion conductive layer 23 and the second ion conductive layer 24 are deposited as metal bridges 36 on the surface of the second electrode 22, and the first electrode 21 and the second electrode are deposited by the deposited metal bridges 36. The electrode 22 is connected. When the first electrode 21 and the second electrode 22 are electrically connected via the metal bridge 36, the switch is turned on. During the transition from the off state to the on state, the first metal contained in the alloy layer 25 is contained in the metal bridge 36.

  On the other hand, when the second electrode 22 is grounded and a negative voltage is applied to the first electrode 21 in the ON state, the metal bridge 36 dissolves as metal ions 35 in the first ion conductive layer 23 and the second ion conductive layer 24. Then, a part of the metal bridge 36 is cut. At this time, the metal ions 35 are dispersed in the first ion conductive layer 23 and the second ion conductive layer 24, or collected by the alloy layer 25 and the first electrode 21. Thereby, the electrical connection between the first electrode 21 and the second electrode 22 is cut, and the switch is turned off. To make a transition from the off state to the on state, a positive voltage may be applied to the second electrode 22 again. Also, the first electrode 21 is grounded and a negative voltage is applied to the second electrode 22 to turn on the switch, or the first electrode 21 is grounded and a positive voltage is applied to the second electrode 22 to turn off the switch. Or may be in a state.

  When the switch is turned off, the electrical characteristics such as the resistance between the first electrode 21 and the second electrode 22 increases and the capacitance between the electrodes changes from the stage before the electrical connection is completely cut off. There is a change and eventually the electrical connection is broken.

  Next, the manufacturing method of the switching element of this embodiment is demonstrated. 4A to 4D are schematic cross-sectional views illustrating manufacturing steps of the switching element of the present embodiment.

  As shown in FIG. 4A, a tantalum film having a thickness of 20 nm is formed on the surface of the low resistance silicon substrate 46 by a sputtering method, and a copper film having a thickness of 100 nm is formed thereon by a sputtering method. A laminated film of tantalum and copper is used as the first electrode 21.

  Subsequently, as shown in FIG. 4B, a first metal having a film thickness of 0.5 nm is formed on the first electrode 21 by sputtering, and argon (flow rate: 20 sccm) and oxygen (flow rate: 20 sccm) are placed in the chamber of the film forming apparatus. A mixed gas having a flow rate of 20 sccm is introduced to oxidize the first metal. Here, the first metal is Ti, Zr, Hf or Al. Further, a first metal having a thickness of 0.5 nm is formed on the oxidized first metal film by a sputtering method, and a mixed gas of argon (flow rate: 20 sccm) and oxygen (flow rate: 20 sccm) is placed in the chamber. Introduced and oxidized the first metal deposited additionally. In this way, the first ion conductive layer 23 is formed by stacking the oxide films of the first metal. In the process of forming the first ion conductive layer 23, the alloy layer 25 is spontaneously formed as shown in FIG. 4B. When forming the first ion conductive layer 23, the film thickness of the alloy layer 25 may be increased by heat treatment in an environment of 350 ° C. under vacuum.

  Since the alloy layer 25 is formed on the first electrode 21 side from the interface between the first electrode 21 and the first ion conductive layer 23, the subsequent steps will be described in the case of the configuration shown in FIG. 2A. . That is, in FIG. 4C and FIG. 4D, illustration of the alloy layer is omitted.

  Next, as shown in FIG. 4C, a SiOCH-based polymer film having a thickness of 7 nm is formed as a second ion conductive layer 24 on the first ion conductive layer 23 by a plasma CVD method. The method will be specifically described. The raw material of cyclic organosiloxane and helium, which is a carrier gas, flow into the reaction chamber, the supply of both stabilizes, and when the pressure in the reaction chamber becomes constant, application of RF power is started, and a predetermined film thickness is formed. Then, the application of RF power is stopped. The flow rate of the raw material supplied to the reaction chamber is 10 to 200 sccm. As for the supply of helium to the reaction chamber, the flow rate through the raw material vaporizer is 500 sccm, and the direct flow rate through another line is 500 sccm.

  Thereafter, as shown in FIG. 4D, an alloy of ruthenium and titanium is deposited to a thickness of 30 nm on the second ion conductive layer 24 by co-sputtering. The titanium content in the ruthenium-titanium alloy is 25 atm%. Subsequently, titanium nitride having a thickness of 50 nm is deposited on the alloy. The titanium content in titanium nitride is 70 atm%. When these films are deposited, the second electrode 22 having a square shape with a side pattern of 30 μm to 150 μm is formed by depositing through a shadow mask made of stainless steel or silicon.

  Next, the configuration of the semiconductor device when the switching element of this embodiment is formed in a multilayer wiring structure will be described. FIG. 5 is a schematic cross-sectional view showing a configuration example of the semiconductor device of this embodiment.

  As shown in FIG. 5, the semiconductor device has a configuration in which a multilayer wiring structure is provided on a semiconductor substrate 51. The multilayer wiring structure in FIG. 5 includes a first wiring 55, a second wiring 68, and a plug 69 that connects the first wiring 55 and the second wiring 68. A switching element 63 is provided between the plug 69 and the first wiring 55. In the present embodiment, the multilayer wiring is described as a two-layered structure including a first wiring and a second wiring. However, the number of wiring layers is not limited to two.

  In addition, the multilayer wiring structure includes an interlayer insulating film 52, a barrier insulating film 53, an interlayer insulating film 54, a barrier insulating film 57, a protective insulating film 64, an interlayer insulating film 65, an etching stopper film 66, an interlayer insulating film on the semiconductor substrate 51. 67 and a barrier insulating film 71 are sequentially stacked. A first wiring 55 is buried in a wiring groove formed in the interlayer insulating film 54 and the barrier insulating film 53 via a barrier metal 56. A second wiring 68 is embedded in a wiring groove formed in the interlayer insulating film 67 and the etching stopper film 66. Plugs 69 are embedded in prepared holes formed in the interlayer insulating film 65, the protective insulating film 64 and the hard mask film 62. The second wiring 68 and the plug 69 are integrally formed, and the side surfaces and the bottom surface of the second wiring 68 and the plug 69 are covered with a barrier metal 70.

  Between the multilayer wirings, an ion conductive layer 59, a lower second electrode 60 and an upper second electrode 61 formed in the opening of the barrier insulating film 57, and a first wiring 55 formed in the interlayer insulating film 54 are provided. A switching element 63 is provided. The ion conductive layer 59 includes a first ion conductive layer 59a and a second ion conductive layer 59b. A hard mask film 62 is formed on the upper second electrode 61. The upper surface and side surfaces of the stacked body of the ion conductive layer 59, the lower second electrode 60, the upper second electrode 61, and the hard mask film 62 are covered with a protective insulating film 64.

  When the switching element 63 is compared with the configuration shown in FIG. 2B, the lower second electrode 60 and the upper second electrode 61 correspond to the second electrode 22. The first ion conductive layer 59 a and the second ion conductive layer 59 b correspond to the first ion conductive layer 23 and the second ion conductive layer 24. The first electrode 21 shown in FIG. 2B corresponds to the first wiring 55. By using a part of the first wiring 55 as the lower electrode of the switching element 63, it is possible to reduce the electrode resistance while simplifying the number of steps. In the semiconductor device shown in FIG. 5, two lithography processes are added to the normal copper damascene wiring process. Therefore, the switching element 63 can be mounted only by creating a 2PR mask set necessary for the additional process. As a result, it is possible to reduce the resistance and cost of the element at the same time.

  As shown in FIG. 5, in the switching element 63, the first ion conductive layer 59a and the first wiring 55 are in direct contact with each other in the region of the opening formed in the barrier insulating film 57. An alloy layer 58 containing the diffused first metal is formed on the first wiring 55. The concentration of the first metal diffused in the alloy layer 58 decreases as the distance from the first ion conductive layer 59a increases, that is, as the distance toward the semiconductor substrate 51 increases. In the switching element 63, the plug 69 and the upper second electrode 61 are electrically connected via the barrier metal 70. The plug 69 is integrated with the second wiring 68 as described above.

  When a voltage is applied between the first wiring 55 and the second wiring 68 or a current flows, the switching element 63 performs on / off control. For example, the switching element 63 performs on / off control using electric field diffusion of metal ions supplied from the alloy layer 58 into the first ion conductive layer 59a and the second ion conductive layer 59b.

  Next, each configuration of the semiconductor device illustrated in FIG. 5 will be described in detail.

  The semiconductor substrate 51 is a substrate on which a semiconductor element (not shown) is formed. As the semiconductor substrate 51, for example, a substrate such as a silicon substrate, a single crystal substrate, an SOI (Silicon on Insulator) substrate, a TFT (Thin Film Transistor) substrate, and a liquid crystal manufacturing substrate can be used.

  The interlayer insulating film 52 is an insulating film formed on the semiconductor substrate 51. For the interlayer insulating film 52, for example, an insulating film such as a silicon oxide film or a low dielectric constant film (for example, a SiOCH film) having a relative dielectric constant lower than that of the silicon oxide film is used. The interlayer insulating film 52 may have a configuration in which a plurality of insulating films are stacked.

  The barrier insulating film 53 is an insulating film interposed between the interlayer insulating film 52 and the interlayer insulating film 54 and having a barrier property. The barrier insulating film 53 serves as an etching stopper layer when the wiring groove for the first wiring 55 is processed. For the barrier insulating film 53, for example, a silicon nitride film, a SiC film, a silicon carbonitride film, or the like is used. A wiring groove for embedding the first wiring 55 is formed in the barrier insulating film 53, and the first wiring 55 is embedded in the wiring groove via a barrier metal 56. The barrier insulating film 53 can also be removed depending on the selection of the etching conditions for the wiring trench.

  The interlayer insulating film 54 is an insulating film formed on the barrier insulating film 53. As the interlayer insulating film 54, for example, a silicon oxide film, a low dielectric constant film (for example, a SiOCH film) having a relative dielectric constant lower than that of the silicon oxide film, or the like is used. The interlayer insulating film 54 may have a configuration in which a plurality of insulating films are stacked. A wiring groove for embedding the first wiring 55 is formed in the interlayer insulating film 54, and the first wiring 55 is embedded in the wiring groove via a barrier metal 56.

  The first wiring 55 is a wiring embedded in a wiring groove formed in the interlayer insulating film 54 and the barrier insulating film 53 via a barrier metal 56. The first wiring 55 also serves as a lower electrode of the switching element 63 and is in direct contact with the first ion conductive layer 59a. The lower surface of the second ion conductive layer 59b is in direct contact with the first ion conductive layer 59a, and the upper surface is in direct contact with the lower second electrode 60. As the metal constituting the first wiring 55, a metal that can be diffused and ion-conducted in the ion conductive layer 59 is used. For example, copper or the like is used. The metal (for example, copper) constituting the first wiring 55 may be alloyed with aluminum.

  An alloy layer 58 of the first metal and the metal constituting the first wiring 55 is formed at the interface between the first wiring 55 and the first ion conductive layer 59a. The alloy layer 58 is not formed on the entire first wiring 55 but on the opening surface side of the barrier insulating film 57. If the entire first wiring 55 is the alloy layer 58, the specific resistance of the first wiring 55 is increased, and the power consumption during transmission of the logic signal is deteriorated. Further, if the entire first wiring 55 is the alloy layer 58, it may cause Joule heat generation, so that the generation of voids due to electromigration may be promoted and the wire may be disconnected. Therefore, the alloy layer 58 should not be formed on the entire first wiring 55.

  The barrier metal 56 is a conductive film having a barrier property that covers the side and bottom surfaces of the wiring for preventing the metal constituting the first wiring 55 from diffusing into the interlayer insulating film 54 and the lower layer. For the barrier metal 56, for example, when the first wiring 55 is made of a metal element whose main component is copper, a refractory metal such as tantalum, tantalum nitride, titanium nitride, tungsten carbonitride, or a nitride thereof, etc. Or a laminated film thereof.

  The barrier insulating film 57 is formed on the interlayer insulating film 54 including the first wiring 55 and has a role of preventing oxidation of the metal (for example, copper) forming the first wiring 55. The barrier insulating film 57 serves to prevent the metal constituting the first wiring 55 from diffusing into the interlayer insulating film 65, or during processing of the upper second electrode 61, the lower second electrode 60, and the ion conductive layer 59. It also serves as an etching stopper layer. For the barrier insulating film 57, for example, a SiC film, a silicon carbonitride film, a silicon nitride film, or a laminated film thereof is used. The barrier insulating film 57 is preferably made of the same material as the protective insulating film 64 and the hard mask film 62.

  The ion conductive layer 59 is formed on a part of the upper surface of the first wiring 55, the tapered surface of the opening of the barrier insulating film 57, and the barrier insulating film 57. In the outer peripheral region of the connection portion between the first wiring 55 and the first ion conductive layer 59a, the ion conductive layer 59 is provided along the tapered surface at least on the tapered surface of the opening of the barrier insulating film 57. Yes.

  The first ion conductive layer 59a and the second ion conductive layer 59b are films whose resistance changes (resistance change layer). For these ion conductive layers, a material whose resistance is changed by the action (diffusion, ion conduction, etc.) of metal ions generated from the metal constituting the first wiring 55 is used. When the resistance change of the switching element 63 accompanying the switching from the off state to the on state is performed by metal deposition by reduction of metal ions, a film capable of ion conduction is used for these ion conductive layers.

  The second ion conductive layer 59b is formed using a plasma CVD method. Specifically, the raw material of cyclic organosiloxane and helium, which is a carrier gas, flow into the reaction chamber, the supply of both stabilizes, and when the pressure in the reaction chamber becomes constant, application of RF power is started, Stop when film thickness is formed. The supply amount of the raw material is 10 to 200 sccm, and the supply amount of helium is 500 sccm via the raw material vaporizer.

  The first ion conductive layer 59a prevents the metal constituting the first wiring 55 from diffusing into the second ion conductive layer 59b during heating or plasma processing while the second ion conductive layer 59b is being deposited. Have a role to play. Further, the first ion conductive layer 59a has a role of preventing the first wiring 55 from being oxidized and facilitating diffusion to the second ion conductive layer 59b. The metal that forms the first ion conductive layer 59a is the first metal described above. When the first metal is, for example, zirconium, hafnium, aluminum, or titanium, these metals are exposed to an oxygen atmosphere under reduced pressure in the chamber of the film forming apparatus after film formation, and zirconium oxide, hafnium oxide, aluminum oxide, It becomes titanium oxide. These oxides become part of the ion conductive layer 59.

  The optimum film thickness of the metal film that forms the first ion conductive layer 59a is 0.5 to 1 nm. When the film thickness is 0.5 nm or more, the first ion conductive layer 59a is not formed by one “film formation and oxidation”, but the combination of “film formation and oxidation” is divided into two or more times. . The oxygen atmosphere is preferably in a state where argon at a flow rate of 20 sccm and oxygen at a flow rate of 20 sccm are mixed.

  The oxidation treatment for forming the first ion conductive layer 59a has the following trade-off relationship between the antioxidant power of copper and the degree of oxidation of the first ion conductive layer 59a. In order to prioritize the oxidation of the first ion conductive layer 59a, if the thickness of the metal film that becomes the element of the first ion conductive layer 59a is reduced, even the first wiring 55 is oxidized. On the other hand, in order to suppress the oxidation of the first wiring 55, if the thickness of the metal film that becomes the element of the first ion conductive layer 59a is increased, the metal film cannot be sufficiently oxidized, and the unoxidized metal is secondly oxidized. By diffusing into the ion conductive layer 59b, the leakage current at the off time increases. In addition, the metal film may be oxidized by exposing the metal film to the atmosphere or increasing the atmospheric pressure or the pressure of the chamber of the film forming apparatus. In these cases, the first wiring 55 is oxidized. In this embodiment, after the metal film is formed, the oxidation treatment is performed under reduced pressure in the chamber of the film forming apparatus without exposure to the atmosphere. Accordingly, the first ion conductive layer 59a can be formed by sufficiently oxidizing the metal film without oxidizing the first wiring 55.

  The metal film that forms the first ion conductive layer 59a is not limited to a single layer film, and may be a laminated film. The metal film is preferably formed by a sputtering method. The metal atoms or metal ions that have gained energy by sputtering enter the first wiring 55 and then diffuse and become part of the configuration of the alloy layer 58.

  In the alloy layer 58, when forming the first ion conductive layer 59a, the first metal diffuses into the first wiring 55 from the metal film that becomes the element of the first ion conductive layer 59a, and the metal constituting the first wiring 55 And the first metal are mixed. The concentration of the first metal contained in the alloy layer 58 decreases as the distance from the first ion conductive layer 59a increases. Further, since the concentration of the first metal is lower in the alloy layer 58 than in the first ion conductive layer 59a, when a positive voltage is applied to the first wiring 55, the copper in the first wiring 55 is ionized and the first metal 55 is ionized. It is injected into the first ion conductive layer 59a and the second ion conductive layer 59b and does not inhibit the electrochemical reaction.

  In order to promote the thickening of the alloy layer 58, a heat treatment may be performed either before or after the oxidation treatment, or both, after forming a metal film that becomes the element of the first ion conductive layer 59a. The heating temperature is preferably 400 ° C. or less, particularly 350 ° C. Further, the inside of the chamber may be brought into an oxygen atmosphere while being heated, and the formation of the first ion conductive layer 59a may be started. The first metal contained in the alloy layer 58 together with copper is a metal whose standard Gibbs energy is larger in the negative direction than copper, for example, zirconium, hafnium, aluminum, and titanium. When the alloy layer 58 contains the first metal, the first metal is mixed into the metal bridge from the alloy layer 58 when the switch transitions from the OFF state to the ON state. Adhesiveness increases and retention improves.

  In addition, the resistance temperature coefficient of metal cross-linking is reduced and the thermal stability is increased, which contributes to the improvement of retention. At that time, the resistivity increases compared to the case where the metal bridge is composed of pure copper only, so the efficiency of Joule heat generation at the transition to the off state is improved, and the current at the transition to the off is increased. It is possible to improve only the retention.

  The lower second electrode 60 is an electrode on the lower layer side of the upper electrode of the switching element 63, and is in direct contact with the second ion conductive layer 59b. In the lower second electrode 60, ruthenium, which is a metal that is less ionized than the metal constituting the first wiring 55 and is difficult to diffuse and ion-conduct in the second ion conductive layer 59b, and the metal that forms the first wiring 55 An alloy with a second metal having good adhesion is used. The second metal is, for example, titanium, tantalum, zirconium, hafnium, or aluminum.

  In the ruthenium alloy used as the material of the lower second electrode 60, as a second metal added to ruthenium, the standard generated Gibbs energy in the process of generating metal ions from the metal (oxidation process) is larger in the negative direction than ruthenium. It is desirable to select a metal. Titanium, tantalum, zirconium, hafnium, and aluminum have the property that the standard generation Gibbs energy in the process of generating metal ions from metal (oxidation process) is larger in the negative direction than ruthenium, and the chemical reaction is more likely to occur spontaneously than ruthenium. As shown, the reactivity is high. For this reason, as a ruthenium alloy for forming the lower second electrode 60, the use of an alloy of the second metal with ruthenium makes it possible to achieve adhesion with the metal bridge formed of the metal constituting the first wiring 55. improves.

  On the other hand, if the lower second electrode 60 is made of only the second metal without containing ruthenium, the reactivity is increased and the transition to the off state is not achieved. The reason will be explained. The transition from the on state to the off state proceeds by an oxidation reaction (dissolution reaction) of the metal bridge. When the lower second electrode 60 is composed of only the second metal, the standard generation Gibbs energy in the process of generating metal ions from the metal (oxidation process) is larger in the negative direction than the metal composing the first wiring 55. It will be. As a result, since the oxidation reaction of the lower second electrode 60 proceeds more than the oxidation reaction of the metal bridge formed of the metal constituting the first wiring 55, the transition to the off state cannot be made.

  For this reason, the metal material of the lower second electrode 60 needs to be an alloy containing ruthenium whose standard generation Gibbs energy in the process of generating metal ions from the metal (oxidation process) is smaller in the negative direction than copper.

  Furthermore, when copper, which is a metal bridging component, is mixed into the lower second electrode 60, the effect of adding a metal having a large standard Gibbs energy in the negative direction is diminished, so the metal added to ruthenium is a barrier against copper and copper ions. A material having a property is preferable. For example, tantalum or titanium. On the other hand, it is known that the on-state is stabilized as the amount of the added metal is increased, and it is known that the stability is improved even when the content of the added metal is 5 atm%. In particular, when the additive metal is titanium, the transition to the off state and the on state stability are excellent. Therefore, it is particularly preferable that the lower second electrode 60 is made of an alloy of ruthenium and titanium, and the titanium content is in the range of 20 atm% to 30 atm%. The ruthenium content in the ruthenium alloy is preferably 60 atm% or more and 90 atm% or less.

  It is desirable to use a sputtering method for forming the lower second electrode 60. As a method for forming an alloy film using a sputtering method, there are the above-described three methods (a method using an alloy target of ruthenium and a second metal, a co-sputtering method, and an intermixing method).

  Of the above three methods, the cosputtering method is preferable when the method using an alloy target of ruthenium and a second metal is compared with the cosputtering method. In the method using an alloy target composed of ruthenium and a second metal, since the sputtering yield of each material is different, the composition of the target is shifted during continuous use, and the composition of the film to be formed is dense. May be out of control. On the other hand, in the co-sputtering method, since the power applied to each target electrode can be set individually in advance, the composition of the film to be formed can be precisely controlled. In particular, the effect is large when titanium or tantalum is used as the second electrode.

  The upper second electrode 61 is an upper layer electrode in the upper electrode of the switching element 63, and is formed on the lower second electrode 60. The upper second electrode 61 has a role of protecting the lower second electrode 60. That is, since the upper second electrode 61 protects the lower second electrode 60, damage to the lower second electrode 60 during the manufacturing process can be suppressed, and the switching characteristics of the switching element 63 can be maintained. For the upper second electrode 61, for example, tantalum, titanium, tungsten, or a nitride thereof is used. The upper second electrode 61 also has a function as an etching stopper film when the plug 69 is formed on the lower second electrode 60. Therefore, it is preferable that the etching rate is low with respect to the plasma of the fluorocarbon gas used for etching the interlayer insulating film 65.

  The upper second electrode 61 is made of a metal nitride. The material of the upper second electrode 61 is particularly preferably a nitride of titanium, tantalum, zirconium, hafnium, or aluminum that functions as an etching stopper film and has conductivity. If a metal that is not a nitride is used for the upper second electrode 61, a part of the metal diffuses into the lower second electrode 60 due to heating or plasma damage during the process, so that defects are present in the lower second electrode 61. As a result, the breakdown voltage of the ion conductive layer 59 may be lowered starting from these defects. By using a stable metal nitride which is a compound having electrical conductivity for the upper second electrode 61, diffusion of metal to the lower second electrode 60 can be prevented.

  In particular, the nitride metal constituting the upper second electrode 61 and the additive metal of the ruthenium alloy constituting the lower second electrode 60 are preferably the same metal. Thereby, the diffusion failure of the additive metal of the ruthenium alloy can be prevented more efficiently. For example, when the lower second electrode 60 is an alloy electrode of ruthenium and titanium, the upper second electrode 61 is preferably a titanium nitride electrode. Alternatively, when the lower second electrode 60 is an alloy of ruthenium and tantalum, the upper second electrode 61 is a tantalum nitride electrode. Even if the metal of the upper second electrode 61 is diffused to the lower second electrode 60 by matching the additive metal of the lower second electrode 60 and the metal component contained in the upper second electrode 61, the defect Becomes difficult to form. At this time, the ratio of the metal to nitrogen of the nitride constituting the upper second electrode 61 may be made larger than the ratio of the additive metal to ruthenium of the ruthenium alloy constituting the lower second electrode 60. In this case, it is possible to prevent the additive metal in the lower second electrode 60 from diffusing into the nitride constituting the upper second electrode 61 and changing the composition of the ruthenium alloy constituting the lower second electrode 60. Specifically, when the upper second electrode 61 is titanium nitride, the titanium content is more preferably 60 atm% or more and 80 atm% or less.

  It is desirable to use a sputtering method for forming the upper second electrode 61. In the case of forming a metal nitride film using a sputtering method, it is preferable to use a reactive sputtering method in which a metal target is evaporated using plasma of a mixed gas of nitrogen and argon. The metal evaporated from the metal target reacts with nitrogen to form a metal nitride and is deposited on the substrate.

  The hard mask film 62 is a film that serves as a hard mask film and a passivation film when etching the upper second electrode 61, the lower second electrode 60, the second ion conductive layer 59b, and the first ion conductive layer 59a. For the hard mask film 62, for example, a silicon nitride film or the like is used.

  The hard mask film 62 is preferably made of the same material as the protective insulating film 64 and the barrier insulating film 57. That is, by surrounding the entire periphery of the switching element 63 with the same material, the material interface is integrated, so that intrusion of moisture and the like from the outside can be prevented, and oxygen and metal detachment from the switching element 63 itself can be prevented. It becomes like this.

  The protective insulating film 64 is an insulating film having a function of preventing detachment of oxygen from the second ion conductive layer 59b without damaging the switching element 63. As the protective insulating film 64, for example, a silicon nitride film, a silicon carbonitride film, or the like is used. The protective insulating film 64 is preferably made of the same material as the hard mask film 62 and the barrier insulating film 57. When these films are made of the same material, the protective insulating film 64, the barrier insulating film 57, and the hard mask film 62 are integrated to improve the adhesion at the interface and further enhance the protection of the switching element 63. it can.

  The interlayer insulating film 65 is an insulating film formed on the protective insulating film 64. For the interlayer insulating film 65, for example, a silicon oxide film, a SiOC film, a low dielectric constant film (for example, a SiOCH film) having a relative dielectric constant lower than that of the silicon oxide film, or the like is used. The interlayer insulating film 65 may have a configuration in which a plurality of insulating films are stacked. The interlayer insulating film 65 may be made of the same material as the interlayer insulating film 67.

  A pilot hole for embedding the plug 69 is formed in the interlayer insulating film 65, and the plug 69 is embedded through the barrier metal 70 in the pilot hole.

  The etching stopper film 66 is an insulating film interposed between the interlayer insulating film 65 and the interlayer insulating film 67. The etching stopper film 66 serves as an etching stopper layer when processing the wiring groove for the second wiring 68. For the etching stopper film 66, for example, a silicon nitride film, a SiC film, a silicon carbonitride film, or the like is used. In the etching stopper film 66, a wiring groove for embedding the second wiring 68 is formed, and the second wiring 68 is embedded in the wiring groove via a barrier metal 70. The etching stopper film 66 can be removed depending on the selection of the etching conditions for the wiring trench.

  The interlayer insulating film 67 is an insulating film formed on the etching stopper film 66. As the interlayer insulating film 67, for example, a silicon oxide film, a SiOC film, a low dielectric constant film (for example, a SiOCH film) having a relative dielectric constant lower than that of the silicon oxide film, or the like is used. The interlayer insulating film 67 may have a configuration in which a plurality of insulating films are stacked. The interlayer insulating film 67 may be made of the same material as the interlayer insulating film 65. In the interlayer insulating film 67, a wiring groove for embedding the second wiring 68 is formed, and the second wiring 68 is embedded in the wiring groove via the barrier metal 70.

  The second wiring 68 is a wiring formed by burying a conductive material through a barrier metal 70 in a wiring groove provided in the interlayer insulating film 67 and the etching stopper film 66. The second wiring 68 is integrated with the plug 69. The plug 69 is embedded in a prepared hole formed in the interlayer insulating film 65, the protective insulating film 64, and the hard mask film 62 via a barrier metal 70. The plug 69 is electrically connected to the upper second electrode 61 through the barrier metal 70. For example, copper is used as the material of the second wiring 68 and the plug 69.

  The barrier metal 70 is formed on the side surfaces and bottom surfaces of the second wiring 68 and the plug 69 in order to prevent the metal constituting the second wiring 68 and the plug 69 from diffusing into the interlayer insulating film 65, the interlayer insulating film 67, and the lower layer. A conductive film having a barrier property to be coated. For example, when the second wiring 68 and the plug 69 are made of a metal element whose main component is copper, the barrier metal 50 includes a refractory metal such as tantalum, tantalum nitride, titanium nitride, tungsten carbonitride, or nitride thereof. A thing etc. or those laminated films can be used. The barrier metal 70 is preferably made of the same material as the upper second electrode 61. For example, when the barrier metal 70 has a laminated structure of tantalum nitride (lower layer) / tantalum (upper layer), it is preferable to use tantalum nitride, which is a lower layer material, as the material of the upper second electrode 61.

  The barrier insulating film 71 is formed on the interlayer insulating film 67 including the second wiring 68 to prevent oxidation of the metal (for example, copper) constituting the second wiring 68, and the metal constituting the second wiring 68 is an upper layer. It is an insulating film having a role of preventing diffusion. For the barrier insulating film 71, for example, a silicon carbonitride film, a silicon nitride film, and a laminated structure thereof are used.

  Next, the characteristics of the switching element of this embodiment will be described.

  In the experiment, the semiconductor device shown in FIG. 5 was used. The semiconductor device used in the experiment has a configuration in which switching elements of a 4 kilobit array are provided in a multilayer wiring structure. Two types of experimental samples were prepared. Of the two types of experimental samples, one experimental sample is a semiconductor device including a switching element manufactured according to the manufacturing method of the present embodiment, and the other experimental sample is a switching element manufactured by a method different from the present embodiment. A semiconductor device including The other experimental sample is hereinafter referred to as “comparative example”.

  The experimental sample according to the present embodiment is obtained by repeating the process of forming 0.5 nm of zirconium and the oxidation process described with reference to FIG. 4B twice when forming the first ion conductive layer 59a. is there. In the experimental sample of the comparative example, after 1 nm of zirconium was formed as a metal film for forming the first ion conductive layer, the process was advanced to the next step without performing the oxidation treatment in the chamber. In both experimental samples, the thickness of zirconium serving as a metal film for forming the first ion conductive layer is 1 nm.

  In the OFF state and the ON state of the switching elements of the 4-kilobit array of each experimental sample, the current flowing between the wirings when 0.4 V was applied between the wirings of the respective elements was measured. The current value in the off state of the switching element is referred to as off current, and the current value in the on state is referred to as on current. In the transition from the OFF state to the ON state of the switching element, a positive voltage is applied to the first wiring 55 shown in FIG. 5, and in the transition from the ON state to the OFF state, a negative voltage is applied to the first wiring 55. For the on-state current and off-state current of each experimental sample, a normal distribution of measured current values for 4 kilobits was overlaid and plotted on a graph. FIG. 6A is a graph showing measurement results of on-state current and off-state current of the switching element of the comparative example, and FIG. 6B is a graph showing measurement results of on-state current and off-current of the switching element of this embodiment.

  The distribution of resistance values of semiconductors and resistance change elements is generally plotted as a normal distribution. When the distribution deviates from the normal distribution, it indicates an abnormal state such as a failure, and the normal probability plot is widely used as a plotting method for identifying such an event. In general, a normal probability plot indicates a normal distribution if there is linearity. The vertical axis “cumulative probability” in FIGS. 6A and 6B more accurately indicates “multiple of standard deviation” or “difference of standard deviation from average”. On the horizontal axis of the so-called histogram, the position is shifted by the standard deviation from the average value (the value with the highest frequency, usually 50%). The scale of the vertical axis “cumulative probability” in FIGS. 6A and 6B indicates “multiple of standard deviation” or “difference of standard deviation from average” when the average value of measured current values is set to “0”. Indicates. This value in probability display is used as a “cumulative failure probability” for reliability evaluation.

  The result shown in FIG. 6B is almost the same as the result shown in FIG. 6A, but the off-current is about one digit lower. That is, the off-state leakage current is about an order of magnitude lower. From this, it can be seen that the switching element of the present embodiment has a higher resistance in the off state than the switching element of the comparative example. In addition, the result shown in FIG. 6B does not change the slope of the normal distribution as compared with the result shown in FIG. 6A. From this, it can be seen that the switching element of this embodiment does not increase the variation in off-resistance as compared with the switching element of the comparative example.

  In addition, for each switching element of the 4-kilobit array of each experimental sample, the set voltage, which is a voltage that changes from the off-current to the on-state, and the off-state current (leakage current at the off time) were measured and plotted on a graph.

  FIG. 6C is a graph showing the relationship between the set voltage and the off current of the switching element of the comparative example, and FIG. 6D is a graph showing the relation between the set voltage and the off current of the switching element of this embodiment.

  Usually, in order to reduce the off-state current, a method of increasing the thickness of the first ion conductive layer or the second ion conductive layer is taken, but in this case, the set voltage also increases. However, when FIG. 6C is compared with FIG. 6D, only the off-state current can be reduced without increasing the set voltage in the switching element according to the method of forming the first ion conductive layer 59a described above. From this, it can be seen that the switching element of the present embodiment solves the trade-off relationship between the set voltage and the leakage current in the off state.

  Further, regarding the retention, when the switching element of the comparative example and the switching element of the present embodiment were compared, there was no difference.

  From these experimental results, in the switching element of the present embodiment, the alloy layer 58 is formed at the interface between the first wiring 55 and the first ion conductive layer 59a, and the metal bridge formed in the ion conductive layer 59 in the ON state. It is considered that the copper contained in the alloy layer 58 and zirconium serving as the element of the first ion conductive layer 59a are contained therein. In the manufacturing method of the present embodiment, the first ion conductive layer 59a is completely oxidized, and the alloy layer 58 is formed at the interface between the first wiring 55 and the first ion conductive layer 59a. An element in which 58 is not oxidized is formed.

  As a result, only the leakage current in the off state can be reduced.

  Further, in the switching element of the present embodiment, an increase in specific resistance and a decrease in reliability of the first wiring 55 were not confirmed. From this, it is considered that the alloy layer 58 is not diffused throughout the first wiring 55 but exists only in the vicinity of the interface between the first wiring 55 and the first ion conductive layer 59a. Further, in the first wiring 55, the concentration of the metal that becomes the element of the first ion conductive layer 59a decreases as the distance from the interface between the first wiring 55 and the first ion conductive layer 59a increases. It is thought that there is.

  Next, a method for manufacturing the semiconductor device shown in FIG. 5 will be described. 7A to 7L are schematic cross-sectional views showing manufacturing steps of the semiconductor device shown in FIG.

  A process until the first wiring 55 shown in FIG. 5 is formed will be described with reference to FIG. 7A. An interlayer insulating film 52 (for example, a silicon oxide film, a film thickness of 500 nm) is deposited on the semiconductor substrate 51. Subsequently, a barrier insulating film 53 (for example, a silicon carbonitride film, a film thickness of 30 nm) is deposited on the interlayer insulating film 52. After that, a laminated film made of a low dielectric constant film (for example, SiOCH film, film thickness 150 nm) and a silicon oxide film (for example, film thickness 100 nm) having a low relative dielectric constant is formed on the barrier insulating film 53 as the interlayer insulating film 54. accumulate. Further, a wiring groove is formed in the interlayer insulating film 54 and the barrier insulating film 53 by using a lithography method (including a process of forming a photoresist, dry etching, and removing a photoresist). Thereafter, the first wiring 55 (for example, copper) is embedded in the wiring groove through the barrier metal 56 (for example, a tantalum nitride / tantalum laminated film, film thickness of 5 nm / 5 nm).

  The interlayer insulating film 52 and the interlayer insulating film 54 can be formed by a plasma CVD method. The first wiring 55 can be formed as follows, for example. A barrier metal 56 is formed in the wiring groove by the PVD method, and subsequently a copper seed is formed by the PVD method, and then copper is embedded in the wiring groove by an electrolytic plating method. Thereafter, the formed copper is heat-treated at a temperature of 200 ° C. or higher, and then excess copper other than the copper embedded in the wiring trench is removed by a CMP (Chemical Mechanical Polishing) method. A general method in semiconductor manufacturing technology can be used for such a series of copper wiring forming methods.

  Here, the CMP method means that the wafer surface is brought into contact with a rotated polishing pad while flowing a polishing liquid over the wafer surface in order to flatten the unevenness of the wafer surface that occurs during the multilayer wiring formation process. This is a polishing method. By using the CMP method, excess copper protruding from the wiring trench is polished and removed, whereby a buried wiring (damascene wiring) is formed. In addition, by using the CMP method for an interlayer insulating film having an uneven surface, the surface of the interlayer insulating film can be polished and planarized.

  Although the case where the interlayer insulating film 52 is formed on the semiconductor substrate 51 has been described, another insulating film or a semiconductor element (for example, a resistance element) is formed between the semiconductor substrate 51 and the interlayer insulating film 52. Also good. A semiconductor element (for example, a transistor element) may be formed on the surface of the semiconductor substrate 51. The illustration of these semiconductor elements is omitted.

  After forming the first wiring 55, as shown in FIG. 7B, a barrier insulating film 57 (for example, a silicon nitride film or a silicon carbonitride film, a film thickness of 30 nm) is formed on the interlayer insulating film 54 including the first wiring 55. To do. The barrier insulating film 57 can be formed by a plasma CVD method. The thickness of the barrier insulating film 57 is preferably about 10 nm to 50 nm.

  Subsequently, as illustrated in FIG. 7C, a hard mask film 78 (for example, a silicon oxide film, a film thickness of 40 nm) is formed on the barrier insulating film 57. At this time, it is preferable that the hard mask film 78 is made of a material different from that of the barrier insulating film 57 from the viewpoint of keeping a large etching selection ratio in the dry etching process. The hard mask film 78 may be an insulating film or a conductive film. For the hard mask film 78, for example, a silicon oxide film, a silicon nitride film, titanium nitride, titanium, tantalum, tantalum nitride, or the like can be used. For example, a silicon nitride / silicon oxide film stack may be used for the hard mask film 78.

  Next, a photoresist (not shown) is formed on the hard mask film 78, and openings are patterned in the photoresist. Subsequently, an opening pattern is formed in the hard mask film 78 by dry etching using a photoresist having an opening as a mask. Thereafter, the photoresist is removed by oxygen plasma ashing or the like. The state is shown in FIG. 7D. At this time, the dry etching is not necessarily stopped on the upper surface of the barrier insulating film 57 and may reach the inside of the barrier insulating film 57.

  Using the hard mask film 78 shown in FIG. 7D as a mask, the barrier insulating film 57 exposed in the opening of the hard mask film 78 is etched back (dry etching). By this process, an opening is formed in the barrier insulating film 57 and the first wiring 55 is exposed from the opening of the barrier insulating film 57. Thereafter, the opening of the barrier insulating film 57 is exposed to plasma using a mixed gas of nitrogen and argon, thereby removing the copper oxide formed on the exposed surface of the first wiring 55, and at the same time, etching complex generated during the etch back. Remove products and the like. The state is shown in FIG. 7E.

  In the etch back of the barrier insulating film 57, the wall surface of the opening of the barrier insulating film 57 can be tapered by using reactive dry etching. In reactive dry etching, a gas containing fluorocarbon can be used as an etching gas. The hard mask film 78 is preferably completely removed during the etch-back, but may remain as it is when it is an insulating material. The planar pattern shape of the opening of the barrier insulating film 57 is, for example, a circle, and the circle has a diameter of 30 nm to 500 nm. The removal of the oxide on the surface of the first wiring 55 is performed by RF (Radio Frequency) etching using a non-reactive gas. As the non-reactive gas, helium or argon can be used.

  Subsequently, as illustrated in FIG. 7F, an ion conductive layer 59 is formed on the barrier insulating film 57 including the first wiring 55. This process will be described more specifically.

  First, zirconium having a film thickness of 0.5 nm is deposited on the barrier insulating film 57 including the first wiring 55 by a sputtering method. Subsequently, argon (flow rate: 20 sccm) and oxygen (flow rate: 20 sccm) are deposited in the chamber of the film formation apparatus. Zirconium is oxidized by flowing a mixed gas. This process is repeated twice to form a first ion conductive layer 59a composed of zirconium oxide having a total zirconium film thickness of 1 nm. At that time, the metal (zirconium) that becomes the element of the first ion conductive layer 59a diffuses into the portion of the first wiring 55 in contact with the first ion conductive layer 59a, and the alloy layer 58 is spontaneously formed. By performing annealing in a vacuum environment at a temperature of 350 ° C., the thickness of the alloy layer 58 can be increased. The annealing time is preferably about 2 minutes. Subsequently, as the second ion conductive layer 59b, a SiOCH-based polymer film is formed on the first ion conductive layer 59a by plasma CVD. The second ion conductive layer 59b is formed by supplying a cyclic organosiloxane raw material and a carrier gas helium into the reaction chamber, stabilizing the supply of both, and applying RF power when the pressure in the reaction chamber becomes constant. Is started and stopped when a predetermined film thickness is formed. The supply amount of the raw material is a flow rate of 10 to 200 sccm. Helium is supplied to the reaction chamber at a flow rate of 500 sccm via a raw material vaporizer, and is directly supplied to the reaction chamber via a separate line at a flow rate of 500 sccm.

  In addition, since moisture and the like are attached to the opening of the barrier insulating film 57 by the organic peeling process, it is removed by applying a heat treatment under reduced pressure at a temperature of about 250 ° C. to 350 ° C. before the ion conductive layer 59 is formed. It is preferable to gas.

  Next, as shown in FIG. 7G, an alloy of ruthenium and titanium (hereinafter referred to as an alloy film in the description of the manufacturing method) is formed on the second ion conductive layer 59b as the lower second electrode 60 with a thickness of 10 nm. The film thickness is formed by co-sputtering. At this time, the ruthenium target and the titanium target exist in the same chamber, and an alloy film is deposited by sputtering at the same time. Further, the power applied to the ruthenium target is 150 W, and the power applied to the titanium target is 50 W, so that the ruthenium content in the alloy film is 75 atm%.

  Subsequently, as shown in FIG. 7G, the upper second electrode 61 is formed on the lower second electrode 60. As the upper second electrode 61, titanium nitride is formed by reactive sputtering with a film thickness of 25 nm. At this time, the power applied to the titanium target is 600 W, and nitrogen gas and argon gas are introduced into the chamber for sputtering. Further, by setting the flow rate of nitrogen and the flow rate of argon to 1: 1, the content of titanium in titanium nitride is set to 70 atm%.

  Next, as shown in FIG. 7H, a hard mask film 62 (for example, a silicon nitride film or a silicon carbonitride film, a film thickness of 30 nm) and a hard mask film 83 (for example, a silicon oxide film, a film) are formed on the upper second electrode 61. Are stacked in order. The hard mask film 62 and the hard mask film 83 can be formed using a plasma CVD method. The hard mask film 62 and the hard mask film 83 can be formed using a general plasma CVD method in the semiconductor manufacturing technology.

The hard mask film 62 and the hard mask film 83 are preferably different types of films. For example, the hard mask film 62 is a silicon nitride film and the hard mask film 83 is a silicon oxide film. At this time, the hard mask film 62 is preferably made of the same material as the protective insulating film 64 and the barrier insulating film 71. In this case, by surrounding the entire periphery of the switching element with the same material, the material interface can be integrated to prevent intrusion of moisture and the like from the outside, and to prevent the desorption of oxygen and metal from the switching element itself. The hard mask film 62 can be formed by a plasma CVD method. As the hard mask film 62, for example, a high-density silicon nitride film formed by high-density plasma using a mixed gas of SiH ₄ / N ₂ is preferably used.

  Next, a photoresist (not shown) that covers a portion corresponding to the pattern of the switching element 63 is formed on the hard mask film 83 on the upper surface of the hard mask film 83. Then, using the photoresist as a mask, the hard mask film 83 is dry etched until the hard mask film 62 appears. Thereafter, the photoresist is removed using oxygen plasma ashing and organic peeling. The state is shown in FIG. 7I.

Subsequently, as shown in FIG. 7J, the hard mask film 62, the upper second electrode 61, the lower second electrode 60, and the ion conductive layer 59 are continuously dry-etched using the hard mask film 83 as a mask. At this time, the hard mask film 83 is preferably completely removed during the etch back, but may remain as it is. When the upper second electrode 61 is titanium nitride, the upper second electrode 61 can be processed by Cl ₂ -based RIE (Reactive Ion Etching). Further, when the lower second electrode 60 is an alloy of ruthenium and titanium, the alloy film can be processed by RIE with a mixed gas of Cl ₂ / O ₂ .

In the etching of the ion conductive layer 59, it is necessary to stop the dry etching on the barrier insulating film 57 on the lower surface. Here, as in the example described above, the second ion conductive layer 59b is a SiOCH-based polymer film, the first ion conductive layer 59a is zirconium oxide, and the barrier insulating film 57 is a silicon nitride film or a silicon carbonitride film. Consider a case. If such a film structure, CF _{4 based,} CF 4 / Cl _{2 system,} by adjusting the gas mixture in the etching conditions such as CF 4 / _Cl 2 / Ar system, processing the ion-conducting layer 59 by RIE be able to.

  By using such a hard mask RIE method, the laminated film can be processed into the pattern of the switching element 63 without exposing a portion corresponding to the switching element 63 to oxygen plasma ashing for resist removal. Further, when the oxidation process is performed by oxygen plasma after processing, the portion of the switching element 63 is covered with the hard mask film 83, so that the oxidation plasma process can be irradiated without depending on the resist peeling time. become.

  Next, a protective insulating film 64 (for example, nitrided) is formed on the barrier insulating film 57 including the hard mask film 83, the hard mask film 62, the upper second electrode 61, the lower second electrode 60, and the ion conductive layer 59 shown in FIG. A silicon film or a silicon carbonitride film (thickness 20 nm) is deposited. The state is shown in FIG. 7K.

Although the protective insulating film 64 can be formed by plasma CVD, it is necessary to maintain the pressure in the reaction chamber under reduced pressure before the film formation. At this time, oxygen is desorbed from the side surface of the ion conductive layer 59, and There arises a problem that the leakage current increases. In order to suppress the release of oxygen, it is preferable that the protective insulating film 64 be formed at a temperature of 300 ° C. or lower. Further, since the film is exposed to a film forming gas under a reduced pressure before film formation, it is preferable not to use a reducing gas. As the protective insulating film 64, for example, it is preferable to use a silicon nitride film formed by using a high-density plasma with a mixed gas of SiH ₄ / N ₂ at a substrate temperature of 300 ° C.

  Next, an interlayer insulating film 65 (for example, silicon oxide film), an etching stopper film 66 (for example, silicon nitride film), and an interlayer insulating film 67 (for example, silicon oxide film) are sequentially deposited on the protective insulating film 64. Thereafter, a wiring groove for the second wiring 68 and a pilot hole for the plug 69 are formed in the laminated film, and a barrier metal 70 (for example, tantalum nitride / tantalum) is formed in the wiring groove and the pilot hole using a copper dual damascene wiring process. The second wiring 68 (for example, copper) and the plug 69 (for example, copper) are simultaneously formed through the vias. Further, a barrier insulating film 71 (for example, a silicon nitride film) is deposited on the interlayer insulating film 67 including the second wiring 68. The state is shown in FIG. 7L.

  The formation of the second wiring 68 can use the same process as the formation of the lower layer wiring. At this time, by using the same material for the barrier metal 70 and the upper second electrode 61, the contact resistance between the plug 69 and the upper second electrode 61 can be reduced, and the device performance can be improved. The interlayer insulating film 65 and the interlayer insulating film 67 can be formed by a plasma CVD method. In order to eliminate the level difference caused by the switching element 63, the interlayer insulating film 65 may be deposited thick, and the interlayer insulating film 65 may be cut and flattened by CMP to make the interlayer insulating film 65 have a desired thickness.

  In the switching element of the present embodiment, since the first metal contained in the first ion conductive layer is alloyed with the copper of the first electrode, the metal bridge formed in the ion conductive layer when transitioning to the ON state It is taken in as a different metal. As a result, the thermal stability of the metal bridge is increased, and the adhesion is improved and the retention performance is improved by including the same metal in the metal bridge and the copper electrode. On the other hand, since the generation efficiency of Joule heat at the time of current application increases due to the increase in specific resistance accompanying alloying, the current at reset does not increase, and it resets with a current comparable to that of pure copper metal bridge it can.

  If the first metal is segregated at the interface between the copper electrode and the first ion conductive layer, or if the metal layer remains without being oxidized, the copper ionization reaction is hindered. Further, if the first metal is uniformly present in the copper wiring, the resistivity and reliability of the wiring are deteriorated. With respect to this problem, in this embodiment, an alloy layer of copper and a first metal is provided at the interface between the first electrode and the first ion conductive layer. Further, the first metal is distributed such that the concentration thereof is highest at the interface between the first electrode and the first ion conductive layer, and decreases from the interface toward the first electrode. Thus, the first metal is distributed with a concentration profile that is optimal for the formation of metal bridges.

  In the present embodiment, the metal layer is thermally diffused into the first electrode from the first metal film that is the element of the first ion conductive layer, so that the alloy layer is formed at the optimum position as described above. Specifically, after forming the first metal constituting the first ion conductive layer, by exposing to an oxygen atmosphere in a low temperature film forming chamber and oxidizing at a low speed, the copper electrode is not oxidized, A first ion conductive layer of a metal oxide having a composition close to the stoichiometric ratio can be formed. Further, according to this method, since the oxidation of the alloy layer can be prevented, a high purity alloy layer that does not contain oxygen can be formed. As a result, diffusion of the metal or copper in the low oxidation state into the ion conductive layer is suppressed, and the resistance value in the off state can be kept high. As a result, off-state leakage current can be reduced.

(Second Embodiment)
Although the case of a two-terminal switching element has been described in the first embodiment, the present embodiment relates to a three-terminal switching element. The switching element of this embodiment is provided with two switching elements described in the first embodiment, and the second electrode corresponding to the upper electrode is shared by the two switching elements. If it demonstrates with the structure shown to FIG. 2B, the switching element of this embodiment is the structure by which the 1st electrode 21 was isolate | separated into two.

  The configuration of the semiconductor device when the three-terminal switching element of this embodiment is formed in a multilayer wiring structure will be described. FIG. 8 is a schematic cross-sectional view showing a configuration example of the semiconductor device of this embodiment.

  First, in the semiconductor device shown in FIG. 8, attention is paid to the switching element of this embodiment, and its configuration will be briefly described.

  The multilayer wiring includes two first wirings 115a and 115b provided in the same layer and a second wiring 128 provided in a layer above the first wiring. The first wirings 115a and 115b are connected via the switching element 132 and the plug 129 of this embodiment.

  The switching element 132 includes a first wiring 115a corresponding to one of the two lower electrodes, a first wiring 115b corresponding to the other of the two lower electrodes, an ion conductive layer 119 corresponding to the resistance change layer, and an upper electrode. A corresponding lower second electrode 120 and upper second electrode 121 are provided.

  The upper second electrode 121 is electrically connected to the plug 129. The ion conductive layer 119 is configured to be interposed between the lower second electrode 120 and the first wirings 115a and 115b. The first wirings 115a and 115b serve not only as wiring but also as a lower electrode of the switching element 132. The ion conductive layer 119 includes a first ion conductive layer 119a and a second ion conductive layer 119b. The first ion conductive layer 119a is connected to two independent first wirings 115a and 115b made of copper through one opening provided in the barrier insulating film 117. The opening provided in the barrier insulating film 117 reaches the inside of the interlayer insulating film 114 in which the first wirings 115a and 115b are formed.

  In the switching element of this embodiment, if the first wiring 115a is the first electrode and the first wiring 115b is the third electrode, the first electrode and the third electrode are provided in the same layer, and the second electrode is the first electrode. The electrode and the third electrode are provided in a different layer.

  Next, the overall configuration of the semiconductor device shown in FIG. 8 will be described.

  In the multilayer wiring structure, an interlayer insulating film 112, a barrier insulating film 113, an interlayer insulating film 114, a barrier insulating film 117, a protective insulating film 124, an interlayer insulating film 125, an interlayer insulating film 127, and a barrier insulating film 131 are formed on a semiconductor substrate 111. It has the insulating laminated body laminated | stacked in order. First wirings 115a and 115b are embedded in wiring trenches formed in the interlayer insulating film 114 and the barrier insulating film 113 via barrier metals 116a and 116b. A second wiring 128 is embedded in a wiring groove formed in the interlayer insulating film 127. Plugs 129 are embedded in prepared holes formed in the interlayer insulating film 125, the protective insulating film 124, and the hard mask film 122. The second wiring 128 and the plug 129 are integrally formed, and the side surface and the bottom surface of the second wiring 128 and the plug 129 are covered with the barrier metal 130.

  Between the multilayer wirings, the ion conductive layer 119, the lower second electrode 120 and the upper second electrode 121 formed in the opening of the barrier insulating film 117, and the first wirings 115a and 115b formed in the interlayer insulating film 114, A switching element 132 having the above is provided. A hard mask film 122 is formed on the upper second electrode 121. The upper surface and side surfaces of the stacked body of the ion conductive layer 119, the lower second electrode 120, the upper second electrode 121, and the hard mask film 122 are covered with a protective insulating film 124.

  Since the first wiring 115a and the first wiring 115b also serve as the lower electrode of the switching element 132, the electrode resistance can be reduced while simplifying the number of processes. In the semiconductor device shown in FIG. 8, the lithography process added to the normal copper damascene wiring process is two steps. Therefore, the switching element 132 can be mounted only by creating a 2PR mask set necessary for the additional process. As a result, it is possible to reduce the resistance and cost of the element at the same time.

  Next, the configuration of the switching element of this embodiment will be described in detail. The switching element 132 is a variable resistance nonvolatile switching element. For example, the switching element 132 can be operated as a switching element using metal ion movement and electrochemical reaction in the ion conductor. As described above, the switching element 132 includes the first wiring 115a and the first wiring 115b serving as the lower electrode, and the upper second electrode 121 and the lower second electrode 120 that are electrically connected to the plug 129. The ion conductive layer 119 is interposed.

  As shown in FIG. 8, in the switching element 132, the first ion conductive layer 119a and the first wirings 115a and 115b are in direct contact with each other in the region of the opening formed in the barrier insulating film 117, and the upper second electrode On 121, the plug 129 and the upper second electrode 121 are electrically connected via the barrier metal 130.

  The operation of the switching element of this embodiment will be briefly described.

  The switching element 132 performs on / off control when a voltage is applied between the first wirings 115 a and 115 b and the second wiring 128 or a current flows. The switching element 132 performs on / off control by utilizing, for example, electric field diffusion of metal ions of the metals constituting the first wirings 115 a and 115 b from these wirings into the ion conductive layer 119.

  Next, each configuration of the semiconductor device illustrated in FIG. 8 will be described in detail.

  A detailed description of the same configuration as that described in the first embodiment is omitted. For example, the semiconductor substrate 111 corresponds to the semiconductor substrate 51 of the first embodiment. Each of the interlayer insulating films 112, 114, 125, and 127 corresponds to each of the interlayer insulating films 52, 54, 65, and 67 of the first embodiment. Each of the barrier insulating films 113, 117, and 131 corresponds to each of the barrier insulating films 53, 57, and 71 of the first embodiment.

  The protective insulating film 124 corresponds to the protective insulating film 64 of the first embodiment. The barrier metal 130 and the second wiring 128 correspond to the barrier metal 70 and the second wiring 68 of the first embodiment. The first ion conductive layer 119a and the second ion conductive layer 119b correspond to the first ion conductive layer 59a and the second ion conductive layer 59b of the first embodiment. The lower second electrode 120 and the upper second electrode 121 correspond to the lower second electrode 60 and the upper second electrode 61 of the first embodiment.

  First, the configuration of the first wirings 115a and 115b will be described with reference to FIG. The first wiring 115a and the first wiring 115b are wirings embedded in the wiring grooves formed in the interlayer insulating film 114 and the barrier insulating film 113 through the barrier metal 116a and the barrier metal 116b. As described above, the first wirings 115a and 115b serve as the lower electrode of the switching element 132 and are in direct contact with the first ion conductive layer 119a.

  As the material of the first wirings 115a and 115b, a metal that is a source of metal ions that can be diffused and ion-conducted in the ion conductive layer 119 is used. For example, copper or the like can be used as the first wirings 115a and 115b. The metal (for example, copper) constituting the first wirings 115a and 115b may be alloyed with aluminum.

  An electrode layer or the like may be inserted between the first wirings 115a and 115b and the first ion conductive layer 119a. When forming an electrode layer, the electrode layer and the metal film that becomes the element of the first ion conductive layer 119a may be deposited in a continuous process and processed in a continuous process. Further, the lower part of the first ion conductive layer 119a is not connected to the lower layer wiring via the contact plug.

  The barrier metal 116a and the barrier metal 116b are formed on the side and bottom surfaces of the wiring for preventing the metal (for example, copper) constituting the first wiring 115a and the first wiring 115b from diffusing into the interlayer insulating film 114 or the lower layer. A conductive film having a barrier property to be coated. Since the configuration and formation method of the barrier metals 116a and 116b are the same as those of the barrier metal 56 described in the first embodiment, detailed description thereof is omitted here.

  The barrier insulating film 117 has an opening in a region including a part of the upper surface of each of the first wiring 115a and the first wiring 115b. In the opening of the barrier insulating film 117, the first wirings 115a and 115b and the first ion conductive layer 119a are in contact with each other. The opening of the barrier insulating film 117 is formed so as to partially overlap the area of each planar pattern of the first wiring 115a and the first wiring 115b. With such a configuration, the switching element 132 can be formed on the surfaces of the first wirings 115a and 115b with small unevenness.

  The wall surface of the opening of the barrier insulating film 117 is a tapered surface that increases in area as the distance from the upper surface of the first wirings 115a and 115b increases. The tapered surface of the opening of the barrier insulating film 117 is set to have an angle of 85 ° or less with respect to the upper surfaces of the first wirings 115a and 115b. With such a configuration, electric field concentration at the outer periphery of the connection portion between the first wirings 115a and 115b and the first ion conductive layer 119a (near the outer periphery of the opening of the barrier insulating film 117) is reduced, and the insulation resistance Can be improved.

  The ion conductive layer 119 is a film whose resistance changes, and includes a second ion conductive layer 119b and a first ion conductive layer 119a. For the second ion conductive layer 119b, a material whose resistance is changed by the action (diffusion, ion conduction, etc.) of metal ions by the metal constituting the first wirings 115a and 115b (lower electrode) is used. When the resistance change of the switching element 132 accompanying the switching to the on state is performed by metal deposition by reduction of metal ions, a film capable of ion conduction is used for the second ion conductive layer 119b. For example, a SiOCH polymer film is used as the second ion conductive layer 119b.

  In the first ion conductive layer 119a, the metal constituting the first wirings 115a and 115b diffuses into the second ion conductive layer 119b during heating or plasma processing while the second ion conductive layer 119b is deposited. There is a role to prevent. The first ion conductive layer 119a has a role of preventing the first wirings 115a and 115b from being oxidized and facilitating diffusion to the second ion conductive layer 119b.

  The configuration and formation method of the first ion conductive layer 119a and the second ion conductive layer 119b are the same as those of the first ion conductive layer 59a and the second ion conductive layer 59b described in the first embodiment. Detailed description is omitted.

  The alloy layer 126a and the alloy layer 126b are spontaneously formed when the first ion conductive layer 119a is formed and the metal that becomes the element of the first ion conductive layer 119a diffuses into the first wiring 115a and the first wiring 115b. Is done. Since the configuration, role, and formation method of the alloy layers 126a and 126b are the same as those of the alloy layer 58 described in the first embodiment, detailed description thereof is omitted here.

  The lower second electrode 120 is an electrode on the lower layer side of the upper electrode of the switching element 132, and is in direct contact with the second ion conductive layer 119b. It is desirable to use a sputtering method to form the lower second electrode 120. As described in the first embodiment, there are three methods for forming an alloy film using a sputtering method. Among them, when the intermixing method is adopted, it is preferable to add a heat treatment at 400 ° C. or lower in order to flatten the mixed state after completing the ruthenium film formation.

  The upper second electrode 121 is an upper layer electrode in the upper electrode of the switching element 132 and is formed on the lower second electrode 120. The upper second electrode 121 and the barrier metal 130 are preferably made of the same material. With such a configuration, the barrier metal 130 of the plug 129 and the upper second electrode 121 can be integrated, the contact resistance can be reduced, and the reliability can be improved by improving the adhesion.

  Since the lower second electrode 120 and the upper second electrode 121 have the same configuration as the lower second electrode 60 and the upper second electrode 61, detailed description thereof is omitted here.

  The second wiring 128 is a wiring formed by burying a conductive material through a barrier metal 130 in a wiring groove provided in the interlayer insulating film 127. The second wiring 128 is integrated with the plug 129. The plug 129 is embedded in a prepared hole formed in the interlayer insulating film 125, the protective insulating film 124, and the hard mask film 122 through the barrier metal 130. The plug 129 is electrically connected to the upper second electrode 121 through the barrier metal 130.

  For the second wiring 128 and the plug 129, for example, copper can be used. The diameter or area of the planar region where the plug 129 (strictly speaking, the barrier metal 130 covering the bottom surface of the plug 129) and the upper second electrode 121 are in contact with each other is limited by the first wiring. 115a, 115b and the first ion conductive layer 119a are set so as to be smaller than the diameter or area of the planar region in contact.

  Since the second wiring 128 and the plug 129 have the same configuration as the second wiring 68 and the plug 69 described in the first embodiment, a detailed description thereof is omitted here.

  Next, a method for manufacturing the semiconductor device shown in FIG. 8 will be described. 9A to 9L are schematic cross-sectional views showing manufacturing steps of the semiconductor device shown in FIG.

  The method for forming the multilayer wiring in the semiconductor device shown in FIG. 8 is the same as the method for forming the multilayer wiring described with reference to FIGS. 7A to 7L in the first embodiment. Detailed description is omitted. The film types, film thicknesses, and materials of the conductive film and the insulating film shown in FIGS. 9A to 9L are the same as those described with reference to FIGS. 7A to 7L, respectively. It is assumed that the thickness and material are the same, and detailed description thereof is omitted here.

  First, steps required until the first wirings 115a and 115b shown in FIG. 8 are formed will be described with reference to FIG. 9A.

  An interlayer insulating film 112 is deposited on the semiconductor substrate 111. Subsequently, a barrier insulating film 113 is deposited on the interlayer insulating film 112. Thereafter, a laminated film made of a low dielectric constant film having a low relative dielectric constant and a silicon oxide film is deposited on the barrier insulating film 113 as the interlayer insulating film 114. Further, two wiring trenches are formed in the interlayer insulating film 114 and the barrier insulating film 113 by using a lithography method (including a photoresist formation process, a dry etching process, and a photoresist removal process). Thereafter, conductive films (for example, copper) are buried in the two wiring trenches via the barrier metals 116a and 116b to form the first wirings 115a and 115b.

  In this step, the first wiring 115a and the first wiring 115b can be formed as follows. For example, barrier metals 116a and 116b are formed by the PVD method, and subsequently a copper seed is formed by the PVD method, and then copper is embedded in the wiring trench by the electrolytic plating method. Then, after heat-processing with respect to the formed copper at the temperature of 200 degreeC or more, excess copper other than the copper embedded in the wiring groove | channel is removed by CMP method. A general method in semiconductor manufacturing technology can be used for such a series of copper wiring forming methods.

  As shown in FIG. 9B, a barrier insulating film 117 (for example, a silicon carbonitride film, a film thickness of 30 nm) is formed on the interlayer insulating film 114 including the first wirings 115a and 115b. Subsequently, as shown in FIG. 9C, a hard mask film 148 is formed on the barrier insulating film 117. Since the configuration and the formation method of the hard mask film 148 are the same as those of the hard mask film 78 described with reference to FIG. 7C, detailed description thereof is omitted.

  Next, a photoresist (not shown) is formed on the hard mask film 148, and openings are patterned in the photoresist. Subsequently, an opening pattern is formed in the hard mask film 148 by dry etching using a photoresist having an opening as a mask. Thereafter, the photoresist is removed by oxygen plasma ashing or the like. The state is shown in FIG. 9D.

  Using the hard mask film 148 shown in FIG. 9D as a mask, the barrier insulating film 117 exposed in the opening of the hard mask film 148 is etched back (dry etching). By this treatment, an opening is formed in the barrier insulating film 117, and a part of the upper surface of the first wirings 115a and 115b is exposed from the opening of the barrier insulating film 117. At this time, the opening may reach the inside of the interlayer insulating film 114. Thereafter, the opening of the barrier insulating film 117 was exposed to plasma using a mixed gas of nitrogen and argon, thereby removing the copper oxide formed on the exposed surfaces of the first wirings 115a and 115b and generating the etch back. Etching byproducts are removed. This state is shown in FIG. 9E.

  In this step, by using reactive dry etching for etch back of the barrier insulating film 117, the wall surface of the opening of the barrier insulating film 117 can be tapered.

  Subsequently, as illustrated in FIG. 9F, an ion conductive layer 119 is formed on the barrier insulating film 117 including the first wirings 115a and 115b. Since the formation method of the ion conductive layer 119 is the same as the formation method of the first ion conductive layer 59a and the second ion conductive layer 59b described with reference to FIG. 7F, detailed description thereof is omitted here. In brief, the first ion conductive layer 119a is formed by repeating a process of forming a 0.5 nm-thickness zirconium film and a process of oxidizing zirconium under reduced pressure twice. At this time, alloy layers 126a and 126b are formed at the interface between the first wirings 115a and 115b and the first ion conductive layer 119a. The second ion conductive layer 119b is formed on the first ion conductive layer 119a by plasma CVD using a SiOCH polymer film.

  For the purpose of removing moisture and the like attached to the opening of the barrier insulating film 117, degassing is performed by applying a heat treatment under reduced pressure at a temperature of about 250 ° C. to 350 ° C. before the ion conductive layer 119 is formed. It is preferable to keep the same as in the first embodiment. At that time, care should be taken such as making the inside of the chamber a vacuum or a nitrogen atmosphere so as not to oxidize the copper surface again. In this step, before the ion conductive layer 119 is formed, gas cleaning using hydrogen gas or plasma using argon gas is applied to the first wirings 115a and 115b exposed in the openings of the barrier insulating film 117. A cleaning process may be performed. By such treatment, when the ion conductive layer 119 is formed, copper oxidation of the first wirings 115a and 115b can be suppressed, and thermal diffusion (mass transfer) of copper during the process can be suppressed.

  Next, as shown in FIG. 9G, an alloy of ruthenium and titanium (hereinafter referred to as an alloy film in the description of the manufacturing method) is formed as a lower second electrode 120 on the second ion conductive layer 119b. The film thickness is formed by co-sputtering. At this time, the power applied to the ruthenium target is 150 W, and the power applied to the titanium target is 50 W, so that the titanium content in the alloy film is 25 atm% and the ruthenium content is 75 atm%.

  Subsequently, as illustrated in FIG. 9G, the upper second electrode 121 is formed on the lower second electrode 120. As the upper second electrode 121, titanium nitride is formed with a thickness of 25 nm by reactive sputtering.

  Next, as shown in FIG. 9H, a hard mask film 122 (for example, a silicon nitride film, a film thickness of 30 nm) and a hard mask film 153 (for example, a silicon oxide film, a film thickness of 80 nm) are sequentially formed on the upper second electrode 121. Laminate. The configuration and formation method of the hard mask film 122 and the hard mask film 153 are the same as those of the hard mask film 62 and the hard mask film 83 described with reference to FIG.

  The hard mask film 122 can be formed by a plasma CVD method, but it must be maintained under reduced pressure in the reaction chamber before the film formation. However, there is a problem that oxygen is desorbed from the ion conductive layer 119 while being held under reduced pressure, and leakage current of the ion conductive layer 119 increases due to oxygen defects. In order to suppress the problem, it is preferable to set the film forming temperature to 350 ° C. or lower. Further, since the film is exposed to a film forming gas under reduced pressure before film formation, it is preferable not to use a reducing gas. For example, it is preferable to use a silicon nitride film formed by high density plasma using a mixed gas of SiH 4 / N 2 as a raw material.

  Next, a photoresist (not shown) that covers a portion corresponding to the pattern of the switching element 132 is formed on the hard mask film 153 on the upper surface of the hard mask film 153. Then, using the photoresist as a mask, the hard mask film 153 is dry etched until the hard mask film 122 appears. Thereafter, the photoresist is removed using oxygen plasma ashing. The state is shown in FIG. 9I.

  Subsequently, using the hard mask film 153 as a mask, the hard mask film 122, the upper second electrode 121, the lower second electrode 120, and the ion conductive layer 119 are continuously dry-etched. At this time, the hard mask film 153 is preferably completely removed during the etch back, but may remain as it is. FIG. 9J shows the case where the hard mask film 153 is removed. Since the etching conditions in this step are the same as those described with reference to FIG. 7J, detailed description thereof is omitted.

  Next, a protective insulating film 124 (for example, a silicon nitride film, a film) is formed on the barrier insulating film 117 including the hard mask film 122, the upper second electrode 121, the lower second electrode 120, and the ion conductive layer 119 shown in FIG. 9J. 20 nm thick) is deposited. The state is shown in FIG. 9K. The method of forming the protective insulating film 124 in this step is the same as that of the protective insulating film 64 described with reference to FIG.

  Subsequently, on the protective insulating film 124, an interlayer insulating film 125 (for example, a silicon oxide film, a film thickness of 150 nm) and an interlayer insulating film 127 (for example, a laminated film of a 150 nm thick SiOC film and a 100 nm thick silicon oxide film) ) In order. Thereafter, a wiring groove for the second wiring 128 and a pilot hole for the plug 129 are formed, and the second wiring 128 (for example, copper copper) is formed through the barrier metal 130 in the wiring groove and the pilot hole using a copper dual damascene wiring process. ) And plug 129 (eg, copper) are formed simultaneously. Further, a barrier insulating film 131 (for example, a silicon nitride film) is deposited on the interlayer insulating film 127 including the second wiring 128. The state is shown in FIG. 9L.

  The configuration and formation method of the interlayer insulating films 125 and 127, the plug 129, and the second wiring 128 are the same as those of the interlayer insulating films 65 and 67, the plug 69, and the second wiring 68 described with reference to FIG. The detailed explanation is omitted.

  According to the present embodiment, the same effect as that of the first embodiment can be obtained even in a three-terminal switching element.

  As described above, in the switching elements of the first and second embodiments, both the on-state retention performance can be improved and the off-state leakage current can be reduced. Therefore, when this switching element is applied to a programmable logic wiring changeover switch, both low power consumption and high reliability during operation can be achieved. In addition, even when a plurality of switching elements are connected in parallel, the leakage current is kept low, so that information can be simultaneously written into a large number of elements.

  Note that the switching element of the present embodiment may have the following configuration.

(Appendix 1)
A first electrode;
A second electrode provided in a different layer from the first electrode;
A third electrode provided in the same layer as the first electrode;
A variable resistance layer provided between the first electrode, the third electrode, and the second electrode;
The variable resistance layer includes a first ion conductive layer in contact with the first electrode and the third electrode, and a second ion conductive layer in contact with the second electrode,
The first electrode and the third electrode include the same type of metal as the metal included in the first ion conductive layer,
The metal is distributed such that the concentration of the metal decreases from the interface between each of the first electrode and the third electrode and the first ion conductive layer toward the inside of each of the first electrode and the third electrode. Switching element.

  The resistance change element of the present invention can be used as a nonvolatile switching element. In particular, the variable resistance element of the present invention can be used as a nonvolatile switching element constituting an electronic device such as a programmable logic and a memory.

  The present invention has been described above using the above-described embodiment as an exemplary example. However, the present invention is not limited to the above-described embodiment. That is, the present invention can apply various modes that can be understood by those skilled in the art within the scope of the present invention.

  This application claims the priority on the basis of Japanese application Japanese Patent Application No. 2015-72245 for which it applied on March 31, 2015, and takes in those the indications of all here.

21 1st electrode 22 2nd electrode 23, 59a, 119a 1st ion conduction layer 24, 59b, 119b 2nd ion conduction layer 63, 132 Switching element 55, 115a, 115b 1st wiring 68, 128 2nd wiring 60, 120 Lower second electrode 61, 121 Upper second electrode

Claims (10)

A first electrode and a second electrode;
A variable resistance layer provided between the first electrode and the second electrode,
The variable resistance layer includes a first ion conductive layer in contact with the first electrode and a second ion conductive layer in contact with the second electrode.
The first electrode includes the same kind of metal as the metal included in the first ion conductive layer,
The switching element, wherein the metal is distributed so that a concentration of the metal decreases from an interface between the first electrode and the first ion conductive layer in a direction in the first electrode.   The switching element according to claim 1, wherein the metal contained in the first ion conductive layer includes at least one of titanium, tantalum, zirconium, hafnium, and aluminum.   The switching element according to claim 1, wherein the first ion conductive layer is a metal oxide.   4. The switching element according to claim 1, wherein a concentration of the metal contained in the first ion conductive layer is higher than a concentration of the metal in the first electrode. 5.   5. The switching element according to claim 1, wherein the first electrode includes copper, and the second electrode includes ruthenium. 6. The switching element according to any one of claims 1 to 5,
Multilayer wiring having wiring provided in at least two layers,
Of the two layers of wiring, one wiring is the first electrode,
The semiconductor device, wherein the other of the two layers of wiring is connected to the second electrode through a plug. Forming a first electrode on the substrate;
Forming a metal film on the first electrode;
After forming the metal film, without exposing to the atmosphere, the metal film is oxidized under reduced pressure to form a first ion conductive layer,
Forming a second ion conductive layer on the first ion conductive layer;
Forming a second electrode on the second ion conductive layer;
A method for manufacturing a switching element.   The method for manufacturing a switching element according to claim 7, wherein a combination of the formation of the metal film and the formation of the first ion conductive layer is repeated at least twice.   The method of manufacturing a switching element according to claim 7 or 8, wherein in forming the first ion conductive layer, the metal film is heated under reduced pressure before the metal film is oxidized.   10. The method of manufacturing a switching element according to claim 7, wherein in forming the first ion conductive layer, the metal film is oxidized while being heated.

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