JPWO2016093075A1 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JPWO2016093075A1
JPWO2016093075A1 JP2016563610A JP2016563610A JPWO2016093075A1 JP WO2016093075 A1 JPWO2016093075 A1 JP WO2016093075A1 JP 2016563610 A JP2016563610 A JP 2016563610A JP 2016563610 A JP2016563610 A JP 2016563610A JP WO2016093075 A1 JPWO2016093075 A1 JP WO2016093075A1
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semiconductor device
laminated structure
thickness
adhesive layer
component
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JP6419845B2 (en
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雄志 金野
雄志 金野
菊地　広
広 菊地
聡 池尾
聡 池尾
健次 桑野
健次 桑野
徳安　昇
徳安　　昇
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Hitachi Astemo Ltd
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Hitachi Automotive Systems Ltd
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    • C—CHEMISTRY; METALLURGY
    • C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09J—ADHESIVES; NON-MECHANICAL ASPECTS OF ADHESIVE PROCESSES IN GENERAL; ADHESIVE PROCESSES NOT PROVIDED FOR ELSEWHERE; USE OF MATERIALS AS ADHESIVES
    • C09J7/00—Adhesives in the form of films or foils
    • C09J7/10—Adhesives in the form of films or foils without carriers
    • C—CHEMISTRY; METALLURGY
    • C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09J—ADHESIVES; NON-MECHANICAL ASPECTS OF ADHESIVE PROCESSES IN GENERAL; ADHESIVE PROCESSES NOT PROVIDED FOR ELSEWHERE; USE OF MATERIALS AS ADHESIVES
    • C09J201/00—Adhesives based on unspecified macromolecular compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/52—Mounting semiconductor bodies in containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

積層部品の厚さに、例えば公差に基づくばらつきがある場合でも、積層構造体の総厚を一定に制御することができる半導体装置を提供することにある。本発明の半導体装置１は、複数の構成部品２０、３０、４０、５０、６０が積層されて構成された積層構造体２を有する。積層構造体２は、第１の構成部品２０と第２の構成部品４０との間に介在されて接着し、厚さ方向に圧縮されることにより塑性変形して厚さが薄くなる接着剤層３０を有する。An object of the present invention is to provide a semiconductor device capable of controlling the total thickness of a laminated structure to be constant even when the thickness of the laminated component varies, for example, due to tolerances. The semiconductor device 1 of the present invention has a laminated structure 2 configured by laminating a plurality of component parts 20, 30, 40, 50, 60. The laminated structure 2 is interposed between and bonded to the first component 20 and the second component 40, and is compressed in the thickness direction so as to be plastically deformed to reduce the thickness of the adhesive layer. 30.

Description

本発明は、複数の構成部品が積層されて構成された積層構造体を有する半導体装置に関する。   The present invention relates to a semiconductor device having a stacked structure formed by stacking a plurality of component parts.

特許文献１には、半導体チップや放熱板等の複数の構成部品を厚さ方向に順番に積層して構成された半導体装置の構造が示されている。   Patent Document 1 discloses a structure of a semiconductor device configured by sequentially stacking a plurality of components such as a semiconductor chip and a heat sink in the thickness direction.

特開２０１２−１５２２５号公報JP 2012-15225 A

半導体チップや放熱板等の各構成部品は厚さにそれぞれ公差を有しているので各構成部品を重ねて積層構造体を構成した場合に、各構成部品の公差が加算され、積層構造体全体の厚さ方向の公差も大きくなる。したがって、例えば積層構造体を金線ワイヤで接続する際に、公差を吸収するための調整が必要となる。また、積層構造体の表面に設けられたセンサが封止樹脂から部分的に露出する封止構造を半導体装置が有する場合には、積層構造体の表面と封止樹脂の表面との間の段差距離が個体毎に異なり、検出精度への影響が懸念される。   Each component, such as a semiconductor chip and heat sink, has a tolerance in thickness, so when each component is stacked to form a laminated structure, the tolerance of each component is added, and the entire laminated structure The tolerance in the thickness direction is also increased. Therefore, for example, when connecting laminated structures with gold wire, adjustment for absorbing tolerance is required. Further, when the semiconductor device has a sealing structure in which the sensor provided on the surface of the laminated structure is partially exposed from the sealing resin, a step between the surface of the laminated structure and the surface of the sealing resin The distance varies from individual to individual, and there is concern about the effect on detection accuracy.

本発明は、上記の点に鑑みてなされたものであり、その目的とするところは、積層部品の厚さに、例えば公差に基づくばらつきがある場合でも、積層構造体の総厚を一定に制御することができる半導体装置を提供することにある。   The present invention has been made in view of the above points, and an object of the present invention is to control the total thickness of the laminated structure to be constant even when the thickness of the laminated component has variations due to tolerances, for example. An object of the present invention is to provide a semiconductor device that can be used.

上記課題を解決する本発明の半導体装置は、複数の構成部品が積層されて構成された積層構造体を有する半導体装置であって、前記積層構造体は、第１の構成部品と第２の構成部品との間に介在されて接着し、厚さ方向に圧縮されることにより塑性変形して厚さが薄くなる接着剤層を有することを特徴とする。   A semiconductor device of the present invention that solves the above-described problem is a semiconductor device having a laminated structure in which a plurality of component parts are laminated, and the laminated structure includes a first component and a second component. It is characterized by having an adhesive layer that is interposed between and bonded to a component and is plastically deformed by being compressed in the thickness direction so that the thickness is reduced.

本発明によれば、圧縮力を印加することで接着剤層を塑性変形させ、各構成部品の厚さのばらつきを接着剤層の変形で吸収して、積層構造体の総厚を設定値に調整することができる。なお、上記した以外の課題、構成及び効果は、以下の実施形態の説明により明らかにされる。   According to the present invention, the adhesive layer is plastically deformed by applying a compressive force, and variations in the thickness of each component are absorbed by the deformation of the adhesive layer, so that the total thickness of the laminated structure is set to a set value. Can be adjusted. Problems, configurations, and effects other than those described above will be clarified by the following description of the embodiments.

本発明に係る半導体装置の積層構造体の一実施形態を説明する図。4A and 4B illustrate an embodiment of a stacked structure of a semiconductor device according to the invention. 総厚が基準値に調整された積層構造体を示す断面図。Sectional drawing which shows the laminated structure in which total thickness was adjusted to the reference value. 本発明に係る半導体装置の積層構造体を樹脂モールドした構造を示す断面図。Sectional drawing which shows the structure which resin-molded the laminated structure of the semiconductor device which concerns on this invention. 第２の接着剤層により積層構造体の総厚が一定に調整された半導体装置の構造を示す断面図。Sectional drawing which shows the structure of the semiconductor device by which the total thickness of the laminated structure was adjusted uniformly by the 2nd adhesive bond layer. 従来の積層構造体の構成を示す断面図。Sectional drawing which shows the structure of the conventional laminated structure. 従来の半導体装置の構造を示す断面図。Sectional drawing which shows the structure of the conventional semiconductor device.

半導体装置である半導体パッケージは、一般的にセラミックパッケージと樹脂パッケージに分類される。樹脂パッケージは、リードフレーム上に半導体チップを搭載し、全体を樹脂で封止するトランスファーモールド法により製造される。トランスファーモールド法により製造された半導体パッケージは、半導体チップの周囲がモールド樹脂で覆われるため、外部環境から機械的に遮断された構造となっている。   A semiconductor package which is a semiconductor device is generally classified into a ceramic package and a resin package. The resin package is manufactured by a transfer mold method in which a semiconductor chip is mounted on a lead frame and the whole is sealed with resin. The semiconductor package manufactured by the transfer molding method has a structure in which the periphery of the semiconductor chip is mechanically cut off from the external environment because the periphery of the semiconductor chip is covered with the mold resin.

近年、モールド樹脂の一部を開口し、従来はモールド樹脂内に覆われていた半導体チップやリードフレームや放熱部品等を外部環境に露出する、外部露出型の半導体パッケージが使われるようになっている。例えば、特許文献１に記載されている外部露出型の半導体パッケージは、放熱板の一部をパッケージ外部に露出することにより、半導体チップの発生する熱を低熱抵抗で外部に放熱する効果を発揮している。また、同様に、半導体センサ等の一部をパッケージ外部に露出させることで、センサの感度を向上させるなどの目的で使用されている場合もある。   In recent years, externally exposed semiconductor packages have been used in which a part of the mold resin is opened to expose the semiconductor chip, lead frame, heat dissipation component, etc. that were previously covered in the mold resin to the external environment. Yes. For example, the externally exposed semiconductor package described in Patent Document 1 exhibits the effect of radiating the heat generated by the semiconductor chip to the outside with a low thermal resistance by exposing a part of the heat radiating plate to the outside of the package. ing. Similarly, a part of a semiconductor sensor or the like may be used for the purpose of improving the sensitivity of the sensor by exposing it to the outside of the package.

前記した外部露出型の半導体パッケージを製造する場合、内蔵する製品の外部に露出したい部分とモールド金型の間に、離型フィルムを挟んだ上で押圧し、その状態でトランスファーモールドを行って外部露出部を形成させる場合がある。このとき、押圧力が過大だと半導体チップ等のパッケージ構成部品が破損し、押圧力が過小だと、モールド用離型フィルムと外部に露出したい部品との間にモールド樹脂が侵入し、外部露出部にモールド樹脂がかぶった状態（以下、樹脂モレという）となる恐れがある。   When manufacturing an externally exposed semiconductor package as described above, a release film is sandwiched between a part to be exposed to the outside of a built-in product and a mold and then pressed, and transfer molding is performed in that state to perform external molding. An exposed part may be formed. At this time, if the pressing force is excessive, the package components such as the semiconductor chip are damaged. If the pressing force is excessive, the mold resin enters between the mold release film and the part to be exposed to the outside, and the external exposure There is a risk that the part will be covered with mold resin (hereinafter referred to as resin mole).

そのため、バネ等によって押圧力を一定とすることで、パッケージの構成部品の破損を防止するような製造装置を用いる場合ある。この場合、構成部品の厚さに例えば公差によるばらつきがあると、半導体パッケージ外形に対する外部露出部の位置がばらつく。よって、外部露出部にセンサ等を搭載する場合、センサの精度が悪化する要因となる。   For this reason, there is a case where a manufacturing apparatus is used that prevents damage to the components of the package by making the pressing force constant by a spring or the like. In this case, if the thickness of the component parts varies due to tolerances, for example, the position of the externally exposed portion with respect to the outer shape of the semiconductor package varies. Therefore, when a sensor or the like is mounted on the externally exposed portion, the accuracy of the sensor deteriorates.

本発明は、構成部品の一部がモールド樹脂から外部に露出する外部露出型半導体パッケージにおいて、構成部品の厚さに、例えば公差に基づくばらつきがある場合でも、モールド後においても半導体パッケージ外形に対する外部露出部の位置を高精度に制御することができる半導体装置を提供することを目的の一つとしている。   The present invention provides an externally exposed semiconductor package in which a part of a component is exposed to the outside from a mold resin. Even when the thickness of the component varies depending on, for example, tolerance, it is external to the semiconductor package outer shape after molding. An object of the present invention is to provide a semiconductor device capable of controlling the position of the exposed portion with high accuracy.

以下、図面を参照しながら。本発明の実施の形態について説明する。   Hereinafter, referring to the drawings. Embodiments of the present invention will be described.

図１は、本発明に係る半導体装置の積層構造体の一実施形態を説明する図であり、図１（ａ）は断面図、図１（ｂ）は平面図である。   1A and 1B are diagrams for explaining an embodiment of a laminated structure of a semiconductor device according to the present invention. FIG. 1A is a cross-sectional view and FIG. 1B is a plan view.

半導体装置は、例えば自動車の内燃機関に吸入される被計測気体の流量を検出するエアフローセンサに用いられるものであり、複数の構成部品を積層して構成された積層構造体２を有する。積層構造体２は、図１に示すように、基板となるリードフレーム（第１の構成部品）２０と、リードフレーム２０の上面に第２の接着剤層（接着剤層）３０を介して接着固定された中間部材（第２の構成部品）４０と、中間部材４０の上面に第１の接着剤層５０を介して接着固定された半導体チップ６０を有している。   The semiconductor device is used for, for example, an air flow sensor that detects a flow rate of a gas to be measured sucked into an internal combustion engine of an automobile, and includes a stacked structure 2 configured by stacking a plurality of components. As shown in FIG. 1, the laminated structure 2 is bonded to a lead frame (first component) 20 serving as a substrate and a top surface of the lead frame 20 via a second adhesive layer (adhesive layer) 30. A fixed intermediate member (second component) 40 and a semiconductor chip 60 bonded and fixed to the upper surface of the intermediate member 40 via a first adhesive layer 50 are provided.

半導体チップ６０は、Ｓｉのセンサデバイスであり、ＭＥＭＳ（マイクロエレクトロメカニカルシステム）構造を有している。半導体チップ６０には、一部を空洞化して形成された薄膜部（ダイアフラム）７０が設けられており、被計測気体の流量を計測する熱式の流量検出部（検出部）が形成されている。   The semiconductor chip 60 is a Si sensor device and has a MEMS (micro electro mechanical system) structure. The semiconductor chip 60 is provided with a thin film portion (diaphragm) 70 formed by hollowing a part thereof, and a thermal flow rate detection portion (detection portion) for measuring the flow rate of the gas to be measured is formed. .

第２の接着剤層３０は、中間部材４０と同じ大きさの平面形状を有しており、中間部材４０とリードフレーム２０との間に介在されて、中間部材４０を全面に亘ってリードフレーム２０に接着している。第２の接着剤層３０は、厚さ方向に圧縮されることにより塑性変形して厚さが薄くなる接着剤層であり、例えばＤＡＦ（ダイアタッチフィルム）等の公知の熱可塑性のシート状接着剤により構成されている。   The second adhesive layer 30 has a planar shape that is the same size as the intermediate member 40, and is interposed between the intermediate member 40 and the lead frame 20, so that the intermediate member 40 extends over the entire surface of the lead frame. 20 is adhered. The second adhesive layer 30 is an adhesive layer whose thickness is reduced by being plastically deformed by being compressed in the thickness direction. For example, a known thermoplastic sheet-like adhesive such as DAF (die attach film) is used. It is comprised by the agent.

積層構造体２は、各構成部品が順番に積層配置された後、加熱された状態で厚さ方向に圧力が印加されて作成される。積層構造体２に圧力を印加する方法としては、金型で挟んでもよく、また、一対のプレスローラの間を通過させてもよい。かかる圧力の印加により、第２の接着剤層３０が厚さ方向に圧縮されて塑性変形し、厚さが薄くなり、積層構造体２の総厚ｔｃが予め設定された基準値に調整される。したがって、複数の積層構造体２の総厚ｔｃを均一化させることができる。本実施の形態では、積層構造体２の総厚ｔｃの厚さ精度が第２の接着剤層３０の厚さｔｄの２０％以下となっている。   The laminated structure 2 is created by applying pressure in the thickness direction in a heated state after the respective components are laminated in order. As a method of applying pressure to the laminated structure 2, it may be sandwiched between molds or may be passed between a pair of press rollers. By applying such pressure, the second adhesive layer 30 is compressed in the thickness direction and plastically deformed, the thickness is reduced, and the total thickness tc of the laminated structure 2 is adjusted to a preset reference value. . Therefore, the total thickness tc of the plurality of laminated structures 2 can be made uniform. In the present embodiment, the thickness accuracy of the total thickness tc of the laminated structure 2 is 20% or less of the thickness td of the second adhesive layer 30.

リードフレーム２０、中間部材４０、半導体チップ６０等の第２の接着剤層３０以外の各構成部品に、厚さムラや上面と下面との平行度のばらつきがある場合には、第２の接着剤層３０の変形でこれらを吸収でき、積層構造体２の平行度、すなわち、半導体チップ６０の上面とリードフレーム２０の下面との平行度を向上させることができる。本実施の形態では、半導体チップ６０の上面とリードフレーム２０の下面との間の平行度は、第２の接着剤層３０の厚さｔｄの２０％以下となっている。   If each component other than the second adhesive layer 30 such as the lead frame 20, the intermediate member 40, and the semiconductor chip 60 has a thickness unevenness or a variation in parallelism between the upper surface and the lower surface, the second bonding is performed. These can be absorbed by deformation of the agent layer 30, and the parallelism of the laminated structure 2, that is, the parallelism between the upper surface of the semiconductor chip 60 and the lower surface of the lead frame 20 can be improved. In the present embodiment, the parallelism between the upper surface of the semiconductor chip 60 and the lower surface of the lead frame 20 is 20% or less of the thickness td of the second adhesive layer 30.

図５は、従来の積層構造体の構成を示す断面図である。   FIG. 5 is a cross-sectional view showing a configuration of a conventional laminated structure.

図５（ａ）〜（ｃ）に示す積層構造体１２０は、各構成部品を積層して構成されるが、第２の接続剤層１３０は、いずれも一定の厚さｔｄを有しており、圧縮しても塑性変形せず、厚さも薄くならない。そして、図５（ａ）〜（ｃ）に示す中間部材４０は、厚さにばらつきを有している（ｔｅ１＞ｔｅ２＞ｔｅ３）。   The laminated structure 120 shown in FIGS. 5A to 5C is configured by laminating each component, and the second connecting agent layer 130 has a constant thickness td. Even if it is compressed, it does not plastically deform and the thickness does not decrease. And the intermediate member 40 shown to Fig.5 (a)-(c) has dispersion | variation in thickness (te1> te2> te3).

図５（ａ）は、中間部材４０の厚さｔｅ１が公差中央値より厚い場合、図５（ｂ）は、中間部材４０の厚さｔｅ２が公差中央値付近の場合、図５（ｃ）は、中間部材４０の厚さｔｅ３が公差中央値より薄い場合を示している。このように、積層構造体１２０を構成する部品には必ず厚さばらつきがあり、そのままの状態では積層構造体１２０の総厚ｔｃ１、ｔｃ２、ｔｃ３は一定ではない（ｔｃ１＞ｔｃ２＞ｔｃ３）。したがって、例えば半導体チップ６０の上面とリードフレーム２０の上面との間を金線ワイヤで接続する際に、公差を吸収するための調整が必要となる。したがって、製造作業が煩雑となり、工数増加により生産タクトの時間短縮が困難で生産数を増大させることができない。   FIG. 5A shows a case where the thickness te1 of the intermediate member 40 is thicker than the median tolerance, FIG. 5B shows a case where the thickness te2 of the intermediate member 40 is around the median tolerance, and FIG. The case where the thickness te3 of the intermediate member 40 is thinner than the median tolerance is shown. As described above, the thickness of the components constituting the laminated structure 120 always varies, and the total thickness tc1, tc2, tc3 of the laminated structure 120 is not constant in the state as it is (tc1> tc2> tc3). Therefore, for example, when connecting the upper surface of the semiconductor chip 60 and the upper surface of the lead frame 20 with a gold wire, adjustment for absorbing tolerance is required. Therefore, the manufacturing operation becomes complicated, and it is difficult to shorten the production tact time due to the increase in the number of steps, and the number of production cannot be increased.

図２は、総厚が基準値に調整された積層構造体を示す断面図である。   FIG. 2 is a cross-sectional view showing a laminated structure in which the total thickness is adjusted to a reference value.

リードフレーム２０の上面から半導体チップ６０の上面までの総厚ｔｃは、第２の接着剤層３０の厚さｔｄ、中間部材４０の厚さｔｅ、第１の接着剤層５０と半導体チップ６０を合わせた厚さｔｆを合計した値（ｔｃ＝ｔｄ＋ｔｅ＋ｔｆ）となる。   The total thickness tc from the upper surface of the lead frame 20 to the upper surface of the semiconductor chip 60 is the thickness td of the second adhesive layer 30, the thickness te of the intermediate member 40, the first adhesive layer 50 and the semiconductor chip 60. The total thickness tf is a total value (tc = td + te + tf).

図２（ａ）は、中間部材４０の厚さｔｅ１が公差中央値より厚い場合であり、第２の接着剤層３０の変形量は大きい。図２（ｂ）は、中間部材４０の厚さｔｅ２が公差中央値付近の場合であり、第２の接着剤層３０の変形量も中央値である。図２（ｃ）は、中間部材４０の厚さｔｅ３が公差中央値より薄い場合であり、第２の接着剤層３０の変形量は小さい。積層構造体２は、厚さ方向に均一に圧力が印加され、第２の接着剤層３０を塑性変形させることで、積層構造体２の総厚ｔｃが一定となるように高精度にコントロールされる。したがって、例えば半導体チップ６０の上面とリードフレーム２０の上面との間を金線ワイヤで接続する際に、個体差を吸収するための調整が不要となり、製造作業を容易なものとすることができる。   FIG. 2A shows a case where the thickness te1 of the intermediate member 40 is thicker than the median tolerance, and the deformation amount of the second adhesive layer 30 is large. FIG. 2B shows a case where the thickness te2 of the intermediate member 40 is around the tolerance center value, and the deformation amount of the second adhesive layer 30 is also the median value. FIG. 2 (c) shows a case where the thickness te3 of the intermediate member 40 is thinner than the median tolerance, and the deformation amount of the second adhesive layer 30 is small. The laminated structure 2 is controlled with high accuracy so that the total thickness tc of the laminated structure 2 is constant by applying pressure uniformly in the thickness direction and plastically deforming the second adhesive layer 30. The Therefore, for example, when the upper surface of the semiconductor chip 60 and the upper surface of the lead frame 20 are connected by a gold wire, adjustment for absorbing individual differences is not necessary, and the manufacturing operation can be facilitated. .

図３は、本発明に係る半導体装置の積層構造体を樹脂モールドした構造を示す断面図である。   FIG. 3 is a cross-sectional view showing a structure in which a laminated structure of a semiconductor device according to the present invention is resin-molded.

半導体装置１は、積層構造体２をモールド樹脂１０によってモールドすることによって作成される。モールド樹脂１０は、半導体チップ６０の一部である薄膜部７０を外部露出部として外部に露出させている。被計測気体の流量は、薄膜部７０の表面に沿って通過することによって検出される。   The semiconductor device 1 is created by molding the laminated structure 2 with a mold resin 10. The mold resin 10 exposes the thin film portion 70 that is a part of the semiconductor chip 60 to the outside as an externally exposed portion. The flow rate of the measurement target gas is detected by passing along the surface of the thin film portion 70.

リードフレーム２０の上面からモールド樹脂１０の上面１１までの厚さである総厚ｔａは、リードフレーム２０の上面から半導体チップ６０の上面までの総厚ｔｃに、半導体チップ６０の上面からモールド樹脂１０の上面１１までの厚さ分（段差距離ｔｂ）を加算した値（ｔａ＝ｔｃ＋ｔｂ）となる。積層構造体２は、モールド樹脂１０によってモールドされる前に、加熱状態で厚さ方向に圧力が印加されて第２の接着剤層３０が厚さ方向に圧縮され、総厚ｔｃが予め設定された基準値に調整される。そして、その後でモールドされるので、半導体チップ６０の上面からモールド樹脂１０の上面１１までの厚さ方向の距離（半導体パッケージ外形に対する外部露出部の厚さ方向の距離）である段差距離ｔｂを一定に制御することができる。   The total thickness ta, which is the thickness from the upper surface of the lead frame 20 to the upper surface 11 of the mold resin 10, is the total thickness tc from the upper surface of the lead frame 20 to the upper surface of the semiconductor chip 60, and from the upper surface of the semiconductor chip 60 to the mold resin 10. This is a value (ta = tc + tb) obtained by adding the thicknesses (step distance tb) up to the upper surface 11. Before the laminated structure 2 is molded with the mold resin 10, pressure is applied in the thickness direction in a heated state to compress the second adhesive layer 30 in the thickness direction, and the total thickness tc is set in advance. Adjusted to the reference value. Then, since the molding is performed thereafter, a step distance tb that is a distance in the thickness direction from the upper surface of the semiconductor chip 60 to the upper surface 11 of the mold resin 10 (a distance in the thickness direction of the externally exposed portion with respect to the semiconductor package outer shape) is constant. Can be controlled.

第２の接着剤層３０は、圧縮前は各構成部品の公差を考慮して積層構造体２の総厚ｔｃを基準値よりも大きい厚さとし、圧縮後は積層構造体２の総厚ｔｃを基準値にすることが可能な厚さに設定されている。   The second adhesive layer 30 has a total thickness tc of the laminated structure 2 larger than a reference value in consideration of the tolerance of each component before compression, and the total thickness tc of the laminated structure 2 after compression. It is set to a thickness that can be set to a reference value.

図６は、従来の半導体装置の構造を示す断面図である。   FIG. 6 is a cross-sectional view showing the structure of a conventional semiconductor device.

図６（ａ）〜（ｃ）に示す半導体装置１０１の積層構造体１２０は、中間部材４０の厚さにばらつきがあり（ｔｅ１＞ｔｅ２＞ｔｅ３）、総厚ｔｃも一定ではない（ｔｃ１＞ｔｃ２＞ｔｃ３）。したがって、バネ等によって薄膜部７０への押圧力を一定とすることで、パッケージの構成部品の破損を防止するような製造装置を用いてモールドを行った場合に段差距離ｔｂがばらつく（ｔｂ１＜ｔｂ２＜ｔｂ３）。   In the stacked structure 120 of the semiconductor device 101 shown in FIGS. 6A to 6C, the thickness of the intermediate member 40 varies (te1> te2> te3), and the total thickness tc is not constant (tc1> tc2). > Tc3). Accordingly, by making the pressing force to the thin film portion 70 constant by a spring or the like, the step distance tb varies when the molding is performed using a manufacturing apparatus that prevents damage to the components of the package (tb1 <tb2). <Tb3).

図６（ａ）に示すように、中間部材４０の厚さｔｅ１が公差中央値より厚い場合には段差距離ｔｂ１は比較的小さくなり、図６（ｃ）に示すように、中間部材４０の厚さｔｅ３が公差中央値より薄い場合には段差距離ｔｂ３は比較的大きくなり、図６（ｂ）に示すように、中間部材４０の厚さｔｅ２が公差中央値付近の場合には段差距離ｔｂ２は、図６（ａ）と図６（ｃ）に示す場合の中間の値となる。このように、段差距離ｔｂがばらつくと、外部露出部にセンサ等を搭載する場合、センサの精度が悪化する要因となる。   As shown in FIG. 6 (a), when the thickness te1 of the intermediate member 40 is larger than the median tolerance, the step distance tb1 becomes relatively small, and as shown in FIG. 6 (c), the thickness of the intermediate member 40 is reduced. When the thickness te3 is smaller than the tolerance center value, the step distance tb3 is relatively large. As shown in FIG. 6B, when the thickness te2 of the intermediate member 40 is near the tolerance center value, the step distance tb2 is These are intermediate values in the case shown in FIGS. 6 (a) and 6 (c). As described above, when the step distance tb varies, the accuracy of the sensor deteriorates when a sensor or the like is mounted on the externally exposed portion.

図４は、第２の接着剤層により積層構造体の総厚が一定に調整された半導体装置の構造を示す断面図である。   FIG. 4 is a cross-sectional view showing the structure of the semiconductor device in which the total thickness of the laminated structure is adjusted to be constant by the second adhesive layer.

図４（ａ）は、中間部材４０の厚さｔｅ１が公差中央値より厚い場合であり、第２の接着剤層３０の変形量は大きい。図４（ｂ）は、中間部材４０の厚さｔｅ２が公差中央値付近の場合であり、第２の接着剤層３０の変形量も中間である。図４（ｃ）は、中間部材４０の厚さｔｅ３が公差中央値より薄い場合であり、第２の接着剤層３０の変形量は小さい。   FIG. 4A shows a case where the thickness te1 of the intermediate member 40 is thicker than the median tolerance, and the deformation amount of the second adhesive layer 30 is large. FIG. 4B shows a case where the thickness te2 of the intermediate member 40 is near the tolerance center value, and the deformation amount of the second adhesive layer 30 is also intermediate. 4C shows a case where the thickness te3 of the intermediate member 40 is thinner than the median tolerance, and the deformation amount of the second adhesive layer 30 is small.

図４（ａ）〜（ｃ）に示す各半導体装置１は、各中間部材４０の厚さｔｅ１、ｔｅ２、ｔｅ３の相違にかかわらず（ｔｅ１＞ｔｅ２＞ｔｅ３）、段差距離ｔｂは均一である（ｔｂ１＝ｔｂ２＝ｔｂ３）。したがって、外部露出部にセンサ等を搭載する場合に、センサの精度を悪化させることがない。   In each of the semiconductor devices 1 shown in FIGS. 4A to 4C, the step distance tb is uniform regardless of the difference between the thicknesses te1, te2, and te3 of the intermediate members 40 (te1> te2> te3) ( tb1 = tb2 = tb3). Therefore, when a sensor or the like is mounted on the externally exposed portion, the accuracy of the sensor is not deteriorated.

本発明の半導体装置１によれば、積層構造体２全体の総厚をコントロールすることにより、構成部品の厚さにばらつきがある場合でも、モールド後においても半導体パッケージ外形に対する外部露出部の厚さ方向の位置を高精度に制御できる。したがって、外部露出部にセンサ等を搭載する場合、センサの精度を悪化させる要因を排除できる。   According to the semiconductor device 1 of the present invention, by controlling the total thickness of the entire laminated structure 2, the thickness of the externally exposed portion with respect to the external shape of the semiconductor package after molding even when the thickness of the component parts varies. The direction position can be controlled with high accuracy. Therefore, when a sensor or the like is mounted on the externally exposed portion, a factor that deteriorates the accuracy of the sensor can be eliminated.

上述の実施の形態では、本発明の接着剤層が第２の接着剤層３０である場合を例に説明したが、係る構成に限定されるものではなく、第１の接着剤層５０に用いてもよく、第１の接着剤層５０と第２の接着剤層３０の両方に用いてもよい。また、上述の実施の形態では、半導体チップ６０の一部である薄膜部７０が外部露出部としてモールド樹脂１０から露出している場合を例に説明したが、積層構造体２全体がモールド樹脂１０によって樹脂モールドされている構成であってもよい。   In the above-described embodiment, the case where the adhesive layer of the present invention is the second adhesive layer 30 has been described as an example. However, the embodiment is not limited to such a configuration, and is used for the first adhesive layer 50. It may be used for both the first adhesive layer 50 and the second adhesive layer 30. Further, in the above-described embodiment, the case where the thin film portion 70 that is a part of the semiconductor chip 60 is exposed from the mold resin 10 as an externally exposed portion has been described as an example, but the entire laminated structure 2 is the mold resin 10. The resin mold may be used.

以上、本発明の実施形態について詳述したが、本発明は、前記の実施形態に限定されるものではなく、特許請求の範囲に記載された本発明の精神を逸脱しない範囲で、種々の設計変更を行うことができるものである。例えば、前記した実施の形態は本発明を分かりやすく説明するために詳細に説明したものであり、必ずしも説明した全ての構成を備えるものに限定されるものではない。また、ある実施形態の構成の一部を他の実施形態の構成に置き換えることが可能であり、また、ある実施形態の構成に他の実施形態の構成を加えることも可能である。さらに、各実施形態の構成の一部について、他の構成の追加・削除・置換をすることが可能である。   Although the embodiments of the present invention have been described in detail above, the present invention is not limited to the above-described embodiments, and various designs can be made without departing from the spirit of the present invention described in the claims. It can be changed. For example, the above-described embodiment has been described in detail for easy understanding of the present invention, and is not necessarily limited to one having all the configurations described. Further, a part of the configuration of an embodiment can be replaced with the configuration of another embodiment, and the configuration of another embodiment can be added to the configuration of an embodiment. Furthermore, it is possible to add, delete, and replace other configurations for a part of the configuration of each embodiment.

１ 半導体装置
２ 積層構造体
１０ モールド樹脂
２０ リードフレーム（第１の構成部品）
３０ 第２の接着剤層（接着剤層）
４０ 中間部材（第２の構成部品）
５０ 第１の接着剤層
６０ 半導体チップ
７０ 薄膜部（検出部）
DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Laminated structure 10 Mold resin 20 Lead frame (1st component)
30 Second adhesive layer (adhesive layer)
40 Intermediate member (second component)
50 First adhesive layer 60 Semiconductor chip 70 Thin film part (detection part)

Claims (12)

複数の構成部品が積層されて構成された積層構造体を有する半導体装置であって、
前記積層構造体は、第１の構成部品と第２の構成部品との間に介在されて接着し、厚さ方向に圧縮されることにより塑性変形して厚さが薄くなる接着剤層を有することを特徴とする半導体装置。A semiconductor device having a stacked structure formed by stacking a plurality of component parts,
The laminated structure has an adhesive layer that is interposed and bonded between the first component and the second component, and is plastically deformed by being compressed in the thickness direction so that the thickness is reduced. A semiconductor device. 前記接着剤層は、熱可塑性のシート状接着剤により構成されていることを特徴とする請求項１に記載の半導体装置。   The semiconductor device according to claim 1, wherein the adhesive layer is made of a thermoplastic sheet adhesive. 前記積層構造体は、モールド樹脂でモールドされており、前記積層構造体の表面に設けられたセンサデバイスの少なくとも一部が前記モールド樹脂から外部に露出していることを特徴とする請求項１に記載の半導体装置。   The laminated structure is molded with a mold resin, and at least a part of a sensor device provided on a surface of the laminated structure is exposed to the outside from the mold resin. The semiconductor device described. 前記積層構造体の厚さ精度が、前記接着剤層の厚さの２０％以下であることを特徴とする請求項１に記載の半導体装置。   2. The semiconductor device according to claim 1, wherein the thickness accuracy of the laminated structure is 20% or less of the thickness of the adhesive layer. 前記複数の構成部品は、半導体チップと、該半導体チップが搭載される基板とを有し、
該半導体チップの上面と前記基板の下面との平行度が前記接着剤層の厚さの２０％以下であることを特徴とする請求項１に記載の半導体装置。The plurality of components include a semiconductor chip and a substrate on which the semiconductor chip is mounted,
2. The semiconductor device according to claim 1, wherein the parallelism between the upper surface of the semiconductor chip and the lower surface of the substrate is 20% or less of the thickness of the adhesive layer. 前記半導体チップは、ＭＥＭＳ構造を有することを特徴とする請求項５に記載の半導体装置。   The semiconductor device according to claim 5, wherein the semiconductor chip has a MEMS structure. 前記半導体チップは、ダイアフラムを有していることを特徴とする請求項６に記載の半導体装置。   The semiconductor device according to claim 6, wherein the semiconductor chip has a diaphragm. 前記積層構造体全体がモールド樹脂でモールドされていることを特徴とする請求項１に記載の半導体装置。   The semiconductor device according to claim 1, wherein the entire laminated structure is molded with a mold resin. 前記センサデバイスは、被計測気体の流量を検出する流量検出部であることを特徴とする請求項３に記載の半導体装置。   The semiconductor device according to claim 3, wherein the sensor device is a flow rate detection unit that detects a flow rate of the measurement target gas. 複数の構成部品を積層して、第１の構成部品と第２の構成部品の間に、厚さ方向に圧縮することにより塑性変形して厚さが薄くなる接着剤層を介在させ、前記複数の構成部品を厚さ方向に圧縮することにより積層構造体を作成する工程と、
該積層構造体をモールド樹脂でモールドする工程と、を含むことを特徴とする半導体装置の製造方法。A plurality of component parts are laminated, and an adhesive layer that is plastically deformed and thinned by being compressed in the thickness direction is interposed between the first component part and the second component part. A step of creating a laminated structure by compressing the component parts in the thickness direction;
And a step of molding the laminated structure with a mold resin. 前記積層構造体を作成する工程では、前記複数の構成部品を金型に挟んで圧縮することを特徴とする請求項１０に記載の半導体装置の製造方法。   The method of manufacturing a semiconductor device according to claim 10, wherein in the step of creating the laminated structure, the plurality of component parts are sandwiched between molds and compressed. 前記積層構造体を作成する工程では、前記複数の構成部品を一対のプレスローラの間に通して圧縮することを特徴とする請求項１０に記載の半導体装置の製造方法。   The method of manufacturing a semiconductor device according to claim 10, wherein in the step of forming the laminated structure, the plurality of component parts are compressed by passing between a pair of press rollers.
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