JPWO2015083225A1 - Information processing apparatus, storage, and access control method - Google Patents

Abstract

One system to which the present invention is applied exists on a processing unit, a plurality of storage devices from which data is erased in units of blocks, and one or more storage devices allocated among the plurality of storage devices. A plurality of storage units used for storing control information representing spare blocks that are blocks for writing data, and a processing unit that issues a write command for requesting data writing to a plurality of storage devices, a plurality of An access unit that selects a storage unit that uses control information from among the storage units, and writes data requested by a write command to a spare block specified by the control information stored in the selected storage unit; Have

Description

  The present invention relates to a technique for managing a plurality of storage devices that erase data in units of blocks.

  Most current information processing apparatuses (computers) are equipped with nonvolatile semiconductor memories. In recent years, flash memory, which is a kind of nonvolatile semiconductor memory, has been widely used for storage. An SSD (Solid State Drive) is a typical storage that employs a flash memory as a storage medium. Flash memory has come to be widely adopted because large-capacity flash memory has become relatively inexpensive and has a higher operating speed than magnetic disk devices (for example, hard disk devices). Because.

  Flash memory includes NAND type and NOR type. Here, for the sake of convenience, a general control method will be described by taking a NAND flash memory (hereinafter referred to as “NAND flash memory”; NOR flash memory is referred to as “NOR flash memory”) as an example.

  Compared with a NOR flash memory, a NAND flash memory has the advantages that it is easy to increase the capacity (high integration) and can perform writing at high speed. However, the NAND flash memory cannot be read in units of 1 byte, and has a disadvantage that reading by random access is slower than the NOR flash memory. Both the NAND flash memory and the NOR flash memory can be erased / written only in block units of several KB to several tens KB.

  In the NAND flash memory, reading / writing is normally performed in units of pages, and erasing is performed in units called “blocks” having a capacity for a plurality of pages. The block where the page is written cannot be overwritten immediately. When overwriting, after erasing the block in which the page is written, the page to be overwritten and the other pages of the block must be written. In many cases, the page to be written is written to another block along with other pages in the block where the page is written.

  In a memory element (cell) of a flash memory, an oxide film serving as an insulator is deteriorated by electrons penetrating the oxide film. Therefore, there is a limit to the number of times that each block can be erased and written. For this reason, in the flash memory, access control for leveling is performed so that erasure / writing to a specific block is not concentrated. In order to control access for leveling, a flash memory is usually provided with a controller that controls access to the flash memory.

  As a conventional access control method for leveling to prevent concentration of erasing / writing to a specific block, there is a method using FIFO (First In First Out).

  In this conventional access control method, an unused block in the NAND flash memory is used as a spare block for writing data, and control information representing the spare block is stored in the FIFO. When writing a page, the page is written in a spare block specified by the control information output from the FIFO together with other pages of the block in which the page is written. The block in which the page is written is erased as a spare block, and the control information of the spare block is registered in the FIFO.

  As such, in this conventional access control method, a newly generated spare block is managed so as to be allocated last among the spare blocks existing at that time. For this reason, concentration of erasing / writing on a specific block is avoided, and the allocation of spare blocks is leveled.

  In this conventional access control method, only one FIFO is used. Therefore, the spare block to be allocated among the spare blocks is fixedly determined. As a result of fixedly determining the spare block to be allocated, the access speed may be greatly reduced depending on the system configuration or the situation.

  For example, in a system configuration in which a plurality of NAND flash memories are connected to a controller through a plurality of channels, the NAND flash memory can be accessed for each channel. As a result, in this system configuration, there is a case where a spare block to be accessed using the channel is allocated under a situation where access using the channel is performed or access is performed.

  If a spare block must be accessed through a channel where access is concentrated, the more concentrated the access, the longer the latency. As a result, the time required for writing data to the spare block becomes longer and the access speed is greatly reduced. In addition, there is a possibility that the access speed of access performed after the access for writing data in the spare block is greatly reduced.

  Concentration of access itself tends to occur when garbage collection or data update is performed. In the FIFO, control information of spare blocks is stored according to the past situation. Therefore, the spare block is selected regardless of the current situation based on the control information output from the FIFO. Accordingly, there is a possibility that spare blocks to be accessed through channels where access is concentrated are continuously selected.

  In the NAND flash memory, when an access for writing data is performed, an access for erasing a block is also performed. For this reason, the number of accesses required per unit time (the number of issued instructions) is likely to increase compared to the case where a semiconductor memory capable of overwriting data in the same area is employed. This means that access concentration is likely to occur.

  The access speed tends to decrease as the access concentrates, that is, as the number of accesses per unit time increases. The access speed itself greatly affects performance. The spare block for writing data can basically be arbitrarily selected. For this reason, it is considered important to suppress a decrease in access speed in access for writing data to the spare block. This is true for all storage devices that cannot immediately overwrite data.

Japanese Patent Laid-Open No. 7-78485 Japanese Patent Laid-Open No. 5-198198 JP 2006-252695 A

  In one aspect, an object of the present invention is to provide a technique for suppressing a decrease in access speed to a storage device in which data cannot be overwritten immediately.

  One system to which the present invention is applied exists on a processing unit, a plurality of storage devices from which data is erased in units of blocks, and one or more storage devices allocated among the plurality of storage devices. A plurality of storage units used for storing control information representing spare blocks that are blocks for writing data, and a processing unit that issues a write command for requesting data writing to a plurality of storage devices, a plurality of An access unit that selects a storage unit that uses control information from among the storage units, and writes data requested by a write command to a spare block specified by the control information stored in the selected storage unit; Have

  In one system to which the present invention is applied, it is possible to suppress a decrease in access speed to a storage device in which data cannot be overwritten immediately.

It is a figure explaining the structural example of the information processing apparatus by this embodiment. It is a figure explaining the structural example of SSD. It is a figure explaining the functional structural example of a write-control mechanism. It is a figure explaining operation | movement of the controller at the time of the writing of the data to SSD. It is a time chart explaining the example of access performed via each channel at the time of data writing. It is a flowchart showing operation | movement of the controller at the time of data writing.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a diagram illustrating a configuration example of the information processing apparatus according to the present embodiment. The information processing apparatus according to the present embodiment is, for example, a server, and as illustrated in FIG. 1, two CPUs (Central Processing Unit) 1 (1-1, 1-2), two memories 2 (2-1, 2-2) Two SSDs (Solid State Drives) 3 (3-0, 3-1), an I / O (Input / Output) hub 4 and an FWH (FirmWare Hub) 5 are provided.

  Each SSD 3 is a storage according to the present embodiment. The two SSDs 3 are mounted on the information processing apparatus for redundancy, for example. Each CPU 1 can access each SSD 3 by reading the firmware stored in the FWH 5 into the memory 2 and executing it.

  Each SSD 3 stores, for example, a program executed by each CPU 1, specifically an OS (Operating System), an application program, and the like in addition to data used by each CPU 1 for processing. The OS includes a file system that is a program for managing data on various storage devices including the SSD 3 and data on various recording media. The OS also supports virtual storage.

  Each SSD 3 includes a controller (indicated as “NAND Controller” in FIG. 1) 30 and a plurality of NAND flash memories (indicated as “Device” in FIG. 1; hereinafter referred to as “device”) 31 (31-0-0). ~ 31-n-2). The controller 30 and each device 31 are connected by a total of n + 1 channels.

  In the present embodiment, three devices 31 are connected to each channel. The last “0” of “31-0-0” attached to the device 31 as a code indicates that the device number, which is identification information between the devices 31 connected to the same channel, is “0”. . The preceding “0” indicates that the number (channel number) assigned as channel identification information is 0. As a result, “31-0-0” represents that the device 31 has a device number 0 connected to a channel having a channel number 0. Further, “31-n−1” represents that the device 31 with the device number connected to the channel with the channel number n is 1.

  FIG. 2 is a diagram for explaining a configuration example of an SSD. As shown in FIG. 2, the controller 30 has three devices 31 connected to each channel. The controller 30 includes an address conversion unit 301, a demultiplexer 302, a write control mechanism 303, a data queue 304, a plurality of FIFOs 305 (305-0-0 to 305-n-2), and a multiplexer 306. In FIG. 2, the I / O hub 4 existing between each CPU 1 and each SSD 3 is omitted for convenience.

  “305-0-0” added to the FIFO 305 as a code indicates that the device 31 connected to the channel with the channel number 0 is the FIFO 31 for the device 31-0-0 with the device number 0, as with the device 31. Represents. “CH # 0 for DEV # 0” shown in FIG. 2 represents this. That is, “CH # 0” and “DEV # 0” represent the channel with the channel number 0 and the device 31 with the device number 0, respectively. Further, “305-n-2” represents that the FIFO 31 for the device 31-n-2 whose device number is 2 connected to the channel whose channel number is n. “CH # n DEV # 2” shown in FIG. 2 represents this. As described above, in this embodiment, the FIFO 305 is provided for each channel and for each device 31.

  The CPU 1 issues a command when accessing the SSD 3. In the case of a read command for requesting data reading, the command includes command type data indicating the command type and a logical address indicating the access destination. The write command that requests data writing includes data (page) to be written. The logical address is input to the address conversion unit 301. Command type data is input to the write control mechanism 303, and data (page) is input to the data queue 304.

  The OS executed by the CPU 1 supports virtual storage. Therefore, the CPU 1 handles data with logical addresses. However, access to the device 31 must be made with a physical address. Accordingly, the address conversion unit 301 converts the input logical address into a physical address.

  FIG. 4 is a diagram for explaining the operation of the controller when data is written to the SSD. In FIG. 4, for the sake of easy understanding, only one device 31 is assumed. Now, with reference to FIG. 4, the operation of the controller 30 including the address conversion unit 301 when the write command is issued will be specifically described.

  Each device 31 mounted on the SSD 3 can be erased and written only in units of storage areas called blocks. In an information processing apparatus using virtual storage, data reading / writing is usually performed in units of pages. The block has a capacity for a plurality of pages.

  The file system 40 installed in the OS manages data in units of pages using logical addresses. Here, in order to clarify the correspondence with the blocks on the SSD 3, the pages managed by the file system 40 are divided into virtual blocks. In FIG. 4, the virtual block is denoted as “logical block” and is distinguished from the block on the device 31. A block on the device 31 is described as a “physical block”.

  “Logical block # 0 (L0)” shown in FIG. 4 indicates that another expression of the logical block having the block number “0” is “L0”. “L0-0” to “L0-3” represent pages constituting the logical block having the block number “0”. Thereby, it is assumed here that each logical block (and each physical block on the device 31) includes four pages. Hereinafter, for the sake of convenience, when referring to a specific logical block, “L0”, “L1”, etc. will be given as symbols. When an arbitrary logical block is indicated, “L” is attached as a symbol.

  On the other hand, “physical block # 0 (P0)” shown in FIG. 4 indicates that another representation of the physical block to which “0” is assigned as the block number is “P0”. Similarly to the logical block L, in the physical block, “P0”, “P1” or the like is attached as a code when indicating a specific physical block, and “P” is added as a code when indicating an arbitrary physical block. To do.

  The controller 30 uses the block conversion table 301a for specifying the correspondence between the logical block L (logical address) and the physical block P (physical address). The block conversion table 301 a is a table managed by the address conversion unit 301, and represents a physical block P associated with the logical block L for each logical block L. Therefore, the address conversion unit 301 identifies the logical block L from the logical address designated by the file system 40 (CPU 1) with an instruction, refers to the block conversion table 301a using the identified logical block L, and physically accesses the physical block to be accessed. Block P can be identified. FIG. 4 shows that the address conversion unit 301 has specified the physical block P7 by designating the logical address in the logical block L4 from the file system 40.

  When the access requested by the file system 40 is reading, the controller 30 reads data from the physical block P7 identified with reference to the block conversion table 301a. Reading of data is realized by outputting a physical address from the address conversion unit 301 and outputting a necessary control signal from the write control mechanism 303.

  The physical address output from the address conversion unit 301 for reading data is input to the device 31 storing the data via the demultiplexer 302. For this purpose, the address conversion unit 301 controls the demultiplexer 302 to output the physical address to the channel to be output. Control signals output from the write control mechanism 303 include command latch enable, address latch enable, chip enable, write enable, read enable, and the like.

  Data read from the physical block P is output to the CPU 1 via the data queue 304. The data queue 304 is a storage device for outputting data from each device 31 to the CPU 1 and outputting data from the CPU 1 to each device 31. Data read from each device 31 is temporarily stored in the data queue 304. Data output from the CPU 1 is also temporarily stored in the data queue 304.

  When the access requested by the file system 40 is writing, the controller 30 writes data to any physical block P among the unused physical blocks P. In FIG. 4, the physical block P8 is selected from the unused physical blocks P, and the pages L4-0 to L4-3 to which the physical block P7 has been assigned are written to the physical block P8. . As a result, in the block conversion table 301a, the physical block P associated with the logical block L4 is updated from the physical block P7 to the physical block P8. The physical block P7 is erased and is not associated with any logical block L in the block conversion table 301a. Thereby, the physical block P7 is treated as an unused physical block P hereinafter. The unused physical block P is hereinafter referred to as “reserve block”. In FIG. 4, this is why “reserved” is written in the physical block P8 before the pages L4-0 to L4-3 are allocated.

  As described above, the FIFO 305 is provided for each channel and for each device 31. These FIFOs 305 are used to select a spare block P to which data is written.

  Data (page) cannot be overwritten on the physical block P in which data is stored. Therefore, when overwriting a physical block P in which data (page) is already stored, the physical block P must be erased. However, there is a limit to the number of times that the physical block P can be erased and written. Due to the limitation, it is necessary to level the access for erasing / writing so that the erasing / writing for a specific physical block P is not concentrated. For leveling, the FIFO 305 provided for each channel and each device 31 is used.

  When the physical block P is erased or when the association of the logical block L with the physical block P is canceled on the block conversion table 301a, the address conversion unit 301 stores information indicating the physical block P (for example, the block Number (hereinafter referred to as “identification information”) is held in the corresponding FIFO 305. For example, when a physical block P that has been erased or released from association exists on the device 31-0-0, the address translation unit 301 identifies the physical block P with the identification information (the physical block P and the device Information that can specify 31-0-0) is held in the FIFO 305-0-0. Here, it is assumed that the retention of identification information in the FIFO 305 is performed by erasing data.

  The physical block P is erased by issuing an erase command requesting the erase. Identification information (for example, a block number) specifying the physical block P to be erased is given as an address. The address conversion unit 301 identifies the physical block P to be erased from the command type and address (block number) notified from the write control mechanism 303, for example, and stores the identification information of the physical block P in the corresponding FIFO 305. To do.

  One of the identification information output from each FIFO 305 is selected by the multiplexer 306, and the selected identification information is output to the address conversion unit 301. As a result, the address conversion unit 301 outputs a physical address for accessing the physical block P represented by the identification information input from the multiplexer 306. The FIFO 305 for which the identification information is selected outputs the identification information to be output next, for example, under the control of the address conversion unit 301. As a result, the content held in the FIFO 305 is updated by selecting the identification information. Selection of the identification information in the multiplexer 306 is performed according to a selection signal output from the write control mechanism 303.

  FIG. 5 is a time chart for explaining an example of access performed through each channel when data is written. Here, with reference to FIG. 5, the selection method of the identification information output from each FIFO 305 and the access realized through the selection of the identification information will be specifically described.

  In FIG. 5, “reserved block designated from FIFO” shown in FIG. 5A is a spare block P designated by the identification information output from the multiplexer 306 to the address conversion unit 301. “CH0 DEV1 block 1” shown in FIG. 5A means the physical block P with the block number 1 on the device 31-0-1 connected to the channel with the channel number 0. In the configuration shown in FIG. 2, three devices 31 are connected to each channel. However, in FIG. 5, it is assumed that four or more devices 31 are connected to each channel.

  “CPU-IF” shown in FIG. 5B represents data input from the CPU 1. As the data, FIG. 5B-1 shows a write command (write command), and FIG. 5B-2 shows data requested to be written (write data). Here, the write command is used to indicate the data of the portion excluding the write data.

  “A command” to “E command” shown in FIG. 5B-1 represent different write commands. “A data” to “E data” shown in FIG. 5B-2 represent write data of “A command” to “E command”.

  “Controller-IF” shown in FIG. 5C represents a channel that is accessed under the control of the controller 30. Here, it is assumed that there are a total of five channels, channels 0 to 4, to which channel numbers 0 to 4 are assigned (FIGS. 5 (c-0) to 5 (c-4). )).

  When the A to E commands from the CPU 1 as shown in FIG. 5B-1 are input, in the channels 0 to 4, A to E as shown in FIG. 5 (c-0) to FIG. 5 (c-4). Command processing is performed in parallel, and writing of A to E data is performed independently. The selection of the identification information as shown in FIG. 5A is performed so that the A to E commands can be processed in parallel in channels 0 to 4, in other words, distributed to channels 0 to 4.

  Selection of identification information as shown in FIG. 5A means that priority is given to the use of channels that are not accessed by other commands among channels 0 to 4. Therefore, the waiting time for waiting for the end of access by another command can be minimized. As a result, even if a plurality of write commands are continuously input from the CPU 1, the time required for processing the plurality of write commands can be minimized or close to the minimum. This means that a decrease in access speed of access due to a write command can be minimized.

  By minimizing the decrease in the access speed due to the execution of the write command, it is possible to suppress the occurrence of channels where access is concentrated. This is because the number of accesses possible per unit time can be maintained at the maximum level. Therefore, not only the access speed of the access by the write command but basically a decrease in the access speed of all accesses is suppressed.

  In this embodiment, as shown in FIG. 5 (c) (FIG. 5 (c-0) to FIG. 5 (c-4)), there are a plurality of channels that are not accessed among the channels 0 to 4. If so, you are trying to select different channels.

  For example, in channel 0, after the writing of A data is completed, the state shifts to a state where another write command can be processed. Even in this situation, the channels used for processing the D and E commands are selected in the order of channel 3 → channel 4. This is to prevent the selection of the spare block P from being biased between channels. By prioritizing the use of different channels, leveling between channels can be realized.

  A plurality of devices 31 are connected to each channel. In selecting the spare block P in each channel, different devices 31 are selected. Thereby, for example, in the three devices 31-0-0 to 31-0-2 connected to the channel 0 shown in FIG. 2, after the spare block P of the device 31-0-0 is selected, the device 31-0 The selection of the spare block P of -1 or 31-0-2 is prioritized. This is to prevent bias in selection of the spare block P between the devices 31 connected to the same channel. By prioritizing the use of different devices 31, leveling between devices 31 connected to the same channel can be realized.

  When the FIFO 305 is provided for each of a plurality of channels, it is not always possible to select the spare block P while avoiding the channel being accessed. Therefore, in this embodiment, a FIFO 305 is provided for each channel.

  Even if one FIFO 305 is provided for each channel, it is possible to perform access using a channel that allows quick access. However, the identification information extracted from each FIFO 305 is the identification information held in the FIFO 305 according to the past situation. Therefore, the flow of identification information sequentially extracted from one FIFO 305 may not match the current situation. Even if there is a bias in access to each device 31 connected to the same channel, it is difficult to correct the bias. For this reason, in this embodiment, FIFOs 305 corresponding to the number of devices 31 connected to each channel are provided for each channel. By providing the FIFO 305 for each device 31, it is possible to correct past access bias and achieve more desirable leveling.

  The multiplexer 306 selects the FIFO 305 according to the selection signal output from the write control mechanism 303. The leveling between the devices 31 connected to the same channel between the channels and the access control as shown in FIG. 5 are realized through the selection of the FIFO 305 using the multiplexer 306. In the following, the write control mechanism 303 that realizes leveling between devices, leveling between devices 31 connected to the same channel, and access control as shown in FIG. 5 will be described in detail.

  FIG. 3 is a diagram for explaining a functional configuration example of the write control mechanism. As shown in FIG. 3, the write control mechanism 303 includes a spare block check circuit 331, a busy check circuit 332, a status check circuit 333, a channel selection circuit 334, a device selection circuit 335, a memory 336, and two interfaces 337 and 338. I have.

  The interface 337 is a component that performs communication with the CPU 1. When a write command is input from the CPU 1, the interface 337 outputs the input write command to the status check circuit 333.

  The spare block check circuit 331 checks whether the identification information of the spare block P exists for each FIFO 305. The usage status information acquired from each FIFO 305 is used to check whether the identification information of the spare block P exists. This usage status information is information indicating the presence or absence of identification information output from the FIFO 305, for example. The identification information output from the FIFO 305 can be used as usage status information.

  Each device 31 outputs a busy signal (RY / BY = “L”) during a write operation, an erase operation, or a read operation, and upon completion of the operation, a ready signal (RY / BY = “H”) is output. The busy check circuit 332 checks whether a busy signal is output for each channel.

  The status check circuit 333 confirms whether or not the data can be written. The confirmation is performed using the confirmation results of the spare block check circuit 331 and the busy check circuit 332. Accordingly, the status check circuit 333 determines that data can be written when there is a device 31 that is connected to a channel to which no busy signal is output and has the spare block P. The determination result is output to the channel selection circuit 334.

  The memory 336 stores history information representing the processing result of the write command. The history information is information that can at least identify the identification information (channel number) of the channel selected by the immediately preceding write command and the identification information representing the device 31 selected last in each channel. The history information also refers to the channel selection circuit 334 and the device selection circuit 335.

  The channel selection circuit 334 refers to the confirmation results of the spare block check circuit 331 and the busy check circuit 332 and the history information in the memory 336, and selects a channel to be used for writing to the spare block P. The channel selection satisfies the condition that the busy signal is not output from the channel to which the channel number next to the channel number represented by the history information is assigned, and the device 31 having the spare block P is connected. It is done by checking whether or not. The channel selection result is output to the device selection circuit 335.

  The device selection circuit 335 refers to the confirmation result of the spare block check circuit 331 and the history of the memory 336, and selects the device 31 that writes data from the devices 31 connected to the channel selected by the channel selection circuit 334. select. The selection of the device 31 is connected to the channel selected by the channel selection circuit 334, and it is confirmed whether or not the spare block P exists from a device 31 different from the device 31 selected last in the channel indicated by the history. It is done by doing.

  When the device selection circuit 335 selects the device 31, the FIFO 305 that should select the identification information is determined. Accordingly, the device selection circuit 335 outputs a selection signal generated from the selection result of the device 31 to the multiplexer 306. Further, the device selection circuit 335 outputs the selection result of the device 31 to the interface 338.

  The interface 338 outputs a control signal for accessing each device 31. The interface 338 outputs a control signal to the device 31 specified by the selection result of the device selection circuit 335. The device 31 outputs a logical address from the address conversion unit 301 and data for one physical block P from the data queue 304, respectively. Therefore, data for one physical block P is written to the spare block P of the device 31.

  The generation of the selection signal by the device selection circuit 335 reflects the access status performed in each channel, the status of each device 31 connected to each channel (presence / absence of a spare block), and history information. Therefore, leveling between devices 31 connected to the same channel and access control as shown in FIG. 5 are realized through selection of the FIFO 305 (identification information) by the multiplexer 306 according to the selection signal.

  FIG. 6 is a flowchart showing the operation of the controller during data writing. Finally, with reference to FIG. 6, the operation of the controller 30 when a write command (write command) is received from the CPU 1 will be described in detail. The operation represented by the flowchart in FIG. 6 is based on the assumption that only one write command received from the CPU 1 is processed.

  In FIG. 6, the symbols “333” to “335” are attached to the three frames, respectively. The processing steps in the frames with “333” to “335” represent the operations of the status check circuit 333, the channel selection circuit 334, and the device selection circuit 335, respectively.

  The write command issued from the CPU 1 is received by the interface 337 of the write control function 303, and the received write command is output from the interface 337 to the status check circuit 333. The status check circuit 333 receives the confirmation result of the busy signal performed for each channel from the busy check circuit 332 in response to the input of the write command, and determines whether there is a channel for which the busy signal is not output ( S1). If no busy signal is output in any channel, the determination in S1 is Yes and the process proceeds to S3. When busy signals are output on all channels, the determination in S1 is No and the process proceeds to S2.

  In S2, the status check circuit 333 waits for a predetermined time. The fixed time is, for example, the time until a new confirmation result is input from the busy check circuit 332. When a certain time has elapsed, the process returns to S1. Thereby, the status check circuit 333 waits until a channel that does not output a busy signal appears in a situation where busy signals are output in all channels.

  In S3, the status check circuit 333 receives the confirmation result from the spare block check circuit 331, and whether the spare block P exists on any device 31 connected to any channel for which no busy signal is output. Judge whether or not. If there is one or more channels to which no busy signal is output, and the device 31 having the spare block P is connected to any of the existing channels, the determination in S3 is Yes and the process proceeds to S5. . If the device 31 having the spare block P is not connected to all channels for which no busy signal is output, the determination in S3 is No and the process proceeds to S4.

  A new confirmation result by the busy check circuit 332 is input to the status check circuit 333 as needed. Therefore, in S3, the device 31 having the spare block P is confirmed for a channel for which a busy signal is no longer output.

  In S4, the status check circuit 333 waits for a predetermined time. The fixed time is, for example, the time until a new confirmation result is input from the spare block check circuit 331. When a certain time has elapsed, the process returns to S3.

  The transition to S5 due to Yes in S3 is performed by the status check circuit 333 notifying the channel selection circuit 334 of a determination result that data can be written. The channel selection circuit 334 that has received the notification refers to the history information stored in the memory 336 and selects a channel having a channel number that is one greater than the previously selected channel (S5). Next, the channel selection circuit 334 refers to the confirmation result input from the busy check circuit 332 and determines whether or not a busy signal is output to the selected channel (S6). If the busy signal is not output to the selected channel, the determination in S6 is Yes and the process proceeds to S8. When the busy signal is output to the selected channel, the determination in S6 is No and the process proceeds to S7.

  In S7, the channel selection circuit 334 newly selects a channel that is one larger than the current channel number. After the selection, the process returns to S6. Thereby, the channel selection circuit 334 specifies and selects the channel from which the busy signal is not output, starting from the one with the smaller channel number, while reflecting the selection result of the immediately preceding channel.

  In S8, the channel selection circuit 334 refers to the confirmation result input from the spare block check circuit 331 as needed, and determines whether or not the spare block P exists in the selected channel. If there is no spare block P in any device 31 connected to the selected channel, the determination in S8 is No and the process proceeds to S9. When the device 31 having the spare block P is connected to the selected channel, the determination in S8 is Yes and the process proceeds to S10.

  In S9, the channel selection circuit 334 newly selects a channel that is one larger than the current channel number. After the selection, the process returns to S6. As a result, the channel selection circuit 334 reflects the selection result of the previous channel, and the channel 31 to which the device 31 having the spare block P is connected and the busy signal is not output from the one with the smaller channel number. Identify and select.

  The shift to S10 due to Yes in S8 is performed by the channel selection circuit 334 notifying the device selection circuit 335 of the channel determined to be used for data writing. The device selection circuit 335 that has input the notification refers to the history information stored in the memory 336, and selects the device 31 having a device number one larger than the device 31 selected last time (S10). Next, the device selection circuit 335 refers to the confirmation result input from the spare block check circuit 331, and determines whether or not the spare block P exists in the selected device 31 (S11). When the spare block P does not exist in the selected device 31, the determination in S11 is No and the process proceeds to S12. If there is a spare block P in the selected device 31, the determination in S11 is No and the process proceeds to S13.

  In S12, the device selection circuit 335 newly selects a device 31 that is one larger than the current device number. After the selection, the process returns to S11. Thereby, the device selection circuit 335 specifies and selects the device 31 having the spare block P from the device number with the smallest device number while reflecting the selection result of the immediately preceding device 31 in the same channel.

  The device 31 having the spare block P for writing data and the channel to which the device 31 is connected are determined as described above. As a result, the selection signal output to the multiplexer 36 realizes leveling between the channels, between the devices 31 connected to the same channel, and access control as shown in FIG.

  In S13, the device selection circuit 335 outputs a selection signal according to the determination result of the channel and the device 31, and instructs the interface 338 to output the control signal to the determined channel. In this way, the device selection circuit 335 causes data to be written in the spare block P of the determined device 31. Since control information output from the interface 338 is necessary for writing data, S13 is outside the frame 335 in FIG.

  The device 31 to which data is written outputs a busy signal during the data writing operation, and outputs a ready signal instead of the busy signal upon completion of the writing operation (RY / BY = “L” → “H”). ). The busy check circuit 332 monitors the change of the signal and notifies the interface 337 of the change from the busy signal to the ready signal, for example. In response to the notification, the interface 337 returns a write completion notification indicating that the data writing is completed to the CPU 1 that has transmitted the write command (S14). By replying to the writing completion notification, the processing for one write command received from the CPU 1, that is, the operation of the flowchart shown in FIG.

  In the present embodiment, the FIFOs 305 are provided for the number of devices 31 for leveling between the devices 31 connected to the same channel. However, one FIFO may be provided for one channel. good. This is because a decrease in access speed can be sufficiently suppressed by providing one FIFO 305 for one channel. In the SSD 3 having many channels, one FIFO 305 may be provided for two or more channels.

One system to which the present invention is applied exists on a processing unit, a plurality of storage devices from which data is erased in units of blocks, and one or more storage devices allocated among the plurality of storage devices. A plurality of storage units used for storing control information representing spare blocks that are blocks for writing data, and a processing unit that issues a write command for requesting data writing to a plurality of storage devices, a plurality of An access unit that selects a storage unit that uses control information from among the storage units, and writes data requested by a write command to a spare block specified by the control information stored in the selected storage unit; It possesses other a storage unit for storing history information representing the selection result storage unit by the access unit, and the plurality of storage devices, is connected to the storage device one or more multiple channels Each channel to which the storage device is connected is assigned one or more storage units from among a plurality of storage units, and the access unit is connected to each channel connected to each channel. Based on the status and history information stored in other storage units, there is a spare block specified by the control information stored in the storage unit selected most recently by the access unit among a plurality of channels. A storage unit used to store control information for specifying a spare block existing in a storage device connected to a channel other than the channel to which the storage device was connected is selected .

Claims (7)

A processing unit;
A plurality of storage devices in which data is erased in units of blocks;
A plurality of storage units each used for storing control information representing a spare block that is a block for writing data, which exists on one or more storage devices allocated among the plurality of storage devices;
When the processing unit issues a write command for requesting data writing to the plurality of storage devices, the storage unit that uses the control information is selected from the plurality of storage units, and the selected storage unit An access unit for writing the data requested by the write command to the spare block specified by the stored control information;
An information processing apparatus comprising: The plurality of storage devices are each connected to one or more storage devices in a plurality of channels,
Each channel to which the storage device is connected is assigned one or more storage units among the plurality of storage units.
The information processing apparatus according to claim 1. The access unit selects a storage unit that uses the control information among the plurality of storage units based on the state of the storage device connected to each channel.
The information processing apparatus according to claim 2. Another storage unit storing history information representing a selection result of the storage unit by the access unit;
The access unit uses the control information in the plurality of storage units based on the state of the storage device connected to each channel and the history information stored in the other storage unit. Select storage part,
The information processing apparatus according to claim 2, wherein the information processing apparatus is an information processing apparatus. A plurality of storage devices in which data is erased in units of blocks;
A plurality of storage units respectively used for storing control information representing spare blocks that are blocks for writing the data on one or more storage devices allocated among the plurality of storage devices;
When a write command for requesting writing of data to the plurality of storage devices is received, a storage unit that uses the control information is selected from the plurality of storage units and stored in the selected storage unit An access unit for writing the data requested by the write command to the spare block specified by the control information;
Storage characterized by having. The plurality of storage devices are each connected to one or more storage devices in a plurality of channels,
Each channel to which the storage device is connected is assigned one or more storage units of the plurality of storage units,
The access unit selects a storage unit that uses the control information among the plurality of storage units based on the state of the storage device connected to each channel.
The storage according to claim 5. In the information processing device,
A plurality of storage devices in which data is erased in units of blocks;
A plurality of storage units respectively used for storing control information representing spare blocks that are blocks for writing the data on one or more storage devices allocated among the plurality of storage devices; ,
When a write command for requesting writing of data to the plurality of storage devices is issued, the storage unit using the control information is selected from the plurality of storage units,
Writing the data requested by the write command in a spare block specified by the control information stored in the selected storage unit;
An access control method characterized by the above.

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