JPWO2015060069A1 - Fine pattern forming method, semiconductor device manufacturing method, substrate processing apparatus, and recording medium - Google Patents

Abstract

A core pattern forming step for forming a core pattern with a predetermined line width on the substrate surface side, a side wall forming step for forming a side wall with respect to the core pattern formed in the core pattern forming step, and after the side wall forming step, And a core pattern removing step of removing the core pattern using an etching gas while leaving the sidewalls, in the core pattern removing step, in parallel with the removal of the core pattern. The film deposited on the back side of the substrate in the core pattern forming step is removed.

Description

  The present invention relates to a technique for forming a fine pattern using an etching process, a method for manufacturing a semiconductor device using this technique, a substrate processing apparatus, and a recording medium.

  In semiconductor devices, pattern miniaturization is being promoted in order to achieve higher integration. In order to realize a fine pattern, various methods using an etching process (for example, see Patent Document 1) have been studied. By utilizing these methods, it is possible to form a pattern having extremely fine grooves and columns.

  In recent years, transistor dimensions have been reduced along with transistor scaling, and it has become impossible to expect improvement in transistor performance due to the miniaturization limit in a conventionally used flat transistor structure. As a method for overcoming this limitation, for example, a 3D transistor called Fin-FETs has been put into practical use. In the Si-Fin pattern of the Fin-FET, after the 22 nm generation, a fine pitch less than the resolution limit dimension in the most advanced immersion ArF lithography technology is required. Further, with respect to the pattern pitch of the gate electrode, a fine pitch less than the same resolution limit dimension is required after the 14 nm generation.

  As a technique for forming such a fine pattern, a self-alignment is performed in which a sidewall is formed on the side wall of a core pattern formed by lithography and dry etching, and a dimension less than the resolution limit is formed by processing using the sidewall as a mask. A double pattern technique (Self-Align Double Patterning: hereinafter abbreviated as SADP method) is used.

The following process is used as a general SADP method. For example, a SiO ₂ film (silicon oxide film), a Si ₃ N ₄ film (silicon nitride film), an amorphous Si film, a carbon hard mask (CHM), and an Si antireflection film are laminated in this order on a Si (silicon) substrate. A multilayer film is formed. And after apply | coating a photoresist on this multilayer film, it exposes with a lithography technique and forms the resist pattern of the line width more than a resolution limit. Thereafter, the Si antireflection film and the CHM film are processed to the same line width as the resist pattern by dry etching.

Next, the amorphous Si film, which is a base film, is patterned using the patterned CHM film as a mask, and a core pattern having the same line width as the resist is formed using the amorphous Si film. Next, a SiO ₂ film is formed on the core pattern, and a sidewall having a line width less than the resolution limit dimension is formed of SiO ₂ . Then, after forming the sidewall, the Si core pattern is removed by etching.

The Si core pattern removal process requires high etching selectivity so as not to etch the SiO ₂ film that is the sidewall material and, for example, the Si ₃ N ₄ film that is the base film. Until now, removal of the Si core pattern by dry etching using reactive ions has been common, but the selectivity for both the SiO ₂ film and the Si ₃ N ₄ film in the etching process of the Si core pattern. It was difficult to ensure.

Further, the minimum processing size of a semiconductor device represented by recent LSI, DRAM (Dynamic Random Access Memory) and Flash Memory is smaller than 30 nm width. In wet etching, which is one of the manufacturing processes of such a semiconductor device, for example, there is a collapse of a pattern due to the surface tension of a liquid used during wet etching, and miniaturization while maintaining the quality of the semiconductor device and an improvement in manufacturing throughput. The achievement of is becoming difficult.

As described above, the conventional dry etching technique (etching technique using reactive ions) and the wet etching technique cannot cope with the miniaturization of such next-generation semiconductor devices.

JP 2011-44493 A

  An object of the present invention is to provide a fine pattern formation technique using an etching technique suitable for the next generation semiconductor device, and a semiconductor device manufacturing method and a substrate processing apparatus using the technique.

  According to one embodiment of the present invention, a core pattern forming step for forming a core pattern having a predetermined line width on the substrate front side, and a sidewall formation for forming a sidewall with respect to the core pattern formed in the core pattern forming step And a core pattern removing step of removing the core pattern using an etching gas after the sidewall forming step while leaving the sidewall, wherein the core pattern removal method comprises: In the process, there is provided a fine pattern forming method for removing the film deposited on the back side of the substrate in the core pattern forming step in parallel with the removal of the core pattern.

  According to the configuration of the present invention, an etching technique suitable for the next generation semiconductor device can be provided.

1 is a schematic cross-sectional view of a substrate processing apparatus according to an embodiment of the present invention. It is a schematic longitudinal cross-sectional view of the substrate processing apparatus which concerns on one Embodiment of this invention. It is a longitudinal cross-sectional view of the 1st processing unit which the substrate processing apparatus concerning one Embodiment of this invention has. It is a longitudinal cross-sectional view of the susceptor which the 1st processing unit has. It is a longitudinal cross-sectional view of the 2nd processing unit which the substrate processing apparatus which concerns on one Embodiment of this invention has. It is a structural diagram of a controller according to an embodiment of the present invention. It is a figure which shows the processing flow of the substrate processing method which concerns on one Embodiment of this invention. It is a figure which shows the board | substrate front side in the 1st step of the fine pattern formation process which concerns on one Embodiment of this invention. It is a figure which shows the board | substrate back side in the said 1st step. It is a figure which shows the 2nd step of the fine pattern formation process which concerns on one Embodiment of this invention. It is a figure which shows the 3rd step of the fine pattern formation process which concerns on one Embodiment of this invention. It is a figure which shows the 4th step of the fine pattern formation process which concerns on one Embodiment of this invention. It is a figure which shows the 5th step of the fine pattern formation process which concerns on one Embodiment of this invention. It is a figure which shows the 6th step of the fine pattern formation process which concerns on one Embodiment of this invention. It is a figure which shows the board | substrate back side in the said 6th step. It is a figure which shows the 7th step of the fine pattern formation process which concerns on one Embodiment of this invention. It is a figure which shows the 8th step of the fine pattern formation process which concerns on one Embodiment of this invention. It is a figure which shows the 9th step of the fine pattern formation process which concerns on one Embodiment of this invention. It is a figure which shows the 10th step of the fine pattern formation process which concerns on one Embodiment of this invention. It is a figure which shows the processing flow in the substrate processing apparatus which concerns on one Embodiment of this invention. It is a figure which shows the processing flow in the substrate processing apparatus which concerns on one Embodiment of this invention. It is a figure which shows the processing flow in the substrate processing apparatus which concerns on one Embodiment of this invention. It is a figure for demonstrating the fine pattern formation process in one Embodiment of this invention. It is a figure for demonstrating the fine pattern formation process in one Embodiment of this invention. It is a figure for demonstrating the fine pattern formation process in one Embodiment of this invention. It is a figure for demonstrating the fine pattern formation process in one Embodiment of this invention. It is a figure for demonstrating the fine pattern formation process in one Embodiment of this invention. It is a figure which shows the state before removing the silicon film etc. of a substrate back side in one Embodiment of this invention. It is a figure which shows the state after removing the silicon film etc. of a substrate back side in one Embodiment of this invention. It is sectional drawing of the channel length direction of a transistor before the etching process of one Embodiment of this invention. It is sectional drawing of the channel width direction of a Fin-FET transistor before the etching process in one Embodiment of this invention. It is a three-dimensional schematic diagram of a Fin-FET transistor before the etching process in one embodiment of the present invention. It is sectional drawing of the channel length direction of a Fin-FET transistor after the etching process of one Embodiment of this invention. It is sectional drawing of the channel width direction of a Fin-FET transistor after the etching process of one Embodiment of this invention. It is a three-dimensional schematic diagram of a Fin-FET transistor after the etching process of one embodiment of the present invention. It is a figure which shows the state before removing the polysilicon film of a substrate back side in one Embodiment of this invention. It is a figure which shows the state after removing the polysilicon film of a substrate back side in one Embodiment of this invention. It is sectional drawing of the channel width direction of a Fin-FET transistor before the etching process of one Embodiment of this invention. It is a three-dimensional schematic diagram of a Fin-FET transistor before the etching process of one embodiment of the present invention. It is sectional drawing of the channel width direction of a Fin-FET transistor after the etching process in one Embodiment of this invention. It is a three-dimensional schematic diagram of a Fin-FET transistor after the etching process in one embodiment of the present invention. It is a figure which shows the state before removing the phosphorus addition polysilicon film of a substrate back side in one Embodiment of this invention. It is a figure which shows the state after removing the phosphorus addition polysilicon film of the substrate back side in one Embodiment of this invention. It is the structure of the substrate processing apparatus which concerns on other embodiment of this invention. It is a structural example of the board | substrate before the process which concerns on other embodiment of this invention. It is a structural example of the controller which concerns on other embodiment of this invention. It is an example of a flow of a substrate processing process concerning other embodiments of the present invention. (a) is a schematic longitudinal cross-sectional view for demonstrating the formation method of a resist pattern. (B) is a schematic longitudinal cross-sectional view for demonstrating the formation method of a resist pattern. (C) is a schematic longitudinal cross-sectional view for demonstrating the formation method of a resist pattern. (D) is a schematic longitudinal cross-sectional view for demonstrating the formation method of a resist pattern. (E) is a schematic longitudinal cross-sectional view for demonstrating the formation method of a resist pattern. (F) is a schematic longitudinal cross-sectional view for demonstrating the formation method of a resist pattern. (G) is a schematic longitudinal cross-sectional view for demonstrating the formation method of a resist pattern. (H) is a schematic longitudinal cross-sectional view for demonstrating the formation method of a resist pattern. (I) is a schematic longitudinal cross-sectional view for demonstrating the formation method of a resist pattern. (J) is a schematic longitudinal cross-sectional view for demonstrating the formation method of a resist pattern. (K) is a schematic longitudinal cross-sectional view for demonstrating the formation method of a resist pattern. (L) is a schematic longitudinal cross-sectional view for demonstrating the formation method of a resist pattern. (M) is a schematic longitudinal cross-sectional view for demonstrating the formation method of a resist pattern. FIG. 41 (a) is an example of substrate processing according to an embodiment of the present invention. FIG. 41B shows another example of substrate processing according to an embodiment of the present invention. It is a figure which shows the vapor pressure characteristic of the etching gas which concerns on one Embodiment of this invention.

In order to solve the above-described problems, the inventors have performed dry etching using an etching gas, which will be described later, so that at least silicon oxide (SiO ₂ ) and silicon nitride (Si ₃ N ₄ ) in a certain temperature range. ), Titanium nitride (TiN), amorphous carbon (a-C), etc., it was found that the Si film mainly composed of silicon (Si) element can be removed selectively. Further, it has been found that by using an etching gas which will be described later, the Si film containing Si element as a main component can be removed isotropically while maintaining high selectivity without making the etching gas into plasma.

Here, a Si film containing Si element as a main component (silicon as a main component) (for example, a film containing 90% or more of Si element. Note that “high selectivity” means, for example, silicon as a main component. The etching rate of the first film (for example, silicon film) is a film having a lower silicon content than the first film (for example, a silicon oxide film, a silicon oxynitride film, a silicon nitride film, etc.). It means to make it higher than the film, and better means to etch the first film without etching the second film.

FIG. 42 is a diagram regarding the vapor pressure characteristics of IF ₇ (or IF ₅ ) gas, which is one of the etching gases used in the present embodiment.

As shown in FIG. 42, iodine heptafluoride (IF ₇ ) (or iodine pentafluoride (IF ₅ )) gas is a gas that is clearly a gas in the etching process condition C in the present embodiment to be described later. is there. IF ₇ (or IF ₅ ) gas maintains high selectivity to the Si film as described above under such conditions that the temperature is 30 ° C. to 50 ° C. (or 40 ° C. to 50 ° C.) under such reduced pressure. However, the Si film can be isotropically etched.

Here, IF ₇ gas, it is considered that IF ₅ gas is generated as a by-product from the known production process. However, under conditions where the temperature is 30 ° C. to 50 ° C. (or 40 ° C. to 50 ° C.) under reduced pressure as in etching processing condition C described later, IF ₅ gas is used as a by-product as described above along with etching with IF ₇ gas. Since it is also a gas, it can be easily purged without adhering to the substrate.

In order to reliably remove the IF ₅ gas, it is preferable to heat the substrate temperature to 100 ° C. or higher as shown in FIG. Therefore, in consideration of removal of by-products, it is preferable to raise the temperature in the purge process in which the etching gas is removed from the processing chamber.

<First Embodiment>

(1) Configuration of Substrate Processing Apparatus Hereinafter, a substrate processing apparatus according to an embodiment of the present invention will be described with reference to the drawings. In the present embodiment, as an example, the substrate processing apparatus is configured as a semiconductor manufacturing apparatus that performs a processing step in a manufacturing method of a semiconductor device (IC: Integrated Circuit). In addition, the substrate processing apparatus of the present embodiment is configured as a single wafer apparatus capable of performing etching processing and ashing processing on one substrate in one processing chamber. FIG. 1 is a schematic cross-sectional view of a substrate processing apparatus according to an embodiment of the present invention. FIG. 2 is a schematic longitudinal sectional view of the substrate processing apparatus according to the embodiment of the present invention.

  As shown in FIGS. 1 and 2, the substrate processing apparatus 20 includes a process including an EFEM (Equipment Front End Module) 100, a load lock chamber 200, a transfer module 300, and a processing chamber in which an etching process is performed. And a chamber portion 400. 1 is referred to as a horizontal direction, and the z direction in FIG. 2 is referred to as a vertical direction. In the present embodiment, the xy plane is parallel to the horizontal plane, and the z direction is the vertical direction.

  The EFEM 100 includes a load port 120 on which a FOUP (Front Opening Unified Pod) 110 is placed, and a first transfer that transfers a wafer 60 as a substrate between the FOUP 110 on the load port 120 and the load lock chambers 250 and 260. And an atmospheric transfer robot 130 as a unit.

  The FOUP 110, which is a substrate container, can accommodate up to 25 wafers 60. The FOUP 110 containing the unprocessed substrate is placed on the load port 120 by the transport means outside the apparatus, and the FOUP 110 containing the processed substrate is unloaded from the load port 120 by the transport means outside the apparatus. The

  The atmospheric transfer robot 130 has five tweezers 131 and can transfer five wafers 60 at the same time. The atmospheric transfer robot 130 can horizontally rotate in the direction of the arrow D1 on the xy plane in FIG. 1, and can move horizontally in the direction of the arrow D2 (direction yy ′). The tweezer 131 of the atmospheric transfer robot 130 can move up and down in the direction of arrow D4 (zz ′ direction) in FIG. 2, and can move back and forth in the direction of arrow D3 (xx ′ direction) in FIG.

  The load lock chamber unit 200 includes load lock chambers 250 and 260. The load lock chamber 250 includes a buffer unit 210 that holds the wafer 60 transferred from the FOUP 110. The buffer unit 210 includes a boat 211 and an index assembly 212 below the boat 211. The boat 211 and the index assembly 212 below the boat 211 are horizontally rotatable in the direction of arrow D5 in FIG. By this rotation, the substrate entrance / exit of the boat 211 can be directed to the atmospheric transfer robot 130 or the vacuum transfer robot 320. The index assembly 212 is a lifting mechanism that lifts and lowers the boat 211.

  The load lock chamber 260, the buffer unit 220, the boat 221, and the index assembly 222 provided in the load lock chamber 260 have the same structure as the load lock chamber 250, the buffer unit 210, the boat 211, and the index assembly 212, respectively. It has a function.

  The boat 211 can stack up to five wafers 60 in a horizontal posture in a state where they are spaced apart from each other in the vertical direction (z direction). The load lock chamber 250 includes an evacuation device (not shown), and makes the load lock chamber 250 in a vacuum state (that is, a low pressure state) or an atmospheric pressure state with a predetermined pressure based on a command from the controller 600 described later. Is possible.

  The transfer module unit 300 includes a transfer module 310 used as a vacuum transfer chamber, and the above-described load lock chamber 250 (260) is attached to the transfer module 310 via a gate valve 311 (312). The transfer module 310 is provided with a vacuum transfer robot 320 used as a second transfer unit. The vacuum transfer robot 320 transfers the wafer 60 between the load lock chambers 250 and 260 and the processing units 410 and 510. The inside of the transfer module unit 300 is always maintained in a vacuum state at a predetermined pressure.

  The process chamber unit 400 includes a processing unit 410 that performs an etching process and a plasma processing unit 510 that can perform an etching process and an ashing process. The processing unit 410 (510) is attached to the transfer module 310 via a gate valve 313 (314). The processing units 410 and 510 are always maintained in a vacuum state at a predetermined pressure. Here, in the present embodiment, the etching process and the ashing process are configured to be shared by the second processing unit 510. However, the present invention is not limited to this embodiment. Rather, the etching process and the ashing process are separately performed. It is preferable that the processing unit is implemented. The configurations of the processing unit 410 and the processing unit 510 will be described later.

  The substrate processing apparatus 20 further includes a controller 600 that is electrically connected to each component of the substrate processing apparatus 20, that is, connected by an electrical signal. The controller 600 controls the operation of each component. The configuration of the controller 600 will be described later.

  In the substrate processing apparatus 20 configured as described above, the wafer 60 is transferred from the FOUP 110 on the load port 120 to the load lock chamber 250 (260) in the atmospheric pressure state. At this time, first, as shown in FIG. 2, the atmospheric transfer robot 130 inserts the tweezer 131 into the FOUP 110 and simultaneously places five wafers on the tweezer 131. At this time, the tweezer 131 of the atmospheric transfer robot 130 is moved up and down in accordance with the height position of the wafer 60 to be taken out.

  After placing the wafer 60 on the tweezer 131 and taking it out of the FOUP 110, the atmospheric transfer robot 130 rotates in the direction of the arrow D1, and puts the wafer 60 on the boat 211 (221) in the buffer unit 210 (220) in the atmospheric pressure state. Mount. At this time, the boat 211 (221) receives five wafers 60 from the atmospheric transfer robot 130 by the operation of the boat 211 (221) in the Z direction. After receiving the five wafers 60, the boat 211 (221) is moved up and down in the Z direction so that the position of the wafer 60 in the lowermost layer of the boat 211 (221) matches the height position of the transfer module unit 300. .

  Next, after the inside of the load lock chamber 250 (260) is evacuated to a predetermined pressure, one of the wafers 60 held by the boat 211 (221) in the load lock chamber 250 (260) is removed. The vacuum transfer robot 320 is transferred onto the susceptor table 411 (511) in the processing unit 410 (510). At this time, the vacuum transfer robot 320 mounts one wafer 60 held in the boat 211 (221) on the finger 321 and removes it from the boat 211 (221), and then rotates in the arrow D7 direction. The finger 321 is extended in the direction of arrow D8 and transferred onto the susceptor table 411 (511) in the processing unit 410 (510).

  When the wafer 60 is transferred from the finger 321 to the susceptor table 411 (511), the wafer 60 is transferred onto the susceptor table 411 (511) by the cooperation of the finger 321 and the lifter pin 413 (513). The Specifically, when the finger 321 on which the wafer 60 is placed moves to a predetermined position on the susceptor table 411 (511), the lifter pins 413 (513) are raised, and the wafer 60 placed on the finger 321. Is supported apart from the finger 321. After the lifter pins 413 (513) support the wafer 60, the fingers 321 are retracted in the direction of the arrow D8. Thereafter, the lifter pins 413 (513) are lowered to place the wafer 60 on the susceptor table 411 (511).

  When the processed wafer 60 is transferred from the susceptor table 411 (511) to the boat 211 (221) in the load lock chamber 250 (260), the vacuum transfer robot 320 and the lifter pins 413 (513) are described above. An operation opposite to the operation of transferring the wafer 60 onto the susceptor table 411 (511) is performed.

  As described above, in the substrate processing apparatus 20, the wafer 60 is transferred from the FOUP 110 on the load port 120 to the load lock chamber 250 (260) in the atmospheric pressure state. Thereafter, the inside of the load lock chamber 250 (260) is evacuated (vacuum replacement), and the wafer 60 is transferred from the load lock chamber 250 (260) to the processing unit 410 (510) via the transfer module 310.

  Then, the processing unit 410 performs a first etching process (non-plasma process without using plasma), and the wafer 60 subjected to the first etching process is transferred to the processing unit 510 via the transfer module 310. Then, the second etching process (plasma process) is performed in the processing unit 510, and the wafer 60 subjected to the second etching process is transferred to the processing unit 410 again through the transfer module 310. Then, a third etching process (non-plasma process) is performed in the processing unit 410, and the wafer 60 subjected to the third etching process is transferred to the load lock chamber 250 (260) through the transfer module 310. Thereafter, the wafer 60 in the load lock chamber 250 (260) is returned to the FOUP 110 on the load port 120. Thus, according to the present embodiment, the first etching process and the third etching process are both non-plasma etching processes.

  Alternatively, the wafer 60 that has been subjected to the first etching process in the processing unit 410 and from which the object to be etched has been removed is transferred to the load lock chamber 250 (260) through the transfer module 310, and then on the load port 120. It is also possible to return to the FOUP 110.

  Alternatively, the wafer 60 transferred from the lock chamber 250 (260) is subjected to the second etching process (plasma process) in the processing unit 510, and the wafer 60 subjected to the second etching process passes through the transfer module 310. Then, it can be transferred again to the load lock chamber 250 (260) and then returned to the FOUP 110 on the load port 120.

  As described above, the substrate processing apparatus 20 can perform single processing using only the processing unit 410, single processing using only the processing unit 510, and continuous processing using the processing unit 410 and the processing unit 510.

(First Processing Unit) The first processing unit 410 will be described with reference to FIGS. 3 and 4. FIG. 3 is a longitudinal sectional view of a first processing unit included in the substrate processing apparatus according to the present embodiment. FIG. 4 is a longitudinal sectional view of a susceptor included in the first processing unit. The first processing unit 410 is, for example, a processing unit that performs non-plasma etching on a semiconductor substrate. As shown in FIG. 3, the processing unit 410 includes a gas buffer chamber 430 and a processing chamber 445 that accommodates a wafer 60 such as a semiconductor substrate. The processing unit 410 is configured, for example, by disposing a gas buffer chamber 430 above a horizontal base plate 448 as a gantry and a processing chamber 445 below the base plate 448. The processing container 431 includes at least a gas buffer chamber 430 and a processing chamber 445.

  A processing gas is supplied to the gas buffer chamber 430 from the gas inlet 433. The inner wall of the gas buffer chamber 430 is formed in a cylindrical shape from high-purity quartz glass or ceramics. The walls are arranged so that the axis of the cylinder is vertical. A top plate 454 is provided at the upper end of the processing container 431. The top plate 454 is supported on the inner wall and the upper end of the outer shield. The upper end of the gas buffer chamber 430 is hermetically sealed by a top plate 454.

  The top plate 454 includes a lid portion 454a that closes the upper end of the processing container 431, and a support portion 454b that supports the lid portion 454a. A gas inlet 433 is provided in the approximate center of the lid 454a. An O-ring 453 is provided between the flange portion at the tip of the processing container 431 (the part protruding outward from the processing container 431) and the support portion 454b, and the gas buffer chamber 430 is configured to be airtight. .

  The side wall 446 of the processing chamber 445 is formed in a cylindrical shape with high-purity quartz glass or ceramics. The side wall 446 is disposed so that the axis of the cylinder is vertical. An inner wall of the gas buffer chamber 430 is disposed at the upper end of the side wall 446. A bottom plate 469 is disposed at the lower end of the side wall 446. The side wall 446 is airtightly provided above the bottom plate 469 so as to keep the inside of the processing chamber 445 airtight.

  Below the processing chamber 445, a susceptor 459 as a substrate mounting portion supported by a plurality of (for example, four) support columns 461 is provided. The susceptor 459 includes a susceptor table 411, a heater 463 that is provided inside the susceptor 459 and heats the wafer 60 on the susceptor 459, and a susceptor coolant channel 464 described later.

  An exhaust plate 465 is disposed below the susceptor 459. The exhaust plate 465 is supported by the bottom plate 469 via the guide shaft 467. The elevating plate 471 is provided to move up and down with the guide shaft 467 as a guide. The lift plate 471 supports at least three lifter pins 413.

  As shown in FIG. 3, the lifter pin 413 passes through the susceptor table 411 of the susceptor 459. A support portion 414 that supports the wafer 60 is provided on the top of the lifter pins 413. The support portion 414 extends in the center direction of the susceptor 459. The wafer 60 can be placed on the susceptor table 411 or lifted from the susceptor table 411 by raising and lowering the lifter pins 413.

  The lifting plate 471 is connected to a lifting shaft 472 that penetrates the bottom plate 469. The elevating shaft 472 is connected to the elevating drive unit 473. As the elevating drive unit 473 moves the elevating shaft 472 up and down, the support unit 414 moves up and down via the elevating plate 471 and the lifter pin 413.

  A baffle ring 458 is provided between the susceptor 459 and the exhaust plate 465. A first exhaust chamber 474 is formed so as to be surrounded by the baffle ring 458, the susceptor 459, and the exhaust plate 465. The cylindrical baffle ring 458 is provided with a large number of air holes (not shown) uniformly on its side surface. Therefore, the first exhaust chamber 474 is separated from the processing chamber 445 by the baffle ring 458 and communicates with the processing chamber 445 through the vent holes.

  A second exhaust chamber 476 is formed so as to be surrounded by the exhaust plate 465 and the concave bottom plate 469. An exhaust communication hole 475 is provided at the center of the exhaust plate 465. Accordingly, the first exhaust chamber 474 and the second exhaust chamber 476 are communicated with each other through the exhaust communication hole 475.

(First Exhaust Portion) An exhaust pipe 480 extending in the gravity direction, that is, the z direction is provided so as to penetrate the bottom plate 469. The second exhaust chamber 476 communicates with the exhaust pipe 480. The exhaust pipe 480 is provided with a pressure adjustment valve 479 and an exhaust pump 481 in order from the upstream. Thus, by providing the exhaust pipe 480 below the susceptor 459 and in the direction of gravity, the gas supplied to the processing chamber 445 is easily exhausted without staying in the processing chamber 445. Therefore, it is possible to reduce the degree of danger due to contact with gas when maintenance is performed by maintenance personnel. A first exhaust unit that exhausts the gas (atmosphere) in the processing chamber 445 is configured to include at least the exhaust pipe 480 and the pressure adjustment valve 479. Note that the exhaust pump 481 may be included in the first exhaust part.

(First and Second Gas Supply Units) The top plate 454 above the processing container 431 has a first gas supply unit 482 (first gas supply unit) and a second gas supply unit 483 (second gas). Supply section). The first gas supply unit 482 includes a gas supply pipe 482a connected to the gas introduction port 433 and an inert gas supply pipe 482e connected to the gas supply pipe 482a. In the gas supply pipe 482a, a first gas source 482b that is a gas source of the first gas, a mass flow controller 482c, and an on-off valve 482d are provided in order from the upstream. The inert gas supply pipe 482e is provided with an inert gas source 482f, a mass flow controller 482g, and an on-off valve 482h, which are inert gas sources, in order from the upstream.

  By controlling the mass flow controller 482c and the on-off valve 482d, the flow rate of the first gas can be controlled. Further, the flow rate of the inert gas can be controlled by controlling the mass flow controller 482g and the on-off valve 482h. The inert gas is used as a purge gas for purging (removing) the residual gas in the gas supply pipe 482a, and further as a carrier gas for the first gas supplied to the gas supply pipe 482a.

  The first gas supply unit 482 is configured to have at least a gas supply pipe 482a, a mass flow controller 482c, and an on-off valve 482d. Note that the first gas supply unit 482 may include a purge gas supply pipe 482e, a mass flow controller 482g, and an on-off valve 482h. Further, a first gas source 482b and an inert gas source 482f may be included.

In the present embodiment, iodine heptafluoride (IF ₇ ) gas is used as the first gas. As the first gas, for example, chlorine trifluoride (ClF ₃ ), xenon difluoride (XeF ₂ ), bromine trifluoride (BrF ₃ ), bromine pentafluoride (BrF ₅ ), iodine pentafluoride ( Any gas among IF ₅ ) can also be used. As an inert gas supplied from the inert gas source 482f, for example, nitrogen (N ₂ ) gas or the like is used.

  The second gas supply unit 483 is provided adjacent to the gas supply unit 482 in the top plate 454 on the upper side of the processing container 431. The second gas supply unit 483 has a gas supply pipe 483 a connected to the gas inlet 433. In the gas supply pipe 483a, a second gas source 483b that is a gas source of the second gas, a mass flow controller 483c, and an on-off valve 483d are provided in order from the upstream.

  By controlling the mass flow controller 483c and the on-off valve 483d, the flow rate of the second gas can be controlled. The second gas supply unit 483 is configured to include at least a gas supply pipe 483a, a mass flow controller 483c, and an on-off valve 483d. Note that the second gas supply unit 483 may include the second gas source 483b.

For example, an inert gas such as nitrogen (N ₂ ) is used as the _second gas. This inert gas is used as a dilution gas for the first gas or as a purge gas for the residual gas in the processing chamber 445.

  In the present embodiment, the gas introduction port from the first gas supply unit 482 and the second gas supply unit 483 is the common gas introduction port 433. However, the present invention is not limited to this. A gas inlet corresponding to each of the gas supply unit 482 and the second gas supply unit 483 may be provided.

  By controlling the mass flow controllers 482c, 483c, etc. and the pressure adjustment valve 479 to adjust the gas supply amount and the gas exhaust amount from the processing chamber 445, the pressure in the processing chamber 445 and the partial pressure of the introduced gas can be reduced. Adjusted.

  A porous shower plate 484 is provided in the gas buffer chamber 430. The shower plate 484 has a plate portion 484a and a plurality of holes 484b provided in the plate portion 484a. The gas introduced from the gas introduction port 433 collides with the plate portion 484 a of the shower plate 484, passes through the hole portion 484 b, and is supplied to the surface of the wafer 60. Thus, the gas introduced into the gas buffer chamber 430 is uniformly dispersed by the shower plate 484 and supplied onto the wafer 60.

(First Temperature Control Unit) FIG. 4 is a longitudinal sectional view of a susceptor 459 included in the first processing unit 410. The susceptor table 411 includes a heater 463 and a susceptor coolant channel 464. The heater 463 and the susceptor coolant channel 464 are provided in the susceptor table 411 and control the temperature of the wafer 60 placed on the susceptor 459.

  The heater 463 is connected to the heater temperature control unit 485 via the heater power supply line 487. In the vicinity of the heater 463, a susceptor 459 and a temperature detection unit 488 for detecting the temperature of the wafer 60 placed on the susceptor 459 are provided. The temperature detection unit 488 is electrically connected to the controller 600. The temperature data detected by the temperature detection unit 488 is input to the controller 600. The controller 600 instructs the heater temperature control unit 485 to control the amount of power supplied to the heater 463 based on the detected temperature data, and controls the heater 463 so that the wafer 60 reaches a desired temperature.

  The susceptor coolant channel 464 is connected to the external susceptor coolant channel 489. Specifically, the coolant introduction port of the susceptor coolant channel 464 is connected to the external susceptor coolant channel 489a, and the coolant discharge port of the susceptor coolant channel 464 is connected to the external susceptor coolant channel 489b. ing. In the susceptor coolant channel 464 and the external susceptor coolant channel 489, the coolant flows in the direction of arrow D10. A coolant supply unit 491 is connected to the external susceptor coolant channel 489. The coolant supply unit 491 keeps the temperature of the coolant flowing through the external susceptor coolant channel 489a within a predetermined value range and controls the flow rate based on an instruction from the coolant flow rate control unit 486.

  In the external susceptor coolant channel 489b upstream of the coolant supply unit 491, a coolant temperature detection unit 492 that detects the temperature of the coolant that has flowed through the susceptor coolant channel 464 is provided. The coolant temperature detection unit 492 and the coolant flow rate control unit 486 are electrically connected to the controller 600. The temperature data detected by the coolant temperature detection unit 492 is input to the controller 600. Based on the detected temperature data, the controller 600 instructs the coolant flow rate control unit 486 to control the coolant flow rate that flows through the external susceptor coolant channel 489a so that the wafer 60 has a desired temperature. The coolant flow rate control unit 486 controls the flow rate of the coolant flowing through the external susceptor coolant channel 489 with respect to the coolant supply unit 491 based on an instruction from the controller 600.

  The first temperature control unit is configured to have at least a heater temperature control unit 485 and a coolant flow rate control unit 486. Note that a heater 463 and a susceptor coolant channel 464 may be included in the first temperature control unit. Furthermore, a coolant supply unit 491, an external susceptor coolant flow path 489, a coolant temperature detection unit 492, and a heater power supply line 487 may be included. The heater 463 and the susceptor coolant channel 464 are collectively referred to as a first temperature adjustment mechanism.

(Second Processing Unit) The second processing unit 510 will be described with reference to FIG. FIG. 5 is a longitudinal sectional view of a second processing unit included in the substrate processing apparatus according to the present embodiment. The second processing unit 510 is a high-frequency electrodeless discharge type plasma processing unit that can perform an etching process or an ashing process on a film formed on a semiconductor substrate by a dry process. As shown in FIG. 5, the processing unit 510 supplies high-frequency power to a plasma generation chamber 530 for generating plasma, a processing chamber 545 for accommodating a wafer 60 such as a semiconductor substrate, and a plasma source such as a resonance coil 521. A high frequency power source 525 for controlling the oscillation frequency of the high frequency power source 525, and the like.

  The reaction vessel 531 is formed in a cylindrical shape with high-purity quartz glass or ceramics. A processing chamber 545 is provided below the reaction vessel 531. Below the processing chamber 545, a susceptor 559 supported by a plurality of (for example, four) support columns 561 is provided. The susceptor 559 includes a susceptor table 511 and a heater 563 provided inside the susceptor 559 and serving as a substrate heating unit that heats the wafer 60 on the susceptor 559. In this embodiment, the susceptor coolant channel is not provided in the susceptor 559, but the susceptor coolant similar to the susceptor coolant channel 464 of the first processing unit shown in FIG. A flow path may be provided and the coolant flow rate control may be performed similarly to the first processing unit.

(Second Temperature Control Unit) The second temperature control unit controls the substrate temperature on the susceptor 559 of the second processing unit, and is configured similarly to the first temperature control unit. That is, the heater 563 is connected to the second temperature control unit via the second heater power supply line. In the vicinity of the heater 563, a susceptor 559 and a second temperature detection unit for detecting the temperature of the wafer 60 placed on the susceptor 559 are provided. The second temperature detection unit is electrically connected to the controller 600. The temperature data detected by the second temperature detection unit is input to the controller 600. The controller 600 instructs the second temperature control unit to control the amount of power supplied to the heater 563 based on the detected temperature data, and controls the heater 563 so that the wafer 60 reaches a desired temperature. Note that a heater 563 may be included in the second temperature control unit.

  An exhaust plate 565 is disposed below the susceptor 559. The exhaust plate 565 is supported by the bottom plate 569 via a guide shaft 567. Below the exhaust plate 565, an elevating plate 571 is provided to move up and down with a guide shaft 567 as a guide. The lifting plate 571 supports at least three lifter pins 513. The lifter pin 513 passes through the susceptor 559. A support portion 514 that supports the wafer 60 is provided on the top of the lifter pins 513. The wafer 60 can be placed on the susceptor 559 or lifted from the susceptor 559 by raising and lowering the lifter pins 513. The lifting shaft 572 of the lifting drive unit 573 is connected to the lifting plate 571 through the bottom plate 569. As the elevating drive unit 573 moves the elevating shaft 572 up and down, the support unit 514 moves up and down via the elevating plate 571 and the lifter pin 513.

(Second exhaust part) A baffle ring 558 is provided between the susceptor 559 and the exhaust plate 565. The cylindrical baffle ring 558 has a large number of air holes uniformly, and the processing chamber 545 and the first exhaust chamber 574 communicate with each other through the air holes. An exhaust communication hole 575 is provided in the exhaust plate 565. The first exhaust chamber 574 and the second exhaust chamber 576 communicate with each other through the exhaust communication hole 575. An exhaust pipe 580 is communicated with the second exhaust chamber 576, and a pressure adjustment valve 579 and an exhaust pump 581 are provided in the exhaust pipe 580. A second exhaust unit that exhausts the gas (atmosphere) in the processing chamber 545 is configured to include at least the exhaust pipe 580 and the pressure adjustment valve 579. Note that the exhaust pump 581 may be included in the second exhaust part.

(Third Gas Supply Unit) A third gas supply unit (third gas supply unit) 582 is connected to the top plate 554 above the reaction vessel 531. The third gas supply unit 582 includes a gas supply pipe 582a connected to the gas inlet 533 and an inert gas supply pipe 582e connected to the gas supply pipe 582a. The gas supply pipe 582a is provided with a third gas source 582b, a mass flow controller 582c, and an on-off valve 582d, which are gas sources of a third gas (O ₂ gas in the present embodiment) in order from the upstream. The inert gas supply pipe 582e is provided with an inert gas source 582f, a mass flow controller 582g, and an on-off valve 582h, which are gas sources of an inert gas (N ₂ gas in the present embodiment) in order from the upstream.

  By controlling the mass flow controller 582c and the on-off valve 582d, the flow rate of the third gas can be controlled. Further, the flow rate of the inert gas can be controlled by controlling the mass flow controller 582g and the on-off valve 582h. The inert gas is a purge gas for purging (removing) the residual gas in the gas supply pipe 582a, or a purge gas for discharging the atmosphere in the processing chamber 545, and further, a third gas supplied to the gas supply pipe 582a. Used as a dilution gas.

  The third gas supply unit 582 is configured to have at least a gas supply pipe 582a, a mass flow controller 582c, and an on-off valve 582d. The third gas supply unit 582 may include a purge gas supply pipe 582e, a mass flow controller 582g, and an on-off valve 582h. Further, a third gas source 582b and an inert gas source 582f may be included.

  Further, a baffle plate 584 made of quartz is provided in the reaction vessel 531 in a substantially disc shape for allowing the processing gas to flow along the inner wall of the reaction vessel 531. Note that the pressure in the processing chamber 545 is adjusted by adjusting the gas supply amount and the exhaust amount by the mass flow controller 582c, the pressure adjustment valve 579, and the like.

  Both ends of the resonance coil 521 is electrically grounded, at least one end of the resonance coil 521 is grounded through a movable tap 522. Reference numeral 523 in FIG. 5 indicates the other fixed ground. Further, for finely adjusting the impedance of the resonance coil 521, between the grounded ends of the resonant coil 521, the feeding unit is constituted by a movable tap 524.

  The outer shield 532 shields the leakage of electromagnetic waves to the outside of the resonance coil 521, and is formed in a cylindrical shape using a conductive material such as aluminum alloy, copper, or copper alloy. An RF sensor 527 is installed on the output side of the high-frequency power source 525 and monitors traveling waves, reflected waves, and the like. The reflected wave power monitored by the RF sensor 527 is input to the frequency matching unit 526. The frequency matching unit 526 controls the frequency so that the reflected wave is minimized.

For example, after the wafer 60 held at room temperature is placed on the susceptor table 511, a processing gas, for example, an etching gas is supplied to the plasma generation chamber 530 from the gas supply pipe 582a. In the present embodiment, oxygen (O ₂ ) gas is used as the processing gas. Moreover, hydrogen, water, ammonia, carbon tetrafluoride (CF ₄ ), or the like can be used as the processing gas. After supplying the processing gas, power is supplied to the resonance coil 521 from the high-frequency power source 525, free electrons are accelerated by an induced magnetic field excited inside the resonance coil 521, and the gas molecules are excited to collide with the gas molecules to excite the plasma. Is generated. In this way, plasma processing such as etching processing or ashing processing is performed with the gas activated by the plasma.

  The first temperature control unit and the second temperature control unit are collectively referred to as a temperature control unit. Together with the first gas supply unit and the second gas supply unit and a third gas supply unit, referred to as a gas supply unit. The first exhaust part and the second exhaust part are collectively referred to as an exhaust part. Therefore, the temperature control unit, means first temperature control unit, or the second temperature control unit, or both the first and second temperature control unit. The meanings of the gas supply unit and the exhaust unit are the same as those of the temperature control unit.

  In the present embodiment, the first temperature control unit and the second temperature control unit have been described as separate components from the controller 600. However, the present invention is not limited to this, and the controller 600 includes the first temperature control unit, It may also serve as the second temperature control unit.

(Controller: Control Unit) Next, the configuration of the controller 600 will be described. FIG. 6 is a structural diagram of the controller according to the present embodiment. As shown in FIG. 6, a controller 600 as a control unit (control means) is configured as a computer including a CPU (Central Processing Unit) 600a, a RAM (Random Access Memory) 600b, a storage device 600c, and an I / O port 600d. Has been. The RAM 600b, the storage device 600c, and the I / O port 600d are configured to exchange data with the CPU 600a via the internal bus 600e. For example, an input / output device 601 configured with a touch panel or the like is connected to the controller 600.

  The storage device 600c is configured by, for example, a flash memory, an HDD (Hard Disk Drive), or the like. In the memory device 600c, a control program for controlling the operation of the substrate processing apparatus 20, process recipe, etc. such as procedures and conditions of the substrate processing is described in the substrate processing apparatus 20 to be described later, it is stored readably . Furthermore, processing conditions are stored for each type of etching gas or ashing gas that is a processing gas. Here, the processing conditions refer to conditions for processing the substrate, such as the temperature zone of the substrate and the susceptor, the pressure in the processing chamber, the partial pressure of gas, the gas supply amount, the coolant flow rate, and the processing time.

  The process recipe is a combination of the controller 600 so that a predetermined result can be obtained by causing the controller 600 to execute a procedure in a substrate processing step of the substrate processing apparatus 20 to be described later, and functions as a program. Hereinafter, the process recipe, the control program, and the like are collectively referred to as simply a program. When the term “program” is used in this specification, it may include only a process recipe alone, may include only a control program alone, or may include both. The RAM 600b is configured as a working memory area (work area) in which programs, data, and the like read by the CPU 600a are temporarily stored.

  The I / O port 600d includes the above-described lift drive units 473, 573, heater temperature control unit 485, temperature detection unit 488, pressure adjustment valves 479, 579, mass flow controllers 482c, 482g, 483c, 582c, 582g, open / close valves 482d, 482h, 483d, 582d, 582h, exhaust pump 481,581, the atmospheric transfer robot 130, a gate valve 311 to 314, the vacuum transfer robot 320, and is connected to the coolant flow rate control unit 486 and the like.

  CPU600a, along with reads and executes the control program from the storage device 600c, and is configured so as reads the process recipe from the memory device 600c according to an input of the operation command from the input-output device 501. Then, the CPU 600a moves the lifter pins (413, etc.) up and down by the elevation drive unit (473, etc.), the heating operation of the wafer 60 by the heater temperature control unit (485, etc.), and the pressure so as to follow the contents of the read process recipe. It is configured to control the pressure adjustment operation by the adjustment valve (479 etc.) and the flow rate adjustment operation of the processing gas by the mass flow controller (482c etc.) and the on-off valve (482d etc.).

  The controller 600 is not limited to being configured as a dedicated computer, and may be configured as a general-purpose computer. For example, the controller 600 according to the present embodiment can be configured by preparing an external storage device 602 storing the above-described program and installing the program in a general-purpose computer using the external storage device 602. The external storage device 602 includes, for example, a magnetic tape, a magnetic disk such as a flexible disk and a hard disk, an optical disk such as a CD and a DVD, a magneto-optical disk such as an MO, and a semiconductor memory such as a USB memory (USB Flash Drive) and a memory card. Is done. The means for supplying the program to the computer is not limited to the case of supplying via the external storage device 602. For example, the program may be supplied without using the external storage device 602 using communication means such as the Internet or a dedicated line.

  As described above, the storage device 600c and the external storage device 602 are configured as computer-readable recording media. Hereinafter, these are collectively referred to simply as a recording medium. Note that in this specification, the term recording medium may include only the storage device 600c alone, may include only the external storage device 602 alone, or may include both.

(2) Substrate Processing Method Next, an example of a substrate processing step in which the substrate processing method according to this embodiment is performed will be described below with reference to FIGS. This substrate processing step is performed as a step of forming a fine pattern and a step of manufacturing a semiconductor device. FIG. 7 is a diagram showing a processing flow of the substrate processing method according to the embodiment of the present invention. 8, FIG. 10 to FIG. 14, and FIG. 16 to FIG. 19 are views showing the first to tenth stages of the fine pattern forming process according to the embodiment of the present invention, respectively. FIGS. 9 and 15 are diagrams showing the back side of the substrate at the stage of FIGS. 8 and 14, respectively.

  In the substrate processing apparatus 20 of the present embodiment, at least step S6 (core pattern removal process) in FIG. 7 is performed.

First, as shown in step S <b> 1 of FIG. 7, a resist pattern 1 having a desired line width is formed on the Si film 2. This line width is a line width greater than the resolution limit of the exposure apparatus. Specifically, as shown in FIG. 8, on the front side of the Si substrate 9, a SiO ₂ film 8, a Si ₃ N ₄ film 7, a SiO ₂ film 6, a Si ₃ N ₄ film 5, an amorphous Si film 4, and a hard containing carbon. A carbon hard mask (CHM) film 3 as a mask and an Si film 2 as an antireflection film are laminated in this order to form a multilayer film. And after apply | coating a photoresist on this multilayer film, it exposes with a lithography technique, Then, it develops and the resist pattern 1 is formed. Thus, a multilayer resist film is formed.

The SiO ₂ film 8 is a thermal oxide film having a film thickness of about 3 to 10 nm and formed on the Si substrate 9 at an oxidation temperature of 600 to 1100 ° C., for example. The SiO ₂ film 8 is intended to protect the surface of the Si substrate 9 in the process of removing the Si ₃ N ₄ film 7 with hot phosphoric acid. The Si ₃ N ₄ film 7 has a film thickness of about 30 to 50 nm and is formed on the SiO ₂ film 8 at a temperature of 500 to 900 ° C. by a CVD (Chemical Vapor Deposition) method. The Si ₃ N ₄ film 7 is a stopper film at the time of the CMP process for flattening the SiO ₂ film buried in the groove 21 after the formation of the groove 21 of the Si substrate 9 shown in FIG.

The SiO ₂ film 6 has a film thickness of about 30 to 50 nm and is formed on the Si ₃ N ₄ film 7 by a CVD method at a temperature of 500 to 900 ° C. The SiO ₂ film 6 forms a groove 21 of the Si substrate 9 shown in FIG. 19 by dry etching the underlying Si ₃ N ₄ film 7, the SiO ₂ film 8, and the underlying Si substrate 9. It becomes a hard mask.

The Si ₃ N ₄ film 5 has a thickness of about 5 to ₂₀ nm and is formed on the SiO ₂ film 6 by a CVD method at a temperature of 500 to 900 ° C. The Si ₃ N ₄ film 5 is a film for transferring the SiO ₂ film pattern of the sidewall used in the SADP process. The sidewall SiO ₂ film formed at a low temperature has low dry etching resistance, and it is difficult to process the thick Si ₃ N ₄ film 7 using the sidewall SiO ₂ film as a mask. Therefore, a process (step S7 described later) for temporarily transferring the SiO ₂ film pattern on the sidewall to the thin Si ₃ N ₄ film 5 is used.

The amorphous Si film 4 has a thickness of about 40 to 60 nm and is formed on the Si ₃ N ₄ film 5 by a CVD method at a temperature of 400 to 550 ° C. The CHM film 3 is an amorphous carbon film having a thickness of about 100 to 500 nm, and is formed on the amorphous Si film 4 by a CVD method at a temperature of 200 to 550 ° C. The amorphous Si film 2 has a thickness of about 2 to 10 nm and is formed on the CHM film 3 by a CVD method at a temperature of 400 to 550 ° C. The amorphous Si film 2 functions as an antireflection film during exposure by lithography.

  When the films 8-2 are stacked on the front side of the Si substrate 9, the films 8-2 are stacked in this order on the back side of the Si substrate 9, as shown in FIG. Even when the back side of the Si substrate 9 is supported by a flat susceptor, the laminated films 8 to 2 are formed at least on the periphery of the back side of the Si substrate 9. Of these, the laminated films 4 and 2 are fragile films that are relatively easily peeled off. Therefore, they may be peeled off and cause particles in a process performed after the substrate processing process, which is not preferable. Therefore, the laminated films 4 and 2 are removed in step S6 of FIG.

Next, as shown in step S <b> 2 of FIG. 7, a CHM pattern is formed with the same line width as the resist pattern 1. Specifically, as shown in FIG. 10, the underlying amorphous Si film 2 is processed by a known dry etching process using, for example, Cl ₂ gas, using the patterned resist 1 as a mask, and then the CHM film 3 Is processed by a known dry etching process using, for example, O ₂ gas. Thereafter, the resist 1 is removed by a known ashing process using, for example, O ₂ gas. Note that the etching of the Si film 2 is anisotropic etching performed in a direction perpendicular to the surface of the Si substrate 9, and therefore the amorphous Si film 2 on the back side of the Si substrate 9 is not removed.

Next, as shown in step S <b> 3 of FIG. 7, the core pattern 4 is formed with the same line width as the CHM film 3. Specifically, as shown in FIG. 11, with the CHM film 3 as a mask, the underlying amorphous Si film 4 is processed by a known dry etching process using, for example, Cl ₂ gas or CF ₂ Cl ₂ gas. The core pattern 4 having the same line width as the resist pattern 1 is formed from the amorphous Si film 4. Thereafter, the CHM film 3 is removed by a known dry etching process using, for example, O ₂ gas. At this time, the CHM film 3 on the back side of the Si substrate 9 is not removed because the Si film 2 on the back side of the Si substrate 9 is not removed.

  As described above, the core pattern forming process includes an exposure development process and a dry etching process. Then, in the exposure and development process, by developing the resist film to form a pattern having a predetermined line width after exposure to form a resist pattern 1. In the dry etching process, the core pattern 4 is formed by etching the antireflection film (Si film 2) and the hard mask film (CHM film 3) using the resist pattern 1 as a mask.

  Then, at the stage where the formation of the core pattern 4 is completed, on the back side of the Si substrate 9, on the back side core material film, which is the same material film as the core pattern 4 on the front side of the Si substrate 9, and on the back side core material film There is a back side hard mask film formed and a back side antireflection film formed on the back side hard mask film. The back side core material film is formed simultaneously with the core pattern 4 on the front side of the Si substrate 9, the back side hard mask film is formed simultaneously with the CHM film 3 on the front side of the Si substrate 9, and the back side antireflection film is formed on the Si substrate 9. It is formed simultaneously with the antireflection Si film 2 on the front side.

Next, as shown in step S < _b > 4 of FIG. 7, the SiO ₂ film 10 is formed on the core pattern 4 and the Si ₃ N ₄ film 5. Specifically, as shown in FIG. 12, aminosilane gas or chlorosilane gas and H ₂ O gas are alternately supplied in a low temperature, for example, 0 to 400 ° C., preferably 0 to 100 ° C., and in a low pressure (for example, 399 Pa) atmosphere. Thus, the SiO ₂ film 10 is deposited and formed. When supplying aminosilane gas and H ₂ O gas, pyridine is simultaneously supplied as a catalyst to each. Also, inserting a N ₂ purge of the processing space between the alternate supply, that is, when switching the alternating supply gas, performs N ₂ purge.

In the SADP process, the reason why the SiO ₂ film 10 is formed at a low temperature of 100 ° C. or lower or 400 ° C. or lower is to obtain a sidewall film with a small film stress. When the film stress of the side wall film is large, the side wall remaining after the core pattern 4 is removed may be tilted or tilted.

Then, when forming the SiO ₂ film 10 on the front side of the Si substrate 9, also the rear side of the peripheral portion of the Si substrate 9, SiO ₂ film 10 is deposited to form. However, the SiO ₂ film 10 on the back side of the peripheral portion of the Si substrate 9 is removed in step S5 of FIG.

Next, as shown in step S5 of FIG. 7, the SiO ₂ film 10 is processed to form sidewalls. Specifically, as shown in FIG. 13, the SiO ₂ film 10 is processed by a known dry etching process using, for example, a mixed gas of CF ₄ gas and H ₂ gas. At this time, the line width of the sidewall 10 is smaller than that of the resist pattern 1, that is, a line width less than the resolution limit. Thus, the sidewall film 10 remaining on the front side of the substrate is in a state of being formed with a line width less than the resolution limit dimension of lithography. At this time, even when the back side of the Si substrate 9 is supported by a flat susceptor, the mixed gas reaches at least the peripheral part on the back side of the Si substrate 9, so that it is deposited on the back side of the peripheral part of the Si substrate 9. The SiO ₂ film 10 is removed.

  Next, as shown in step S6 of FIG. 7, a process of removing the Si core pattern 4 is performed. Specifically, as shown in FIG. 14, the Si film 4 sandwiched between the sidewalls 10 is removed by dry etching without removing the sidewalls 10, that is, with the sidewalls 10 left. . This core pattern removal process is a feature of the present invention.

In the present embodiment, in the processing unit 410 shown in FIG. 3, IF7 gas is used as the etching gas for the core pattern removal processing, and the etching processing is performed under the following processing conditions C1. The processing condition C1 is that the substrate temperature is in the range of room temperature (here 30 ° C.) to 50 ° C., preferably in the range of room temperature to 40 ° C., the pressure in the processing chamber 445 is in the range of 100 Pa to 1000 Pa, preferably in the range of 200 to 500 Pa, IF7 The gas flow rate is in the range of 0.5 slm to 4 slm, preferably in the range of 0.5 slm to 1 slm, and the flow rate of the N ₂ gas as the carrier gas is in the range of 0 slm to 1 slm. Further, the time for supplying the IF ₇ gas may be a time when the Si film 4 can be removed. Even if the etching time is somewhat increased, there is no concern about over-etching because of the selectivity specific to the IF ₇ gas, and because it depends on the film thickness of the etching target film 4, it is not limited here.

When IF ₇ gas is used, the etching rate of Si is improved by carrying out at 50 ° C. or lower, and it becomes possible to secure a high selection ratio with the Si ₃ N ₄ film 5 that is the base. Moreover, when it is 40 degrees C or less, a still higher selection ratio is securable. Moreover, when the pressure is 100 Pa to 1000 Pa, a high selection ratio can be secured, and when the pressure is 200 to 500 Pa, a further high selection ratio can be secured. Further, when the flow rate of the IF ₇ gas is 0.5 slm to 4 slm, a high selection ratio can be secured, and when it is 0.5 slm to 1 slm, a further high selection ratio can be secured. Furthermore, in order to ensure a high selection ratio, it is preferable to supply the IF ₇ gas alone without supplying any gas other than the etching gas such as the carrier gas.

In this way, the Si core pattern 4 can be etched with high selectivity with respect to the SiO ₂ film 10 as the sidewall film, and Si with high selectivity with respect to the underlying Si ₃ N ₄ film 5 as well. Can be etched. That is, Si of the core pattern 4 can be removed by highly selective etching while suppressing the etching of the SiO ₂ film 10 and the Si ₃ N ₄ film 5. At this time, by performing etching at a temperature of 50 ° C. or lower, it is possible to prevent the SiO ₂ film 10 formed at a low temperature of 100 ° C. or lower or 400 ° C. or lower from changing with temperature.

Preferably, in the core pattern removal process, (a) a first etching process that does not use plasma by IF ₇ gas, (b) a second etching process that uses plasma by, for example, O ₂ gas, and (c) by IF ₇ gas A third etching process without using plasma is performed in this order. In the present embodiment, (a) a first etching process using IF ₇ gas is performed using the processing unit 410 shown in FIG. 3, and then (b) a second etching process using O ₂ gas is performed using the processing unit 510. Then, (c) a third etching process using IF ₇ gas is performed using the processing unit 410. The processing conditions (a) and (c) are the same as the processing condition C1 described above.

(A) In the first etching process using IF ₇ gas, the Si core pattern 4 on the surface of the Si substrate 9 and the Si film 2 on the back surface are removed. The surface of the Si substrate 9 is composed of the SiO ₂ film 10 on the side wall and the underlying Si ₃ film. Only the N ₄ film 5 is provided. Next, (b) the CHM film 3 on the back surface is removed by plasma treatment (second etching treatment) using O ₂ gas. This O ₂ plasma treatment is performed under the condition that there is no oxidizing power enough to oxidize the surface of the underlying Si ₃ N ₄ film 5. This condition of no oxidizing power can be realized by, for example, reducing the low pressure and the O ₂ gas flow rate. Therefore, the CHM film 3 on the back surface of the Si substrate 9 is removed without causing a reaction on the surface of the Si substrate 9. (C) In the third etching process using the IF ₇ gas, the Si film 4 under the CHM film 3 on the back surface of the Si substrate 9 is removed. As described above, the IF ₇ gas can remove the Si film 4 on the back surface of the Si substrate 9 while suppressing the etching of the SiO ₂ film 10 and the Si ₃ N ₄ film 5 with high selectivity. On the other hand, in (b) plasma treatment with O ₂ gas, the SiO ₂ film 10 on the side wall of the Si substrate 9 may be cured (hardened). In such a case, the SiO ₂ film 10 on the side wall of the Si substrate 9 is modified by O ₂ plasma treatment, and the dry etching resistance is improved.

  In this way, as shown in FIG. 15, in parallel with the removal of the Si core pattern 4 on the front side of the substrate, the laminated film of the Si film 2, the CHM film 3 and the Si film 4 can be removed on the back side of the substrate. it can. At least, the Si film 4 deposited on the substrate rear side at the time of forming the substrate front side of the Si core pattern 4 can be removed. Specifically, the process (a), removing the substrate back side of the Si film 2 (the back side antireflective film), by treatment (b), removing the CHM film 3 of the substrate rear side (back side hard mask layer), the process (c ), The film made of the same material as the Si core pattern 4 on the front side of the substrate (back side core material film) can be removed. Thus, in the process of removing the Si core pattern 4, and the back reflection preventing film and the back hard mask layer and the core material film is removed.

As described above, the CHM film 3 that is an amorphous carbon film is particularly vulnerable to a high temperature annealing process, an oxidation process, and an O ₂ asher process performed in a subsequent process after the substrate processing process. In order to suppress particles caused by film peeling, it is necessary to remove the particles. Since the Si film 2 or the Si film 4 is a conductive film, it may cause a problem when it becomes particles, and thus needs to be removed. In addition, the back side of the substrate is preferably covered with an insulating film because contamination occurs in the Si substrate when Si is exposed. Therefore, the films 5 to 8 on the back side of the substrate are left.

Next, as shown in step S7 of FIG. 7, the underlying Si ₃ N ₄ film 5 is processed using the SiO ₂ film 10 as a side wall as a mask. Specifically, as shown in FIG. 16, for example, the Si ₃ N ₄ film 5 is processed by a known dry etching process using Cl ₂ gas, and the pattern of the Si ₃ N ₄ film 5 is formed with the same line width as that of the sidewall. Form.

Next, as shown in step S8 of FIG. 7, the underlying SiO ₂ film 6 is processed using the patterned Si ₃ N ₄ film 5 as a mask. Specifically, as shown in FIG. 17, for example, the SiO ₂ film 6 is processed by a known dry etching process using a mixed gas of CF ₄ gas and H ₂ gas, and the pattern of the SiO ₂ film 6 is changed to Si ₃ N _4. It is formed with the same line width as the film 5.

Next, as shown in step S9 in FIG. 7, the underlying Si ₃ N ₄ film 7 is processed using the patterned SiO ₂ film 6 as a mask. Specifically, as shown in FIG. 18, the Si ₃ N ₄ film 7 is processed by a known dry etching process using, for example, Cl ₂ gas, and the pattern of the Si ₃ N ₄ film 7 is the same line as the SiO ₂ film 6. Form with width.

Next, as shown in step S10 in FIG. 7, the lower SiO ₂ film 8 and the Si substrate 9 are processed using the patterned SiO ₂ film 6 as a mask. Specifically, as shown in FIG. 19, by a known dry etching process using a mixed gas of Cl ₂ gas, or Cl ₂ gas and CFH ₃ gas, processing the SiO ₂ film 8 and the Si substrate 9, SiO ₂ The pattern of the film 8 and the Si substrate 9 is formed with the same line width as that of the SiO ₂ film 6. As a result, a Si line pattern or space pattern having a line width less than the lithography resolution limit dimension is formed.

In this example, as shown in FIG. 19, the patterned SiO ₂ film 6, Si ₃ N ₄ film 7, and SiO ₂ film 8 remain on the pattern of the Si substrate 9 in which the groove 21 is formed. Since the SiO ₂ film 6 can secure the highest etching selectivity with Si, it remains on the surface as a mask when the groove 21 of the Si substrate 9 is processed. As described above, the Si ₃ N ₄ film 7 is a CMP process in which the groove 21 of the Si substrate 9 is filled with an oxide film and then the surface is flattened in the post process after the substrate processing of the present embodiment. Stopper film. As described above, the SiO ₂ film 8 is intended to protect the surface of the Si substrate 9 when the Si ₃ N ₄ film 7 is removed with hot phosphoric acid.

(3) Substrate processing method in substrate processing apparatus of this embodiment Next, an example of the substrate processing process in the substrate processing apparatus 20 of this embodiment is demonstrated below. In this substrate processing step, the above-described core pattern removal step S6 is performed, and the core pattern removal step S6 is performed using the first processing unit 410 and the second processing unit 510. This substrate processing step is performed as one step of a semiconductor manufacturing step for manufacturing a semiconductor device on a substrate, for example. In this substrate processing step, the operation of each component of the substrate processing apparatus 20 is controlled by the controller 600. S21 to S80 described below are referred to as substrate processing steps in the substrate processing apparatus 20 of the present embodiment.

In (initial coolant flow rate control step S21) the first processing unit 410, the coolant flow rate control unit 486 controls the coolant supply unit 491, the coolant is adjusted to a preset flow rate and temperature, external The susceptor coolant channel 489a, the susceptor coolant channel 464, and the external susceptor coolant channel 489b are circulated in the direction of the arrow 489c.

(Initial Heater Temperature Adjustment Step S22) In the first processing unit 410, the heater temperature control unit 485 supplies the preset initial power to the heater 463, and the heater 463 generates heat so that the susceptor table 411 has a desired temperature. Let Also in the second processing unit 510, the heater temperature control unit of the second processing unit 510 performs the same control as the heater temperature control unit 485 of the first processing unit 410.

(Susceptor Temperature Detection Step S23) After the initial coolant flow rate control step S21 and the initial heater temperature adjustment step S22, the temperature detection unit 488 of the first processing unit 410 detects the temperature of the susceptor 459. Also in the second processing unit 510, the temperature detection unit of the second processing unit 510 detects the temperature of the susceptor 559. Information on the detected susceptor temperature is input to the controller 600.

(Susceptor temperature determination step S24) the controller 600, if the detected temperature data (temperature of the susceptor 459 and the susceptor 559) is determined to be the temperature at a predetermined range, i.e., when "Yes", the next substrate mounting to migrate to the location process S31.

  When the detected temperature data is information different from the predetermined temperature range, that is, when it is “No”, the initial coolant flow rate control step S21 and the initial heater temperature adjustment step until the temperature reaches a predetermined temperature. S22 and the subsequent susceptor temperature detection step S23 are repeated.

  S21 to S24 are preparatory steps before the wafer is processed. Here, S21 to S24 are called initial steps.

(First process step) Next, it consists of the following S31 to S40, performing a first process step comprising a first etching step S32.

(Wafer Placement Step S31) After the susceptor temperature falls within a predetermined temperature range, the vacuum transfer robot 320 transfers the wafer 60 to the processing chamber 445. Specifically, the finger 321 of the vacuum transfer robot 320 on which the wafer 60 is mounted enters the processing chamber 445, and the finger 321 places the wafer 60 on the lifter pin 413 that has been raised. When the lifter pins 413 on which the wafer 60 is placed are lowered, the wafer 60 is placed on the susceptor table 411. The wafer 60 is subjected to the above-described steps S1 to S5. On the front side of the wafer 60, a core pattern and sidewalls are formed as shown in FIG. On the back side of the wafer 60, as shown in FIG. 9, SiO ₂ film 8, Si ₃ N ₄ film 7, SiO ₂ film 6, Si ₃ N ₄ film 5, amorphous Si film 4, CHM film 3, Si film 2 Is formed. Also in the second embodiment described later, the silicon hard mask 4 is formed on the multilayer hard mask 25 on the front side of the wafer 60 as shown in FIG. On the back side of the wafer 60, the silicon hard mask 4 is formed on the multilayer hard mask 25, the carbon film 3 is formed on the silicon hard mask 4, and the silicon antireflection film 2 is formed on the carbon film 3. ing.

(First Etching Process Step S32) When the wafer 60 subjected to steps S1 to S5 is placed on the susceptor table 411, the wafer 60 is heated and maintained in a predetermined temperature range described later by the temperature control unit. Is done. Here, the predetermined temperature range refers to a temperature range in which high selectivity can be maintained without the etching gas obtaining strong external energy (for example, high frequency power). For example, in the case of iodine heptafluoride, it is 30 ° C. or higher and 50 ° C. or lower, preferably 30 ° C. or higher and 40 ° C. or lower. At this time, the lower limit of the temperature is determined in consideration of, for example, temperature controllability and the temperature at which the gas does not liquefy.

  Note that “high selectivity” means, for example, that the etching rate of a first film (for example, a silicon film) containing silicon as a main component is smaller than that of the first film (for example, a silicon oxide film or silicon). It means higher than the second film which is an oxynitride film or a silicon nitride film. Even better, it refers to etching the first film without etching the second film. By doing so, the core pattern 4 can be etched while suppressing the etching of the sidewalls.

Next, the second gas supply unit 483 is controlled to supply nitrogen gas as a dilution gas into the processing chamber 445. At the same time, the first gas supply unit 482 is controlled to supply the etching gas (IF ₇ gas) from the gas inlet 433 into the processing chamber 445. The supplied etching gas collides with the plate portion 484a of the shower plate 484, and is supplied to the wafer 60 in a diffused state through the hole portion 484b. By diffusing, the gas is uniformly supplied onto the wafer 60, so that the inside of the wafer can be uniformly etched.

At this time, in the first gas supply unit 482, the flow rate of the IF ₇ gas from the first gas source 482b is set to a predetermined gas flow rate of 0.5 slm to 4 slm, preferably 1 slm. The flow rate of N ₂ gas (carrier gas) from the inert gas source 482f is set to a predetermined gas flow rate from 0 slm to 1 slm. The flow rate of N ₂ gas (dilution gas) from the second gas supply unit 483 is set to a predetermined gas flow rate, preferably 0.5 slm, of 0.1 slm to 3 slm. The pressure in the processing chamber 445 is set to a predetermined pressure, preferably 200 Pa to 500 Pa, for example, from 100 Pa to 1000 Pa.

  By the way, the etching gas has a property of generating heat when it reacts with the silicon film. The generated reaction heat is conducted to the metal film or the substrate by heat conduction, and as a result, the characteristic deterioration of the metal film or the warpage of the substrate may occur. Furthermore, it is conceivable that the temperature of the wafer 60 deviates from a predetermined temperature range and the etching gas loses high selectivity.

  Since the etching gas concentration and the etching rate are in a proportional relationship, and the etching rate and the reaction heat amount are in a proportional relationship, the above phenomenon becomes more prominent when the etching rate is increased by increasing the etching gas concentration. .

  Therefore, by supplying a dilution gas together with the etching gas to the processing chamber 445, the concentration of the etching gas is reduced, and an excessive temperature rise due to reaction heat is suppressed. The supply amount of the dilution gas is preferably larger than the supply amount of the etching gas, for example.

  Although the supply of the dilution gas and the etching gas is started almost simultaneously here, the present invention is not limited to this, and it is better to supply the etching gas after supplying the dilution gas. In this case, the etching gas is preferably a gas that contains a material heavier than the dilution gas, such as halogen, and can be etched without obtaining strong energy from the outside. If a halogen-containing gas and a dilution gas are supplied simultaneously, the halogen-containing gas reaches the substrate before the dilution gas. That is, the etching gas having a high concentration reaches the substrate before the dilution gas. In this case, since the etching is performed rapidly, it is conceivable that the temperature is rapidly increased and high etching selectivity is lost. In order to prevent this, it is desirable to supply the etching gas after supplying the dilution gas.

  More preferably, the etching gas is supplied after the pressure in the processing chamber is stabilized in a state where the processing chamber is filled with the diluted gas atmosphere. This is a case where the amount of dilution gas is sufficiently larger than the amount of etching gas, and is effective, for example, in a process for controlling the etching depth. Since etching is performed in a state where the pressure is stable, the etching rate can be stabilized. As a result, the etching depth can be easily controlled.

  Furthermore, in the present embodiment, while the etching gas is in contact with the wafer, the wafer 60 is maintained in a desired temperature range, thereby maintaining a high etching rate, preventing deterioration of the characteristics of the film constituting the substrate, and warping of the substrate. Either preventing, maintaining high etch selectivity, or any combination thereof is achieved simultaneously.

(Wafer Temperature Detection Step S33) As described above, while the etching gas is in contact with the wafer 60, the wafer 60 is heated by the reaction heat. Here, the temperature detector 488 detects the temperature of the wafer 60 heated by the reaction heat.

(Wafer Temperature Determination Step S34) The temperature data detected in the wafer temperature detection step S33 is input to the controller 600. The controller 600 determines whether the temperature data is within a predetermined temperature range. If the temperature is within the predetermined temperature range, that is, if “Yes”, the process proceeds to the heater / coolant control maintaining step of S37. If the detected temperature data is not within the desired temperature range, that is, “No”, the process proceeds to a step (S35, S36) of adjusting the temperature control unit so that the wafer temperature becomes the desired temperature.

(Heater Temperature Adjustment Step S35) If it is determined in the wafer temperature determination step S34 that the wafer temperature is not within the predetermined temperature range, the heater temperature control unit 485 controls the amount of power supplied to the heater 463. In the case of this embodiment, the temperature of the wafer 60 rises to a temperature higher than the upper limit value of the predetermined temperature range due to the reaction heat, so that the temperature of the heater 463 is lowered to maintain the predetermined temperature.

(Coolant Flow Rate Adjustment Step S36) If it is determined that the wafer temperature is not within the predetermined temperature range, the coolant flow rate control unit 486 controls the flow rate and temperature of the coolant. In the case of this embodiment, the temperature of the wafer 60 rises to a temperature higher than the upper limit value of the predetermined temperature range due to the reaction heat, so that the coolant flow rate is increased or the coolant temperature is maintained in order to maintain the predetermined temperature Reduce. By doing so, the cooling efficiency of the wafer 60 is increased.

  By controlling the heater 463 and the coolant flow rate as in the heater temperature adjustment step S35 and the coolant flow rate adjustment step S36, the wafer 60 is adjusted to be in a predetermined temperature range. After the adjustment, the process proceeds to the wafer temperature detection step S33. Thus, S33 to S36 are repeated until the wafer 60 reaches a predetermined temperature range.

  In the present embodiment, the coolant flow rate adjustment step S36 is performed after the heater temperature adjustment step S35, but is not limited thereto. For example, the coolant flow rate adjustment step S36 may be performed after the wafer temperature determination step S34, and then the heater temperature adjustment step S35 may be performed. Alternatively, the coolant flow rate adjustment step S36 and the heater temperature adjustment step S35 may be performed in parallel after the wafer temperature determination step S34.

  In the present embodiment, in order to lower the temperature of the wafer 60, lowers the temperature of the heater 463 has been controlled to increase the flow rate of the coolant is not limited to, control of the heater 463 and by cooperation of the control of the coolant flow rate, resulting in a temperature of the wafer 60 may be controlled to be within a predetermined temperature range decreases.

  Further, when the temperature of the wafer 60 becomes lower than the lower limit value of the predetermined temperature range, the temperature of the wafer 60 is increased as a result by cooperation of the control of the heater 463 and the control of the coolant flow rate. Just control.

(Heater / coolant control maintaining step S37) If the wafer temperature is determined to be within the predetermined temperature range in the wafer temperature determining step S34, the heater control and the coolant flow rate control are maintained in order to maintain the wafer temperature. to maintain the temperature of the wafer 60.

(Processing Time Determination Step S38) It is determined whether or not the etching processing time in S32 has elapsed, that is, whether or not the first etching processing for the wafer 60 has been completed. If it is determined that the predetermined time has passed, that is, if “Yes”, the process proceeds to S39. If it is determined that the predetermined time has not elapsed, that is, if “No”, the process returns to S32 to continue the etching process.

  At the stage where the first etching process is completed, the entire Si film 4 of the core pattern is removed on the front side of the wafer 60, and the Si film 2 is removed on the back side of the wafer 60 by the first etching process. . It is also possible to remove at least a part of the core pattern Si film 4 in the first etching process and remove the remainder of the core pattern Si film 4 in the second etching process described later. Also in the second embodiment to be described later, all of the silicon hard mask 4 is removed on the front side of the wafer 60, and the silicon antireflection film 2 is removed on the back side of the wafer 60 by the first etching process. . It is also possible to remove at least a part of the silicon hard mask 4 in the first etching process and remove the remainder of the silicon hard mask 4 in the third etching process described later.

(Gas Supply Stopping Step S39) When it is determined in the processing time determining step S38 that a predetermined time has elapsed, the first gas supply unit 482 is controlled to stop the supply of the etching gas. After stopping the supply of the etching gas, the purge gas supply system of the first gas supply unit 482 is controlled to discharge the residual gas from the gas supply pipe 482a so that the etching gas does not remain in the processing chamber 445. The gas supply unit 483 is controlled to supply an inert gas into the processing chamber 445, and the atmosphere in the processing chamber 445 is discharged. Thus, the atmosphere in the processing chamber 445 is replaced with an inert gas.

(Wafer Unloading Step S40) After the atmosphere in the processing chamber 445 is replaced with an inert gas, the vacuum transfer robot 320 transfers the wafer 60 from the processing chamber 445 to the transfer module in the reverse procedure of placing the wafer 60. Carry out to 310.

(Second process step) Next, it consists of the following S51～S59, executing the second processing step including the second etching step S52.

(Wafer Placement Step S51) Following the wafer unloading step S40, the vacuum transfer robot 320 transfers the wafer 60 to the processing chamber 545 of the second processing unit 510. Specifically, the finger 321 loaded with the wafer 60 enters the processing chamber 545, and the finger 321 places the wafer 60 on the lifter pins 513 raised. By lifter pins 513 wafer 60 is placed is lowered, the wafer 60 is placed on the susceptor table 511.

(Second Etching Process Step S52) When the wafer 60 is placed on the susceptor table 511, the wafer 60 is heated and maintained in a predetermined temperature range by the temperature controller. Here, the predetermined temperature range is 0 ° C. or higher and 200 ° C. or lower.

Next, the third gas supply unit 582 is controlled to supply O ₂ gas, which is a processing gas, from the gas inlet 533 into the processing chamber 545. The supplied O ₂ gas is introduced into the plasma generation chamber 530 through the baffle plate 584 in a diffused state. Then, the O ₂ gas activated in the plasma generation chamber 530 is supplied to the wafer 60 on the susceptor table 511. The O ₂ gas flow rate from the third gas supply unit 582 is set to 0.25 slm, for example. The pressure in the processing chamber 545 is set to 200 Pa, for example.

(Wafer Temperature Detection Step S53) The temperature detection unit disposed in the susceptor 599 detects the temperature of the wafer 60.

(Wafer Temperature Determination Step S54) The temperature data detected in the wafer temperature detection step S53 is input to the controller 600. The controller 600 determines whether the temperature data is within a predetermined temperature range. If the temperature is within the predetermined temperature range, that is, if “Yes”, the process proceeds to the heater control maintaining step of S56. If the detected temperature data is not within the desired temperature range, that is, if “No”, the process proceeds to the heater temperature adjustment step S55 so that the wafer temperature becomes the desired temperature.

(Heater Temperature Adjustment Step S55) In the heater temperature adjustment step S55, the controller 600 controls the amount of power supplied to the heater 563 so that the wafer 60 is in a predetermined temperature range. Thus, S53 to S55 are repeated until the wafer 60 reaches a predetermined temperature range.

(Heater Control Maintenance Step S56) If the wafer temperature is determined to be within a predetermined temperature range in the wafer temperature determination step S54, the temperature control to the heater 563 is maintained to maintain the temperature, and the temperature of the wafer 60 is maintained. To do.

(Processing Time Determination Step S57) It is determined whether or not the etching processing time of S52 has elapsed, that is, whether or not the etching processing of the wafer 60 has been completed. If it is determined that the predetermined time has elapsed, that is, if “Yes”, the process proceeds to S58. If it is determined that the predetermined time has not elapsed, that is, if “No”, the process returns to S52 to continue the etching process. At the stage where the etching process of S52 is completed, the CHM film 3 is removed by the etching process on the back side of the wafer 60. On the other hand, the O ₂ gas supplied in S52 is supplied under processing conditions that do not oxidize the surface of the Si ₃ N ₄ film 5 on the front side of the wafer 60, and no reaction occurs on the surface of the Si ₃ N ₄ film 5. . However, the Si film 10 as the sidewall may be hardened (hardened) by the activated O ₂ gas. Also in the second embodiment to be described later, the carbon film 3 is removed by the etching process on the back side of the wafer 60 when the etching process of S52 is completed. On the other hand, the O ₂ gas supplied in S52 is supplied under processing conditions that do not oxidize the surface of the underlying multilayer hard mask 5 on the front side of the wafer 60, and no reaction occurs on the surface of the multilayer hard mask 5.

(Gas Supply Stopping Step S58) If it is determined in the processing time determining step S57 that the predetermined time has elapsed, the third gas supply unit 582 is controlled to stop the supply of the processing gas, and from the high frequency power source 525 to the resonance coil. to stop the power supply to the 521. After the supply of the processing gas is stopped, the third gas supply unit 582 is controlled so that the processing gas does not remain in the processing chamber 545, and the inert gas is supplied from the inert gas source 582f into the processing chamber 545. Then, the atmosphere in the processing chamber 545 is discharged. Thus, the atmosphere in the processing chamber 545 is replaced with an inert gas.

(Wafer Unloading Step S59) After the atmosphere in the processing chamber 545 is replaced with an inert gas, the vacuum transfer robot 320 transfers the wafer 60 from the processing chamber 545 to the transfer module in the reverse procedure of placing the wafer 60. It is carried out to the 310.

(Third process step) Next, it consists of the following S71～S80, implementing the third processing step including the third etching step S72.

(Wafer Placement Step S71) Following the wafer unloading step S59, the vacuum transfer robot 320 transfers the wafer 60 to the processing chamber 445. Then, the wafer 60 is placed on the susceptor table 411 in the same manner as in the first processing step.

(Third Etching Process Step S72) When the wafer 60 is placed on the susceptor table 411, the wafer 60 is heated and maintained in a predetermined temperature range by the temperature control unit. Here, the predetermined temperature range is the same as the temperature range during the first etching process described above.

Next, the second gas supply unit 483 is controlled to supply nitrogen gas as a dilution gas into the processing chamber 445. At the same time, the first gas supply unit 482 is controlled to supply IF ₇ gas as an etching gas into the processing chamber 445 from the gas inlet 433. The supplied etching gas is supplied to the wafer 60 in a diffused state via the shower plate 484.

IF ₇ gas flow rate from the first gas source 482b in the first gas supply unit 482, the flow rate of _{N 2} gas from the inert gas source 482f (carrier gas), the _{N 2} gas from the second gas supply unit 483 The flow rate of the (dilution gas) and the pressure in the processing chamber 445 are set in the same manner as in the first etching processing step S32 described above.

(Wafer Temperature Detection Step S73) The temperature detection unit 488 detects the temperature of the wafer 60.

(Wafer Temperature Determination Step S74) The temperature data detected in the wafer temperature detection step S33 is input to the controller 600. The controller 600 determines whether the temperature data is within a predetermined temperature range. If it is within the predetermined temperature range, that is, if “Yes”, the routine proceeds to the heater / coolant control maintaining step of S77. If the detected temperature data is not in the desired temperature range, that is, if “No”, the process proceeds to steps (S75, S76) for adjusting the temperature control unit so that the wafer temperature becomes the desired temperature.

At (heater temperature adjusting step S75) wafer temperature determining step S74, When the wafer temperature is determined not to be the predetermined temperature range, the heater temperature control unit 485, as in the case of the first process described above, the heater 463 Control the amount of power supply.

(Coolant Flow Rate Adjusting Step S76) If it is determined that the wafer temperature is not within the predetermined temperature range, the coolant flow rate control unit 486 controls the flow rate and temperature of the coolant as in the first process described above. .

  By controlling the heater 463 and the coolant flow rate as in the heater temperature adjustment step S75 and the coolant flow rate adjustment step S76, the wafer 60 is adjusted to be in a predetermined temperature range. After the adjustment, the process proceeds to the wafer temperature detection step S73. Thus, S73 to S76 are repeated until the wafer 60 reaches a predetermined temperature range.

(Heater / coolant control maintaining step S77) If the wafer temperature is determined to be within the predetermined temperature range in the wafer temperature determining step S74, the heater control and the coolant flow rate control are maintained in order to maintain the wafer temperature. The temperature of the wafer 60 is maintained.

(Processing Time Determination Step S78) It is determined whether or not the third etching processing time in S72 has passed a predetermined time. If it is determined that the predetermined time has passed, that is, if “Yes”, the process proceeds to S79. If it is determined that the predetermined time has not elapsed, that is, if “No”, the process returns to S72 to continue the etching process. At the stage where the third etching process is completed, the Si film 4 of the core pattern is removed on the front side of the wafer 60, and the amorphous Si film 4 is removed on the back side of the wafer 60 by the third etching process. ing.

(Gas Supply Stopping Step S79) If it is determined in the processing time determination step S78 that the predetermined time has elapsed, it is determined that the etching process of the wafer 60 has ended, and the first gas supply unit 482 is controlled to control the etching gas. Stop supplying. After stopping the supply of the etching gas, the purge gas supply system of the first gas supply unit 482 is controlled to discharge the residual gas from the gas supply pipe 482a so that the etching gas does not remain in the processing chamber 445. The gas supply unit 483 is controlled to supply an inert gas into the processing chamber 445, and the atmosphere in the processing chamber 445 is discharged. Thus, the atmosphere in the processing chamber 445 is replaced with an inert gas.

(Wafer Unloading Step S80) After the atmosphere in the processing chamber 445 is replaced with an inert gas, the vacuum transfer robot 320 transfers the wafer 60 in the processing chamber 445 in the reverse order of the placement of the wafer 60. Carry out into module 310. Subsequently, the vacuum transfer robot 320 transfers the wafer 60 in the transfer module 310 to the buffer unit 210 of the load lock chamber unit 200, and then the atmospheric transfer robot 130 loads the wafer 60 in the buffer unit 210. Transport to FOUP 110 on port 120.

(Effect of this embodiment) The effect acquired by embodiment described above is an effect of at least 1 or more among the effects described in (1)-(4) below. (1) In the core pattern removal step, the Si core pattern is etched with a high selectivity with respect to the silicon oxide film (SiO ₂ film) and the silicon nitride film (Si ₃ N ₄ film) which are films other than the Si core pattern. can do. Specifically, the Si core pattern 4 can be etched with high selectivity with respect to the SiO ₂ film 10 as the sidewall film and the underlying Si ₃ N ₄ film 5. (2) In the core pattern removal step, the first etching process without using the plasma, the second etching process using the plasma, and the third etching process without using the plasma are performed in this order, so that the substrate backside is formed. The formed Si core pattern film, CHM film, and Si antireflection film can be removed. Thereby, generation | occurrence | production of the particle resulting from Si core pattern film | membrane, CHM film | membrane, and Si antireflection film | membrane formed into a film by the back side of a board | substrate can be suppressed. (3) Since the substrate temperature of the first and third etching processes is set to 30 to 50 ° C., the Si core pattern 4 can be etched with high selectivity. Further, since the temperature is preferably set to 40 to 50 ° C., the Si core pattern 4 can be etched more selectively. (4) In the second etching process using plasma, since the silicon nitride film (Si ₃ N ₄ film) is not oxidized, only the CHM film 3 on the back surface of the substrate can be removed. Preferably, conditions for curing (hardening) the silicon oxide film (SiO ₂ film) are preferable. In this case, the dry etching resistance is improved by modifying the SiO ₂ film 10 which is a sidewall film by plasma.

(2nd Embodiment) Next, the example of the substrate processing process in which the substrate processing method which concerns on this embodiment (2nd Embodiment) is implemented is demonstrated below using FIGS. This substrate processing step is performed as a step of forming a fine pattern and a step of manufacturing a semiconductor device. FIG. 23 to FIG. 27 are diagrams for explaining the fine pattern forming process in the second embodiment of the present invention, and show, for example, a process of producing a fine pattern using immersion ArF lithography and dry etching. FIG. The process of FIG. 27 (silicon hard mask removal process) is a characteristic part of the present invention, and shows an example of a process of performing gas etching with high selectivity to silicon, that is, a high etching rate. In the substrate processing apparatus 20 of the present embodiment, at least the process of FIG. 27 is performed. The substrate processing method according to this embodiment is the same as that of the first example. Therefore, the description of the second embodiment with reference to FIGS. 9A to 9C is omitted.

  In FIG. 23, on the front side of the substrate, a carbon film 3 is formed on the silicon hard mask 4, a silicon antireflection film 2 is formed on the carbon film 3, and a resist 1 is applied on the silicon antireflection film 2. FIG. 6 is a diagram showing a slimming process after patterning a resist 1 using immersion ArF lithography and dry etching. Specifically, as shown in FIG. 23, a patterned layer 26, a multilayer hard mask 25, a silicon hard mask 4 as an etching target film, a carbon film 3, and a silicon antireflection film 2 are laminated in this order on the front side of the silicon substrate. To form a film. And after apply | coating a photoresist on this, it exposes by lithography technique and develops after that, The pattern of the resist 1 processed into the predetermined line width is formed.

  When the silicon hard mask 4, the carbon film 3, and the silicon antireflection film 2 are laminated on the front side of the silicon substrate, the silicon hard mask 4, the carbon film 3, and the silicon antireflection film 2 are laminated in this order also on the back side of the silicon substrate. Is done. Even when the back side of the silicon substrate is supported by a flat susceptor, the laminated films 4 to 2 are formed at least on the periphery of the back side of the silicon substrate. Since these laminated films 4 and 2 are fragile films that are relatively easily peeled off, they may peel off and cause particles in a process performed after the substrate processing process, which is not preferable. Therefore, it is necessary to remove the laminated films 4 and 2.

  The silicon hard mask 4 has a film thickness of about 40 to 60 nm and is formed on the multilayer hard mask 25 by a CVD method at a temperature of 400 to 550 ° C., for example. The carbon film 3 is, for example, a CVD carbon film (carbon-containing film formed by a CVD method) or a spin-on carbon film, and has a film thickness of about 100 to 500 nm. For example, the carbon film 3 is formed by a CVD method at a temperature of 200 to 550 ° C. It is deposited on top of the hard mask 4. Silicon antireflection film 2, a thickness of approximately 2 to 10 nm, for example, by a CVD method at a temperature 400 to 550 ° C., is deposited on the carbon film 3. The silicon antireflection film 2 functions as an antireflection film at the time of exposure by lithography.

In this example, in order to process the film to be patterned 26, for example, a silicon hard mask 4 is used. Therefore, the silicon hard mask 4 is formed under the carbon film 3. Under the silicon hard mask 4, a multilayer hard mask 25 composed of a plurality of hard masks is formed. As the multilayer hard mask 25, for example, a SiO ₂ film, a Si ₃ N ₄ film, a TiN film, or the like is used. The silicon content of the silicon hard mask 4 and the silicon antireflection film 2 is larger than the silicon content of the carbon film 3 and the multilayer hard mask 25.

  The film thickness of the silicon antireflection film 2 may be the same as the film thickness of the silicon hard mask 4 (for example, about 40 nm). In this way, over-etching can be suppressed when the resist 1 is patterned. The film thickness of the carbon film 3 may be the same as the film thickness of the multilayer hard mask 25 (for example, about 500 nm). In this way, over-etching can be suppressed when the silicon hard mask 4 is patterned.

FIG. 24 shows a state after the silicon antireflection film 2 and the carbon film 3 are dry-etched using the patterned resist 1 as a mask. At this time, using the patterned resist 1 as a mask, the underlying silicon antireflection film 2 is processed by a known dry etching process using, for example, Cl ₂ gas, and then the carbon film 3 is processed, for example, by O ₂ gas. It processes by the well-known dry etching process using this. Thereafter, the resist 1 is removed by a known ashing process using, for example, O ₂ gas.

  Note that the etching of the silicon antireflection film 2 on the front side of the silicon substrate is anisotropic etching performed in a direction perpendicular to the surface of the silicon substrate, so that the silicon antireflection film 2 on the back side of the silicon substrate is removed. it is not.

Next, as shown in FIG. 25, the silicon film 4 which is a hard mask is patterned. Specifically, the pattern of the carbon film 3 is used as a mask, and the silicon hard mask 4 as the underlying film is processed by a known dry etching process using, for example, Cl ₂ gas or CF ₂ Cl ₂ gas. Thereafter, the carbon film 3 is removed by a known dry etching process using, for example, O ₂ gas. At this time, since the silicon antireflection film 2 on the back side of the silicon substrate is not removed, the carbon film 3 on the back side of the silicon substrate is not removed.

Next, as shown in FIG. 26, using the pattern of the silicon hard mask 4 as a mask, the underlying multilayer hard mask 25 is subjected to, for example, a known dry etching process using Cl ₂ gas or CF ₂ Cl ₂ gas. Process and pattern.

  Next, as shown in FIG. 27, the silicon hard mask 4 is removed by dry etching. In the removal process of the silicon hard mask 4, it is required to completely remove only the silicon film 4 without removing the multilayer hard mask 25. This is because the shape of the multilayer hard mask 25 affects the final processing of the layer to be patterned 26. In this step, gas etching using a gas having a high etching rate is performed on silicon (that is, silicon hard mask 4), and a silicon film is etched without etching a film other than silicon (that is, multilayer hard mask 25). Only the silicon hard mask 4 is removed.

In the present embodiment, IF ₇ gas is used as an etching gas for the removal process of the silicon hard mask 4 in the processing unit 410 shown in FIG. The processing conditions different from those in Example 1 are only the time for supplying the IF ₇ gas, and the other processing conditions such as the substrate temperature, the processing chamber pressure, the IF ₇ gas flow rate, and the carrier gas flow rate are the same. I will omit it. The time for supplying the IF ₇ gas may be a time for removing the silicon hard mask 4. Even if the etching time is increased, there is no concern about over-etching because there is selectivity specific to the IF ₇ gas. Therefore, it is set appropriately according to the film thickness of the silicon hard mask 4 that is the etching target film.

When IF ₇ gas is used, the etching rate of silicon is improved by performing it at 50 ° C. or less, and it becomes possible to secure a high selection ratio with the multilayer hard mask 25 which is the base. Moreover, when it is 40 degrees C or less, a still higher selection ratio is securable. Moreover, when the pressure is 100 Pa to 1000 Pa, a high selection ratio can be secured, and when the pressure is 200 to 500 Pa, a further high selection ratio can be secured. Further, when the flow rate is 0.5 slm to 4 slm, a high selection ratio can be ensured, and when the flow rate is 0.5 slm to 1 slm, a further high selection ratio can be ensured.

In this way, the substrate front side is highly selectively applied to the multilayer hard mask 25 composed of SiO ₂ film, Si ₃ N ₄ film, TiN film, etc., that is, the multilayer hard mask 25 having a silicon content lower than that of the silicon film. The state shown in FIG. 27 can be obtained by etching the silicon hard mask 4. That is, the silicon hard mask 4 on the front side of the substrate is removed by highly selective etching while suppressing the etching of the multilayer hard mask 25. At this time, by performing etching at a temperature of 50 ° C. or lower, the multilayer hard mask 25 formed of a SiO ₂ film or the like formed at a low temperature of 100 ° C. or lower or 400 ° C. or lower changes depending on the temperature. Can be prevented.

Preferably, in the removal process of the silicon hard mask 4 on the front side of the substrate, (a) a first etching process that does not use plasma by IF ₇ gas, (b) a second etching process that uses plasma by, for example, O ₂ gas, c) A third etching process using no plasma with IF ₇ gas is performed in this order in the same manner as in the first embodiment.

Also in this embodiment, (a) the first etching process using IF ₇ gas is performed using the processing unit 410 shown in FIG. 3 to remove the silicon hard mask 4 on the front side of the silicon substrate and the silicon antireflection film 2 on the back side. . Next, (b) a second etching process using O ₂ gas is performed using the processing unit 510 to remove the carbon film 3 on the back side of the silicon substrate. Thereafter, (c) a third etching process using IF ₇ gas is performed using the processing unit 410, and the silicon hard masks 4 on the front side and the back side of the silicon substrate are removed. That is, in Example 1 and Example 2, since the film deposited on the back side of the silicon substrate is the same in the silicon antireflection film 2, the carbon film 3, and the silicon hard mask 4, the processing conditions (a) and (c) are performed. These are the same as the processing conditions C1 described in detail in the first embodiment.

  In this manner, the laminated film of the silicon antireflection film 2, the carbon film 3, and the silicon hard mask 4 is removed on the back side of the substrate in parallel with the removal of the silicon hard mask 4 on the front side of the substrate, as in the first embodiment. can do. At least the silicon hard mask 4 deposited on the back side of the substrate when the silicon hard mask 4 on the front side of the substrate is formed can be removed. For more information, concurrently with the removal of the silicon hard mask 4 in the substrate front side, by the processing (a), removing the film of silicon antireflection film 2 of the same material of the substrate backside, by treatment (b), the substrate backside carbon The film of the same material as that of the film 3 is removed, and the film of the same material as that of the silicon hard mask 4 on the back side of the substrate can be removed by the process (c).

The film deposited on the back side of the silicon substrate is the silicon antireflection film 2, the carbon film 3, and the silicon hard mask 4. As in the first embodiment, the carbon film 3 is a post process after the substrate processing process. Since it is weak to the high temperature annealing process, oxidation process, and O ₂ asher process that are performed, it is necessary to remove particles in order to suppress particles due to film peeling on the back side of the substrate in a later step. Since the silicon antireflection film 2 and the silicon hard mask 4 are conductive films, they may become a problem when they become particles, and thus need to be removed.

FIG. 28 is a diagram showing a state before removing the silicon antireflection film 2, the carbon film 3, and the silicon hard mask 4 on the back side of the substrate in the second embodiment of the present invention. In the example of FIG. 28, a SiO ₂ film 27 is formed on the silicon substrate 28 by thermal oxidation or the like on the back side of the substrate. Although a multilayer hard mask may be formed on the silicon substrate 28 (example in FIG. 23), the example in FIG. 28 is a case where the SiO ₂ film 27 is formed instead of the multilayer hard mask.

  FIG. 29 is a view showing a state after removing the silicon antireflection film 2, the carbon film 3, and the silicon hard mask 4 on the back side of the substrate in the second embodiment of the present invention. As described above, the silicon hard mask 4 on the front side of the wafer is removed, and at the same time, the laminated film of the silicon film (silicon hard mask 4), the carbon film, and the silicon film (silicon antireflection film 2) is removed on the back side of the wafer. Is possible.

The effects obtained by the second embodiment described above are at least one of the effects described in (1) to (4) below. (1) In the silicon hard mask removing step, the silicon hard mask 4 can be etched with a high selectivity with respect to the multilayer hard mask 25 having a silicon content smaller than that of the silicon hard mask. (2) In the silicon hard mask removal step, the silicon hard mask film 4 and the carbon film formed on the back side of the substrate are processed in the order of the first etching process, the second etching process, and the third etching process. 3 and the silicon antireflection film 2 can be removed. (3) Since the substrate temperature of the first and third etching processes is set to 30 to 50 ° C., the silicon hard mask 4 which is the Si etching target film can be etched with high selectivity. Further, since the temperature is preferably set to 40 to 50 ° C., the silicon hard mask 4 can be etched more selectively. (4) In the second etching process using plasma, the silicon nitride film (Si ₃ N ₄ film) is treated so as not to be oxidized, so that only the carbon film 3 on the back surface of the substrate can be removed. Preferably, conditions for curing (hardening) the silicon oxide film (SiO ₂ film) are preferable.

In the above embodiment, the second processing unit that performs the plasma processing is configured to include the plasma generation chamber. However, the present invention is not limited to this, and etching processing by a remote plasma method that does not bring plasma into the processing chamber or plasma is performed. An etching process that is not used, for example, an etching process using O ₃ gas (ozone gas) may be performed.

Further, the etching process without using plasma can be performed by the first processing unit, and in this case, the second processing unit is unnecessary. In this case, IF ₇ gas is introduced into the processing chamber, an etching process using IF ₇ gas is performed, and then the processing chamber is replaced with an inert gas. Thereafter, an O ₃ gas is introduced into the processing chamber, an etching process using the O ₃ gas is performed, and then the processing chamber is replaced with an inert gas. Thereafter, an etching process using IF ₇ gas is performed. In the first embodiment, there is a case where an effect of modifying the SiO ₂ film, which is a side wall film, by O ₃ gas can be expected.

Third Example A third example of the substrate processing method according to the present embodiment will be described with reference to FIGS. 30A to 32B. FIG. 30A is a cross-sectional view of the Fin-FET transistor in the channel length direction before the etching process according to the third embodiment of the present invention, and shows a state immediately before the dummy polysilicon gate electrodes 11a and 11b are removed in the gate last process. An example is shown. After removing dummy polysilicon gate electrodes 11a and 11b, a metal gate electrode is formed. The etching process of the third embodiment uses, for example, IF ₇ gas as in the first and second embodiments. In the processing unit 410 shown in FIG. 3, the etching process is the same as in the first and second embodiments. This is performed under the processing condition C1.

  Figure 30B is before the etching process in the third embodiment of the present invention, is a cross-sectional view in the channel width direction of the Fin-FET transistor. Ranges A and B in FIG. 30B correspond to ranges A and B in FIG. 30A, respectively. A cross-sectional view taken along the line CC ′ of FIG. 30B is FIG. 30A. FIG. 30C is a three-dimensional schematic diagram of the Fin-FET transistor before the etching process in the third embodiment of the present invention.

  In FIG. 30A, 11a and 11b are dummy polysilicon electrodes. In the channel length direction (X direction in the figure) of the gate electrode, the length of the dummy polysilicon electrode 11a is about 20 nm, and the length of the dummy polysilicon electrode 11b is about 150 nm. A side wall spacer 12 is formed to support the side walls of the dummy polysilicon electrodes 11a and 11b. 13 is an etching stop layer, 14 is PMD (Pre Metal Dielectric), 15a is a gate oxide film, 16 is Si-Fin, 17 is STI (Shallow Trench Isolation), 18 is a source or drain epitaxial layer, and 19 is a silicon substrate. .

  As described above, on the front side of the substrate, dummy polysilicon gate electrodes 11a and 11b (polysilicon film), which are silicon films, are formed in the groove portion in which the gate oxide film 15a is formed on the bottom portion and the gate electrode is embedded. Is filled and formed. This groove part is a step part and is a recessed part. A plurality of grooves are provided in the channel length direction, and the lengths of the plurality of grooves in the channel length direction are different from each other.

For example, an SiO ₂ film, an HfO ₂ film, an Al ₂ O ₃ film, or the like is used for the gate oxide film 15a that is a base oxide film of the dummy polysilicon electrodes 11a and 11b. For the sidewall spacer 12, for example, a SiO ₂ film, a Si ₃ N ₄ film, a SiCN film, a SiOCN film, a SiOC film, or the like is used. The silicon content of the dummy polysilicon electrodes 11 a and 11 b is larger than the silicon content of the gate oxide film 15 a and the sidewall spacer 12.

  In the example of FIG. 30A, there are a thin dummy polysilicon gate electrode 11a with a gate length of 20 nm or less and a thick dummy polysilicon gate electrode 11b with a gate length of 150 nm or more, and it is necessary to remove both polysilicons simultaneously. In general, the etching rate varies depending on the amount of the film to be etched. Therefore, in order to simultaneously etch patterns having different widths, a polycrystal is applied to the base film and the sidewall film so that the narrow patterns are not over-etched. High selectivity for etching only silicon with high selectivity is required.

  Further, in the Fin-FET having a 3D structure, it is necessary to sufficiently etch and remove the polysilicon up to the bottom of the step portion of the Fin. That is, it is necessary to sufficiently remove the polysilicon film filled in the plurality of grooves is covered with a gate oxide film 15a. While etching up to the bottom of the Fin stepped portion, the upper portion of the Fin is not over-etched, that is, the underlying oxide film 15a and the sidewall spacer 12 above the Fin are not etched. Etching selectivity for etching only polysilicon with respect to the wall spacer 12 is very important.

FIG. 31A is a cross-sectional view in the channel length direction of the Fin-FET transistor after the etching process of the third embodiment of the present invention, and shows a state in which the dummy polysilicon electrodes 11a and 11b are removed in FIG. 30A. This etching process is performed, for example, using IF ₇ gas as in the first embodiment, and in the processing unit 410 shown in FIG. 3 under the same processing conditions C1 as in the first and second embodiments.

  Figure 31B is after the etching process of the third embodiment of the present invention, a cross-sectional view in the channel width direction of the Fin-FET transistor shows a state in which the removal of the dummy polysilicon electrode 11a in FIG. 30B. FIG. 31C is a three-dimensional schematic diagram of a Fin-FET transistor after the etching process of the third embodiment of the present invention.

  In this way, by performing gas etching having a high etching rate only on silicon, the remaining etching of the polysilicon is suppressed, and the dummy polysilicon is maintained while maintaining the shapes of the base oxide film 15a and the sidewall film 12 on the side wall. Only the gate electrodes 11a and 11b can be removed.

  Then, after removing the dummy polysilicon gate electrodes 11a and 11b, the plurality of groove portions are filled with a metal-containing film by a known film forming process, and a metal gate is formed.

FIG. 32A is a diagram showing a state before removing the polysilicon film on the back side of the substrate in the third embodiment of the present invention. The outermost polysilicon (Poly-Si) film 11c on the back side of the substrate is a polysilicon film formed simultaneously with the formation of the dummy polysilicon gate electrodes 11a and 11b on the front side of the substrate. The underlying oxide film 15b is an oxide (SiO ₂ ) film formed simultaneously with the formation of the gate oxide film 15a on the front side of the substrate. Thus, on the back side of the substrate, a polysilicon film 11c made of the same material as the polysilicon films 11a and 11b on the front side of the substrate and an oxide film 15b made of the same material as the gate oxide film 15a on the front side of the substrate are formed. Hereinafter, the polysilicon films 11a, 11b, and 11c, which are etching target films, may be simply referred to as the polysilicon film 11.

The SiN film 29 under the oxide film 15b and the SiO ₂ film 10 in contact with the silicon substrate 19 are formed on the substrate surface side in a general STI formation process performed at an early stage of the CMOS process. It is also formed on the back side. The SiN film 29 is a film serving as a hard mask when the silicon substrate 19 is dry-etched to form a trench for filling the STI, and a stopper when the buried oxide film (STI 17 in FIG. 11A) is planarized by CMP. It is a film. The SiO ₂ film 10 in contact with the silicon substrate 19 is a film formed on the back side of the substrate when the surface of the silicon substrate 19 is oxidized before the SiN film 29 is formed.

  FIG. 32B is a diagram showing a state after the polysilicon film on the back side of the substrate is removed in the third embodiment of the present invention. Thus, in the third embodiment, the polysilicon 11a and 11b on the front side of the substrate are removed by etching with a gas having high etching selectivity with respect to silicon, and at the same time, the polysilicon film 11c is formed on the back side of the substrate. It is possible to remove.

  For example, when a part of the back side of the substrate is supported by a boat column like a vertical apparatus, as shown in FIG. 32A, when forming a polysilicon film on the front side of the substrate, the film forming gas wraps around the back side of the substrate, A polysilicon film may also be formed on the back side of the substrate. Also in the case of a single wafer apparatus, there is a case where a film forming gas wraps around the back side peripheral portion of the substrate placed on the substrate mounting table, and a polysilicon film is formed on the substrate back side peripheral portion. In such a case, according to the third embodiment, the polysilicon films formed on the front side and the back side of the substrate can be removed with high selectivity.

  The effects obtained by the third embodiment described above are at least one of the effects described in (1) to (3) below. (1) In the gate-last process of the Fin-FET transistor, the polysilicon film 11 formed as a dummy gate is compared with the underlying gate oxide film 15a and sidewall spacers 12 having a silicon content smaller than that of the polysilicon film 11. Can be removed with high selection. (2) Furthermore, the polysilicon film 11 formed on both the front side and the back side of the substrate can be removed with high selectivity. (3) Since the substrate temperature of the etching process is set to 30 to 50 ° C., the polysilicon film 11 which is the Si etching target film can be etched with high selectivity. Further, since the temperature is preferably set to 40 to 50 ° C., the polysilicon film 11 can be etched more selectively.

(Fourth Embodiment) In a Fin-FET that is a 3D transistor, it is difficult to uniformly dope silicon ion using ion implantation because there is a vertical silicon surface region. Therefore, a technique using solid phase diffusion has been studied as an alternative technique. In the third embodiment, solid phase diffusion is performed using a polysilicon film to which phosphorus is added, and then the phosphorus-added polysilicon film is removed by etching.

A fourth example of the substrate processing method according to the present embodiment will be described with reference to FIGS. 33A to 35B. The etching process of the fourth embodiment uses, for example, IF ₇ gas as in the first to third embodiments. In the processing unit 410 shown in FIG. 3, the etching process is the same as that of the first to third embodiments. This is performed under the processing condition C1.

  FIG. 33A is a cross-sectional view in the channel width direction of the Fin-FET transistor before the etching process according to the fourth embodiment of the present invention. FIG. 33B is a three-dimensional schematic diagram of the Fin-FET transistor before the etching process according to the fourth embodiment of the present invention. 11d is a silicon film containing Group III or Group V impurities, in this example, a phosphorus-added polysilicon film. 33A and 33B, the same components as those in FIGS. 30A to 30C are denoted by the same reference numerals. Hereinafter, the polysilicon films 11d and 11e containing a group III or group V impurity which is a film to be etched may be simply referred to as a polysilicon film 11.

  First, as shown in FIGS. 33A and 33B, on the surface side of the substrate on which the Si-Fin structure is formed, the silicon Fin 16 is covered with a thin oxide film 15a, and a phosphorous doped polysilicon film 11d is formed thereon, and then annealed. Phosphorus in the phosphorus-added polysilicon film 11d is diffused into the silicon Fin16. Thereafter, phosphorus in the silicon Fin 16 is activated and further diffused by high-temperature annealing as necessary. The silicon content of the phosphorus-added polysilicon film 11d is larger than the silicon content of the oxide film 15a.

Specifically, the phosphorus-added polysilicon film 11d is formed on the SiO ₂ film 15a, which is the underlying gate oxide film, at any temperature within the range of 400 ° C. to 700 ° C. by the CVD method. Next, annealing is performed for any time in the range of 1 min to 60 min in an N ₂ gas atmosphere at any temperature in the range of 900 ° C. to 1050 ° C., and phosphorus is added into the Si-Fin 16 from the phosphorus-added polysilicon 11d. Spread. Then, spike annealing at about 1100 ° C. is performed using flash lamp annealing or laser annealing to activate phosphorus in Si-Fin 16.

  Next, as shown in FIGS. 34A and 34B, the phosphorus-added polysilicon film 11d is removed. FIG. 34A is a cross-sectional view in the channel width direction of the Fin-FET transistor after the etching process according to the fourth embodiment of the present invention. FIG. 34B is a three-dimensional schematic diagram of the Fin-FET transistor after the etching process in the fourth embodiment of the present invention.

In such a 3D structure typified by a Fin-FET, it is necessary to completely remove the phosphorus-added polysilicon 11d in the groove between the Fins. For this purpose, isotropic etching in which etching in the horizontal direction as well as the vertical direction proceeds is preferable, has a high etching rate with respect to silicon, and has a high selectivity with respect to the underlying SiO ₂ film 15a. Etching is required. Therefore, also in this etching step, the phosphorus-added polysilicon 11d is removed by using an etching gas (for example, IF ₇ gas) capable of highly selective isotropic etching.

In this way, by performing gas etching having a high etching rate only on silicon, there is no etching residue of phosphorus-added polysilicon, and only the phosphorus-added polysilicon 11d is removed while maintaining the shape of the underlying SiO ₂ film 15a. It can be removed.

FIG. 35A is a diagram showing a state before the phosphorus-added polysilicon film on the back side of the substrate is removed in the fourth embodiment of the present invention. The outermost phosphorus-added polysilicon film 11e on the back side of the substrate is a phosphorus-added polysilicon film formed at the same time as the phosphorus-added polysilicon film 11d on the front side of the substrate and made of the same material as the phosphorus-added polysilicon film 11d. The underlying oxide film 15b is an oxide film (SiO ₂ film) formed at the same time as the gate oxide film 15a on the substrate surface and formed of the same material as the gate oxide film 15a.

Similar to the third embodiment, the SiN film 29 under the oxide film 15b and the SiO ₂ film in contact with the silicon substrate 19 are formed on the front side of the substrate in a general STI formation process performed at an early stage of the CMOS process. The formed film is also formed on the back side of the substrate.

  FIG. 35B is a diagram showing a state after the phosphorus-added polysilicon film on the back side of the substrate is removed in the fourth embodiment of the present invention. As described above, in the fourth embodiment, the phosphorus-added polysilicon 11d on the wafer front side is removed by etching with a gas having high etching selectivity with respect to silicon, and at the same time, the phosphorus-added polysilicon 11e on the wafer back side. Can be removed. In this embodiment (fourth embodiment), phosphorus-added polysilicon is used. However, it is also possible to use boron-added polysilicon instead of phosphorus.

  Further, in a vertical apparatus or a single wafer apparatus, a film forming gas may wrap around the back side of the substrate or the peripheral edge of the back side of the substrate. At this time, a phosphorus-added polysilicon film or a boron-added polysilicon film is formed on the back side of the substrate or the peripheral portion on the back side of the substrate. In such a case, according to this embodiment (fourth embodiment), the phosphorus-added polysilicon film or boron-added polysilicon film formed on the front side of the substrate is removed in the same manner as in the third embodiment. In this case, the phosphorus-added polysilicon film or boron-added polysilicon film formed on the back side of the substrate can be removed with high selectivity.

  The effects obtained by the fourth embodiment described above are at least one of the effects described in (1) to (3) below. (1) In a gate-last process of a Fin-FET transistor, a phosphorus-added polysilicon film or a boron-added polysilicon film formed for ion implantation into silicon Fin is more than a phosphorus-added polysilicon film or a boron-added polysilicon film. The base gate oxide film having a small silicon content can be removed with high selectivity. (2) Further, when removing the phosphorus-added polysilicon film or boron-added polysilicon film formed on the front side of the substrate, the phosphorus-added polysilicon film or boron-added polysilicon film formed on the back side of the substrate is Can be removed to selection. (3) Since the substrate temperature of the etching process is set to 30 to 50 ° C., the polysilicon film 11 containing a group III or group V impurity which is a Si etching target film can be etched with high selectivity. In addition, since the temperature is preferably set to 40 to 50 ° C., the polysilicon film 11 containing a group III or group V impurity can be etched more selectively.

Fifth Embodiment Hereinafter, a fifth embodiment of the present invention will be described in more detail with reference to the drawings.

(1) Configuration of Substrate Processing Apparatus First, the configuration of a substrate processing apparatus according to this embodiment (fifth embodiment) will be described mainly with reference to FIG. FIG. 36 is a schematic configuration diagram of a substrate processing apparatus according to the present embodiment (fifth embodiment), and shows a processing unit 410 in a longitudinal section. The substrate processing apparatus shown in FIG. 36 has a configuration in which the first processing unit (FIG. 3) and the second processing unit (FIG. 5) of the substrate processing apparatus according to the first to fourth embodiments are combined into one processing unit. It is. Accordingly, in FIG. 36, components having the same functions and configurations as those in FIGS. 3 and 5 are denoted by the same reference numerals. (Substrate) On the wafer 60 as a substrate, for example, as shown in FIG. 37, a silicon-containing film 64 and a modified layer 65 are formed on the silicon-containing film 64. The silicon-containing film 64 is removed in a silicon-containing film removing process described later. The denatured layer 65 is, for example, a silicon-containing oxide film formed by oxygen adsorbing or diffusing on the surface or upper part of the silicon-containing film.
In this embodiment (fifth embodiment), in particular, in addition to the first embodiment to the fourth embodiment, there is a modified layer removing step to be described later. For example, for a substrate as shown in FIG. It is characterized by substrate processing for removing a silicon-containing film by combining a layer removing process and a silicon-containing film removing process.

(Processing chamber) The processing container 431 is generally formed in a cylindrical shape from a non-metallic material such as quartz glass or ceramics. However, a metal material may be used if there is no particular inconvenience. The upper end of the processing container 431 is closed by a top plate 454, the lower end is closed by a horizontal base plate 448 and a bottom plate 469 as a gantry, and is hermetically sealed by a pressure adjusting mechanism described later. The upper space in the processing container 431 becomes a mixing chamber 630 in which gas is mixed. The gas mixing chamber 630 is optimized according to a desired gas flow and mixing state. Further, a shower plate may be provided in the gas mixing chamber 630 so that the gas is directly supplied to the processing chamber 445 described later. In addition, a space below the base plate 448 and in which the wafer 60 is provided is a processing chamber 445. When the silicon oxide film is removed using plasma, the plasma is in a plasma mixing chamber 630 (equivalent to the plasma generation chamber 530), and in a space where a resonance coil 521 as an excitation unit described later faces. Generated.

(Substrate Support Unit) A susceptor 459 is provided on the bottom surface of the processing chamber 445. The susceptor 459 includes a susceptor table 411 and a substrate heating unit 463 that maintains the wafer on the susceptor at a predetermined temperature. In addition, the substrate heating unit 463 may include a cooling mechanism for removing excessive heat as necessary. The susceptor 459 has a structure supported by a plurality of support columns 461. A plurality of lifter pins 413 are provided through the susceptor table 411, and wafer support pins 414 as substrate support portions are provided above the lifter pins 413. Wafer support pins 414 extend toward the center of the susceptor 459. The wafer 60 is placed on the susceptor table 411 or the wafer support pins 414. Here, the wafer support pins 414 are configured to support the outer peripheral portion of the wafer 60, but may be configured to support the vicinity of the center of the wafer 60 as necessary. By supporting the vicinity of the center of the substrate, it is possible to reduce the bending of the substrate that occurs when a large-diameter substrate having a substrate diameter of 450 mm is supported, and to improve the processing uniformity. For example, when the substrate is bent, the gas flow near the bent portion and the wafer temperature are different from the flow and temperature other than the bent portion, and the processing uniformity may change. The substrate support portion is composed of wafer support pins 414. In some cases, the susceptor table 411 and the lifter pin 413 may be considered. The lifter pin 413 is connected to the lifting plate 471 and is configured to be lifted and lowered by the lifting drive unit 473 along the guide shaft 467.

(Exhaust Unit) An exhaust unit is provided below the susceptor 459. The exhaust part has an APC (Auto Pressure Control) valve 479 and an exhaust pipe 480 as pressure adjusting parts (pressure adjusting mechanisms). In some cases, the exhaust pump 481 may be included in the exhaust section. The valve opening degree of the APC valve 479 is configured to be feedback controlled based on the pressure in the processing chamber 445. The pressure in the processing chamber 445 is measured by a pressure sensor (not shown). The fluorine-containing gas used in this embodiment is heavier than nitrogen (N ₂ ) gas, which is a general purge gas. For example, iodine heptafluoride (IF ₇ ) gas, which is one of the iodine-containing gases described later, has a specific gravity at room temperature of about 2.7 and is about 2.8 times heavier than nitrogen (N ₂ ) gas. Therefore, providing an exhaust port at the bottom of the processing chamber where the fluorine-containing gas tends to stay is useful for suppressing the residual fluorine-containing gas. Moreover, in order to accelerate | stimulate discharge | emission of fluorine-containing gas, you may comprise so that purge gas can be supplied to an exhaust part.

(Baffle Ring) In order to improve the flow of the processing gas, a cylindrical baffle ring 458 and an exhaust plate 465 may be provided. The baffle ring 458 is uniformly provided with a large number of ventilation holes on the side surface of the cylinder, and the exhaust plate 465 is provided with an exhaust communication hole 475 at the center. The first exhaust chamber 474 is formed by the susceptor 459, the baffle ring 458, and the exhaust plate 465, and the second exhaust chamber 476 is formed by the exhaust plate 465 and the bottom plate 469. The two exhaust chambers 476 are communicated with each other through an exhaust communication hole 475. An exhaust pipe 480 is communicated with the second exhaust chamber 476. By providing each of the first exhaust chamber 474 and the second exhaust chamber 476, the exhaust can be performed uniformly from the entire circumference of the wafer 60, and the processing uniformity on the wafer 60 can be improved.

(Gas Supply Unit) A gas supply pipe 455 for supplying a plurality of required processing gases from a gas supply facility (not shown) is attached to the gas inlet 433 on the top plate 454 at the top of the processing vessel 431. Yes. The gas supply pipe 455 includes a processing gas supply unit that supplies a halogen-containing gas as a processing gas to the substrate, a removing agent supply unit that supplies a removing agent (removal gas) as the processing gas to the substrate, and other gases. Here, a third supply unit (not shown) for supplying purge N2 gas, cleaning chlorine fluoride (ClF ₃ ) gas, and the like is provided as necessary. As the removing agent, for example, hydrogen fluoride (HF) gas or the like is used as the removing agent. Note that, here, an example in which gas is supplied as the removing agent is shown, but the present invention is not limited thereto, and it may be configured to be removable by an etching method by supplying liquid. When removing the modified layer by sputtering, a rare gas such as argon may be flowed. The gas supply units are respectively provided with mass flow controllers 477 (a) and 477 (b) and on-off valves 478 (a) and 478 (b) which are flow rate control units, so that the gas supply amount can be controlled. . Although only the removal agent supply unit is described here, there may be a third or later gas supply unit. Further, the gas to be used may be mixed in advance and then flowed to the gas inlet 433. Further, a baffle plate 460 made of quartz glass or ceramics is provided in the processing container 431 to adjust the flow of the processing gas. Moreover, you may make it the structure which uses a shower plate as needed. By adjusting the supply amount and the exhaust amount by the flow rate control unit and the APC valve 479, the pressures in the processing container 431 and the processing chamber 445 are controlled to desired values.

(Excitation part) When removing a modified | denatured layer film | membrane using plasma, the excitation part which generate | occur | produces a plasma may be provided.
Since the resonance coil 432 as the excitation unit forms a standing wave of a predetermined wavelength, the winding diameter, the winding pitch, and the number of turns are set so as to resonate in a constant wavelength mode. That is, the electrical length of the resonance coil 432 corresponds to an integral multiple (1 times, 2 times,...), Half wavelength, or ¼ wavelength of one wavelength at a predetermined frequency of power supplied from the high frequency power supply 444. Set to the length to be. For example, in the case of 27.12 MHz, the length of one wavelength is about 11 meters. The frequency and resonant coil length to be used are preferably selected according to the desired plasma generation state, the mechanical dimensions of the plasma generation chamber 630, and the like.

More specifically, the resonance coil 432 takes into account the applied power, the generated magnetic field strength, the outer shape of the applied device, and the like, for example, 0.01 to 10 by high frequency power of 800 kHz to 50 MHz and 0.5 to 5 kW. In order to generate a Gaussian magnetic field, it has an effective sectional area of 50 to 300 mm ² and a coil diameter of 200 to 500 mm, and is wound about 2 to 60 times on the outer peripheral side of the processing vessel 431. . As a material constituting the resonance coil 432, a copper pipe, a copper thin plate, an aluminum pipe, an aluminum thin plate, a material obtained by evaporating a copper plate or aluminum on a polymer belt, or the like is used. The resonant coil 432 is formed of an insulating material in a flat plate shape, and is supported by a plurality of support portions that are vertically provided on the upper end surface of the base plate 448.

  Both ends of the resonance coil 432 are electrically grounded, but at least one end of the resonance coil 432 finely adjusts the electrical length of the resonance coil during the initial installation of the apparatus or when processing conditions are changed. Therefore, it is grounded via the movable tap 522. For example, it is grounded by a fixed ground location. Further, in order to finely adjust the impedance of the resonance coil 432 when the apparatus is first installed or when the processing conditions are changed, a power feeding unit is configured by a movable tap 524 between the grounded ends of the resonance coil 432. Is done.

  That is, the resonance coil 432 includes ground portions that are electrically grounded at both ends, and includes a power feeding portion that is supplied with power from the high-frequency power source 444 between the ground portions. Further, at least one of the ground portions may be a variable ground portion whose position is adjustable, and the power feeding portion may be a variable power feeding portion whose position is adjustable. When the resonance coil 432 includes a variable ground portion and a variable power supply portion, the resonance frequency and load impedance of the plasma generation chamber 630 can be adjusted more easily as will be described later. .

  Further, a waveform adjustment circuit including a coil and a shield may be inserted at one end (or both ends) of the resonance coil 432 so that the phase and antiphase currents flow to the target with respect to the electrical midpoint of the resonance coil 432. Such a waveform adjusting circuit is configured as an open circuit by setting the end of the resonance coil 432 to an electrically disconnected state or an electrically equivalent state. Further, the end of the resonance coil 432 may be ungrounded by a choke series resistor and may be DC-connected to a fixed reference voltage.

  The outer shield 452 is provided to shield leakage of electromagnetic waves to the outside of the resonance coil 432 and to form a capacitance component necessary for configuring a resonance circuit between the resonance coil 432 and the outer shield 452. The outer shield 452 is generally formed in a cylindrical shape using a conductive material such as aluminum alloy, copper, or copper alloy. The outer shield 452 is arranged at a distance of, for example, about 5 to 10 mm from the outer periphery of the resonance coil 432. In general, the outer shield 452 is grounded so that the potential is equal to both ends of the resonance coil 432. To accurately set the resonance number of the resonance coil 432, one end or both ends of the outer shield 452 are tapped positions. The trimming capacitance may be inserted between the resonance coil 432 and the outer shield 452. The outer shield 452 and the resonance coil 432 that are electrically grounded constitute a spiral resonator.

  As the high-frequency power source 444, an appropriate power source such as an RF generator can be used as long as it is a power source that can supply electric power of a necessary voltage and frequency to the resonance coil 432. For example, a high frequency power source capable of supplying power of about 0.5 to 5 kW at a frequency of 80 kHz to 800 MHz is used.

  A reflected wave wattmeter 468 is installed on the output side of the high frequency power supply 444, and the reflected wave power detected by the reflected wave wattmeter 468 is input to the controller 600 used as a control unit. The controller 600 does not simply control only the high-frequency power supply 444 but controls the entire substrate processing apparatus including, for example, the operation of the substrate transfer mechanism and the gate valve. The display as the display device displays, for example, data detected by various detection units provided in the substrate processing apparatus such as a detection result of the reflected wave by the reflected wave wattmeter 468. The high frequency power supply 444 is provided with a frequency matching unit 526 that controls the transmission frequency.

  In the present embodiment, the excitation unit includes the resonance coil 432, but it may be considered including one or more of the high-frequency power source 444, the external shield 452, the reflected wave wattmeter 468, and the frequency matching unit 526.

(Substrate Transport System) Next, the substrate transport system in the present embodiment has the same form as the substrate processing apparatus disclosed in FIGS. 1 and 2, and the transport form is also the same. Then, explanation is omitted.

(Controller) The controller 600 controls the above-described units so as to perform a substrate processing process described later. Description of portions overlapping those in FIG. 6 may be omitted.

(Control Unit) As shown in FIG. 38, a controller 600 that is a control unit (control unit) includes a CPU (Central Processing Unit) 600a, a RAM (Random Access Memory) 600b, a storage device 600c, and an I / O port 600d. Configured as a computer. The RAM 600b, the storage device 600c, and the I / O port 600d are configured to exchange data with the CPU 600a via the internal bus 600e. For example, an input / output device 601 configured as a touch panel or the like is connected to the controller 600.

  The storage device 600c includes, for example, a flash memory, a HDD (Hard Disk Drive), and the like. In the storage device 600c, a control program that controls the operation of the substrate processing apparatus, a process recipe that describes the procedure and conditions of the substrate processing described later, and the like are stored in a readable manner.

  The I / O port 600d includes the above-described lifting drive unit 473, substrate temperature adjustment unit 463, APC valve 479, mass flow controllers 477 (a) and 477 (b), on-off valves 478 (a) and 478 (b), and an exhaust pump. 481, atmospheric transfer robot 130, gate valves 313, 314, vacuum arm robot unit 320, and the like. In the case where the excitation unit is provided, the high frequency power supply 444, the movable tap 524, the reflected power meter 468, and the frequency matching unit 526 are configured to be connectable.

  The CPU 600a is configured to read and execute a control program from the storage device 600c, and to read a process recipe from the storage device 600c in response to an operation command input from the input / output device 601. Then, the CPU 600a moves the lifter pins 413 up and down by the elevation drive unit 473, the heating / cooling operation of the wafer 60 by the substrate temperature adjustment unit 463, the pressure adjustment operation by the APC valve 479, in accordance with the contents of the read process recipe. The flow rate adjustment operation of the processing gas by the mass flow controllers 477 (a) and 477 (b) and the on-off valves 478 (a) and 478 (b) is controlled.

(2) Substrate Processing Step Next, with reference to FIG. 39, a substrate processing step performed as one step of the semiconductor manufacturing process according to the present embodiment will be described. Such a process is performed by the above-described substrate processing apparatus. In the following description, the operation of each unit constituting the substrate processing apparatus is controlled by the controller 600. Here, the difference from the substrate processing step in the first to fourth embodiments is that in addition to the step of selectively etching the Si film by supplying an etching gas containing a halogen element (preferably containing iodine), This is in that a step of removing the modified layer that hinders the penetration of the etching gas is added. The step of removing the denatured layer may be performed either before or after the etching step using an etching gas containing iodine, and is appropriately set depending on the structure of the device formed on the substrate to be etched. Needless to say, the step of removing the denatured layer can also be applied to the substrate processing steps in the first to fourth embodiments.

(Substrate Loading Step S <b> 10) First, the wafer 60 is transferred from the FOUP 110 to the load lock chamber 250 by the atmospheric transfer robot 130. In the load lock chamber 250, evacuation is performed, and the atmosphere or inert gas atmosphere in the EFEM is replaced with a vacuum atmosphere, an inert gas atmosphere, or a decompressed atmosphere to which an inert gas is supplied. When the atmosphere replacement is completed, the gate valve 311 between the load lock chamber 250 and the transfer module 310 is opened, and the wafer 600 is transferred from the load lock chamber 250 into the transfer module 310 by the vacuum arm robot unit 320. . When transported, the gate valve 311 is closed. Thereafter, the wafer is mounted on the wafer support pins 414 on the lifter pins 413 through the gate valve 313 provided between the transfer module 310 and the processing unit 410. When the wafer transfer mechanism is retracted out of the processing chamber 445, the gate valve 313 is closed. When the wafer 60 is transferred, it is preferable that the transfer path is purged with an inert gas and the pressure is reduced. By setting the inert gas atmosphere and reducing the pressure, it is possible to suppress the oxidation (oxygen adsorption) of the semiconductor elements formed on the wafer 60 and the unintentional moisture adsorption.

(Substrate Heating Step S20) Next, the lifter pins 413 are lowered and the wafer 60 is placed on the susceptor table 411. Here, the lifter pin 413 is lifted and lowered by the lift drive unit 473. The substrate temperature adjusting unit 463 provided in the susceptor 459 is heated to a predetermined temperature in advance, and heats the wafer 60 so as to reach a predetermined wafer temperature. If necessary, a cooling mechanism for exhausting excess heat (reaction heat) is also used. Here, the predetermined wafer temperature is a temperature zone in which a later-described removal gas and etching gas are sufficiently vaporized, and is a temperature at which film characteristics formed on the wafer 60 do not change.

(Modified Layer Removal Step S30) Subsequently, a removal gas as a predetermined removing agent is supplied from the gas supply pipe 455 to the wafer 60, and the modified layer is removed from the wafer 60. Here, the denatured layer is an oxide film containing silicon formed on the surface of a film containing silicon as a main component (and a pattern formed by the silicon film). The denatured layer is formed, for example, by a reaction with oxygen contained in the moving atmosphere when the wafer 60 is moved. Further, it is formed by reacting with water or oxygen present in the atmosphere used when performing wet etching, cleaning, or the like. The silicon-based film includes an amorphous silicon film, a polysilicon film, a P (phosphorus) doped silicon film, a B (boron) doped silicon film, an As (arsenic) doped silicon film, a C (carbon) doped silicon film, and the like. is there. The denatured layer is removed by supplying a remover to the wafer 60. For example, the removal gas is supplied. For example, HF gas is used as the removal gas, and is set to a predetermined gas flow rate of 0.1 slm to 10 slm. For example, it is set to 3 slm. The pressure in the processing chamber is, for example, 1 Pa to 1300 Pa. A predetermined pressure is set. For example, it is set to 100 Pa. HF gas is particularly effective for removing the silicon oxide film. In this case, HF gas may be introduced into the treatment chamber, or a mixed gas of iodine heptafluoride (IF ₇ ) gas and hydrogen (H ₂ ) gas is introduced into the treatment chamber to be converted into plasma. A gas component may be generated. In particular, by supplying IF ₇ gas, a preliminary treatment in the Si-containing film removal step described later can be performed. That is, the intermediate layer between the modified layer and the silicon-containing film can be removed, and the silicon-containing film can be more reliably removed in the silicon-containing film removal step. Moreover, although the example which removes a modified layer with HF gas was shown here, it does not restrict to this. For example, a reducing gas may be supplied to remove oxygen. An example of the reducing gas is hydrogen (H ₂ ) gas. If the amount of oxygen adsorbed on the surface by the cleaning liquid or the like is within an allowable range, the modified layer may be removed by a wet etching method using a removing liquid (for example, HF aqueous solution) as a removing agent. Further, the denatured layer is obtained by supplying the wafer 60 with a gas obtained by activating (plasmaizing) one or both of a rare gas such as argon (Ar) and a reducing gas such as hydrogen gas as a removing agent. May be removed. By supplying the activated rare gas to the wafer 60, the modified layer can be removed by sputtering. Moreover, the denatured layer can be reduced by supplying activated hydrogen to the wafer 60. By supplying such an activated removal agent (for example, activated Ar) to the wafer 60, other films formed on the wafer 60 are not damaged as compared with the case of using HF gas. The denatured layer can be removed. That is, the denatured layer 65a can be removed without impairing the function as the embedded film. The modified layer is removed by supplying a gas containing a halogen element, for example. The removal gas is a gas containing two or more halogen elements from fluorine (F), chlorine (Cl), bromine (Br), and iodine (I), for example. For example, iodine pentafluoride (IF ₅ ), iodine heptafluoride (IF ₇ ), bromine trifluoride (BrF ₃ ), bromine pentafluoride (BrF ₅ ), xenon difluoride (XeF ₂ ), trifluoride There is chlorine (ClF ₃ ) and the like.

  After removing the denatured layer, it is preferable to perform a necessary purge process in preparation for a new next step.

(Modified Layer Suppression Step S40) In this step, the modified layer is prevented from growing again after the modified layer is removed. For example, the generation of the modified layer is suppressed by keeping the wafer 60 in an inert gas atmosphere, a reducing atmosphere, or a vacuum atmosphere. In this embodiment, since a series of processing is performed in the same processing chamber, it is possible to quickly move to the next step without mixing oxygen in the atmosphere of the processing chamber.

(Processing gas supply process S50) Subsequently, a predetermined processing gas is supplied from the gas supply pipe 455. The processing gas supplies a gas containing fluorine (fluorine-containing gas) as an etching gas. Further, an inert gas for purging or dilution may be supplied. Here, the fluorine-containing gas is a gas containing one or more fluorine (F). For example, iodine pentafluoride (IF ₅ ), iodine heptafluoride (IF ₇ ), bromine trifluoride (BrF ₃ ), bromine pentafluoride (BrF ₅ ), xenon difluoride (XeF ₂ ), trifluoride There is chlorine (ClF ₃ ) and the like. Preferably, a gas containing iodine (iodine-containing gas) such as iodine pentafluoride (IF ₅ ) or iodine heptafluoride (IF ₇ ), more preferably iodine heptafluoride (IF ₇ ) is used. IF ₇ can positively (selectively) remove the silicon-containing film. Further, for example, nitrogen (N ₂ ) gas is used as the inert gas, but it may be a rare gas such as He, Ne, or Ar.

By adjusting the exhaust amount by the APC valve 479 simultaneously with the gas supply, the total pressure in the processing chamber 445 is in the range of about 1 to 1330 Pa, and the partial pressure of IF ₇ is in the range of about 1 to 1330 Pa. Maintain a predetermined pressure. For example, it is maintained at 100 Pa. Each gas flow rate is set to a predetermined flow rate within a range of about 0.1 to 10 SLM. For example, it is set to 3 SLM. Further, if necessary, a predetermined gas may be supplied after the atmosphere of the processing container 431 and the processing chamber 445 is once exhausted. Further, since the etching of the silicon-containing film is started as soon as the IF ₇ gas is supplied, it is desirable that the pressure and the gas flow rate are quickly set to predetermined values. Here, it goes without saying that the processing condition C1 in the first embodiment and the fourth embodiment can also be applied in the present embodiment.

(Silicon-containing film removal step S60) By maintaining the substrate temperature, pressure, and gas flow rate at predetermined values for a predetermined time, the silicon-containing film is selectively removed by a predetermined amount. In particular, the IF ₇ gas can selectively remove the silicon film at a high etching rate without using plasma at about room temperature (for example, a substrate temperature of 30 ° C. to 50 ° C.).

  At this time, the etching gas may be supplied while the wafer 60 is supported by the wafer support pins 414. By supplying the etching gas while being supported by the wafer support pins 414, the silicon-based film (silicon-containing film) formed on the back surface of the wafer 60 can be removed. Further, the wafer 60 may be supported by the wafer support pins 414 after the etching gas is supplied to some extent or before the etching gas is supplied.

Here, when the front surface and the back surface of the wafer 60 are compared, the surface of the wafer 60 is formed with fine irregularities constituting the semiconductor device, and the back surface is formed with a film mainly composed of silicon on the front surface. It is in the state. Depending on the timing of supporting by the wafer support pins 414, the film mainly composed of silicon formed inside the unevenness may be excessively removed, or the film may remain on the back surface even if removed appropriately. There is a thing. By varying the supply time to the front and back surfaces of the wafer 60, the front and back surfaces of the wafer 60 can be processed uniformly.

(Modified Layer Removal Step S70) If necessary, the modified layer remaining after removing the silicon-containing film is removed. Here, the denatured layer is an oxide film containing silicon formed on the surface of a film containing silicon as a main component. In this case, HF gas may be introduced into the processing chamber, or a mixed gas of IF ₇ gas and H ₂ gas may be introduced into the processing chamber and converted into plasma to generate an HF gas component.

By supplying the IF ₇ gas, the silicon-containing film can be removed even if the silicon-containing film remains in the above-described silicon-containing film removal step. Further, the intermediate film between the silicon-containing film and the modified layer can also be removed. Further, the denatured layer is removed by supplying the wafer 60 with a gas obtained by activating (plasmaizing) one or both of a rare gas such as argon and a reducing gas such as hydrogen gas as a removing agent. May be. By supplying the activated rare gas to the wafer 60, the modified layer can be removed by sputtering. Moreover, the denatured layer can be reduced by supplying activated hydrogen to the wafer 60.

By supplying such an activated removing agent to the wafer 60, the modified layer can be removed without damaging other films formed on the wafer 60. At this time, the removal gas may be supplied after the wafer 60 is supported by the wafer support pins 414. Further, the wafer 60 may be supported by the wafer support pins 414 during the supply of the removal gas. In this case, since the time during which the removal gas is exposed to the silicon electrode (pattern) on the wafer surface and the back surface of the wafer is different, a large amount of the removal gas is exposed to the wafer surface.

Further, since the reactivity of the HF gas depends on the amount of water in the reaction chamber atmosphere, it is effective to remove the denatured layer using a removal gas that is converted into plasma and is sufficiently active.

(Purge / Cooling Step S80) When the necessary removal step is completed, the supply of the removal gas is stopped, and the atmosphere gas in the processing vessel 431 and the processing chamber 445 is exhausted. At this time, exhaust may be performed while flowing an inert gas for purging. Further, as described above, since the halogen-containing gas is heavier than the purge gas, there is a possibility that the removal gas remains. Therefore, it is preferable to perform a sufficient purge so that the removed gas does not remain. For example, the supply of the inert gas for purging and the exhaust of the atmospheric gas are performed alternately. Thereby, it is possible to prevent the halogen-containing gas from remaining in the processing chamber and to flow out of the processing chamber. Also, the lifter pins 413 are raised to cool the wafer 60 to a temperature at which the wafer 60 can be transferred away from the susceptor table 411.

(Substrate Unloading Step S90) When the wafer 60 is cooled to a temperature at which it can be transferred and ready to be unloaded from the processing chamber, it is unloaded by the reverse procedure of the substrate loading step S10.

  In particular, in the substrate processing step as described above, when removing the denatured layer inside the trench structure with respect to the substrate on which the device having the trench structure with a large aspect ratio is formed on the front side, the gas is converted into plasma ( It is effective to make it enter into the trench after activation.

  The effectiveness of the modified layer removing step according to the present embodiment (fifth embodiment) will be described in detail.

When the silicon-containing film to be removed by the etching process is covered with a modified layer, if the modified layer is sufficiently thick and dense, the penetration of IF ₇ gas is inhibited and no silicon removal reaction occurs. However, when the modified layer is a thin and rough film such as a natural oxide film, the IF ₇ gas permeates through the modified layer and reacts with the underlying silicon, and the modified layer remains as a residue while the silicon is removed. ing.

In particular, since the surface of the silicon-containing film is easily naturally oxidized, an unintended residue is generated after removal of the silicon-containing film with IF ₇ gas unless care is taken in removing the natural oxide film.

  Furthermore, even if the substrate can be wet-cleaned before removal of the silicon-containing film, the substrate is often unable to be wet-cleaned after the silicon-containing film is removed because a fine and high aspect ratio structure is exposed. Here, the fine high aspect ratio structure includes, for example, a pillar structure. In such a case, there is a possibility that there is no way to remove the modified layer residue after the silicon-containing film is removed. For example, when the wafer 60 on which a fine and high aspect ratio structure is exposed is subjected to wet cleaning, there is a problem that the pattern collapses as described above. Therefore, it is particularly important to remove the denatured layer that becomes a residue base before removing the silicon-containing film.

(3) Fifth Example (Gas Etching Including Deletion Layer Removal Step) Hereinafter, a back end fine pattern forming flow for suitably carrying out this embodiment will be described with reference to FIGS. 40A to 40M. In particular, FIGS. 40G and 40J show an example of a process for performing gas etching having a high etching rate with respect to silicon and having high selectivity with respect to, for example, a SiO ₂ film, a Si ₃ N ₄ film, and a carbon film. Represents.

Further, FIG. 40A~ Figure 40M is further groove below the lithographic resolution limit sidewalls is etched back the SiO ₂ film by forming a silicon film after the silicon material to form a side wall of the SiO ₂ film to the core The negative SADP method for forming a pattern is shown. In addition, the silicon core pattern formed with the resolution limit dimension or more is patterned using lithography and dry etching, and shows the case of using a multilayer resist film in which a resist is coated on the carbon film and the silicon antireflection film. Yes. Then, an example is shown in which negative SADP is performed on a multilayer film in which a TiN film, a silicon film, and a SiO ₂ film are laminated on the patterning target. These multilayer films are permitted for use in the back end.

In addition, an example process flow that suitably represents the present invention is shown, and there is no particular limitation on the combination of the underlying laminated films.

In the present embodiment, first, as shown in FIG. 40A, the resist 1 is patterned and slimmed by lithography. Subsequently, as shown in FIG. 40B, the pattern is transferred by dry etching the underlying silicon antireflection film 2 and the carbon hard mask 3 using the patterned resist 1 as a mask. Next, after removing the resist 1 with an asher, as shown in FIG. 40C, the underlying silicon film 4 is patterned using the patterned silicon antireflection film layer 2 and carbon hard mask layer 3 as a mask. Next, as shown in FIG. 40D, by removing the carbon hard mask layer 3 with an asher, a core pattern (protrusions mainly composed of silicon) of the silicon film 4 is formed. A first groove 43 is formed between the protrusions mainly composed of silicon.

Next, as shown in FIG. 40E, a SiO ₂ film 35 is formed. It is preferable that the silicon film 4 is formed uniformly with good coverage on the core. By forming the SiO ₂ film 35, the second groove 44 is formed. Next, as shown in FIG. 40F, a silicon film 36 is formed so as to cover the SiO ₂ film 35. At this time, the region where the silicon cores are densely arranged is formed so that the groove between the sidewalls of the adjacent SiO ₂ film 35 is filled with the silicon film 36. The interval between the adjacent sidewalls is adjusted by the core pattern size and pitch of the silicon film 4 and the thickness of the SiO ₂ film 35 so that the silicon film 36 is filled and the interval becomes a desired size. . Specifically, the thickness of the silicon film 36 formed on the second groove 44 in the silicon film 36 formed on the SiO ₂ film 35 is adjusted to be thick. More specifically, the silicon film 36 formed on the SiO ₂ film 35 is preferably adjusted to have the same thickness except for the silicon film 36 formed on the second groove 44.

Next, as shown in FIG. 40G, the silicon film 36 is etched back, and the etching conditions are adjusted so that only the silicon film 36 in the region filled with the silicon film 36 is left in the second trench 44. At this time, in the wide groove pattern (third groove 45), it is necessary to completely remove the silicon film 36 on the side wall and the silicon film 36 on the bottom. For this purpose, isotropic etching is required. At this time, the width of the groove is such that the width of the second groove <the first groove <the width of the third groove. In this process, gas etching using IF ₇ gas is performed as etching having a high etching rate with respect to silicon and high selectivity with respect to the SiO ₂ film. An example of the IF ₇ gas supply condition is performed at a flow rate of 1 liter (only the central condition is shown) and a pressure of 200 to 500 Pa at about room temperature (for example, 30 ° C. to 50 ° C.). At this time, for example, the silicon film 36 (the silicon film 36 on the side wall and the silicon film 36 on the bottom) facing the third groove, and the SiO ₂ film 35 deposited on the silicon film 4 are deposited. The silicon film 36 and the like are completely removed and adjusted so as to leave only the silicon film 36 formed on the second groove 44. Needless to say, the processing conditions C1 in the first and fourth embodiments may be used. In this case, for example, the etching time is adjusted.

  Here, when supplying the etching gas as the processing gas, it is preferable to perform a treatment using a removing agent in advance as described above.

Subsequently, the SiO ₂ film 35 as shown in FIG. 40H dry etching, a groove pattern by removing the SiO ₂ film 35 between the silicon film 36 remaining in the grooves of the core pattern and the SiO ₂ film of the silicon film 4 Form. Next, as shown in FIG. 40I, the underlying SiO ₂ film 37 is patterned by dry etching using the pattern formed in FIG. 40H as a mask. As an example of the etching stopper for the SiO ₂ film 37, a case where a silicon film 38 is laid below is shown. Next, as shown in FIG. 40J, for example, a carbon-based film 39 is embedded in the groove pattern formed by etching the SiO ₂ film. A general resist material may be used instead of the carbon film. It is desirable to apply by spin coating in order to fill from the bottom of the groove. Then, etching is performed until the surfaces of the silicon films 4 and 36 patterned by the etch back appear.

Next, as shown in FIG. 40K, the pattern on the surface of the silicon film is removed under etching conditions that the carbon-based film 39 is not shaved. At this time, the silicon films 4 and 36 are first etched. A film having high selectivity with respect to the carbon-based film 9 together with the underlying SiO 2 film is desirable. For example, gas etching of IF ₇ is used. The IF ₇ gas is supplied under the conditions of a flow rate of 1 liter (only the central condition is shown), a pressure of 200 to 500 Pa, and a temperature of 30 ° C. to 50 ° C. Here, it goes without saying that the processing condition C in the first embodiment and the fourth embodiment may be used. At this time, in the vertical apparatus, since the wafer back surface is exposed, the silicon film on the wafer back surface can be removed at the same time. On the other hand, even in the case of a single wafer apparatus, the silicon film on the back surface of the wafer can be removed simultaneously by sending the etching gas to the back surface of the wafer by floating the wafer 60 with the wafer support pins 414 when supplying the IF ₇ gas. At this time, the removal gas may be supplied after the wafer 60 is supported by the wafer support pins 414. In this case, since the time during which the removal gas is exposed to the silicon electrode (pattern) on the wafer surface and the back surface of the wafer is different, a large amount of the removal gas is exposed to the wafer surface.

Next, switching to SiO ₂ film etching is performed, and the SiO ₂ film 37 is etched using the underlying silicon film 38 as an etching stopper. Next, as shown in FIG. 40L, the two layers of the silicon film 38 and the TiN film 62 as an electrode are continuously etched. Then, the carbon-based film 39 is removed by ashing. The ashing at this time is preferably ashing not containing oxygen-based gas. Next, as shown in FIG. 40M, a groove is formed in the underlying SiO ₂ film 10 using the patterned silicon film 8 and TiN film 62 as a mask. The groove pattern of the copper damascene process in the back-end process can be formed with a pitch less than the resolution limit in lithography.

  In the present embodiment (fifth embodiment), the process of directly removing the target film using the removal gas or the etching gas is described. However, the present invention is not limited to this, and the halogen salt gas is allowed to react with the silicon oxide film. A reaction product may be generated, and the reaction product may be removed by heating and vaporization.

  In this embodiment (fifth embodiment), the silicon oxide film formed on the silicon-containing film is described as the modified layer. However, the present invention is not limited to this. For example, when a plasma treatment using hydrogen and nitrogen is performed during resist ashing, a nitride film is formed on the surface of the substrate or a film formed on the substrate. When this nitride film exists, the same problem as described above may occur, and the amount of remaining nitride film can be suppressed by removing the nitride film (modified layer) before removing the silicon-containing film. it can.

  Further, as described above, according to the present embodiment (fifth embodiment), the modified layer formed on the silicon film is removed with the removing agent, and the silicon film is removed with the etching gas. However, the present invention is not limited thereto. It is not a thing. For example, when removing the dummy gate electrode mainly composed of silicon, the dummy oxide is removed with an etching gas after removing the natural oxide film formed on the surface of the dummy gate electrode with a remover. Alternatively, after removing the natural oxide film formed on the surface of the mold silicon film for electrode formation with a remover, the mold silicon film may be removed with an etching gas.

Thus, according to the present embodiment (fifth embodiment), even if a natural oxide film is deposited on a semiconductor device formed on a substrate, the denatured layer formed on the silicon film is removed with a remover. Then, the silicon film covered with the modified layer can be exposed on the surface, and the silicon film can be removed with an etching gas. In particular, in this embodiment, iodine heptafluoride (IF ₇ ) gas having remarkably remarkable selectivity can be used as an etching gas for the Si film and a film other than the Si film.

(4) Effects According to this Embodiment According to this embodiment, one or more effects shown in (a) to (d) below are exhibited.

(A) In the gas etching process in which the Si film is selectively removed using an etching gas containing fluorine, a modified layer that inhibits the silicon removal reaction can be removed in advance.

(B) Moreover, in the gas etching process which selectively removes Si film | membrane using the etching gas containing a fluorine, the residue resulting from the modified | denatured layer which existed on the silicon-containing film | membrane surface to be removed can be suppressed.

(C) Moreover, it can suppress that a substrate processing apparatus is contaminated with the residue resulting from the said modified | denatured layer.

(D) Moreover, in the gas etching process which selectively removes Si film using the etching gas containing a fluorine, the residue resulting from the modified layer which existed in the location covered with the silicon-containing film to be removed is suppressed. Can do.

(E) Further, by removing the silicon-containing film with a fluorine-containing gas after removing the denatured layer with the removal gas, the silicon-containing film can be removed without collapsing the electrode formed on the substrate.

(F) Moreover, the oxide film formed in the interface of a silicon containing film and an electrode can be removed by performing the removal process of a modified layer after a silicon containing film removal process.

  It goes without saying that the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the invention.

  In the embodiment, the first etching process, the second etching process, and the third etching process are performed in one substrate processing apparatus, but the first etching process and the second etching process are performed. It is also possible to configure the etching process and the third etching process to be performed by different substrate processing apparatuses.

  Next, as another aspect of the processing flow of the substrate, a case where the processing flow of the substrate illustrated with reference to FIG. 39 described above is performed for each element in different places will be illustrated.

FIG. 41A illustrates another aspect of the substrate processing flow. Here, after the modified layer removing step S30 is performed by the modified layer removing device 610, the silicon-containing film removing step S60 is performed by the silicon-containing film removing device 612. Moreover, generation | occurrence | production of a new modified layer is suppressed by storing and conveying a board | substrate in the container 611 of inert gas atmosphere as modified | denatured layer suppression process S40. As a specific example of such a form, for example, the denatured layer film is removed by a wet cleaning apparatus, and the substrate is transferred to an apparatus for removing the silicon-containing film using N ₂ purge FOUP (Front Opening Unified Pod). An example is given. Further, the modified layer removing method is not limited to wet cleaning, and may be a dry process using gas. Here, the method for removing the modified layer and the method for suppressing the new modified layer can be variously improved, changed, and added by those skilled in the art within the scope of the technical idea of the present invention.

  FIG. 42B illustrates still another aspect of the substrate processing flow. Here, using a cluster-type substrate processing apparatus, a reaction chamber 613 for removing a denatured layer and a reaction chamber 614 for removing a silicon-containing film are connected by a vacuum transfer chamber 615 purged with an inert gas. The case where the process of (2) is performed continuously is illustrated. Here, the modified layer removal steps S30 and S70 are performed in the reaction chamber 613, the modified layer suppression step S40 is performed in the vacuum transfer chamber 615, and the silicon-containing film removal step S60 is performed in the reaction chamber 614. The modified layer removal steps S30 and S70 may be performed in separate reaction chambers.

  In the present embodiment, the wafer temperature is adjusted using the heater and the coolant supply path in the first processing unit. However, the present invention is not limited to this, and an etching gas whose liquefaction temperature is lower than room temperature is not used. The temperature may be adjusted with a coolant. Moreover, it is good also as a temperature control mechanism with the function of both cooling and heating by adjusting the liquid temperature to circulate.

  In the above-described embodiment, the single-wafer apparatus has been described as an example. However, the present invention is a vertical apparatus that performs processing in a state where, for example, a plurality of horizontal substrates are stacked on a boat and the boat is loaded into a processing chamber. Can also be applied. In the first embodiment, a plurality of substrates on which the sidewalls have been formed in step S5 described above are mounted on a boat and carried into the processing chamber, and the core pattern removal process in step S6 described above is performed. Then, when the core pattern removal process is completed, the boat is carried out of the processing chamber, and the processing after step S7 described above is performed in another processing apparatus. In the second embodiment, the substrate on which the silicon hard mask shown in FIG. 26 of the second example is formed, the dummy polysilicon film of the third example, and the phosphorus-added polysilicon film of the fourth example are formed. A plurality of substrates are loaded on the boat and carried into the processing chamber, and the silicon hard mask removing process of the second embodiment, the dummy polysilicon film removing process of the third embodiment, and the phosphorus addition of the fourth embodiment are carried out. A polysilicon film removal process is performed.

At this time, also in the vertical apparatus, IF ₇ gas is used as the etching gas for the core pattern removal process, and the etching process is performed under the same temperature and pressure conditions as in the single wafer apparatus. Thus, also in the vertical apparatus, in the first embodiment, the Si core pattern 4 is etched with high selectivity with respect to the SiO ₂ film 10 as the sidewall film and the underlying Si ₃ N ₄ film 5. be able to.

Preferably, also in the vertical apparatus, for example, in the first embodiment, in the core pattern removal process, (d) an etching process using IF ₇ gas, (e) an etching process using, for example, O ₃ gas (ozone gas), (f) Etching with IF ₇ gas is performed in this order. For example, in the second embodiment, (d) an etching process using IF ₇ gas, (e) an etching process using, for example, O ₃ gas (ozone gas), and (f) IF ₇ gas in the silicon hard mask removal process of the second example. Etching processes are performed in this order. Here, the processing conditions (d) and (f) described above are the same temperature and pressure as in the case of the single wafer apparatus. Specifically, IF ₇ gas is introduced into the processing chamber, a first etching process using IF ₇ gas is performed, and then the processing chamber is replaced with an inert gas. Thereafter, an O ₃ gas is introduced into the processing chamber, a second etching process using the O ₃ gas is performed, and then the processing chamber is replaced with an inert gas. Thereafter, a third etching process using IF ₇ gas is performed.

  In this way, even in the vertical apparatus, for example, in the first embodiment, the Si core pattern 4 on the front side of the substrate is removed, and at the same time, the Si film 2 and the CHM film 3 are formed on the back side of the substrate as shown in FIG. The laminated film with the Si film 4 can be removed. Specifically, the Si core pattern 4 on the front side of the substrate and the Si film 4 on the back side of the substrate are removed by the process (d), the CHM film 3 on the back side of the substrate is removed by the process (e), and the substrate is obtained by the process (f). The Si film 2 on the back side can be removed. For example, in the second embodiment, the silicon hard mask on the front side of the substrate is removed, and at the same time, as shown in FIGS. 28 and 29, the antireflection film 2, the carbon film 3, and the silicon hard mask 4 are laminated on the back side of the substrate. The film can be removed. Specifically, the silicon hard mask 4 on the front side of the substrate and the silicon antireflection film 2 on the back side of the substrate are removed by the process (d), the carbon film 3 on the back side of the substrate is removed by the process (e), and the process (f). The silicon hard mask 4 on the back side of the substrate can be removed.

Further, the present invention can be applied to various SADP methods such as a device structure of a DRAM which is a kind of semiconductor memory and formation of a gate electrode of a transistor. In addition, the present invention is not limited to the structure of the multi-layer hard mask underlying the SADP process. Depending on the type of process, for example, may be the case where the Si substrate is a hard mask of _{SiO 2,} Si ₃ N 4, SiO ₂ of three layers, the _Si 3 _{N 4} film and two layers of SiO ₂ film hard There may be a case where there is a mask or any other case.

  Further, in the present invention, in the selective dry etching of the Si film using an etching gas containing fluorine, a step of removing the modified layer existing on the surface of the silicon-containing film to be removed and a step of suppressing the generation of a new modified layer And a step of removing the denatured layer present in the portion covered with the silicon-containing film to be removed, and a substrate processing method and a substrate capable of selectively removing silicon while removing an unnecessary denatured layer A processing apparatus is provided, which includes the number of substrates that can be processed simultaneously, the direction in which the substrate is held, the type of dilution gas or purge gas, the cleaning method, the shape of the substrate processing chamber, heating mechanism, and cooling mechanism, etc. Is not limited.

  Further, in the present invention, not only the process of dry-etching either or both of the modified layer and the silicon-containing film formed on the substrate, but also a process of removing (cleaning) the modified layer and the silicon-containing film deposited in the substrate processing chamber. It can be carried out.

In the present embodiment, pattern miniaturization has been conventionally promoted in order to achieve higher integration. However, as the miniaturization progresses, problems specific to the miniaturized pattern arise. One example is pattern collapse due to the surface tension of the liquid during wet etching. For example, in the silicon (Si) removal step, pure water cleaning is performed after etching with tetramethylammonium hydroxide aqueous solution (TMAH) or the like, and drying is performed while replacing with isopropyl alcohol (IPA) having a surface tension smaller than that of pure water. This prevents the pattern from collapsing due to surface tension. However, with the miniaturization of patterns, even if this method is used, the collapse of the patterns cannot be prevented. As means for solving this problem, dry etching in which silicon is removed by an etching gas containing iodine in the present invention can be applied to future pattern miniaturization.

Furthermore, in this embodiment, in the manufacture of a 3D structure device such as a NAND flash memory, in reactive ion etching using conventional plasma, a polysilicon (Poly-Si) film is replaced with a film other than polysilicon (for example, It has been difficult to remove the silicon oxide (SiO ₂ ) film, silicon nitride (SiN) film, silicon oxynitride (SiON) film, carbon (C) film, etc. with high selectivity. That is, a layer of a polysilicon (Poly-Si) film and a silicon oxide (SiO ₂ ) film exposed on a side wall after a through groove is cut out in a laminated structure of a polysilicon (Poly-Si) film and a silicon oxide (SiO ₂ ) film Of these, etching only the polysilicon (Poly-Si) film requires a problem of selectivity with films other than polysilicon and isotropic etching in the conventional reactive ion etching using plasma. It was very difficult from the point. There is also a problem of selectivity with a hard mask film (for example, a carbon film). It has been difficult to cope with the complexity of the device structure accompanying such pattern miniaturization. As means for solving this problem, dry etching for removing silicon by plasma-less isotropic etching with the etching gas in the present invention can be applied to future pattern miniaturization. In particular, by using an iodine-containing gas containing iodine heptafluoride (iodine-containing gas) as an etching gas, compared with the existing etching gas, it has good selectivity with respect to films other than silicon because of its chemical properties. Can be removed. Accordingly, the present invention can be applied to the complexity of the device structure accompanying future pattern miniaturization.

  The present invention can be applied not only to a semiconductor manufacturing apparatus but also to an apparatus for processing a glass substrate such as an LCD manufacturing apparatus. The present invention can also be applied to various types of single-wafer devices such as a multi-wafer type, an in-line type, and a cluster type, a horizontal substrate processing apparatus, and the like. The present invention is not limited to a semiconductor manufacturing apparatus that processes a semiconductor wafer such as a substrate processing apparatus according to the present embodiment, but is an LCD (Liquid Crystal Display) manufacturing apparatus that processes a glass substrate, a substrate processing apparatus such as a solar cell manufacturing apparatus, MEMS ( The present invention can also be applied to a manufacturing apparatus of Micro Electro Mechanical Systems).

Hereinafter, preferred embodiments of the present invention will be additionally described. <Supplementary Note 1> According to one aspect of the present invention, a side wall is formed on the core pattern forming step of forming a core pattern having a predetermined line width on the substrate front side, and the core pattern formed in the core pattern forming step. A fine pattern forming method comprising: a side wall forming step; and a core pattern removing step after the side wall forming step, using an etching gas containing fluorine to remove the core pattern while leaving the side wall. In addition, in the core pattern removing step, a fine pattern forming method for removing the film deposited on the back side of the substrate in the core pattern forming step is provided in parallel with the removal of the core pattern.

<Additional remark 2> It is a fine pattern formation method of Additional remark 1, Comprising: Preferably, the said core pattern formation process provides the fine pattern formation method containing an exposure image development process and a dry etching process.

<Additional remark 3> It is a fine pattern formation method of Additional remark 2, Comprising: Preferably, the said board | substrate is a hard mask film | membrane formed on the film | membrane which comprises the said core pattern in the front side, On the said hard mask film | membrane An anti-reflection film formed on the anti-reflection film and a resist film formed on the anti-reflection film. In the exposure and development step, the resist film is exposed so as to form a resist pattern having the predetermined line width. Then, in the dry etching step, there is provided a fine pattern forming method for forming the core pattern by etching the antireflection film and the hard mask film using the resist pattern as a mask.

<Additional remark 4> It is a fine pattern formation method of Additional remark 3, Comprising: Preferably, the said board | substrate is the back side core material film | membrane which is a film | membrane of the same material as the said core pattern of the front side of the said board | substrate, and the said back side core A back side hard mask film formed on the material film; and a back side antireflection film formed on the back side hard mask film. In the core pattern removal step, the back side antireflection film and the back side hard mask are formed. A fine pattern forming method for removing the mask film and the back-side core material film is provided.

<Additional remark 5> It is a fine pattern formation method of Additional remark 4, Comprising: Preferably, the said core pattern removal process is the 1st etching process which removes the said back side antireflection film, and the 2nd which removes the said back side hard mask film | membrane There is provided a fine pattern forming method including the etching step and a third etching step of removing the back core material film.

A fine pattern forming method of <Supplementary Note 6> Supplementary Note 5, preferably, in the first and second etching step, the method for forming a fine pattern IF ₇ is used as the etching gas is provided.

<Supplementary Note 7> The fine pattern forming method according to Supplementary Note 1, wherein there is provided a fine pattern forming method in which the film constituting the core pattern is silicon and the film constituting the sidewall is a silicon oxide film. The

<Additional remark 8> It is a fine pattern formation method of Additional remark 3, Comprising: Preferably, the material of the said antireflection film is a silicon | silicone, The material of the said hard mask film | membrane provides the fine pattern formation method containing carbon.

<Additional remark 9> It is a fine pattern formation method of Additional remark 1, Comprising: Preferably, the line | wire width of the said sidewall is smaller than the line | wire width of the said core pattern, The fine pattern formation method is provided.

<Additional remark 10> It is a fine pattern formation method of Additional remark 1, Comprising: Preferably, in the said core pattern removal process, the temperature of the said board | substrate is 30-50 degreeC, The fine pattern formation method is provided.

<Additional remark 11> Furthermore, Preferably, the manufacturing method of the semiconductor device using the fine pattern formation method of Additional remark 1 thru | or Additional remark 10 is provided.

<Supplementary Note 12> According to another aspect of the present invention, a core pattern forming step of forming a core pattern having a predetermined line width on the substrate front side, and a sidewall is formed on the core pattern formed in the core pattern forming step. And a core pattern removing step of removing the core pattern in a state where the sidewall is left by using an etching gas containing fluorine after the sidewall forming step. In the core pattern removing step, a method of manufacturing a semiconductor device is provided in which the film deposited on the back side of the substrate in the core pattern forming step is removed in parallel with the removal of the core pattern.

<Supplementary Note 13> According to still another aspect of the present invention, a core pattern having a predetermined line width and a sidewall formed with respect to the core pattern are provided on the front side, and are configured of the same material as the core pattern. A processing chamber for storing a substrate having a core material film on the back side; a gas supply unit for supplying an etching gas containing fluorine to the processing chamber to remove the core pattern while leaving the sidewall; and the processing An exhaust unit for exhausting an indoor atmosphere; and a control unit for controlling the gas supply unit to supply the etching gas to the processing chamber so as to remove the core pattern and the core material film. A substrate processing apparatus is provided.

<Supplementary Note 14> According to still another aspect of the present invention, a procedure of forming a core pattern having a predetermined line width on the substrate front side, a procedure of forming a sidewall with respect to the core pattern, and forming the sidewall And a step of removing the film deposited on the back side of the substrate when performing the step of forming the core pattern while removing the core pattern while leaving the sidewalls using an etching gas containing fluorine. And a recording medium on which the program is recorded so as to be readable.

<Supplementary Note 15> According to still another aspect of the present invention, at least a silicon hard mask film, a carbon film, a silicon antireflection film, and a resist film are formed on a substrate, and the resist film is processed. A resist pattern forming step for forming a resist pattern having a predetermined line width; a carbon film pattern forming step for forming the carbon film pattern using the resist pattern; and the silicon hard using the carbon film pattern. A silicon hard mask pattern forming step for forming a mask film pattern, and when removing the silicon hard mask film pattern using an etching gas containing fluorine, deposited on the back side of the substrate in the film forming step, A first film made of the same material as the silicon antireflection film, and a first film made of the same material as the carbon film. And a silicon hard mask removing step of removing a second film and a third film made of the same material as the silicon hard mask film.

<Supplementary Note 16> The method for forming a fine pattern according to Supplementary Note 15, wherein the silicon hard mask removing step includes a first etching step of removing the first film, and a step after the first etching step. There is provided a fine pattern forming method including a second etching step for removing the second film and a third etching step for removing the third film after the second etching step.

<Supplementary Note 17> The fine pattern forming method according to Supplementary Note 16, preferably, in the first etching step and the third etching step, there is provided a fine pattern forming method in which IF ₇ gas is used as the etching gas. .

<Supplementary Note 18> Further, preferably, there is provided the fine pattern forming method according to Supplementary Notes 15 to 17, wherein the thickness of the silicon hard mask and the thickness of the silicon antireflection film are the same. Is done.

<Supplementary note 19> Further, preferably, in the fine pattern forming method according to supplementary note 15 to supplementary note 18, in the film formation step, a multilayer hard mask is formed before the formation of the silicon hard mask, and the carbon film is formed. A fine pattern forming method is provided in which the film thickness is the same as the film thickness of the multilayer hard mask.

<Supplementary Note 20> Furthermore, preferably, a method for manufacturing a semiconductor device using the fine pattern forming method of Supplementary Notes 15 to 19 is provided.

<Supplementary Note 21> A substrate on which a first silicon film is formed on the front side of the substrate, and a substrate on which the second silicon film, the carbon film, and the third silicon film are formed in this order on the back side of the substrate is carried into the processing chamber. A carrying-in process and an etching process that removes the first silicon film and, in parallel, the third silicon film, the carbon film, and the second silicon film by using an etching gas containing fluorine. And a substrate carrying-in step of carrying out the substrate subjected to the etching step from a processing chamber.

<Supplementary Note 22> According to still another aspect of the present invention, at least a silicon hard mask film, a carbon film, a silicon antireflection film, and a resist film are formed on a substrate. A resist pattern forming procedure for forming a resist pattern having a line width; a carbon film pattern forming procedure for forming the carbon film pattern using the resist pattern; and the silicon hard mask film using the carbon film pattern. The silicon hard mask pattern forming procedure for forming the pattern of the above, and using the etching gas containing fluorine, the silicon hard mask film pattern is removed and the same material as the silicon antireflection film deposited on the back side of the substrate First film, second film of the same material as the carbon film, silicon A silicon hard mask removing procedure for removing a third film made of the same material as the hard mask film, a program for causing a computer to execute the program, and a recording medium on which the program is recorded in a readable manner are provided.

<Supplementary Note 23> According to still another aspect of the present invention, the first silicon film is formed on the front side of the substrate, and the second silicon film, the carbon film, and the third silicon film are formed in this order on the back side of the substrate. A processing chamber for storing the processed substrate, and an etching gas for removing the third silicon film, the carbon film, and the second silicon film in parallel with the removal of the first silicon film. There is provided a substrate processing apparatus comprising: a gas supply unit that supplies a chamber; and an exhaust unit that exhausts the atmosphere in the processing chamber.

<Supplementary Note 24> According to still another aspect of the present invention, a substrate having a silicon film formed in a groove portion in which a gate oxide film is formed at a bottom portion and a gate electrode is embedded is formed on the substrate front side. Removing the silicon film formed in the groove portion without removing the gate oxide film using a fluorine-containing etching gas, and carrying the substrate into the processing chamber; There is provided a fine pattern forming method including: an etching process for removing a first film made of the same material as a silicon film; and a substrate carrying-in process for carrying out the substrate subjected to the etching process from a processing chamber.

<Supplementary Note 25> The method for forming a fine pattern according to Supplementary Note 24, preferably including a step of forming a metal-containing film in the groove after removing the silicon film in the etching step. Is done.

<Supplementary Note 26> The fine pattern forming method according to Supplementary Note 24 or Supplementary Note 25, wherein a plurality of the groove portions are preferably provided in the channel length direction of the gate electrode, and the lengths of the plurality of groove portions in the channel length direction are mutually equal. Different fine patterning methods are provided.

<Supplementary Note 27> Further, preferably, a method for manufacturing a semiconductor device using the fine pattern forming method of Supplementary Notes 24 to 26 is provided.

<Supplementary Note 28> According to still another aspect of the present invention, a substrate having a silicon film formed in a groove portion in which a gate oxide film is formed at a bottom portion and a gate electrode is embedded is formed on the substrate front side. On the other hand, an etching procedure for removing the silicon film without removing the gate oxide film using an etching gas containing fluorine and removing the first film made of the same material as the silicon film on the back side of the substrate. A program to be executed by a computer and a recording medium on which the program is recorded so as to be readable are provided.

<Supplementary Note 29> According to still another aspect of the present invention, a substrate having a silicon film formed in a groove portion in which a gate oxide film is formed at a bottom portion and a gate electrode is embedded is formed on the substrate front side. An etching gas containing fluorine that removes the silicon film without removing the gate oxide film and removes the first film of the same material as the silicon film on the back side of the substrate. There is provided a substrate processing apparatus comprising: a gas supply unit that supplies gas to the processing chamber; and an exhaust unit that exhausts the atmosphere in the processing chamber.

<Supplementary Note 30> According to still another aspect of the present invention, a Si-Fin structure is formed on the front side of the substrate, and a gate oxide film is formed at the bottom of the groove for embedding the gate electrode. , A substrate carrying-in process for carrying a silicon film containing a Group III or V group impurity into a processing chamber, and using an etching gas containing fluorine, without removing the gate oxide film, An etching process for removing the silicon film formed in the groove and removing a first film of the same material as the silicon film on the back side of the substrate, and a substrate for carrying out the substrate subjected to the etching process from the processing chamber And a fine pattern forming method including a carrying-in process.

<Supplementary Note 31> The method for forming a fine pattern according to Supplementary Note 30, wherein a plurality of the groove portions are provided in the channel length direction of the gate electrode, and the lengths of the plurality of groove portions in the channel length direction are different from each other. A forming method is provided.

<Additional remark 32> Furthermore, Preferably, the manufacturing method of the semiconductor device using the fine pattern formation method of Additional remark 30 or Additional remark 31 is provided.

<Supplementary Note 33> According to still another aspect of the present invention, a Si-Fin structure is formed on the front side of the substrate, and a groove portion in which a gate oxide film is formed on a bottom portion, in which the gate electrode is embedded. The silicon film is removed without removing the gate oxide film by using an etching gas containing fluorine for a substrate on which a silicon film containing a group III or group V impurity is formed. A program for causing a computer to execute an etching procedure for removing the first film made of the same material as the silicon film and a recording medium on which the program is recorded in a readable manner are provided.

<Supplementary Note 34> According to still another aspect of the present invention, a Si-Fin structure is formed on the front side of a substrate, and a gate oxide film is formed at the bottom of the groove for embedding a gate electrode. , A processing chamber for accommodating a substrate on which a silicon film containing a Group III or V group impurity is formed, and the silicon film is removed without removing the gate oxide film; Provided is a substrate processing apparatus comprising: a gas supply unit that supplies an etching gas containing fluorine, which removes a first film of the same material as the film, to the processing chamber; and an exhaust unit that exhausts the atmosphere in the processing chamber. Is done.

<Supplementary Note 35> According to still another aspect of the present invention, a film forming step of depositing a multilayer hard mask film, a silicon hard mask film, a carbon film, a silicon antireflection film, and a resist film on a substrate, and the resist A resist pattern forming step of forming a resist pattern having a predetermined line width by processing the film; a carbon film pattern forming step of forming the carbon film pattern using the resist pattern; and using the carbon film pattern A silicon hard mask pattern forming step for forming the silicon hard mask film pattern, and when removing the silicon hard mask film pattern using an etching gas containing fluorine, the back side of the substrate in the film forming step A first film made of the same material as that of the silicon antireflection film, A silicon hard mask removing step of removing the second film made of the same material as the silicon film, the third film made of the same material as the silicon hard mask film, and forming a predetermined pattern using the pattern of the multilayer hard mask film And a pattern forming step. A method of manufacturing a semiconductor device is provided.

<Supplementary Note 36> According to still another aspect of the present invention, a processing chamber for storing a substrate on which at least a silicon hard mask film, a carbon film, a silicon antireflection film, and a resist film are respectively deposited, and the silicon hard mask Removing the third film made of the same material as the film, supplying a gas supply unit supplying an etching gas containing fluorine to the process chamber, an exhaust unit exhausting the atmosphere in the process chamber, and processing the resist film A resist pattern forming step for forming a resist pattern having a predetermined line width; a carbon film pattern forming step for forming the carbon film pattern using the resist pattern; and the silicon hard using the carbon film pattern. Using a silicon hard mask pattern forming process for forming a mask film pattern and the etching gas, When removing the pattern of the silicon hard mask film, a silicon hard mask removing step of removing the first film, the second film, and the third film deposited on the back surface side of the substrate is performed. And a substrate processing apparatus comprising:

<Supplementary Note 37> According to still another aspect of the present invention, a procedure for forming at least a silicon hard mask film, a carbon film, a silicon antireflection film, and a resist film on the substrate, and processing the resist film to form a predetermined line A resist pattern forming procedure for forming a resist pattern having a width; a carbon film pattern forming procedure for forming the carbon film pattern by using the resist pattern; and a silicon hard mask film by using the carbon film pattern. A silicon hard mask pattern forming procedure for forming a pattern, and using an etching gas containing fluorine, the pattern of the silicon hard mask film is removed, and the same material as the silicon antireflection film deposited on the back side of the substrate is formed. A first film, a second film of the same material as the carbon film, and the silicon wafer. There is provided a recording medium in which a silicon hard mask removing procedure for removing a third film made of the same material as the first mask film and a program for causing a computer to execute are readably recorded.

<Supplementary Note 37> According to still another aspect of the present invention, on the front side of the substrate, there is a groove portion in which a gate oxide film is formed at the bottom, a step of filling a silicon film in the groove portion to form a gate electrode, The silicon film formed in the trench is removed without removing the gate oxide film by contacting the substrate with an etching gas containing, and a first material of the same material as the silicon film is formed on the back side of the substrate. An etching process for removing the film is provided, and a method for manufacturing a semiconductor device is provided.

<Supplementary Note 37> According to still another aspect of the present invention, a groove portion in which a Si-Fin structure is formed on a substrate surface and a gate oxide film is formed on a bottom portion, and in this groove portion, a group III or a group V Forming a gate electrode by embedding a silicon film containing impurities, and removing the silicon film formed in the trench without removing the gate oxide film using an etching gas containing fluorine. An etching process for removing a first film made of the same material as the silicon film on the back side of the substrate is provided.

<Supplementary Note 38> According to still another aspect of the present invention,
Forming a fine pattern of a film mainly composed of silicon, forming an oxide film on a substrate having a first groove formed between the fine patterns, and forming a second groove;
Forming a film containing silicon as a main component on the oxide film;
Supplying an etching gas containing a halogen element to the silicon-based film, and removing the silicon-based film other than the silicon-based film on the second trench; A method of manufacturing a semiconductor device having the above is provided.

<Supplementary Note 39> A method of manufacturing a semiconductor device described in the supplementary note 38, preferably,
In the step of supplying the etching gas, a method for manufacturing a semiconductor device is provided in which the etching gas is supplied after the substrate is supported by a support portion.

<Appendix 40> A method for manufacturing a semiconductor device according to appendix 38, preferably,
In the step of supplying the etching gas, a method for manufacturing a semiconductor device is provided in which the substrate is supported by a support portion while the etching gas is supplied.

<Supplementary note 41> A method for manufacturing a semiconductor device according to any one of supplementary notes 38 to 40, preferably,
Provided is a method for manufacturing a semiconductor device, which includes a step of removing a natural oxide film formed on a film containing silicon as a main component before the step of supplying the etching gas.

<Appendix 42> A method for manufacturing a semiconductor device according to any one of Appendix 38 to Appendix 41, preferably,
A method of manufacturing a semiconductor device is provided in which the etching gas is an iodine-containing gas containing iodine.

<Supplementary Note 43> According to another aspect,
A procedure for forming a fine pattern of a film containing silicon as a main component, and a procedure for forming a second groove by forming an oxide film on a substrate having a first groove formed between the fine patterns;
A step of forming a film containing silicon as a main component on the oxide film;
A step of supplying an etching gas containing fluorine to the film containing silicon as a main component and removing the film containing silicon as a main component other than the film containing silicon as a main component on the second groove; A program to be executed by a computer and a recording medium that can read the program are provided.

<Supplementary Note 44> A program described in the supplementary note 43 and a recording medium that can read the program, preferably,
In the procedure of supplying the etching gas, a program in which the etching gas is supplied after the substrate is supported by a support portion and a recording medium that can read the program are provided.

<Supplementary Note 45> The program described in Supplementary Note 43 and a recording medium that can read the program, preferably,
In the procedure of supplying the etching gas, a program for supporting the substrate with a support portion while supplying the etching gas and a recording medium capable of reading the program are provided.

<Supplementary Note 46> The program described in any one of Supplementary Notes 43 to 45 and a recording medium that can read the program, preferably,
A program having a procedure for removing a natural oxide film formed on the silicon-based film before the procedure for supplying the etching gas and a recording medium capable of reading the program are provided.

<Supplementary note 47> The program described in any one of supplementary notes 43 to 46 and a recording medium capable of reading the program, preferably,
The etching gas is a gas containing iodine (iodine-containing gas) and a recording medium that can read the program.

<Supplementary Note 48> According to still another aspect,
A step of forming a fine pattern of a film containing silicon as a main component, and a step of forming an oxide film and forming a second groove on a substrate on which a first groove composed of the fine pattern is formed;
Forming a film mainly composed of silicon on the oxide film;
Removing a film containing silicon as a main component other than the film containing silicon as a main component in the second groove.

<Supplementary Note 49> The method for manufacturing a semiconductor device according to Supplementary Note 48, preferably,
A method of manufacturing a semiconductor device is provided in which the width of the second groove is shorter than the width of the first groove.

<Supplementary Note 50> According to still another aspect,
A procedure for forming a fine pattern of a film containing silicon as a main component, and a processing chamber for accommodating a substrate having a first groove constituted by the fine pattern;
An oxide film material supply unit for supplying an oxide film material to the substrate;
A silicon material supply unit for supplying silicon material to the substrate;
A remover supply unit for supplying an etching gas containing fluorine to the substrate;
Provided is a substrate processing apparatus having a control unit for controlling the oxide film material supply unit, the silicon material supply unit, and the removal agent supply unit so as to sequentially supply the oxide film material, the silicon material, and the halogen element. Is done.

<Supplementary Note 51> According to still another aspect,
A processing chamber for accommodating a substrate having a first groove formed between protrusions mainly composed of silicon;
An oxide film material supply unit for supplying an oxide film material to the substrate;
A silicon material supply unit for supplying silicon material to the substrate;
A remover supply unit for supplying an etching gas containing fluorine to the substrate;
Supplying the oxide film raw material to the substrate and forming a second groove in the substrate; supplying the silicon raw material to the substrate to form a film containing silicon as a main component; and the etching gas. The oxide film raw material is sequentially applied to the step of supplying the silicon-based film and removing the silicon-based film other than the silicon-based film on the second trench. There is provided a substrate processing apparatus including a supply unit, a silicon raw material supply unit, and a control unit that controls the removal agent supply unit.

<Supplementary Note 52> The substrate processing apparatus according to Supplementary Note 51, preferably,
The control unit is provided with a substrate processing apparatus for controlling the support unit and the gas supply unit so as to supply the etching gas after the substrate is supported by the support unit.

<Supplementary Note 53> The substrate processing apparatus described in Supplementary Note 51, preferably,
The control unit controls the support unit and the gas supply unit so as to be supported by the substrate support unit during the supply of the etching gas to the substrate.

<Supplementary Note 54> The substrate processing apparatus according to any one of Supplementary Notes 51 to 53, preferably,
A removal agent supply unit for supplying a natural oxide film removal agent to the substrate;
A substrate processing apparatus for controlling the gas supply unit and the removal agent supply unit to supply the removal agent before the etching gas is supplied is provided.

<Supplementary Note 55> According to still another aspect,
A processing chamber for accommodating a substrate on which a protrusion mainly composed of silicon is formed;
An oxide film material supply unit for supplying an oxide film material to the substrate;
A silicon material supply unit for supplying silicon material to the substrate;
A remover supply unit for supplying an etching gas containing fluorine to the substrate;
A substrate processing comprising: a control unit that controls the oxide film material supply unit, the silicon material supply unit, and the removal agent supply unit so as to sequentially supply the oxide film material, the silicon material, and the etching gas containing fluorine. An apparatus is provided.

<Appendix 56> According to still another aspect,
A first groove formed of a protrusion mainly composed of silicon, a second groove formed through an oxide film in the first groove, and the second groove are formed. Carrying a substrate formed with a silicon-based film into a processing chamber;
And supplying an etching gas containing fluorine to the film to remove the film other than the film on the second groove.

This application was filed on Japanese Patent Application No. 2013-219854 filed on October 22, 2013, Japanese Application Patent Application No. 2013-248054 filed on November 29, 2013, and filed on April 30, 2014. The claims of priority are claimed on the basis of Japanese application Japanese Patent Application No. 2014-093751, the entire disclosure of which is incorporated herein by reference.

  The present invention is applied to an etching process which is one process of a next-generation semiconductor device manufacturing process.

1 ... resist pattern, 2 ... Si film (antireflection film), 3 ... CHM film, 4 ... target layer (Si film), 5 ... _Si 3 _{N 4} film, 6 ... SiO ₂ film, 7 ... _Si 3 _{N 4} 8 ... SiO ₂ film, 9 ... Si substrate, 10 ... SiO ₂ film, 11a, 11b ... dummy polysilicon electrode, 11c ... polysilicon film, 11d ... phosphorus doped polysilicon electrode, 11e ... phosphorus doped polysilicon, 12 ... Sidewall spacers, 13 ... Etch stop layer, 14 ... PMD (Pre Metal Dielectric), 15a ... Gate oxide film, 15b ... Oxide film, 16 ... Si-Fin, 17 ... STI (Shallow Trench Isolation), 18 ... Source / drain epitaxial layer, 19 ... silicon substrate, 20 ... substrate processing apparatus, 21 ... groove, 25 ... multilayer hard mask layer, 26 ... be patterned layer, 27 ... SiO ₂ film, 8 ... Si film, 29 ... _Si 3 _{N 4} film, 35 ... SiO ₂ film, 36 ... Si film (etching target film), 37 ... SiO ₂ film, 38 ... Si film, 39 ... CHM film, 43 ... first groove, 44 ... second groove, 45 ... third groove, 60 ... wafer, 61 ... _Si 3 _{N 4} film, 62 ... TiN film (TiN electrode), 63 ... _Si 3 _{N 4} film (for collapse prevention electrode Support part), 64 ... silicon-containing film, 65a ... modified layer, 65b ... interface modified layer, 66 ... embedded film, 67 ... Si hard mask film, 100 ... EFEM, 110 ... FOUP, 120 ... load port, 130 ... air transport Robot, 131 ... Tweezer, 200 ... Load lock chamber, 210 ... Buffer unit, 211 ... Boat, 212 ... Index assembly, 220 ... Buffer unit, 221 ... Boat, 222 ... Index Assembly, 250, 260 ... Load lock chamber, 300 ... Transfer module section, 310 ... Transfer module, 311 to 314 ... Gate valve, 320 ... Vacuum transfer robot, 321 ... Finger, 400 ... Process chamber section, 410 ... First processing Units, 411 ... susceptor table, 413 ... lifter pins, 414 ... support, 430 ... gas buffer chamber, 431 ... processing vessel, 432 ... resonance coil, 433 ... gas inlet, 445 ... processing chamber, 446 ... side wall, 448 ... Base plate, 453 ... O-ring, 454 ... Top plate, 454a ... Lid, 454b ... Support, 458 ... Baffle ring, 459 ... Susceptor, 461 ... Post, 463 ... Heater, 464 ... Susceptor coolant channel, 465 ... Exhaust Plate, 467 ... guide shaft 469 ... Bottom plate, 471 ... Elevating plate, 472 ... Elevating shaft, 473 ... Elevating drive unit, 474 ... First exhaust chamber, 475 ... Exhaust communication hole, 476 ... Second exhaust chamber, 479 ... Pressure adjusting valve, 480 ... Exhaust Pipe, 481 ... Exhaust pump, 482 ... First gas supply unit (first gas supply unit), 482a ... Gas supply pipe, 482b ... First gas source, 482c, 482g ... Mass flow controller, 482d, 482h ... Open / close valve , 482e ... inert gas supply pipe, 482f ... inert gas source, 483 ... second gas supply unit (second gas supply unit), 483a ... gas supply pipe, 483b ... second gas source, 483c ... mass flow controller. 483d: On-off valve, 484 ... Shower plate, 484a ... Plate, 484b ... Hole, 485 ... Heater temperature controller, 486 ... Coolant flow rate control 487 ... heater power supply line, 488 ... temperature detector, 489 ... external coolant channel, 491 ... coolant supply unit, 492 ... coolant temperature detector, 510 ... second processing unit, 511 ... susceptor table 513: Lifter pin, 514: Support portion, 521 ... Resonant coil, 522 ... Movable tap, 523 ... Fixed ground, 524 ... Movable tap, 525 ... High frequency power supply, 526 ... Frequency matching unit, 527 ... RF sensor, 530 ... Plasma Generation chamber, 531 ... reaction vessel, 532 ... outer shield, 533 ... gas inlet, 545 ... treatment chamber, 546 ... side wall, 554 ... top plate, 558 ... baffle ring, 559 ... susceptor, 561 ... strut, 563 ... heater, 565 ... Exhaust plate, 567 ... Guide shaft, 569 ... Bottom plate, 571 ... Elevating plate, 572 ... Elevating shaft 573 ... Elevating drive unit, 574 ... first exhaust chamber, 575 ... exhaust communication hole, 576 ... second exhaust chamber, 579 ... pressure regulating valve, 580 ... exhaust pipe, 581 ... exhaust pump, 582 ... third gas supply unit (Third gas supply unit), 582a ... gas supply pipe, 582b ... third gas source, 582c, 582g ... mass flow controller, 582d, 582h ... open / close valve, 582e ... inert gas supply pipe, 582f ... inert gas source 584 ... baffle plate, 600 ... controller (control unit), 600a ... CPU, 600b ... RAM, 600c ... storage device, 600d ... I / O port, 600e ... internal bus, 601 ... input / output device, 602 ... external storage device 610 ... Silicon oxide film removing device 630 ... Mixing chamber.

Claims (20)

A core pattern forming step for forming a core pattern having a predetermined line width on the substrate surface side, a sidewall forming step for forming a sidewall with respect to the core pattern formed in the core pattern forming step, and after the sidewall forming step, A core pattern removing step of removing the core pattern while leaving the sidewall using an etching gas containing fluorine, and a fine pattern forming method including: in the core pattern removing step, In parallel with the removal, the fine pattern formation method of removing the film deposited on the back side of the substrate in the core pattern formation step. A core pattern forming step for forming a core pattern having a predetermined line width on the substrate surface side, a sidewall forming step for forming a sidewall with respect to the core pattern formed in the core pattern forming step, and after the sidewall forming step, A core pattern removing step of removing the core pattern while leaving the sidewall using an etching gas containing fluorine, and a method of manufacturing a semiconductor device, comprising: In parallel with the removal of the semiconductor device, the semiconductor device manufacturing method of removing the film deposited on the back side of the substrate in the core pattern forming step. A processing chamber for containing a substrate having a core pattern of a predetermined line width and a side wall formed on the core pattern on the front side and a core material film made of the same material as the core pattern on the back side; A gas supply unit that supplies the processing chamber with an etching gas containing fluorine that removes the core pattern while leaving the sidewalls; an exhaust unit that exhausts the atmosphere in the processing chamber; and the removal of the core pattern And a controller that controls the gas supply unit to supply the etching gas to the processing chamber so as to remove the core material film. A step of forming a core pattern having a predetermined line width on the front side of the substrate; a step of forming a side wall with respect to the core pattern; and after forming the side wall, using the etching gas containing fluorine, Removing the core pattern in the state of being left, removing the film deposited on the back side of the substrate when the procedure for forming the core pattern is performed, a program for causing a computer to execute, and a recording medium on which the program is recorded so as to be readable . A film forming process for forming at least a silicon hard mask film, a carbon film, a silicon antireflection film, and a resist film on a substrate; and a resist pattern forming process for processing the resist film to form a resist pattern having a predetermined line width. A carbon film pattern forming step for forming the carbon film pattern using the resist pattern; and a silicon hard mask pattern forming step for forming the silicon hard mask film pattern using the carbon film pattern; When removing the pattern of the silicon hard mask film using an etching gas containing fluorine, a first film of the same material as the silicon antireflection film deposited on the back side of the substrate in the film forming step, Second film of the same material as the carbon film, same material as the silicon hard mask film Third film fine pattern forming method comprising, a silicon hard mask removal step of removing the. A film forming process for depositing a multilayer hard mask film, a silicon hard mask film, a carbon film, a silicon antireflection film, and a resist film on a substrate, and processing the resist film to form a resist pattern having a predetermined line width. A resist pattern forming step, a carbon film pattern forming step for forming the carbon film pattern using the resist pattern, and a silicon hard mask for forming the silicon hard mask film pattern using the carbon film pattern When removing the pattern of the silicon hard mask film using a pattern forming process and an etching gas containing fluorine, a first layer of the same material as the silicon antireflection film deposited on the back side of the substrate in the film forming process is used. 1 film, a second film of the same material as the carbon film, and the silicon heart Method of manufacturing a semiconductor device having a silicon hard mask removing step of removing the third film of the mask layer and the same material, and a pattern forming step of forming a predetermined pattern by using the pattern of the multilayer hard mask layer. A processing chamber for accommodating a substrate on which at least a silicon hard mask film, a carbon film, a silicon antireflection film, and a resist film are deposited; and a third film made of the same material as the silicon hard mask film and the silicon hard mask film A gas supply unit that supplies an etching gas containing fluorine to remove the gas to the processing chamber, an exhaust unit that exhausts the atmosphere in the processing chamber, and a resist pattern having a predetermined line width by processing the resist film A resist pattern forming step, a carbon film pattern forming step for forming the carbon film pattern using the resist pattern, and a silicon hard mask for forming the silicon hard mask film pattern using the carbon film pattern Using a pattern forming step and the etching gas, A controller for performing a silicon hard mask removing step of removing the first film, the second film, and the third film deposited on the back surface side of the substrate when removing the pattern of the mask film And a substrate processing apparatus comprising: A procedure for forming at least a silicon hard mask film, a carbon film, a silicon antireflection film, and a resist film on a substrate; a resist pattern forming procedure for processing the resist film to form a resist pattern having a predetermined line width; A carbon film pattern forming procedure for forming the carbon film pattern using a resist pattern; a silicon hard mask pattern forming procedure for forming the silicon hard mask film pattern using the carbon film pattern; A first film made of the same material as the silicon antireflection film and a second film made of the same material as the carbon film deposited on the back side of the substrate when the pattern of the silicon hard mask film is removed using an etching gas containing And a third film made of the same material as that of the silicon hard mask film. Recording medium in which the readable recording program for executing a down hard mask removal steps, to the computer. On the substrate front side, a substrate carrying step for carrying a substrate having a silicon film formed in a groove portion in which a gate oxide film is formed on the bottom portion and a gate electrode is embedded into a processing chamber, and etching containing fluorine Etching process using gas to remove the silicon film formed in the trench without removing the gate oxide film, and removing the first film of the same material as the silicon film on the back side of the substrate And a substrate carrying-in step of carrying out the substrate subjected to the etching step from a processing chamber. A step of forming a silicon film in a groove portion having a gate oxide film formed at the bottom on the surface of the substrate for embedding a gate electrode; and contacting the substrate with an etching gas containing fluorine, and An etching step of removing the silicon film formed in the groove without removing the film, and removing a first film of the same material as the silicon film on the back side of the substrate. Method. On the front side of the substrate, a processing chamber for accommodating a substrate in which a silicon film is formed in a groove portion in which a gate oxide film is formed at a bottom portion for embedding a gate electrode, and removing the gate oxide film Without removing the silicon film, and on the back side of the substrate, the first film made of the same material as the silicon film is removed. The gas supply unit supplies an etching gas containing fluorine to the processing chamber; and A substrate processing apparatus comprising: an exhaust unit that exhausts the atmosphere of On the front side of the substrate, the gate oxide film is formed by using an etching gas containing fluorine on a substrate in which a gate oxide film is formed at the bottom and a silicon film is formed in the groove for embedding the gate electrode. A recording medium in which a program for causing a computer to execute an etching procedure for removing the first film of the same material as the silicon film on the back side of the substrate is recorded in a readable manner without removing the silicon film. On the front side of the substrate, a silicon film containing a group III or V group impurity is formed in a groove portion in which a Si-Fin structure is formed and a gate oxide film is formed at a bottom portion and a gate electrode is embedded. A substrate carrying-in step of carrying the substrate into the processing chamber, and using the etching gas containing fluorine, the silicon film formed in the trench is removed without removing the gate oxide film, and the substrate On the back side, a fine pattern forming method comprising: an etching step for removing a first film made of the same material as the silicon film; and a substrate carrying-in step for carrying out the substrate subjected to the etching step from a processing chamber. A step of forming a gate electrode by embedding a silicon film containing a group III or V group impurity in a groove portion in which a Si-Fin structure is formed on a substrate surface and a gate oxide film is formed on a bottom portion. And using an etching gas containing fluorine, without removing the gate oxide film, the silicon film formed in the trench is removed, and on the back side of the substrate, a first material of the same material as the silicon film is removed. An etching process for removing the film, and a method for manufacturing a semiconductor device. On the front side of the substrate, a silicon film containing a group III or V group impurity is formed in a groove portion in which a Si-Fin structure is formed and a gate oxide film is formed at a bottom portion and a gate electrode is embedded. A processing chamber for storing the processed substrate; removing the silicon film without removing the gate oxide film; and removing fluorine on the back side of the substrate, the first film made of the same material as the silicon film A substrate processing apparatus comprising: a gas supply unit that supplies an etching gas to the processing chamber; and an exhaust unit that exhausts the atmosphere in the processing chamber. On the front side of the substrate, a silicon film containing a group III or V group impurity is formed in a groove portion in which a Si-Fin structure is formed and a gate oxide film is formed at a bottom portion and a gate electrode is embedded. The silicon film is removed from the formed substrate using an etching gas containing fluorine without removing the gate oxide film, and the first film of the same material as the silicon film is removed on the back side of the substrate. A program for causing a computer to execute an etching procedure and a recording medium on which the program is recorded so as to be readable. Forming a fine pattern of a film containing silicon as a main component, forming a second groove by forming an oxide film on a substrate having a first groove formed between the fine patterns, Forming a film containing silicon as a main component on an oxide film; supplying an etching gas containing fluorine to the film containing silicon as a main component; and forming the silicon on the second groove as a main component Removing a film containing silicon as a main component other than the film to be manufactured. 18. The method of manufacturing a semiconductor device according to claim 17, further comprising a step of removing a natural oxide film formed on the film containing silicon as a main component before the step of supplying the etching gas. A processing chamber for accommodating a substrate having a first groove formed between fine patterns of a film containing silicon as a main component, an oxide film material supply unit for supplying an oxide film material to the substrate, and silicon for the substrate A silicon raw material supply unit for supplying the raw material, a removal agent supply unit for supplying an etching gas containing fluorine to the substrate, a step of supplying the oxide film raw material to the substrate and forming a second groove in the substrate; Supplying the silicon raw material to the substrate to form a film containing silicon as a main component; and supplying the etching gas to the film containing silicon as a main component so that the silicon on the second groove is a main component. And a control unit that controls the oxide raw material supply unit, the silicon raw material supply unit, and the removal agent supply unit so as to sequentially perform a step of removing the silicon-based film other than the film to be formed. Base Processing apparatus. A procedure for forming a fine pattern of a film containing silicon as a main component, and a procedure for forming a second groove by forming an oxide film on a substrate having a first groove formed between the fine patterns; A step of forming a film containing silicon as a main component on the oxide film; and an etching gas containing fluorine is supplied to the film containing silicon as a main component, and the silicon on the second groove is used as a main component. And a recording medium capable of reading a program for causing a computer to execute a procedure for removing the silicon-based film other than the film.