JPWO2014208552A1 - Phase adjustment circuit, image forming apparatus, and phase adjustment method - Google Patents

Abstract

Set the optimum phase with higher accuracy. The phase adjustment unit 30 generates a clock signal having an arbitrarily set phase, and converts serial data into parallel data in accordance with the clock signal generated by the phase shift clock generation unit 31. The phase setting is performed so that the phase shift clock generation unit 31 generates a plurality of clock signals having different phases, respectively, the conversion unit 32 that outputs the data, the determination unit 33 that determines whether the parallel data converted by the conversion unit 32 is correct or incorrect Based on the determination result for each of the parallel data converted by the conversion unit 32 according to each of the plurality of clock signals, the phase range in which the serial data is correctly converted into parallel data by the conversion unit 32 is specified. The optimum phase that is a value within the phase range is set in the phase shift clock generator 31. And a control unit 40, a.

Description

  The present invention relates to a phase adjustment circuit, an image forming apparatus, and a phase adjustment method.

  As a data transmission method, a sequential transmission method (serial transmission method) using a single data stream and a parallel transmission method (parallel transmission method) in which a plurality of data streams are arranged in parallel are widely known. The serial transmission method is superior to the parallel transmission method in that less wiring is required for data transmission and in that data transmission can be performed at higher speed.

In the conversion process for converting serial data transmitted by this serial transmission method into parallel data, the phase of the clock signal in the conversion process is important. Details will be described below.
The input timing of the serial data and the output timing of the parallel data in the conversion unit that converts the serial data into parallel data are synchronized with each other by a clock signal output at a predetermined cycle. In other words, the conversion unit converts serial data into parallel data by performing a process of dividing serial data including a series of parallel data into individual parallel data based on the timing of the clock signal. Here, if the timing of processing by the conversion unit based on the clock signal is too early or too late, the conversion to parallel data will not be successful, and an error in data will occur.
The determination of the processing timing according to the clock signal depends on the phase of the clock signal. More specifically, the phase of the clock signal is an element that determines the start and end timings of the setup time and the hold time, which are data change prohibition times in the operations of the flip-flops and latches related to the operation of the conversion unit. The processing is performed correctly when the start and end timings of the setup time and hold time are appropriate. Here, if the clock signal is out of phase with the arrival timing that is too early or too late with respect to the arrival period of the clock signal allowed for correct data processing, a setup time violation or hold time violation may occur. And processing is not performed correctly.

  The optimum phase of the clock signal in the conversion process (hereinafter referred to as “optimum phase”) is the configuration of the circuit including the conversion unit and the clock signal generation source, the operating environment (temperature, etc.) of the circuit, and the serial data for the circuit. The input timing may vary depending on various factors. Therefore, a phase adjustment circuit that uses a phase pattern closest to the optimum phase among a plurality of predetermined phase patterns for conversion processing is known (for example, Patent Document 1).

JP 2012-65094 A

  However, since the conventional phase adjustment circuit only uses the phase pattern closest to the optimum phase among the plurality of phase patterns, the accuracy of the phase adjustment is low. For this reason, the conventional phase adjustment circuit cannot realize the conversion process using the clock signal having the optimum phase, and may cause a data error due to a setup time violation or a hold time violation.

  It is an object of the present invention to provide a phase adjustment circuit, an image forming apparatus, and a phase adjustment method that can set an optimum phase with higher accuracy.

  The phase adjustment circuit according to the first aspect of the invention includes a generation unit that generates a clock signal having an arbitrarily set phase, and converts serial data into parallel data in accordance with the clock signal generated by the generation unit. The phase of the clock signal generated by the generation unit is controlled based on the determination result by the determination unit, the determination unit for determining whether the parallel data converted by the conversion unit is correct, A control unit, wherein the control unit changes the setting of the phase in the generation unit so that the generation unit generates a plurality of clock signals having different phases, and the control unit changes the phase according to each of the plurality of clock signals. Based on the determination result by the determination unit for each of the parallel data converted by the conversion unit, the serial data is converted by the conversion unit. Lay identifies the scope of the phase to be converted into parallel data, and sets the optimum phase is a value within the range of the phase to the generator.

  The invention according to claim 2 is the phase adjustment circuit according to claim 1, wherein the control unit changes the phase setting in the generation unit so as to shift the phase by a first predetermined angle. The generation unit generates a plurality of clock signals having different phases.

  The invention according to claim 3 is the phase adjustment circuit according to claim 2, wherein the control unit has different correctness determination results by the determination unit before and after shifting the phase by the first predetermined angle. The phase in the generating unit is shifted by a second predetermined angle smaller than the first predetermined angle within a range from a phase before shifting the phase by the first predetermined angle to a phase after shifting the phase by the first predetermined angle. The setting is changed.

  A fourth aspect of the present invention is the phase adjustment circuit according to any one of the first to third aspects, wherein the control unit is configured to control each phase of the plurality of clock signals and the plurality of clock signals. Based on the data stored in the storage unit, a storage unit that stores data in which the determination result of the determination unit by the determination unit is associated with each of the parallel data converted by the conversion unit according to each, A specifying unit for specifying the phase range and the optimum phase, and a phase of the generating unit so that the generating unit generates a plurality of clock signals having different phases until the specifying unit specifies the optimum phase. An instruction unit that outputs an instruction signal for changing the setting to the generation unit, and outputs an instruction signal for setting the optimum phase to the generation unit after the optimum phase is specified. The features.

  A fifth aspect of the present invention is the phase adjustment circuit according to any one of the first to fourth aspects, wherein the control unit sets the parallel data until the optimum phase is set in the generation unit. Test serial data to which additional data for detecting the presence or absence of an error is added is converted by the conversion unit.

  According to a sixth aspect of the present invention, there is provided an image forming apparatus for outputting a recording head, a head driving section for driving the recording head, and serial data corresponding to an ejection pattern of ink ejected from each nozzle of the recording head. And a phase adjustment circuit according to any one of claims 1 to 5, wherein the serial data output from the output unit is converted into parallel data and output to the head drive unit. It is characterized by.

  A seventh aspect of the present invention is the phase adjustment method by the phase adjustment circuit according to any one of the first to fifth aspects, wherein the control unit supplies a plurality of clock signals having different phases to the generation unit. A step of changing the setting of the phase in the generation unit so as to be generated, and the control unit determines whether the determination unit corrects each of the parallel data converted by the conversion unit according to each of the plurality of clock signals. Based on the determination result, the step of specifying a phase range in which the serial data is correctly converted into parallel data by the conversion unit, and the control unit generates the optimum phase corresponding to the median of the phase range And a step of setting in the section.

  According to the present invention, the optimum phase can be set with higher accuracy.

1 is a diagram illustrating an example of a main configuration of an image forming apparatus according to an embodiment of the present invention. It is a figure which shows an example of a structure of a head unit. It is a figure which shows an example of a structure of a phase adjustment part. It is a figure which shows the example of a change of the phase by a phase shift clock generation part. Specific examples of specifying the phase range and the optimum phase when the correct / incorrect determination result of the parallel data converted according to the clock signal generated by the phase shift clock generation unit in the initial state is incorrect (NG) FIG. Specific examples of specifying the phase range and the optimum phase when the correct / incorrect determination result of the parallel data converted according to the clock signal generated by the phase shift clock generation unit in the initial state is correct (OK) FIG. It is a timing chart which shows an example of phase adjustment mode. It is a timing chart which shows an example in the case of switching from a phase adjustment mode to a phase fixed mode. It is a flowchart which shows an example of the flow of the process which concerns on adjustment of a phase. It is a figure which shows the specific example which concerns on the specification of the range of a phase using the 1st predetermined angle and the 2nd predetermined angle, and an optimal phase. It is a figure which shows another example which concerns on the specification of the range of a phase using the 1st predetermined angle and the 2nd predetermined angle, and an optimal phase. FIG. 4 is a diagram illustrating an example of a phase adjustment unit, a head drive unit, and a recording head that are daisy chain connected.

  Embodiments of the present invention will be described below with reference to the drawings. However, although various technically preferable limitations for implementing the present invention are given to the embodiments described below, the scope of the invention is not limited to the following embodiments and illustrated examples.

FIG. 1 is a diagram illustrating an example of a main configuration of an image forming apparatus 1 according to an embodiment of the present invention.
The image forming apparatus 1 includes, for example, an acquisition unit 2, an image processing unit 3, an image forming unit 10, an operation display unit 4, a central control unit 5, and the like.

The acquisition unit 2 acquires image data that is a source of an image formed by the image forming apparatus 1.
Specifically, the acquisition unit 2 has a configuration related to communication such as a network interface card (NIC), for example, and acquires image data transmitted from an external device via communication.

The image processing unit 3 performs image processing on the image data acquired by the acquisition unit 2.
Specifically, the image processing unit 3 is, for example, an integrated circuit such as a programmable logic device (PLD) such as a field-programmable gate array (FPGA) or an application specific integrated circuit (ASIC) or a combination thereof. The image processing according to the function mounted on the circuit is performed. Image processing performed by the image processing unit 3 includes, for example, color conversion processing such as converting an RGB image into a CMYK image, gradation conversion processing such as converting a color image into a monochrome image, and a predetermined number of screen lines. Examples thereof include screen processing for converting an image into halftone dots.

The image processing unit 3 has a data output unit 3a. The data output unit 3a is provided as one function mounted on a circuit constituting the image processing unit 3, for example.
The data output unit 3 a functions as an output unit that outputs serial data corresponding to the ejection pattern of ink ejected from each nozzle of the plurality of recording heads 21.
Specifically, for example, the data output unit 3 a forms a plurality of recording heads 21 in order to form an image corresponding to the image data subjected to image processing by the image processing unit 3 on a recording medium conveyed by the conveyance unit 11. The timing and position at which ink is ejected from each nozzle are calculated. That is, the data output unit 3a calculates an ejection pattern of ink ejected from each nozzle of the plurality of recording heads 21 when an image corresponding to the image data is formed on the recording medium. The data output unit 3a outputs serial data including the ejection pattern. Here, the serial data is partial data corresponding to parallel data to be individually output to a plurality of head driving units 23 (see FIG. 2) provided corresponding to each of the plurality of recording heads 21. Is generated as data including In other words, the serial data is generated so that parallel data can be generated based on the serial data.

Further, the data output unit 3a adds error detection additional data to serial data and outputs the serial data.
The additional data is, for example, data for error detection by a cyclic redundancy check (CRC), but is not limited to this example. The specific method of error detection can be changed as appropriate.
The partial data and additional data in the present embodiment are, for example, 10-bit data, but are only examples and are not limited thereto. Specific configurations of the partial data and the additional data can be changed as appropriate.

The data output unit 3a has a function of outputting test serial data.
The test serial data is dummy data having the same format as the serial data generated based on the image data, and the nozzles of the recording head 21 are not driven according to the test serial data.
The data output unit 3a also generates and adds check data for the test serial data.

  The data output unit 3a also switches a predetermined clock signal (SI_CLK) used when converting serial data into parallel data, an enable signal (DATA_EN) indicating whether serial data is output, and a parallel data output destination. The switching signal (SW) shown is output.

  The data output unit 3a is composed of, for example, an integrated circuit such as PLD or ASIC or a combination thereof, and the function as the data output unit 3a is mounted on the circuit. Instead, it can be changed as appropriate.

The image forming unit 10 forms an image on a recording medium based on the image data subjected to image processing by the image processing unit 3.
Specifically, the image forming unit 10 includes, for example, a head unit 20 provided with a plurality of recording heads 21, a transport unit 11 that transports a recording medium, and a head at a position facing the recording medium transported by the transport unit 11. A carriage 12 for supporting the unit 20 is provided. The image forming unit 10 forms an image by an ink jet recording method in which an image is formed on a recording medium by ejecting ink from nozzles of a plurality of recording heads 21 provided in the head unit 20.

The operation display unit 4 performs various inputs and display outputs related to the operation of the image forming apparatus 1.
Specifically, the operation display unit 4 includes, for example, a touch panel type input display device, up / down / left / right movement keys for performing various selection operations, feeding operations, and the like, although not shown in the drawings. A signal corresponding to the user's operation input is output to the central control unit 5. The operation display unit 4 displays various display contents related to the operation of the image forming apparatus 1 on the input display device under the control of the central control unit 5.

  The central control unit 5 includes, for example, a CPU, a RAM, a ROM, and the like (not shown), and reads and executes various software programs, data, and the like corresponding to the processing contents from a storage device such as a ROM. Various processes related to the operation of the image forming apparatus 1 are performed.

Next, the head unit 20 will be described in more detail with reference to FIG.
The head unit 20 includes, for example, a phase adjusting unit 30 and a plurality of head driving units 23 in addition to the plurality of recording heads 21.

The phase adjustment unit 30 is a phase adjustment circuit that converts the serial data output from the data output unit 3 a into parallel data and outputs the parallel data to the head drive unit 23.
Specifically, the phase adjustment unit 30 acquires the serial data output from the data output unit 3a, converts partial data included in the acquired serial data into parallel data, and each of the plurality of head driving units 23. Output to. Here, the process for determining which head drive unit 23 to output the parallel data is performed based on a predetermined rule. For example, the arrangement order of the partial data included in the serial data may correspond to the arrangement order of the head driving unit 23 corresponding to each partial data, or the correspondence relationship between the parallel data and the head driving unit 23 may be changed. The data shown may be included in the partial data. In the present invention, any other rules that can specify the correspondence between the parallel data and the head driving unit 23 can be adopted as appropriate.

The phase adjustment unit 30 has a function of determining whether the parallel data is correct.
Specifically, the phase adjustment unit 30 generates check data for error detection of parallel data, for example. The check data in the present embodiment is data for determining the correctness of parallel data by using it together with additional data. Therefore, the specific mode of the check data is based on the same method as the error detection method employed for the additional data.
The phase adjustment unit 30 determines whether or not the parallel data includes a data error based on the comparison result between the additional data added to the serial data and the check data generated by the phase adjustment unit 30. . The correspondence between the comparison result and the determination result depends on a specific method of error detection.
If no error is included, the phase adjustment unit 30 determines that conversion to correct parallel data has been performed. If an error is included, the phase adjustment unit 30 determines that conversion to erroneous parallel data has been performed.
The phase adjustment unit 30 has a function of adjusting the phase of the clock signal when converting serial data into parallel data. The phase adjustment unit 30 uses the determination result as to whether or not a data error is included in the parallel data in connection with the phase adjustment. By adjusting the phase, the phase adjusting unit 30 can generate correct parallel data more reliably.
Details of the phase adjustment will be described later.

In addition, wiring for transmitting and receiving various data between the data output unit 3a and the phase adjustment unit 30 is provided.
Specifically, for example, as the wiring corresponding to the data output from the data output unit 3a to the phase adjustment unit 30, a predetermined clock signal (SI_CLK), serial data (SI_DATA), enable signal (DATA_EN), and switching signal (SW Wiring corresponding to each of the above is provided. In addition, a wiring corresponding to a completion signal (DONE) indicating completion of phase adjustment is provided as a wiring corresponding to data output from the phase adjustment unit 30 to the data output unit 3a.
For example, LVDS (Low voltage differential signaling) is adopted as a specific technique related to wiring for transmitting and receiving various types of data between the data output unit 3a and the phase adjustment unit 30. It is not restricted to this, It can change suitably.

The plurality of head driving units 23 are provided corresponding to each of the plurality of recording heads 21, and individually drive the plurality of recording heads 21 in accordance with the parallel data output from the phase adjustment unit 30.
Specifically, the head driving unit 23 includes, for example, a circuit and wiring disposed on a substrate provided in the head unit 20, and corresponds to driving data of pressure generating means such as a piezoelectric element included in parallel data. Then, a drive waveform W for driving pressure generating means (for example, a piezoelectric element) provided corresponding to each nozzle of the recording head 21 is generated and output to the pressure generating means. The pressure generating means operates according to the drive waveform W and ejects ink from the nozzles.
In the present embodiment, the head driving unit 23 directly drives the recording head 21, but this is an example and the present invention is not limited to this. For example, a circuit for driving a plurality of nozzles provided in the recording head 21 may be provided in the recording head 21, and in this case, the head driving unit 23 has a configuration corresponding to the circuit. In such a case, the head driving unit 23 outputs the recording head signal including information indicating the timing for outputting the driving signal to each nozzle, information indicating the amount of ink ejected from each nozzle, a latch signal, and the like. Output for each of. The head driving unit 23 may have a function of supplying a voltage for driving each nozzle of the recording head 21 together with the output of the recording head signal.
Further, the plurality of head drive units 23 may be provided collectively on a single circuit board, and the phase adjustment unit 30 may be provided on this circuit board.

Next, the phase adjustment unit 30 will be described in more detail with reference to FIG. In FIG. 3, for the sake of convenience, only one head driving unit 23 is illustrated.
The phase adjustment unit 30 includes a phase shift clock generation unit 31, a conversion unit 32, a determination unit 33, a phase control unit 40, and the like.

The phase shift clock generation unit 31 functions as a generation unit that generates a clock signal having an arbitrarily set phase.
Specifically, for example, as illustrated in FIG. 4, the phase shift clock generation unit 31 arbitrarily changes the phase of a predetermined clock signal (SI_CLK) output from the data output unit 3 a. In FIG. 4, the clock signal C2 whose phase is changed so as to shift the phase by Δθ with respect to the clock signal C1 or the clock signal C3 whose phase is changed so as to be shifted by Δθ with respect to the clock signal C2 is shifted. Is illustrated. In FIG. 4, the degree of phase change is indicated by Δθ, but the phase shift clock generation unit 31 can arbitrarily change Δθ.
In addition, the phase shift clock generation unit 31 outputs the clock signal (CLK_θ) generated by the phase shift clock generation unit 31 to the conversion unit 32. Further, the phase shift clock generation unit 31 outputs an enable signal (CLK_EN) indicating whether or not the clock signal is output together with the clock signal (CLK_θ) to the conversion unit 32.
The phase shift clock generation unit 31 includes an electronic circuit such as a PLL (phase locked loop), for example. However, the phase shift clock generation unit 31 is an example and is not limited thereto, and can be changed as appropriate.

The degree of phase change by the phase shift clock generator 31 is determined in advance, for example.
As an example, when the minimum unit of phase change (phase shift interval) is 20 [psec], the degree of change of the phase of the clock signal is in increments of 0.72 [°].
The above example is set for convenience in the present embodiment, and is not limited to this, and can be changed as appropriate according to the accuracy required for setting the optimum phase.

  Further, the degree of phase change in the initial state of the phase shift clock generation unit 31 can be arbitrarily set and changed. In the present embodiment, the phase shift clock generation unit 31 in the initial state generates a clock signal in which the phase of a predetermined clock signal (SI_CLK) is maintained as it is without changing the phase.

The conversion unit 32 converts serial data into parallel data according to the clock signal generated by the phase shift clock generation unit 31 and outputs the parallel data.
Specifically, the conversion unit 32 parallelizes the serial data (SI_DATA) output from the data output unit 3a in accordance with the processing timing determined by the clock signal (CLK_θ) generated by the phase shift clock generation unit 31. Serial data is converted into parallel data by performing a process of dividing the data.
The conversion unit 32 outputs parallel data. Further, the conversion unit 32 outputs an enable signal (P_VALID) indicating whether or not parallel data is output together with the parallel data.

  When an appropriate phase is set for the clock signal (CLK_θ), when the timing of processing by the conversion unit 32 according to the clock signal is appropriate, processing for converting serial data into parallel data is correctly performed, Correct parallel data can be obtained. On the other hand, if an appropriate phase is not set for the clock signal, the timing of processing by the conversion unit 32 corresponding to the clock signal is inappropriate, conversion to parallel data is not successful, and data error occurs. It becomes.

The determination unit 33 determines whether the parallel data converted by the conversion unit 32 is correct.
Specifically, the determination unit 33 generates, for example, check data for parallel data (P_DATA) converted and output by the conversion unit 32. The determination unit 33 compares the check data with the additional data added to the serial data, and determines whether the parallel data is correct based on the comparison result.

The determination unit 33 performs output according to the determination result of the parallel data.
Specifically, for example, the determination unit 33 outputs (OK) indicating that conversion to correct parallel data has been performed or output (NG) indicating that an error in data has occurred in conversion to parallel data. Is output to the phase control unit 40. Further, in the present embodiment, the determination unit 33 indicates information indicating the phase of the clock signal (CLK_θ) generated by the phase shift clock generation unit 31 and the correct / incorrect determination result of the parallel data converted at the phase. The information (OK or NG) is associated and output to the phase control unit 40.
Since the determination result of “OK” or “NG” can be expressed by binary (1 or 0), the determination result of parallel data correctness / incorrectness can be expressed by at least 1 bit. It is not restricted to this, It can change suitably.

The phase control unit 40 controls the phase of the clock signal generated by the phase shift clock generation unit 31 so that the serial data is correctly converted into parallel data by the conversion unit 32 based on the determination result by the determination unit 33. It functions as a part.
The phase control unit 40 includes, for example, a storage unit 41, a specifying unit 42, an instruction unit 43, and the like.

The storage unit 41 is a data in which each phase of a plurality of clock signals is associated with a correct / incorrect determination result by the determination unit 33 for each of parallel data converted by the conversion unit 32 according to each of the plurality of clock signals. Remember.
Specifically, the storage unit 41 includes, for example, a storage device configured by a flash memory or the like. The determination result output from the determination unit 33, that is, information indicating the phase of the clock signal (CLK_θ) and the phase The data associated with the information (OK or NG) indicating the correctness / incorrectness determination result of the parallel data converted in (1) is stored.

The specifying unit 42 specifies the phase range and the optimum phase based on the data stored in the storage unit 41.
Specifically, for example, the specifying unit 42 reads data stored in the storage unit 41 and specifies the phase range associated with the determination result “OK”. Then, the specifying unit 42 calculates a value within the specified phase range as the optimum phase.
More specifically, the specifying unit 42 sets, for example, the phase corresponding to the median value of the specified phase range as the optimum phase.

Specific examples of the phase range and the optimum phase will be described with reference to FIG.
In the example shown in FIG. 5, a determination result of “OK” is obtained within the phase range of 72 to 144 [°], and a determination result of “NG” is obtained in the other range. In this case, the specifying unit 42 specifies the phase range of 72 to 144 [°] as the phase range associated with the determination result “OK”. Further, the specifying unit 42 sets the phase of 108 [°] corresponding to the median of the phase range of 72 to 144 [°] as the optimum phase.

  The instruction unit 43 changes the phase setting in the generation unit so that the generation unit (phase shift clock generation unit 31) generates a plurality of clock signals having different phases until the optimum phase is specified by the specification unit 42. An instruction signal is output to the generation unit.

  For example, in the case of the example shown in FIG. 5, a determination result of “NG” is obtained at the phase of 0 [°] generated in the initial state of the phase shift clock generation unit 31. The phase is sequentially shifted until the range of phases in which the determination result “OK” necessary for specifying the optimum phase is obtained is specified. Specifically, the instruction unit 43 shifts the phase to one side (for example, the positive direction (right side in FIG. 5 and the like)) by a predetermined degree of phase change (for example, 0.72 [°]). Instruction signals (signals indicated by “shift instruction” in FIG. 3) are sequentially output.

The phase shift clock generation unit 31 sets the phase of the clock signal (CLK_θ) according to the instruction signal from the instruction unit 43. Further, the phase shift clock generation unit 31 outputs a signal indicating that the setting has been completed (a signal indicated by “shift completion” in FIG. 3) to the phase control unit 40.
Thereafter, the phase shift clock generation unit 31 outputs a clock signal (CLK_θ) having a newly set phase. The conversion unit 32 converts serial data into parallel data in accordance with a clock signal (CLK_θ) having a newly set phase. The determination unit 33 determines whether the parallel data converted in accordance with the newly set phase clock signal (CLK_θ) is correct. The storage unit 41 of the phase control unit 40 stores the newly set phase of the clock signal and the correct / incorrect determination result of the parallel data converted by the conversion unit 32 in accordance with the clock signal.
The operation of each unit accompanying the setting of a new phase is performed each time an instruction signal for changing the phase setting is output from the instruction unit 43.
Thus, the phase control unit 40 changes the phase setting in the generation unit (phase shift clock generation unit 31) so as to shift the phase by a first predetermined angle (for example, 0.72 [°]), respectively. A generation unit generates a plurality of clock signals having different phases.

In the case of the example illustrated in FIG. 5, the determination result of “NG” is continuously obtained until the phase of 0 [°], which is the initial state, is set to 72 [°]. When the phase of 72 [°] is set, a determination result of “OK” is obtained. Thereafter, the determination result of “OK” is continuously obtained up to the phase of 144 [°]. Thereafter, when it exceeds 144 [°], the determination result of “NG” is obtained again. When the phase of the clock signal exceeds 144 [°] and the determination result of “NG” is obtained again, the lower limit (for example, 72 [°]) and upper limit (for example, 72 [°]) of the determination result of “OK” are obtained. 144 [°]) is specified. Therefore, the specifying unit 42 specifies the phase range (72 to 144 [°]) indicated by the lower limit and the upper limit of the phase, and optimizes a value within the range (for example, the median value 108 [°]). Phase.
It should be noted that the phase change intervals shown in FIG. 5 and the like are schematic for explanation only, and the actual phase change intervals depend on the degree of phase change according to the instruction signal.

The instruction unit 43 outputs an instruction signal for setting the optimum phase to the phase shift clock generation unit 31 after the optimum phase is specified by the specifying unit 42.
Specifically, the instruction unit 43 ends the output of the instruction signal for sequentially shifting the phase that has been performed until the optimum phase is specified, and outputs the instruction signal for setting the optimum phase to the phase shift clock generation unit To 31. In the case of the example illustrated in FIG. 5, the instruction unit 43 outputs an instruction signal for setting the phase to 108 [°].
Thus, the phase control unit 40 changes the phase setting in the generation unit so that the generation unit (phase shift clock generation unit 31) generates a plurality of clock signals having different phases, and each of the plurality of clock signals. Based on the correct / incorrect determination result by the determination unit 33 for each of the parallel data converted by the conversion unit 32, the phase range in which the serial data is correctly converted into parallel data by the conversion unit 32 is specified, and the phase An optimum phase that is a value within the range is set in the generation unit.

  In the above, until the determination of the optimum phase when the correct / incorrect determination result of the parallel data converted according to the clock signal (CLK_θ) generated by the phase shift clock generation unit 31 in the initial state is “NG”. Although the output pattern of the instruction signal has been described with reference to FIG. 5, the output pattern of the instruction signal until the optimum phase is specified is not limited to this. Another pattern will be described with reference to FIG.

In the case of the example shown in FIG. 6, a determination result of “OK” is obtained with a phase of 0 ° that is the initial state. In this case, the instruction unit 43 sets the phase to one side (for example, in the positive direction) by a predetermined degree of phase change (for example, 0.72 [°]) until the determination result of “NG” is obtained. An instruction signal for shifting is sequentially output.
In the example shown in FIG. 6, the determination result of “OK” is continuously obtained up to a phase of 36 °. When a phase exceeding 36 [°] is set, a determination result of “NG” is obtained. As a result, the phase range (for example, the upper limit) from which the determination result of “OK” is obtained for one side is specified, and thus the instruction unit 43 shifts the phase to one side (for example, the positive direction). The output of the instruction signal is terminated.

Next, the instruction unit 43 proceeds to a process for specifying a phase range (for example, a lower limit) in which a determination result of “OK” is obtained for the other (for example, the negative direction (left side in FIG. 6 and the like)).
Specifically, the instruction unit 43 sets, for example, a phase (for example, −0.72 [°]) obtained by shifting the phase to the other one time from the initial phase of the phase shift clock generation unit 31. The instruction signal is output. In response to the instruction signal, the phase set in the phase shift clock generation unit 31 is −0.72 [°]. If a determination result of “NG” is obtained for the phase, the phase range (for example, the lower limit) where the determination result of “OK” is obtained in the other direction (for example, the negative direction (left side in FIG. 6 and the like)) is obtained. Since the instruction unit 43 ends the output of the instruction signal for shifting the phase, if the determination result of “OK” is obtained in the phase, the instruction unit 43 Until the determination result “NG” is obtained, an instruction signal for shifting the phase in the other direction (for example, in the negative direction) is sequentially output.

In the case of the example illustrated in FIG. 6, the determination result of “OK” is continuously obtained up to the phase of −36 [°]. Thereafter, when the value is below −36 [°], a determination result of “NG” is obtained. Therefore, the output of the instruction signal for shifting the phase to the other side (for example, in the negative direction) is continued until it falls below −36 [°], and the phase of −36 [°] is determined to be “OK” for the other. The range of phases from which the result is obtained is specified. In this case, the optimum phase (for example, the median value) is 0 [°].
In this way, the instruction unit 43 changes the output pattern of the instruction signal so that the optimum phase is specified with a smaller number of instruction signal outputs, according to the determination result of the parallel data obtained first. .

  The conversion unit 32, the determination unit 33, and the phase control unit 40 include, for example, an integrated circuit such as PLD or ASIC or a combination thereof, and functions corresponding to these units are mounted on the circuit. However, the present invention is not limited to this, and can be changed as appropriate.

Next, the operation of the phase adjustment unit 30 before and after setting the optimum phase will be described.
The phase adjustment unit 30 operates in the phase adjustment mode until the optimum phase is set in the phase shift clock generation unit 31. In the phase adjustment mode, the data output unit 3a outputs test serial data. In this case, the phase adjustment unit 30 uses the test serial data to convert the serial data to parallel data, determine whether the parallel data is correct, specify the optimum phase based on the determination result, and set the optimum phase. Perform various processes. In the phase adjustment mode, the parallel data is not output to the head drive unit 23.
Further, the phase adjustment unit 30 operates in the phase fixed mode when the optimum phase is set in the phase shift clock generation unit 31. In the phase fixing mode, the phase of the phase shift clock generator 31 is fixed at the optimum phase. In the phase fixing mode, the data output unit 3a outputs serial data including an ejection pattern generated based on the image data. In this case, the phase adjustment unit 30 converts the serial data into parallel data and outputs the parallel data to the head driving unit 23. Each of the plurality of recording heads 21 operates according to parallel data.
The phase adjustment unit 30 has a function for switching between the phase adjustment mode and the phase fixed mode. Specifically, for example, the phase control unit 40 switches between the phase adjustment mode and the phase fixing mode depending on whether or not a signal (DONE) is output. The data output unit 3a switches the serial data to be output according to the signal.

More specifically, for example, as shown in FIG. 7A, when the DONE signal is not output, the data output unit 3a outputs test serial data. The test serial data includes test partial data TD1, TD2,... TDn (for example, n = 512) converted to parallel data and additional data (CRC). The phase adjustment unit 30 uses the test serial data to convert various serial data into parallel data, determine whether the parallel data is correct, determine the optimal phase based on the determination result, and set the optimal phase. I do.
When the optimum phase is set in the phase shift clock generator 31, a DONE signal is output as shown in FIG. 7B. In this case, the data output unit 3a sets the serial data to be output as serial data including partial data HD1, HD2,... Corresponding to the ejection pattern of each recording head 21 generated based on the image data. When switching from the test serial data to the serial data including the ejection pattern, the serial data is temporarily not output. At this time, whether or not an enable signal (DATA_EN) indicating whether or not serial data is output is also linked to whether or not serial data is output.
As described above, the phase control unit 40 converts the test serial data to which the additional data for detecting the presence or absence of the parallel data error is added until the optimum phase is set in the phase shift clock generation unit 31. To convert to

In addition, as the optimum phase is set in the phase shift clock generation unit 31, a signal (Mode) for initialization is output from the phase control unit 40 to the determination unit 33.
As the optimum phase is set in the phase shift clock generation unit 31, a switching signal (SW) indicating switching of the output destination of parallel data is output from the data output unit 3a. When the switching signal (SW) is output, the conversion unit 32 outputs parallel data to the head driving unit 23. In FIG. 3, the parallel data output to the head driving unit 23 is indicated by “DONE_P_DATA”. Further, the conversion unit 32 outputs a latch signal (DATA_LAT) to the head drive unit 23 together with the parallel data.

Further, an initialization signal (CTL_st) is output to the phase control unit 40 from a CPU or register (not shown) provided in the phase adjustment unit 30 before the phase adjustment mode is started. The initialization signal is also output to the phase shift clock generation unit 31. The stored content related to the past determination result stored in the storage unit 41 of the phase control unit 40 is deleted by the initialization signal. Further, the phase shift clock generation unit 31 is in an initial state by the initialization signal, and the phase setting is in the initial state (for example, 0 [°]).
In the present embodiment, the phase control unit 40 outputs the initialization signal (CTL_st) to the phase shift clock generation unit 31. However, this is an example, and the present invention is not limited to this, and can be changed as appropriate. For example, the initialization signal (CTL_st) may be output to the phase shift clock generation unit 31 directly from a CPU or register (not shown) provided in the phase adjustment unit 30.

Next, an example of the flow of processing related to phase adjustment will be described with reference to the flowchart of FIG.
Until the output of serial data from the data output unit 3a is started, the phase adjustment unit 30 stands by in the phase adjustment mode (step S1, step S2: NO). Thereafter, when test serial data is output from the data output unit 3a and the enable signal (DATA_EN) indicating whether serial data is output becomes high (HIGH: “H”) (step S2: YES), the conversion unit 32 converts the serial data into parallel data (step S3), the determination unit 33 determines whether the parallel data is correct (step S4), and outputs the determination result to the phase control unit 40. Along with the output of the determination result, the determination unit 33 outputs information indicating the phase of the clock signal from which the determination result is obtained to the phase control unit 40.

The storage unit 41 of the phase control unit 40 stores the determination result (step S5). In step S <b> 5, the storage unit 41 stores data in which the phase of the clock signal is associated with the correct / incorrect determination result by the determination unit 33 for the parallel data converted by the conversion unit 32 according to the clock signal of the phase. Remember.
The specifying unit 42 specifies the phase range based on the determination result stored in the storage unit 41. If the determination result sufficient for specifying the phase range is not stored in the storage unit 41 and the phase range cannot be specified (step S6: NO), the instruction unit 43 shifts the phase. An instruction signal for outputting the signal is output (step S7). After step S7, the process proceeds to step S3.
In step S7, the identification of the phase range is completed (step S6: YES), and the identification of the optimum phase that is a value within the phase range (for example, the median value) is completed, the phase shift clock generator 31 The optimum phase is set (step S8), and the phase adjusting unit 30 shifts to the phase fixing mode (step S9).

  As described above, according to the image forming apparatus 1 of the present embodiment, the phase range in which serial data is correctly converted into parallel data by the conversion unit 32 is specified, and the optimum phase that is a value within the phase range is determined as the phase shift clock. Since it is set in the generation unit 31, the optimum phase can be set with higher accuracy, so that serial data can be converted into parallel data with a more appropriate setup time and hold time, and serial data is converted into parallel data. The accuracy of conversion to be converted can be further increased.

  Further, the phase shift clock generator 31 changes the phase setting so that the phase is shifted by a first predetermined angle (for example, 0.72 [°]), thereby generating a plurality of clock signals having different phases. Since it is generated by the unit 31, a plurality of clock signals having different phases can be generated by the phase shift clock generation unit 31 by a simple method of repeating a shift instruction for shifting the phase. A process for setting the optimum phase can be performed.

  Further, the storage unit 41 associates each phase of the plurality of clock signals with the correct / wrong determination result by the determination unit 33 for each of the parallel data converted by the conversion unit 32 according to each of the plurality of clock signals. Until the specifying unit 42 specifies the phase range and the optimum phase based on the data stored in the storage unit 41, and the instruction unit 43 specifies the optimum phase by the specifying unit 42. An instruction signal for changing the phase setting in the phase shift clock generation unit 31 is output to the phase shift clock generation unit 31 so that the phase shift clock generation unit 31 generates a plurality of clock signals having different phases, and the optimum phase is specified. After that, the instruction signal for setting the optimum phase is output to the phase shift clock generation unit 31, so that it changes according to each of the plurality of clock signals. The phase range and the optimum phase can be identified based on the correctness / incorrectness determination result of the parallel data, and the identified optimum phase can be set in the phase shift clock generation unit 31, so that the optimum phase can be set with higher accuracy. can do.

Further, until the optimum phase is set in the phase shift clock generation unit 31, the test serial data to which additional data for detecting the presence or absence of errors in parallel data is added is converted into parallel data by the conversion unit 32. When obtaining the parallel data to be actually used, the optimum phase can be already set, and the optimum phase can be set without causing a wasteful operation on the device using the parallel data (for example, the recording head 21). Can be set.
Of the transmission paths between the data output unit 3a that is a data transmission source and the plurality of head drive units 23 that are a plurality of data transfer targets, from the data output unit 3a to the phase adjustment unit 30 that is a branch point. In the transmission path, serial data including data for all of the plurality of head driving units 23 is transmitted by a serial transmission method, and the serial data is converted into parallel data which is data for each of the plurality of head driving units 23 by the phase adjustment unit 30. By performing conversion processing for conversion and transmitting the converted parallel data from the phase adjustment unit 30 to each of the plurality of head driving units 23, the advantage of the serial transmission method can be utilized.

  The embodiment of the present invention should be considered that the embodiment disclosed this time is illustrative and not restrictive in all respects. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

For example, the optimum phase in the above-described embodiment is a phase corresponding to the median value among the values within the phase range, but is not limited to this example. The optimum phase is a value within the range of the phase and may be any phase that can ensure the accuracy of conversion for converting serial data into parallel data.
Specifically, for example, the optimum phase can be converted from serial data to parallel data more reliably in consideration of various fluctuation factors that may occur in relation to the operation of the phase adjustment circuit among the values within the specified phase range. It may be a value within the range of the phase that can be converted. As various variable factors, for example, the characteristics (temperature characteristics) of the operation of the phase adjustment circuit that can change according to the temperature, the jitter of various signals related to the operation of the phase adjustment circuit, and the operation of the phase adjustment circuit are applied. Voltage fluctuations.
As a specific example, when the specified phase range is set to 100 [%], the phase control unit 40 corresponds to any value within a range of ± 45 [%] from the median value of the phase range. The phase may be set as the optimum phase. In this case, in consideration of various fluctuation factors, it is better not to actively adopt the optimum phase as the optimum phase in order to more reliably satisfy the setup time and hold time related to the process of converting serial data into parallel data. The range is a range corresponding to 5% at both ends close to the upper limit or lower limit of the specified phase range, and is excluded from the range of values set as the optimum phase.

  In the above description, the first predetermined angle is the degree of phase change (0.72 [°]) of the clock signal corresponding to the minimum unit of phase change. However, this is an example, and the present invention is not limited to this. The first predetermined angle can be arbitrarily set. A greater degree of phase change (for example, 7.2 [°] or the like) may be set as the first predetermined angle.

  In addition, the phase control unit 40 shifts the phase by the first predetermined angle from the phase before shifting the phase by the first predetermined angle when the determination result of the determination unit 33 is different before and after shifting the phase by the first predetermined angle. The phase setting in the phase shift clock generator 31 may be changed so as to be shifted by a second predetermined angle smaller than the first predetermined angle within the range up to the first phase.

Specifically, for example, as shown in FIGS. 9 and 10, the first predetermined angle set to have a phase change degree (for example, 7.2 [°]) larger than the minimum unit of phase change. May be used. In this case, the instruction unit 43 first sequentially outputs an instruction signal for shifting the phase to one side by the same shift instruction as in the above embodiment. Accordingly, the phase is shifted by a degree of phase change (for example, 7.2 [°]) larger than the minimum unit of phase change.
Here, as shown in FIG. 9, the determination result switches from “NG” to “OK” between 7.2 [°] and 14.4 [°], and 72 [°] and 79.2 [°]. When the determination result is switched from “OK” to “NG” between the determination unit 43 and the instruction unit 43, each of the instruction units 43 is smaller than the first predetermined angle from the phase before the determination result is switched to the phase after the determination result is switched. 2 The phase setting in the phase shift clock generator 31 is changed so as to be shifted by a predetermined angle (for example, 0.72 [°]). In the case of FIG. 9, the determination result of “NG” is obtained up to 7.92 [°], and the determination result of “OK” is obtained from 8.64 [°]. Further, a determination result of “OK” is obtained up to 77.76 [°], and a determination result of “NG” is obtained again from 78.48 [°]. In this case, the phase range is specified as 8.64 to 77.76 [°], and the optimum phase is 43.2 [°].

As shown in FIG. 10, even when the correct / incorrect determination result of the parallel data converted according to the clock signal generated by the phase shift clock generation unit 31 in the initial state is “OK”, the first predetermined An angle and a second predetermined angle smaller than the first predetermined angle can be used.
Specifically, for the phase shifted to one side (for example, in the positive direction) with respect to the phase of the clock signal generated by the phase shift clock generation unit 31 in the initial state, the determination result of “OK” is obtained. Until a range (for example, upper limit) is specified, first, using a first predetermined angle set to be a degree of phase change (for example, 7.2 [°]) larger than the minimum unit of phase change. In response to a shift instruction similar to that described with reference to FIG. 6, an instruction signal for shifting the phase to one side is sequentially output. Then, after the phase before and after the determination result is switched from “OK” to “NG” is specified, the second predetermined smaller than the first predetermined angle from the phase before the determination result is switched to the phase after the determination result is switched. The phase setting in the phase shift clock generation unit 31 is changed so as to be shifted by an angle (for example, 0.72 [°]).
Similarly, when the phase is shifted in the other direction (for example, in the negative direction) with respect to the phase of the clock signal generated by the phase shift clock generation unit 31 in the initial state, the first predetermined angle and the first predetermined angle are similarly used. A small second predetermined angle can be used.
In the example shown in FIGS. 9 and 10, the phase change using the second predetermined angle is performed with a smaller phase within a range in which the determination result of the parallel data obtained using the first predetermined angle is different. However, the present invention is not limited to this example, and can be changed as appropriate.

  If the determination result by the determination unit 33 is different before and after the phase is shifted by the first predetermined angle, the first predetermined angle from the phase before the phase is shifted by the first predetermined angle to the phase after the phase is shifted by the first predetermined angle. By changing the phase setting in the phase shift clock generation unit 31 so as to shift by a smaller second predetermined angle, it is implemented in accordance with the number of phase setting changes and the phase setting change until the optimum phase is set. The number of executions of various processes such as conversion of serial data to parallel data, determination of correctness of parallel data, and storage of determination results can be reduced, and the processing load related to the setting of the optimum phase can be further reduced. .

  In the above embodiment, the test serial data is used until the optimum phase is set. However, the present invention is not limited to this. For example, serial data that is actually used may be used until the optimum phase is set. In this case, for example, the parallel data is transmitted to the parallel data output target (for example, the head drive unit 23) until the optimum phase is set by the switching signal (SW) indicating the switching of the parallel data output destination. By taking measures such as preventing this, it is possible to prevent parallel data including an error from being transmitted to an output target.

Further, the optimum phase may be reset after the optimum phase is set.
For example, in the above-described embodiment, when the determination of the parallel data is continued by the determination unit 33 even after shifting to the phase fixing mode, and the determination result of “NG” is obtained, the parallel data output target ( For example, the output of parallel data to the head drive unit 23) may be stopped and the optimum phase may be set again. Then, after the resetting of the optimum phase is completed, the parallel data output to the parallel data output target may be resumed. In this case, the parallel data is output to a configuration (for example, the data output unit 3a) that holds the serial data that has been stopped to output parallel data by some means (for example, a buffer) or outputs serial data. The serial data that is stopped is output again. In addition, as in the present embodiment, when image formation is performed by outputting parallel data to the head driving unit 23 of the image forming apparatus 1, the parallel data output is stopped and restarted, and each unit that operates in association with image formation (for example, And the operation of the transport unit 11 and the like).

  Further, a memory may be provided between the data output unit 3a and the phase adjustment unit 30. For example, by providing a FIFO (First In, First Out) memory between the data output unit 3 a and the phase adjustment unit 30, serial data output by the data output unit 3 a and serial data by the conversion unit 32 of the phase adjustment unit 30 are provided. It becomes possible to operate even if the conversion to parallel data is asynchronous. That is, the operating frequencies of the data output unit 3a and the phase adjusting unit 30 can be set to arbitrary operating frequencies individually. The memory can also function as the buffer.

  In the above-described embodiment, the enable signal such as an enable signal (DATA_EN) indicating whether serial data is output or an enable signal (CLK_EN) indicating whether a clock signal is output is indicated by the enable signal. The data is transmitted using a separate wiring, but this is an example and the present invention is not limited to this. For example, the presence / absence of output of the data may be detected in the reception target of the data in accordance with the enable signal added to the head of the data indicated by the enable signal. In this case, the wiring for the enable signal can be omitted.

  In the above embodiment, the phase control unit 40 directly sets the optimum phase for the phase shift clock generation unit 31. However, the phase control unit 40 is an example, and the present invention is not limited to this. For example, the phase control unit 40 may transmit information indicating the optimum phase to a configuration that outputs serial data, such as the data output unit 3a. In this case, information indicating the frequency of the clock signal used when converting the serial data into parallel data and the optimum phase of the clock signal are added to the serial data. The phase shift clock generation unit 31 is set with the frequency of the clock signal added to the serial data and the optimum phase of the clock signal.

  In the above embodiment, the determination unit 33 determines the correctness of the parallel data using the additional data of the serial data, but this is an example and the present invention is not limited to this. For example, the determination unit 33 may determine whether the parallel data is correct or not based on whether or not the parallel data header or footer has a predetermined data arrangement. In this case, additional data is unnecessary. In addition, other methods that currently exist or other methods that can be developed in the future can be adopted as long as they can detect errors in parallel data.

In the above embodiment, the case where a plurality of recording heads 21 and a plurality of head driving units 23 are provided is illustrated, but this is an example and the present invention is not limited thereto. For example, one recording head 21 and one head driving unit 23 may be provided.
In the above-described embodiment, each configuration of the data output unit 3a, the phase adjustment unit 30, and the head drive unit 23 is 1: 1: n (n ≧ 2), and the plurality of head drive units 23 have the phase adjustment. Although the case where it connects in parallel with respect to the part 30 is illustrated, it is an example and it is not restricted to this.
For example, a plurality of head driving units 23 may be connected to the phase adjusting unit 30 in series. In the case of serial connection, the parallel data converted by the phase adjustment unit 30 is directly transmitted to the foremost head drive unit 23 connected directly to the phase adjustment unit 30, but the subsequent subsequent stage head drive unit 23 is sequentially transmitted through the head drive unit 23 in the preceding stage.
Even in such a series connection, parallel data converted by the clock signal having the optimum phase is transmitted by the phase adjustment unit 30, so that no data error occurs in the plurality of head drive units 23. Parallel data with small skew can be transmitted.
Further, in the above embodiment, the case where each configuration of the data output unit 3a, the phase adjustment unit 30, and the head drive unit 23 is 1: 1: n (n ≧ 2) is illustrated as an example. It is not limited to this.
For example, each configuration of the data output unit 3a, the phase adjustment unit 30, and the head drive unit 23 may be 1: n: n (n ≧ 2). In this case, the head driving unit 23 and the corresponding phase adjustment unit 30 may be provided together on one circuit board. In addition, the plurality of phase adjustment units 30 may be connected in parallel to the data output unit 3a, or may be connected in series (daisy chain connection) as shown in the example of FIG. By connecting in series, the number of wirings between the data output unit 3a and the plurality of phase adjustment units 30 can be reduced as compared with the case of connecting in parallel. Although not shown in FIG. 11, a wiring similar to that shown in FIG. 2 is provided between the data output unit 3a and the phase adjustment unit 30 connected in a daisy chain.
For example, when the plurality of head driving units 23 are connected in series and serial / parallel conversion is performed by each head driving unit without providing the phase adjusting unit 30, the serial data transmitted from the data output unit 3a is stored in the plurality of heads. Since the signal is transmitted via the drive unit 23 sequentially, a delay occurs as the head drive unit 23 in the subsequent stage of the serial connection is caused by the propagation characteristics of the transmission path, and the optimum phase of the clock signal in the conversion processing to parallel data Shifts and adversely affects the accuracy of the conversion process. On the other hand, by providing a plurality of phase adjusting units 30 connected in series corresponding to each of the plurality of head driving units 23, the phase adjusting units 30 provided corresponding to the respective head driving units 23 respectively. The optimal phase can be set with high accuracy and parallel conversion can be performed, and deterioration in accuracy of conversion processing due to delay can be prevented.

  Further, the output target of parallel data is not limited to the head drive unit 23, and can be applied to any device that involves processing for converting serial data into parallel data.

Further, serial data may be further generated from parallel data converted from serial data. In this case, for example, the converted parallel data is subjected to predetermined processing (for example, data editing), and the parallel data subjected to the predetermined processing is serialized again for transmission using the serial data transmission path. Operation such as conversion to data can be considered.
In addition, the specific configuration of the acquisition unit 2 described above is an example and is not limited thereto. The acquisition unit 2 may include various interfaces to which a storage device such as a hard disk or a flash memory card can be connected.
In addition, the specific configuration of the embodiment of the present invention can be changed as appropriate without departing from the characteristics of the present invention.

Industrial applicability

  The present invention can be used for a phase adjustment circuit, an image forming apparatus, and a phase adjustment method.

DESCRIPTION OF SYMBOLS 1 Image forming apparatus 2 Acquisition part 3 Image processing part 3a Data output part 4 Operation display part 5 Central control part 10 Image formation part 11 Carrying part 12 Carriage 20 Head unit 21 Recording head 23 Head drive part 30 Phase adjustment part 31 Phase shift clock Generator (Generator)
32 conversion unit 33 determination unit 40 phase control unit (control unit)
41 Storage unit 42 Identification unit 43 Instruction unit

Claims (7)

A generator for generating a clock signal having an arbitrarily set phase;
In accordance with the clock signal generated by the generation unit, a conversion unit that converts serial data into parallel data and outputs the parallel data,
A determination unit that determines whether the parallel data converted by the conversion unit is correct or not;
A control unit that controls a phase of a clock signal generated by the generation unit based on a determination result by the determination unit;
The control unit changes the setting of the phase in the generation unit so that the generation unit generates a plurality of clock signals having different phases, and the parallel converted by the conversion unit according to each of the plurality of clock signals Based on the correct / incorrect determination result by the determination unit for each piece of data, the conversion unit specifies a phase range in which the serial data is correctly converted into parallel data, and an optimum phase that is a value within the phase range is determined. A phase adjustment circuit set in the generation unit.   The control unit causes the generation unit to generate a plurality of clock signals having different phases by changing the phase setting in the generation unit so as to shift the phase by a first predetermined angle. The phase adjustment circuit described in 1.   The control unit shifts the phase by the first predetermined angle from the phase before shifting the phase by the first predetermined angle when the determination result by the determination unit is different before and after shifting the phase by the first predetermined angle. 3. The phase adjustment circuit according to claim 2, wherein the setting of the phase in the generation unit is changed so as to be shifted by a second predetermined angle smaller than the first predetermined angle within a range up to a phase of. The controller is
Stores data in which the phase of each of the plurality of clock signals is associated with the correct / incorrect determination result by the determination unit for each of the parallel data converted by the conversion unit according to each of the plurality of clock signals. A storage unit;
Based on the data stored in the storage unit, a specifying unit that specifies the range of the phase and the optimum phase;
Until the optimum phase is identified by the identifying unit, an instruction signal for changing the setting of the phase in the generating unit is output to the generating unit so that the generating unit generates a plurality of clock signals having different phases, An instruction unit that outputs an instruction signal for setting the optimum phase to the generation unit after the optimum phase is specified;
The phase adjustment circuit according to claim 1, further comprising:   The control unit causes the conversion unit to convert test serial data to which additional data for detecting whether there is an error in the parallel data is set until the optimum phase is set in the generation unit. The phase adjustment circuit according to any one of claims 1 to 4. A recording head;
A head drive unit for driving the recording head;
An output unit that outputs serial data corresponding to an ejection pattern of ink ejected from each nozzle of the recording head;
The phase adjustment circuit according to any one of claims 1 to 5, wherein the serial data output from the output unit is converted into parallel data and output to the head driving unit.
An image forming apparatus comprising: A phase adjustment method using the phase adjustment circuit according to any one of claims 1 to 5,
Changing the setting of the phase in the generation unit so that the control unit causes the generation unit to generate a plurality of clock signals having different phases, and
The control unit correctly converts the serial data to parallel data by the conversion unit based on a determination result of the determination unit by each of the parallel data converted by the conversion unit according to each of the plurality of clock signals. Identifying a range of phases to be converted to
The control unit sets an optimal phase that is a value within the phase range in the generation unit;
A phase adjustment method comprising:

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