JPWO2014024266A1 - Semiconductor device manufacturing method and semiconductor device - Google Patents

Semiconductor device manufacturing method and semiconductor device Download PDF

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JPWO2014024266A1
JPWO2014024266A1 JP2012070145A JP2014508629A JPWO2014024266A1 JP WO2014024266 A1 JPWO2014024266 A1 JP WO2014024266A1 JP 2012070145 A JP2012070145 A JP 2012070145A JP 2014508629 A JP2014508629 A JP 2014508629A JP WO2014024266 A1 JPWO2014024266 A1 JP WO2014024266A1
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silicon layer
fin
formed
resist
wire
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JP5595619B2 (en
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舛岡 富士雄
富士雄 舛岡
広記 中村
広記 中村
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ユニサンティス エレクトロニクス シンガポール プライベート リミテッドUnisantis Electronics Singapore Pte Ltd.
ユニサンティス エレクトロニクス シンガポール プライベート リミテッドUnisantis Electronics Singapore Pte Ltd.
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/4238Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45Ohmic electrodes
    • H01L29/456Ohmic electrodes on silicon
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66666Vertical transistors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827Vertical transistors

Abstract

It is an object of the present invention to provide a manufacturing method of SGT which is a self-alignment process using a thin gate material, a metal gate, and a SGT structure obtained as a result, by reducing parasitic capacitance between the gate wiring and the substrate. A fin-like silicon layer is formed on a silicon substrate, a first insulating film is formed around the fin-like silicon layer, a columnar silicon layer is formed on the fin-like silicon layer, and the diameter of the columnar silicon layer Is the same as the width of the fin-like silicon layer, a gate insulating film is formed around the columnar silicon layer, a metal film and a polysilicon film are formed around the gate insulating film, and the polysilicon film is formed. The third resist for forming the gate wiring is formed, and the gate wiring is formed by anisotropic etching to form the fourth resist. And exposing the polysilicon film on the upper sidewall of the columnar silicon layer, removing the exposed polysilicon film by etching, stripping the fourth resist, and Film is removed by etching, by forming a gate electrode connected to the gate line, to solve the above problems.

Description

  The present invention relates to a method for manufacturing a semiconductor device and a semiconductor device.

  Semiconductor integrated circuits, in particular integrated circuits using MOS transistors, are becoming increasingly highly integrated. Along with this high integration, the MOS transistors used therein have been miniaturized to the nano region. When the miniaturization of such a MOS transistor progresses, it is difficult to suppress the leakage current, and there is a problem that the occupied area of the circuit cannot be easily reduced due to a request for securing a necessary amount of current. In order to solve such a problem, a Surrounding Gate Transistor (hereinafter referred to as “SGT”) having a structure in which a source, a gate, and a drain are arranged in a vertical direction with respect to a substrate and a gate electrode surrounds a columnar semiconductor layer is proposed. (For example, see Patent Document 1, Patent Document 2, and Patent Document 3).

  In the conventional SGT manufacturing method, a silicon pillar having a nitride hard mask formed on a silicon pillar is formed, a diffusion layer under the silicon pillar is formed, a gate material is deposited, and then the gate material is flattened. Etch-back is performed to form insulating film side walls on the side walls of the silicon pillar and the nitride film hard mask. Thereafter, a resist pattern for gate wiring is formed, the gate material is etched, the nitride film hard mask is removed, and a diffusion layer is formed on the silicon pillar (see, for example, Patent Document 4).

  In such a method, when the distance between the silicon pillars becomes narrow, a thick gate material must be deposited between the silicon pillars, and holes called voids may be formed between the silicon pillars. Once the void is formed, a hole is made in the gate material after etch back. Thereafter, when an insulating film is deposited to form an insulating film sidewall, the insulating film is deposited in the void. Therefore, it is difficult to process the gate material.

  Therefore, after forming the silicon pillar, a gate oxide film is formed, and after depositing thin polysilicon, a resist for covering the upper part of the silicon pillar and forming a gate wiring is formed, the gate wiring is etched, and then the oxide film is thickened. It has been shown that the upper part of the silicon pillar is deposited, the thin polysilicon on the upper part of the silicon pillar is removed, and the thick oxide film is removed by wet etching (see Non-Patent Document 1, for example).

 However, a method for using a metal for the gate electrode is not shown. Further, a resist for forming the gate wiring must be formed so as to cover the upper part of the silicon pillar, and therefore, the upper part of the silicon pillar must be covered, which is not a self-alignment process.

  In order to reduce the parasitic capacitance between the gate wiring and the substrate, the conventional MOS transistor uses the first insulating film. For example, in FINFET (Non-patent Document 2), a first insulating film is formed around one fin-like semiconductor layer, the first insulating film is etched back, the fin-like semiconductor layer is exposed, and the gate wiring and the substrate The parasitic capacitance between them is reduced. Therefore, also in SGT, it is necessary to use the first insulating film in order to reduce the parasitic capacitance between the gate wiring and the substrate. In SGT, since there is a columnar semiconductor layer in addition to the fin-shaped semiconductor layer, a device for forming the columnar semiconductor layer is required.

JP-A-2-71556 Japanese Patent Laid-Open No. 2-188966 Japanese Patent Laid-Open No. 3-145761 JP 2009-182317 A

B. Yang, KDBuddharaju, SHGTeo, N. Singh, GDLo, and DLKwong, "Vertical Silicon-Nanowire Formation and Gate-All-Around MOSFET", IEEE Electron Device Letters, VOL. 29, No. 7, July 2008, pp791-794. IEDM2010 CC.Wu, et.al, 27.1.1-27.1.4.

  Accordingly, an object of the present invention is to provide a method for manufacturing SGT that is a self-aligned process using a thin gate material, a metal gate, and a self-aligned process, and a SGT structure obtained as a result, by reducing the parasitic capacitance between the gate wiring and the substrate. .

A method for manufacturing a semiconductor device of the present invention includes:
Forming a fin-like silicon layer on a silicon substrate, forming a first insulating film around the fin-like silicon layer, and forming a columnar silicon layer on the fin-like silicon layer; and The diameter of the columnar silicon layer is the same as the width of the fin-shaped silicon layer,
After the first step, a gate insulating film is formed around the columnar silicon layer, a metal film and a polysilicon film are formed around the gate insulating film, and a third wiring for forming a gate wiring is formed. A second step of forming a gate wiring by forming a resist and performing anisotropic etching, wherein the thickness of the polysilicon film is smaller than the diameter of the columnar silicon layer;
After the second step, a fourth resist is deposited, the polysilicon film on the upper side wall of the columnar silicon layer is exposed, the exposed polysilicon film is removed by etching, and the fourth resist is peeled off And removing the metal film by etching to form a gate electrode connected to the gate wiring;
It is characterized by having.

  The first step forms a first resist for forming a fin-like silicon layer on a silicon substrate, etches the silicon substrate, forms the fin-like silicon layer, and removes the first resist Then, a first insulating film is deposited around the fin-like silicon layer, the first insulating film is etched back, an upper portion of the fin-like silicon layer is exposed, and is orthogonal to the fin-like silicon layer. Forming a second resist on the substrate, etching the fin-like silicon layer, and removing the second resist, so that a portion where the fin-like silicon layer and the second resist are orthogonal to each other is the columnar silicon layer. The columnar silicon layer is formed so that:

  The method may further include a fourth step of forming a first diffusion layer on the pillar-shaped silicon layer and forming a second diffusion layer on the bottom of the pillar-shaped silicon layer and on the fin-shaped silicon layer.

  The method may further include a fifth step of forming silicide on the first diffusion layer, the second diffusion layer, and the gate wiring.

The semiconductor device of the present invention is
A fin-like silicon layer formed on a silicon substrate;
A first insulating film formed around the fin-like silicon layer;
A columnar silicon layer formed on the fin-shaped silicon layer, the diameter of which is the same as the width of the fin-shaped silicon layer;
A gate insulating film formed around the columnar silicon layer;
A gate electrode having a laminated structure of a metal film and a polysilicon film formed around the gate insulating film, wherein the thickness of the polysilicon film is smaller than the diameter of the columnar silicon layer;
A gate wiring extending in a direction orthogonal to the fin-like silicon layer connected to the gate electrode;
A second diffusion layer formed above the fin-like silicon layer and below the columnar silicon layer;
A first diffusion layer formed on the columnar silicon layer;
Silicide formed on top of the second diffusion layer;
Silicide formed on top of the first diffusion layer;
It is characterized by having.

  Further, the gate wiring has a laminated structure of the metal film and silicide.

  According to the present invention, a parasitic capacitance between a gate wiring and a substrate is reduced, a thin gate material is used, a metal gate and a self-aligned SGT manufacturing method, and a resultant SGT structure are provided. Can do. Since the fin-like silicon layer, the first insulating film, and the columnar silicon layer are formed on the basis of a conventional method for manufacturing a FINFET, they can be easily formed.

  In addition, a gate insulating film is formed around the columnar silicon layer, a metal film and a polysilicon film are formed around the gate insulating film, and the thickness of the polysilicon film is smaller than the diameter of the columnar silicon layer. A second step of forming a third resist for forming a gate wiring and performing the anisotropic etching to form the gate wiring; after the second process, Depositing a resist to expose the polysilicon film on the upper side wall of the columnar silicon layer; removing the exposed polysilicon film by etching; stripping the fourth resist; removing the metal film by etching; A self-alignment process is realized by the third step of forming a gate electrode connected to the gate wiring. Since it is a self-alignment process, high integration is possible.

  The gate wiring has a laminated structure of the metal film and silicide. Since the silicide and the metal film are in direct contact, the resistance can be reduced.

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  Below, the manufacturing process for forming the structure of SGT which concerns on embodiment of this invention is demonstrated with reference to FIGS.

  First, a fin-like silicon layer 103 is formed on a silicon substrate 101, a first insulating film 104 is formed around the fin-like silicon layer 103, and a columnar silicon layer 106 is formed on the fin-like silicon layer 103. Indicates. As shown in FIG. 2, a first resist 102 for forming a fin-like silicon layer is formed on the silicon substrate 101.

  As shown in FIG. 3, the silicon substrate 101 is etched to form a fin-like silicon layer 103. Although the fin-like silicon layer is formed using a resist as a mask this time, a hard mask such as an oxide film or a nitride film may be used.

  As shown in FIG. 4, the first resist 102 is removed.

  As shown in FIG. 5, a first insulating film 104 is deposited around the fin-like silicon layer 103. As the first insulating film, for example, an oxide film formed by high-density plasma or an oxide film formed by low-pressure chemical vapor deposition may be used.

  As shown in FIG. 6, the 1st insulating film 104 is etched back and the upper part of the fin-like silicon layer 103 is exposed. The process up to here is the same as the method for manufacturing the fin-like silicon layer of Patent Document 2.

  As shown in FIG. 7, a second resist 105 is formed so as to be orthogonal to the fin-like silicon layer 103. A portion where the fin-like silicon layer 103 and the resist 105 are orthogonal to each other is a portion that becomes a columnar silicon layer. Since a line-shaped resist can be used, the possibility that the resist falls after patterning is low, and the process is stable.

  As shown in FIG. 8, the fin-like silicon layer 103 is etched. A portion where the fin-like silicon layer 103 and the second resist 105 are orthogonally becomes the columnar silicon layer 106. Therefore, the diameter of the columnar silicon layer 106 is the same as the width of the fin-like silicon layer. A columnar silicon layer 106 is formed on the fin-shaped silicon layer 103, and a first insulating film 104 is formed around the fin-shaped silicon layer 103.

  As shown in FIG. 9, the second resist 105 is removed.

  Next, a gate insulating film 107 is formed around the columnar silicon layer 106, a metal film 108 and a polysilicon film 109 are formed around the gate insulating film 107, and the polysilicon film 109 has a thickness of the columnar silicon layer. A manufacturing method of forming the gate wiring 111b by forming the third resist 110 for forming the gate wiring 111b and performing anisotropic etching, which is thinner than the diameter.

  As shown in FIG. 10, a gate insulating film 107 is formed around the columnar silicon layer 106, and a metal film 108 and a polysilicon film 109 are formed around the gate insulating film 107. At this time, a thin polysilicon film 109 is used. Therefore, voids can be prevented from being formed in the polysilicon film. Titanium nitride can be used as the metal film 108, but other metals may be used as long as they are used in the semiconductor manufacturing process and set the threshold voltage of the transistor. As the gate insulating film 107, an insulating film generally used in a semiconductor manufacturing process such as an oxide film, an oxynitride film, or a high dielectric film can be used.

As shown in FIG. 11, a third resist 110 for forming the gate wiring 111b is formed. In this embodiment, the resist height is described as being higher than that of the columnar silicon layer. As the gate wiring width becomes narrower, the polysilicon above the columnar silicon layer is more likely to be exposed.
The resist height may be lower than the columnar silicon layer.

As shown in FIG. 12, the polysilicon film 109 and the metal film 108 are etched.
A gate electrode 111a and a gate wiring 111b are formed. At this time, if the resist thickness on the upper part of the columnar silicon layer is thin or the polysilicon on the upper part of the columnar silicon layer is exposed, the upper part of the columnar silicon layer may be etched during the etching. In this case, when the columnar silicon layer is formed, the height may be set to the sum of a desired columnar silicon layer height and a height that is later removed during gate wiring etching. Therefore, the manufacturing process of the present invention is a self-alignment process.

  As shown in FIG. 13, the third resist is removed. As described above, the gate insulating film 107 is formed around the columnar silicon layer 106, the metal film 108 and the polysilicon film 109 are formed around the gate insulating film 107, and the thickness of the polysilicon film 109 is equal to that of the columnar silicon layer. A manufacturing method is shown in which the gate wiring 111b is formed by forming the third resist 110 for forming the gate wiring 111b and performing anisotropic etching, which is thinner than the diameter.

  Next, a fourth resist 112 is deposited, the polysilicon film 109 on the upper side wall of the columnar silicon layer 106 is exposed, the exposed polysilicon film 109 is removed by etching, the fourth resist 112 is stripped, and a metal film A manufacturing method in which 108 is removed by etching and a gate electrode 111a connected to the gate wiring 111b is formed is shown.

  As shown in FIG. 14, the 4th resist 112 is deposited and the polysilicon film 108 of the upper side wall of the columnar silicon layer 106 is exposed. It is preferable to use resist etchback. Further, a coating film such as spin-on glass may be used.

  As shown in FIG. 15, the exposed polysilicon film 109 is removed by etching. Isotropic dry etching is preferred.

  As shown in FIG. 16, the 4th resist 112 is peeled.

As shown in FIG. 17, the metal film 108 is removed by etching, and the metal film 108 is left on the side walls of the columnar silicon layer 106. Isotropic etching is preferred.
A gate electrode 111 a is formed by the metal film 108 on the sidewall of the columnar silicon layer 106 and the polysilicon film 109. Therefore, it becomes a self-alignment process.

  As described above, the fourth resist 112 is deposited, the polysilicon film 109 on the upper side wall of the columnar silicon layer 106 is exposed, the exposed polysilicon film 109 is removed by etching, the fourth resist 112 is peeled off, and the metal film A manufacturing method is shown in which 108 is removed by etching and a gate electrode 111a connected to the gate wiring 111b is formed.

  Next, a manufacturing method in which the first diffusion layer 114 is formed on the upper part of the columnar silicon layer 106 and the second diffusion layer 113 is formed on the lower part of the columnar silicon layer 106 and the upper part of the fin-like silicon layer 103 will be described.

  As shown in FIG. 18, arsenic is implanted to form a first diffusion layer 114 and a second diffusion layer 113. In the case of pMOS, boron or boron fluoride is implanted.

  As shown in FIG. 19, a nitride film 115 is deposited and heat treatment is performed.

  As described above, the manufacturing method in which the first diffusion layer 114 is formed on the upper part of the columnar silicon layer 106 and the second diffusion layer 113 is formed on the lower part of the columnar silicon layer 106 and the upper part of the fin-like silicon layer 103 is shown. .

  Next, a manufacturing method for forming silicide on the first diffusion layer 114, the second diffusion layer 113, and the gate wiring 111b will be described.

  As shown in FIG. 20, the nitride film 115 is etched to form nitride film side walls 116a and 116b.

  Next, as shown in FIG. 21, a metal is deposited, heat-treated, and unreacted metal is removed, whereby silicide 118 is formed on the first diffusion layer 104, the second diffusion layer 113, and the gate wiring 111b. 117, 119 are formed. When the upper portion of the gate electrode 111a is exposed, the silicide 120 is formed on the upper portion of the gate electrode 111a.

  Since the polysilicon film 109 is thin, the gate wiring 111b tends to have a laminated structure of the metal film 108 and the silicide 119. Since the silicide 119 and the metal film 108 are in direct contact with each other, the resistance can be reduced.

  As described above, the manufacturing method for forming silicide on the first diffusion layer 114, the second diffusion layer 113, and the gate wiring 111b is shown.

  As shown in FIG. 22, a contact stopper 140 such as a nitride film is formed, and an interlayer insulating film 121 is formed.

  As shown in FIG. 23, the 5th resist 122 for forming the contact holes 123 and 124 is formed.

  As shown in FIG. 24, the interlayer insulating film 121 is etched to form contact holes 123 and 124.

  As shown in FIG. 25, the 5th resist 122 is peeled.

  As shown in FIG. 26, the 6th resist 125 for forming the contact hole 126 is formed.

  As shown in FIG. 27, the interlayer insulating film 121 is etched to form a contact hole 126.

  As shown in FIG. 28, the sixth resist 125 is removed.

  As shown in FIG. 29, the contact stopper 140 at the bottom of the contact holes 123, 124, 126 is removed by etching.

  Next, as shown in FIG. 30, metal is deposited to form contacts 127, 128, and 129.

  Next, as shown in FIG. 31, a metal 130 for metal wiring is deposited.

  Next, as shown in FIG. 32, seventh resists 131, 132, and 133 for forming metal wiring are formed.

  Next, as shown in FIG. 33, the metal 130 is etched to form metal wirings 134, 135, and 136.

  Next, as shown in FIG. 34, the seventh resists 131, 132, and 133 are removed.

  Thus, the parasitic capacitance between the gate wiring and the substrate is reduced, a thin gate material is used, a metal gate, and a manufacturing method of SGT which is a self-alignment process has been shown.

  A structure of a semiconductor device obtained by the manufacturing method is shown in FIG. As shown in FIG. 1, the semiconductor device includes a fin-like silicon layer 103 formed on a silicon substrate 101, a first insulating film 104 formed around the fin-like silicon layer 103, and a fin-like silicon layer 103. The columnar silicon layer 106 formed above and the diameter of the columnar silicon layer 106 are the same as the width of the fin-like silicon layer 103, and the gate insulating film 107 formed around the columnar silicon layer 106 and the gate insulation The gate electrode 111a formed of a laminated structure of the metal film 108 and the polysilicon film 109 formed around the film 107, and the thickness of the polysilicon film 109 is smaller than the diameter of the columnar silicon layer 106. A gate wiring 111b extending in a direction orthogonal to the connected fin-like silicon layer 103; And a second diffusion layer 113 formed below the columnar silicon layer 106, a first diffusion layer 114 formed above the columnar silicon layer 106, and an upper portion of the second diffusion layer 113. Silicide 117 and silicide 118 formed on the first diffusion layer 114 are included.

  The gate wiring 111b has a stacked structure of a metal film 108 and a silicide 119. Since the silicide 119 and the metal film 108 are in direct contact with each other, the resistance can be reduced.

  It should be noted that the present invention can be variously modified and modified without departing from the broad spirit and scope of the present invention. Further, the above-described embodiment is for explaining an example of the present invention, and does not limit the scope of the present invention.

For example, in the above embodiment, a method of manufacturing a semiconductor device in which p-type (including p + -type) and n-type (including n + -type) are opposite in conductivity type, and a semiconductor obtained thereby An apparatus is naturally included in the technical scope of the present invention.

101. Silicon substrate 102. First resist 103. Fin-like silicon layer 104. First insulating film 105. Second resist 106. Columnar silicon layer 107. Gate insulating film 108. Metal film 109. Polysilicon film 110. Third resist 111a. Gate electrode 111b. Gate wiring 112. Fourth resist 113. Second diffusion layer 114. First diffusion layer 115. Nitride film 116a. Nitride film sidewall 116b. Nitride film sidewall 117. Silicide 118. Silicide 119. Silicide 120. Silicide 121. Interlayer insulating film 122. Fifth resist 123. Contact hole 124. Contact hole 125. Sixth resist 126. Contact hole 127. Contact 128. Contact 129. Contact 130. Metal 131. Seventh resist 132. Seventh resist 133. Seventh resist 134. Metal wiring 135. Metal wiring 136. Metal wiring 140. Contact stopper

B. Yang, KDBuddharaju, SHGTeo, N. Singh, GDLo, and DLKwong, "Vertical Silicon-Nanowire Formation and Gate-All-Around MOSFET", IEEE Electron Device Letters, VOL. 29, No. 7, July 2008, pp791-794. High performance 22 / 20nm FinFET CMOS devices with advanced high-K / metal gate scheme, IEDM2010 CC.Wu, et.al, 27.1.1-27.1.4 ..

A method for manufacturing a semiconductor device of the present invention includes:
Forming a fin-like silicon layer on a silicon substrate, forming a first insulating film around the fin-like silicon layer, and forming a columnar silicon layer on the fin-like silicon layer; and , the width of the pillar-shaped silicon layer is the same as the width of the fin-shaped silicon layer,
After the first step, a gate insulating film is formed around the columnar silicon layer, a metal film and a polysilicon film are formed around the gate insulating film, and a third wiring for forming a gate wiring is formed. A second step of forming a gate wiring by forming a resist and performing anisotropic etching, wherein the thickness of the polysilicon film is thinner than the width of the columnar silicon layer;
After the second step, a fourth resist is deposited, the polysilicon film on the upper side wall of the columnar silicon layer is exposed, the exposed polysilicon film is removed by etching, and the fourth resist is peeled off And removing the metal film by etching to form a gate electrode connected to the gate wiring;
It is characterized by having.

The semiconductor device of the present invention is
A fin-like silicon layer formed on a silicon substrate;
A first insulating film formed around the fin-like silicon layer;
A columnar silicon layer formed on the fin-shaped silicon layer, the diameter of which is the same as the width of the fin-shaped silicon layer;
A gate insulating film formed around the columnar silicon layer;
A gate electrode having a laminated structure of a metal film and a polysilicon film formed around the gate insulating film, wherein the thickness of the polysilicon film is smaller than the width of the columnar silicon layer;
A gate wiring extending in a direction orthogonal to the fin-like silicon layer connected to the gate electrode;
A second diffusion layer formed above the fin-like silicon layer and below the columnar silicon layer;
A first diffusion layer formed on the columnar silicon layer;
Silicide formed on top of the second diffusion layer;
Silicide formed on top of the first diffusion layer;
It is characterized by having.

In addition, a gate insulating film is formed around the columnar silicon layer, a metal film and a polysilicon film are formed around the gate insulating film, and the thickness of the polysilicon film is thinner than the width of the columnar silicon layer. A second step of forming a third resist for forming a gate wiring and performing the anisotropic etching to form the gate wiring; after the second process, Depositing a resist to expose the polysilicon film on the upper side wall of the columnar silicon layer; removing the exposed polysilicon film by etching; stripping the fourth resist; removing the metal film by etching; A self-alignment process is realized by the third step of forming a gate electrode connected to the gate wiring. Since it is a self-alignment process, high integration is possible.

(A) is a top view of the semiconductor device based on this invention. (B) is sectional drawing in the xx ' line | wire of (a). (C) is sectional drawing in the yy ' line | wire of (a). (A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention. (B) is sectional drawing in the xx ' line | wire of (a). (C) is sectional drawing in the yy ' line | wire of (a). (A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention. (B) is sectional drawing in the xx ' line | wire of (a). (C) is sectional drawing in the yy ' line | wire of (a). (A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention. (B) is sectional drawing in the xx ' line | wire of (a). (C) is sectional drawing in the yy ' line | wire of (a). (A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention. (B) is sectional drawing in the xx ' line | wire of (a). (C) is sectional drawing in the yy ' line | wire of (a). (A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention. (B) is sectional drawing in the xx ' line | wire of (a). (C) is sectional drawing in the yy ' line | wire of (a). (A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention. (B) is sectional drawing in the xx ' line | wire of (a). (C) is sectional drawing in the yy ' line | wire of (a). (A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention. (B) is sectional drawing in the xx ' line | wire of (a). (C) is sectional drawing in the yy ' line | wire of (a). (A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention. (B) is sectional drawing in the xx ' line | wire of (a). (C) is sectional drawing in the yy ' line | wire of (a). (A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention. (B) is sectional drawing in the xx ' line | wire of (a). (C) is sectional drawing in the yy ' line | wire of (a). (A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention. (B) is sectional drawing in the xx ' line | wire of (a). (C) is sectional drawing in the yy ' line | wire of (a). (A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention. (B) is sectional drawing in the xx ' line | wire of (a). (C) is sectional drawing in the yy ' line | wire of (a). (A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention. (B) is sectional drawing in the xx ' line | wire of (a). (C) is sectional drawing in the yy ' line | wire of (a). (A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention. (B) is sectional drawing in the xx ' line | wire of (a). (C) is sectional drawing in the yy ' line | wire of (a). (A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention. (B) is sectional drawing in the xx ' line | wire of (a). (C) is sectional drawing in the yy 'line | wire of (a). (A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention. (B) is sectional drawing in the xx ' line | wire of (a). (C) is sectional drawing in the yy ' line | wire of (a). (A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention. (B) is sectional drawing in the xx ' line | wire of (a). (C) is sectional drawing in the yy ' line | wire of (a). (A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention. (B) is sectional drawing in the xx ' line | wire of (a). (C) is sectional drawing in the yy ' line | wire of (a). (A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention. (B) is sectional drawing in the xx ' line | wire of (a). (C) is sectional drawing in the yy ' line | wire of (a). (A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention. (B) is sectional drawing in the xx ' line | wire of (a). (C) is sectional drawing in the yy ' line | wire of (a). (A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention. (B) is sectional drawing in the xx ' line | wire of (a). (C) is sectional drawing in the yy ' line | wire of (a). (A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention. (B) is sectional drawing in the xx ' line | wire of (a). (C) is sectional drawing in the yy ' line | wire of (a). (A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention. (B) is sectional drawing in the xx ' line | wire of (a). (C) is sectional drawing in the yy ' line | wire of (a). (A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention. (B) is sectional drawing in the xx ' line | wire of (a). (C) is sectional drawing in the yy ' line | wire of (a). (A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention. (B) is sectional drawing in the xx ' line | wire of (a). (C) is sectional drawing in the yy ' line | wire of (a). (A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention. (B) is sectional drawing in the xx ' line | wire of (a). (C) is sectional drawing in the yy ' line | wire of (a). (A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention. (B) is sectional drawing in the xx ' line | wire of (a). (C) is sectional drawing in the yy ' line | wire of (a). (A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention. (B) is sectional drawing in the xx ' line | wire of (a). (C) is sectional drawing in the yy ' line | wire of (a). (A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention. (B) is sectional drawing in the xx ' line | wire of (a). (C) is sectional drawing in the yy ' line | wire of (a). (A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention. (B) is sectional drawing in the xx ' line | wire of (a). (C) is sectional drawing in the yy ' line | wire of (a). (A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention. (B) is sectional drawing in the xx ' line | wire of (a). (C) is sectional drawing in the yy ' line | wire of (a). (A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention. (B) is sectional drawing in the xx ' line | wire of (a). (C) is sectional drawing in the yy ' line | wire of (a). (A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention. (B) is sectional drawing in the xx ' line | wire of (a). (C) is sectional drawing in the yy ' line | wire of (a). (A) is a top view which concerns on the manufacturing method of the semiconductor device which concerns on this invention. (B) is sectional drawing in the xx ' line | wire of (a). (C) is sectional drawing in the yy ' line | wire of (a).

As shown in FIG. 7, a second resist 105 is formed so as to be orthogonal to the fin-like silicon layer 103. A portion where the fin-like silicon layer 103 and the resist 105 are orthogonal to each other is a portion that becomes a columnar silicon layer. Since a line-shaped resist can be used, there is a low possibility that the resist will fall after pattern formation , and the process is stable.

Next, a gate insulating film 107 is formed around the columnar silicon layer 106, a metal film 108 and a polysilicon film 109 are formed around the gate insulating film 107, and the thickness of the polysilicon film 109 is equal to that of the columnar silicon layer. A manufacturing method of forming the gate wiring 111b by forming the third resist 110 for forming the gate wiring 111b and performing anisotropic etching, which is thinner than the width .

As shown in FIG. 13, the third resist is removed. As described above, the gate insulating film 107 is formed around the columnar silicon layer 106, the metal film 108 and the polysilicon film 109 are formed around the gate insulating film 107, and the thickness of the polysilicon film 109 is equal to that of the columnar silicon layer. A manufacturing method has been shown in which the gate wiring 111b is formed by forming the third resist 110 for forming the gate wiring 111b and performing anisotropic etching, which is thinner than the width .

As shown in FIG. 14, the 4th resist 112 is deposited and the polysilicon film 109 of the upper side wall of the columnar silicon layer 106 is exposed. It is preferable to use resist etchback. Further, a coating film such as spin-on glass may be used.

Next, as shown in FIG. 21, a metal is deposited, heat-treated, and unreacted metal is removed, whereby silicide 118 is formed on the first diffusion layer 114 , the second diffusion layer 113, and the gate wiring 111b. 117, 119 are formed. When the upper portion of the gate electrode 111a is exposed, the silicide 120 is formed on the upper portion of the gate electrode 111a.

Claims (6)

  1. Forming a fin-like silicon layer on a silicon substrate, forming a first insulating film around the fin-like silicon layer, and forming a columnar silicon layer on the fin-like silicon layer; and The diameter of the columnar silicon layer is the same as the width of the fin-shaped silicon layer,
    After the first step, a gate insulating film is formed around the columnar silicon layer, a metal film and a polysilicon film are formed around the gate insulating film, and a third wiring for forming a gate wiring is formed. A second step of forming a gate wiring by forming a resist and performing anisotropic etching, wherein the thickness of the polysilicon film is smaller than the diameter of the columnar silicon layer;
    After the second step, a fourth resist is deposited, the polysilicon film on the upper side wall of the columnar silicon layer is exposed, the exposed polysilicon film is removed by etching, and the fourth resist is peeled off And removing the metal film by etching to form a gate electrode connected to the gate wiring;
    A method for manufacturing a semiconductor device, comprising:
  2. The first step includes
    Forming a first resist for forming a fin-like silicon layer on the silicon substrate; etching the silicon substrate; forming the fin-like silicon layer; removing the first resist; and A first insulating film is deposited around the substrate, the first insulating film is etched back, an upper portion of the fin-like silicon layer is exposed, and a second resist is formed so as to be orthogonal to the fin-like silicon layer. Then, by etching the fin-like silicon layer and removing the second resist, the columnar silicon layer is formed such that a portion where the fin-like silicon layer and the second resist are orthogonal to each other becomes the columnar silicon layer. Forming,
    The method of manufacturing a semiconductor device according to claim 1.
  3.   The method further includes a fourth step of forming a first diffusion layer above the columnar silicon layer and forming a second diffusion layer below the columnar silicon layer and above the fin-like silicon layer. A method for manufacturing a semiconductor device according to claim 1.
  4.   4. The method of manufacturing a semiconductor device according to claim 3, further comprising a fifth step of forming silicide on the first diffusion layer, the second diffusion layer, and the gate wiring.
  5. A fin-like silicon layer formed on a silicon substrate;
    A first insulating film formed around the fin-like silicon layer;
    A columnar silicon layer formed on the fin-shaped silicon layer, the diameter of which is the same as the width of the fin-shaped silicon layer;
    A gate insulating film formed around the columnar silicon layer;
    A gate electrode having a laminated structure of a metal film and a polysilicon film formed around the gate insulating film, wherein the thickness of the polysilicon film is smaller than the diameter of the columnar silicon layer;
    A gate wiring extending in a direction orthogonal to the fin-like silicon layer connected to the gate electrode;
    A second diffusion layer formed above the fin-like silicon layer and below the columnar silicon layer;
    A first diffusion layer formed on the columnar silicon layer;
    Silicide formed on top of the second diffusion layer;
    Silicide formed on top of the first diffusion layer;
    A semiconductor device comprising:
  6.   6. The semiconductor device according to claim 5, wherein the gate wiring has a laminated structure of the metal film and silicide.
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