JPWO2013157177A1 - Low distortion mixer and radio receiver including the same - Google Patents

Abstract

The mixer (1) includes first to fourth switch transistors (M1) connected between the first and second input terminals (Vinp, Vinn) and the first and second output terminals (Vap, Van), respectively. To M4), and first and second buffers (10, 11) for receiving the first and second LO signals and supplying the LO signals (Vgp, Vgn) to the gates of the first to fourth switch transistors (M1 to M4). It has. And the 1st and 2nd buffer (10, 11) is provided with the control terminal (Vcnt1-Vcnt4) which adjusts the cross voltage of the signals output from each.

Description

  The present invention relates to a mixer used for an RF (Radio Frequency) front end of a radio receiver, for example.

  In recent years, there has been a demand for both high performance and low cost of wireless receivers. In order to improve the reception performance, it is necessary to improve the distortion performance of the RF front end portion of the radio receiver. In particular, it is important to reduce the distortion of the mixer. Conventionally, distortion performance has been improved by suppressing an interference signal using an external tracking filter. However, by reducing the distortion of the mixer, it is possible to reduce external components and reduce costs.

  In order to reduce the third-order intermodulation distortion in the mixer, a gate bias voltage Vg which is a voltage between the gate and the source of the switch transistor included in the mixer, a threshold voltage Vth of the switch transistor, and an output node of the switch transistor It is known that it is necessary to satisfy the relationship of the following formula (1) with respect to the common voltage Vcm.

  Patent Document 1 discloses a technique for changing a gate bias voltage in a mixer.

  FIG. 7 is a diagram showing an example of a conventional mixer disclosed in Patent Document 1, for example. By adopting such a configuration, it is possible to change the gate bias voltage of at least one of the transistors M71 to M74.

  In order to obtain the same effect, a method of changing the duty ratio D of the LO signals Vlop and Vlon as shown in FIG. 8 has been proposed. According to this method, distortion of the mixer can be improved. Here, in FIG. 8, T indicates a signal period, and a period of 1T indicates one period of the LO signals Vlop and Vlon.

Special table 2010-539810 gazette

  However, in the mixer 70 configured as shown in FIG. 7, bias voltages Vg1 to Vg4 are respectively applied to the LO signals after passing through the capacitors C71 to C74, and the bias voltages Vg1 to Vg4 are adjusted. For example, when the threshold voltages of the transistors M71 to M74 become higher than the design value due to manufacturing variations, it is necessary to set the bias voltages Vg1 to Vg4 higher than the design value in order to satisfy the equation (1). When the amplitude of the LO signal reaches the power supply voltage, adjustment is almost impossible due to the maximum rated voltage of the transistor, and the voltage adjustment range becomes narrow.

  Further, in the configuration of the LO signals Vlop and Vlon as shown in FIG. 8, the period during which the switching transistors are simultaneously turned off is long, and the conversion gain of the mixer is lowered, so that there is a concern that the sensitivity of the radio receiver is deteriorated. For this reason, the LO signals Vlop and Vlon need to eliminate the period in which the switching transistors are simultaneously turned on without greatly changing the duty ratio D.

  In view of the above, an object of the present invention is to provide a low distortion mixer that has a wide voltage adjustment range and is resistant to variations without lowering the conversion gain.

  In the first aspect of the present invention, a first RF (Radio Frequency) signal input to the first input terminal, a second RF signal that is an inverted signal of the first RF signal input to the second input terminal, and the first LO An IF (Intermediate Frequency) signal is generated by multiplying the first LO signal input to the (Local Oscillator) input terminal and the second LO signal that is an inverted signal of the first LO signal input to the second LO input terminal. In the mixer for differential output to the first and second output terminals, the first and second switch transistors respectively connected between the first input terminal and the first and second output terminals; The third and fourth switch transistors connected between the two input terminals and the first and second output terminals, respectively, the first LO input terminal and the first and fourth switches. A first buffer connected between the gate terminals of the first and second transistors; a second buffer connected between the second LO input terminal and the gate terminals of the second and third switch transistors; One end of first and second resistors connected to the second output terminal, respectively, and a first and second bias voltage application terminal to which a bias voltage is applied via the first and second resistors, respectively, Each of the first and second buffers includes a control terminal that adjusts a cross voltage between signals output from the first and second buffers.

  In this aspect, the gate bias voltage of the first to fourth switch transistors is adjusted by adjusting the cross voltage of the output signals of the first and second buffers based on the control signal. Further, by adjusting the bias voltage in addition to the adjustment of the cross voltage, the common voltage of the first and second output terminals can be finely adjusted to an optimum bias point where distortion can be reduced. As a result, a low distortion mixer having a wide voltage adjustment range and being resistant to variations can be realized.

  In the second aspect of the present invention, the wireless receiver includes an LNA (Low Noise Amplifier) that amplifies an input RF signal from an antenna, and an output signal from the LNA that is input to the first and second input terminals. The mixer according to one aspect, a VCO (Voltage Controlled Oscillator) that generates the first and second LO signals input to the first and second LO input terminals of the mixer, and the IF signal output from the mixer A variable gain amplifying circuit for amplifying, an A / D (Analog to Digital) converter for digitally converting an analog output signal of the variable gain amplifying circuit, and a DSP (Digital Signal Processor) for processing a digital signal output from the A / D converter And.

  Since the mixer of the present invention adjusts the bias voltage applied to the gate of the switch transistor by changing the cross voltage of the output signals of the first and second buffers, the voltage adjustment range can be widened. Further, by adjusting the first and second bias voltages together, the common voltage of the first and second output terminals can be finely adjusted to an optimum bias point where distortion can be reduced. As a result, it is possible to realize a mixer that is resistant to variations and has low distortion.

It is a figure which shows the structural example of the mixer which concerns on 1st Embodiment. It is a figure which shows the structural example of the buffer contained in a mixer. It is a figure which shows an example of LO signal waveform after the 1st and 2nd buffer before and after cross voltage adjustment, (a) is LO signal waveform before cross voltage adjustment, (b) is LO signal waveform after cross voltage adjustment. It is. It is a figure which shows the structural example of the mixer which concerns on 2nd Embodiment. It is a figure which shows the structural example of the radio | wireless receiver provided with the mixer which concerns on each embodiment. It is a figure for demonstrating the intermodulation in a nonlinear circuit. It is a figure which shows the structural example of the conventional mixer. It is a figure which shows an example of the LO signal waveform of the conventional mixer. It is a figure which shows the other structural example of the wireless receiver provided with the mixer which concerns on each embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, each terminal and a signal of each terminal will be described with the same reference numerals.

(First embodiment)
FIG. 1 is a diagram illustrating a configuration example of a mixer according to the first embodiment. The mixer 1 of FIG. 1 includes a first input terminal Vinp and a second input terminal Vinn, a first output terminal Vap and a second output terminal Van, and the first input terminal Vinp and the first input node NI1. A first capacitor C1 is connected between the switch transistor M1 connected between the first input node NI1 and the first output terminal Vap, and the first input node NI1 and the second output terminal Van. A switch transistor M2 connected between the second input terminal Vinn and the second input node NI2, and a second capacitor C2 connected between the second input node NI2 and the first output terminal Vap. A switch transistor M3 connected in between, and a switch transistor M4 connected between the second input node NI2 and the second output terminal Van are provided.

  The mixer 1 further includes a first buffer 10 that drives the LO signal input to the first LO input terminal Vlop, and a second buffer 11 that drives the inverted LO signal input to the second LO input terminal Vlon. The output of the first buffer 10 is connected to the gates of the switch transistors M1 and M4, and the output of the second buffer 11 is connected to the gates of the switch transistors M2 and M3. The first bias voltage application terminal Vbias1 is connected to the first output terminal Vap via the resistor R1, and the second bias voltage application terminal Vbias2 is connected to the second output terminal Van via the resistor R2. . Control signals Vcnt1 and Vcnt2 and control signals Vcnt3 and Vcnt4 for adjusting a cross voltage Vgc, which will be described later, are input to the first and second buffers 10 and 11 from the control terminals Vcnt1 and Vcnt2 and the control terminals Vcnt3 and Vcnt4, respectively. ing.

  With the above configuration, the differential RF signal input to the first and second input terminals Vinp and Vinn and the differential LO signal input to the first and second LO input terminals Vlop and Vlon are generated. By multiplying, a differential IF signal is generated and output from the first and second output terminals Vap and Van.

  FIG. 2 is a diagram illustrating a configuration example of the buffer 10 included in the mixer 1. The buffer 10 in FIG. 2 is an inverter composed of a PMOS transistor M11 and an NMOS transistor M12, and includes a PMOS transistor M21 connected in parallel with the PMOS transistor M11 and an NMOS transistor M22 connected in parallel with the NMOS transistor M12. The gate terminal of the PMOS transistor M21 is connected to the gate terminal of the PMOS transistor M11 via the switch SW1, and the gate terminal of the NMOS transistor M22 is connected to the gate terminal of the NMOS transistor M12 via the switch SW2.

  The switches SW1 and SW2 are on / off controlled by control signals Vcnt1 and Vcnt2, respectively, and the number of PMOS transistors and NMOS transistors (the number of parallel transistors) can be switched.

  The second buffer 11 has the same configuration as that of the first buffer 10, and detailed description thereof is omitted here. The second buffer 11 receives an inverted signal of the input LO signal of the first buffer 10, and can switch the number of PMOS and NMOS transistors by the control signals Vcnt3 and Vcnt4.

  FIG. 6 is a diagram for explaining intermodulation and intermodulation distortion in a nonlinear circuit. FIG. 6 shows an example in which two interference signals fud1 and fud2 having frequencies higher than the desired signal fd and different frequencies are input to the nonlinear circuit 60.

  In FIG. 6, when signals fud1 and fud2 are input to the nonlinear circuit 60, frequency components (third-order intermodulation distortion components) of 2fud1-fud2 and 2fud2-fud1 are generated by the intermodulation action. For example, in the case where the frequency of the signal fd is a hatched portion in FIG. 6, the third-order intermodulation distortion component of the frequency 2fud1-fud2 overlaps with a part of the frequency of the signal fd. In such a case, the third-order intermodulation distortion component adversely affects the reception performance of the wireless receiver. Generally, distortion performance is expressed using, for example, IP3 (Third order interceptpoint).

[Cross voltage adjustment]
FIG. 3 is a diagram showing an example of waveforms before and after cross voltage adjustment by the control signal for the LO signals Vgp and Vgn after passing through the first and second buffers 10 and 11. FIG. 3A shows a signal waveform before cross voltage adjustment, and FIG. 3B shows a signal waveform after cross voltage adjustment.

  FIG. 3 (a) shows the waveforms of the LO signals Vgp and Vgn when both the switches SW1 and SW2 are controlled to be off. The LO signal Vgp and Vgn when the time (t) elapses from the left to the right in the figure. The change of the voltage (V) of Vgn is shown.

  Here, the voltage when the differential LO signals Vgp and Vgn cross the rising and falling transition periods is referred to as a cross voltage Vgc, and is indicated by a broken line in FIG. 3 indicates the bias voltage Vbias applied from the first and second bias voltage application terminals Vbias1 and Vbias2, and the alternate long and short dash line indicates the threshold voltage of the switch transistors M1 to M4 to the bias voltage Vbias. A voltage obtained by adding the voltage Vth is shown. Here, the switch transistors M1 to M4 are NMOS transistors, the same bias voltage Vbias is applied from the first and second bias voltage application terminals Vbias1 and Vbias2, and the threshold voltages Vth of the switch transistors M1 to M4 are the same. It is assumed that

  FIG. 3A shows an example in which the cross voltage Vgc (broken line in the figure) is higher than the voltage obtained by adding the threshold voltage Vth of the switch transistors M1 to M4 to the bias voltage Vbias (dashed line in the figure). That is, an example in which there is a relationship of the following expression (2) between the cross voltage Vgc, the bias voltage Vbias, and the threshold voltage Vth of the switch transistors M1 to M4 is shown.

  When there is a relationship such as the above equation (2), for example, at time t1, t2, t3 in FIG. 3A, the cross voltages Vgc are both higher than Vbias + Vth (one-dot chain line in the figure), and the switch transistor M1 to M4 are simultaneously turned on. In such a state, the distortion of the mixer 1 is deteriorated, the conversion gain of the mixer is reduced, and the 1 / f noise is also deteriorated, which causes a deterioration in sensitivity of the radio receiver.

  FIG. 3B shows the case where the switch SW2 of the first and second buffers 10 and 11 is on-controlled by the control signals Vcnt2 and Vcnt4 from the state of FIG. The waveform of the LO signals Vgp and Vgn when the switch SW1 continues to be turned off) is shown. FIG. 3B also shows changes in the voltages (V) of the LO signals Vgp and Vgn over time (t), as in FIG. 3A.

  In FIG. 3B, the switch SW2 is turned on, so that the driving capability of the NMOS transistor is increased, and the falling times of the LO signals Vgp and Vgn are shortened. Thereby, as shown in FIG. 3B, the cross voltage Vgc decreases (see times t1 ', t2', and t3 '). That is, the cross voltage Vgc, the bias voltage Vbias, and the threshold voltage Vth of the switch transistors M1 to M4 have the relationship of the following expression (3).

  When there is a relationship such as the above equation (3), it is possible to avoid the switch transistors M1 to M4 from being simultaneously turned on in the case of FIG. Therefore, distortion and conversion gain and noise of the mixer 1 can be improved.

  Although not shown, the switch SW1 of the first and second buffers 10 and 11 is on-controlled by the control signals Vcnt1 and Vcnt3 (the switch SW2 of the first and second buffers 10 and 11 continues to be off-controlled). In this case, the driving capability of the PMOS transistor is increased and the rise time of the LO signals Vgp and Vgn is shortened. As a result, the cross voltage Vgc increases.

  FIG. 2 shows an example in which two PMOS transistors M11 and M21 and two NMOS transistors M12 and M22 are connected in parallel. However, the number of transistors connected in parallel is not limited to two. , Each may be 3 or more. Further, the parallel number of PMOS transistors and the parallel number of NMOS transistors may be different. When the parallel number of PMOS transistors is m and the parallel number of NMOS transistors is n, the number of switches connected to the gate terminals of the transistors connected in parallel and switched on / off based on the control signal is the case of the PMOS transistor. (M-1) are required, and in the case of an NMOS transistor, (n-1) are required. As a result, the parallel number of at least one of the transistors can be changed, and the adjustable range of the cross voltage can be expanded.

[Adjustment of bias voltage]
In the mixer 1 of the present embodiment, in addition to the adjustment of the cross voltage Vgc of the LO signals Vgp and Vgn, the first and second bias voltages Vbias1 and Vbias2 are adjusted. By adjusting the first and second bias voltages Vbias1 and Vbias2, the common voltages of the first and second output terminals Vap and Van are adjusted. The first and second bias voltages Vbias1 and Vbias2 can be finely adjusted. Therefore, when the first and second bias voltages Vbias1 and Vbias2 are the bias voltage Vbias, the right side in the above formulas (2) and (3) can be finely adjusted by fine adjustment of the bias voltage Vbias. This makes it possible to finely adjust to an optimum bias point that can reduce distortion.

  The first and second bias voltages Vbias1 and Vbias2 may be set to different voltages.

  As described above, according to the present embodiment, the LO signals Vgp and Vgn input to the gates of the switch transistors M1 to M4 are adjusted by changing the cross voltage Vgc, so that the voltage adjustment range can be widened. Further, by adjusting the first and second bias voltages Vbias1 and Vbias2 together, the common voltage of the first and second output terminals Vap and Van can be finely adjusted to an optimum bias point. As a result, it is possible to realize a mixer that is resistant to variations and has low distortion.

  Further, since the mixer 1 of the present embodiment does not require capacitors (capacitors C71 to C74 in FIG. 7) for receiving the first and second LO signals Vlop and Vlon, the area can be reduced as compared with the prior art. .

  In [Adjustment of bias voltage] of the present embodiment, the common voltage is adjusted by adjusting the first and second bias voltages Vbias1 and Vbias2, but the present invention is not limited to this. The same effect can also be obtained in an IQ orthogonal mixer.

  In the second embodiment below, a bias voltage having a predetermined voltage value is applied as the first and second bias voltages Vbias1 and Vbias2, and the resistance values of the resistors R1 and R2 are switched using the resistors R1 and R2 as variable resistors. An example of adjusting the common voltage will be described.

(Second Embodiment)
FIG. 4 is a diagram illustrating a configuration example of a mixer according to the second embodiment. FIG. 4 shows an example of a mixer 1A in which an IF amplifier 2 is connected to the subsequent stage of FIG. In the following description of FIG. 4, repeated description of components common to FIG. 1 may be omitted.

  4, the IF amplifier 2 includes input terminals Vap and Van, output terminals Voutp and Voutn, a resistor Rs, a feedback resistor Rf, and a differential amplifier circuit 12. The input terminal Vap is a differential amplifier circuit via the resistor Rs. 12 is connected to one input terminal, the input terminal Van is connected to the other input terminal of the differential amplifier circuit 12 via a resistor Rs, and the differential amplifier circuit 12 is connected from the output terminals Voutp and Voutn via a feedback resistor Rf. Is fed back to each input terminal. The IF amplifier 2 includes a capacitor Cf (capacitance value is also referred to as Cf) connected in parallel to the feedback resistor Rf.

  The IF amplifier 2 amplifies and outputs an input signal with a gain A determined by A = Rf / Rs, and also has a low-pass filter characteristic with a cutoff frequency fc of fc = 1 / 2πRfCf. Further, the common mode feedback works so that the voltage VCM is output from the differential amplifier circuit 12.

  Common voltages Vapc and Vanc in the mixer 1A of FIG. 4 are expressed by the following equations (4) and (5).

  Here, when 0 V is applied to the first and second bias voltages Vbias1 and Vbias2, the common voltages Vapc and Vanc are voltages obtained by voltage-dividing the voltage VCM from the above equations (4) and (5). For example, when the resistors R1 and R2 are variable resistors, the common voltages Vapc and Vanc can be controlled by switching the resistance values of the resistors R1 and R2, and the bias point can be optimized. The variable resistor is, for example, a plurality of resistance elements connected in series or in parallel, and at least one resistance element of the plurality of resistance elements connected in parallel or in series, and at least performing on / off control of a conduction or non-conduction state. This can be realized by using one switch and controlling each switch on and off.

  As described above, according to the present embodiment, the common voltages Vapc and Vanc can be finely adjusted by adjusting the resistance values of the resistors R1 and R2. Therefore, in this embodiment as well as the first embodiment, it is possible to realize a mixer that is resistant to variations and has low distortion.

  The resistance values of the resistors R1 and R2 may be set to different values. The resistor Rs is not always necessary, and the same effect can be obtained even if it is not necessary.

  In each of the above embodiments, the first to fourth switch transistors have been described using NMOS transistors, but PMOS transistors may be used as the first to fourth switch transistors. In each of the above embodiments, all the transistors used in the mixer are not limited to MOS transistors. For example, the same effect can be obtained even if a circuit is configured using some or all of the bipolar transistors.

(Application example)
FIG. 5 is a diagram illustrating a configuration example of a wireless receiver including the mixer according to the first or second embodiment.

  In FIG. 5, the wireless receiver has an LNA (Low Noise Amplifier) 22 that amplifies an input RF signal from the antenna 21 and an output signal from the LNA 22 as the first or second RF signal in the first or second embodiment. The mixer 23 described, a variable gain amplifier circuit 24 that amplifies the IF signal output from the mixer 23, an A / D converter 25 that analog-digital converts the output signal of the variable gain amplifier circuit 24, and outputs it as a digital signal; And a DSP 26 for processing the digital signal output from the A / D converter 25. The radio receiver further includes a VCO 29 that generates an LO signal, an N frequency dividing circuit 28, and an LO buffer 27 that drives the mixer 23. Thus, the reception performance of the wireless receiver can be improved by using the mixer described in the first or second embodiment for the wireless receiver.

  In the first and second embodiments, the capacitors C1 and C2 have been described as being provided inside the mixer, but the present invention is not limited to this. For example, it may be provided outside the mixer. Specifically, for example, in FIG. 5, the capacitors C1 and C2 may be provided between the LNA 22 and the mixer 23 or inside the LNA 22. Further, the capacitors C1 and C2 may be deleted, and the LNA 22 and the mixer 23 may be directly connected.

  Further, even if the mixer 23 is an IQ orthogonal method, the same effect can be obtained. In that case, a 90 ° phase shifter 30 is required to generate an IQ signal as shown in FIG.

  The many features and advantages of the present invention are apparent from the written description, and thus, it is intended by the appended claims to cover all such features and advantages of the invention. Further, since many changes and modifications will readily occur to those skilled in the art, the present invention should not be limited to the exact configuration and operation as illustrated and described. Accordingly, all suitable modifications and equivalents are intended to be within the scope of the present invention.

  Since the mixer according to the present invention is a low distortion mixer that is resistant to variations, it is useful for radio communication equipment such as an in-vehicle radio tuner.

1, 1A, 23 Mixer 10, 11 First and second buffer 12 Differential amplifier circuit 21 Antenna 22 LNA
24 Variable Gain Amplifier 25 A / D Converter 26 DSP
29 VCO
30 90 ° phase shifters M1, M2, M3, M4 switch transistors (first, second, third and fourth switch transistors)
M11, M21 PMOS transistor (P-type transistor)
M12, M22 NMOS transistor (N-type transistor)
SW1, SW2 switch R1, R2 resistance (first and second resistance)
Rs resistance (third resistance)
Rf feedback resistors C1, C2 capacitances (first and second capacitances)
NI1, NI2 first and second input nodes NO1, NO2, NO3 first, second and third output nodes Vinp, Vinn first and second input terminals Vrop, Vlon first and second LO input terminals Vap, Van first First and second output terminals Vgp and Vgn LO signals (first and second LO signals)
Vcnt1 to Vcnt4 Control terminals Vbias1, Vbias1 First and second bias voltage application terminals Vgc Cross voltage

Claims (7)

A first RF (Radio Frequency) signal input to the first input terminal, a second RF signal that is an inverted signal of the first RF signal input to the second input terminal, and an input to the first LO (Local Oscillator) input terminal The first LO signal and the second LO signal, which is the inverted signal of the first LO signal input to the second LO input terminal, are multiplied to generate an IF (Intermediate Frequency) signal to generate first and second output terminals A differential output to the mixer,
First and second switch transistors respectively connected between the first input terminal and the first and second output terminals;
Third and fourth switch transistors respectively connected between the second input terminal and the first and second output terminals;
A first buffer connected between the first LO input terminal and gate terminals of the first and fourth switch transistors;
A second buffer connected between the second LO input terminal and the gate terminals of the second and third switch transistors;
First and second bias voltage application terminals to which one ends of first and second resistors are connected to the first and second output terminals, respectively, and a bias voltage is applied via the first and second resistors, respectively. With
The first and second buffers each include a control terminal for adjusting a cross voltage between signals output from each of the first and second buffers. The mixer according to claim 1, wherein
A first capacitor having one end receiving the first RF signal and the other end connected to the first input terminal;
A second capacitor having one end receiving the second RF signal and the other end connected to the second input terminal;
The mixer, wherein the first and second input terminals are supplied with the first and second RF signals via the first and second capacitors, respectively. The mixer according to claim 1, wherein
The first and second buffers are inverters composed of P-type transistors and N-type transistors,
A plurality of P-type transistors respectively connected in parallel between a high-potential power supply and the output terminals of the first and second buffers;
A plurality of N-type transistors respectively connected in parallel between a low-potential power source and the output terminals of the first and second buffers;
A conductive state and a non-conductive state are set between the gate terminals of the plurality of P-type transistors and the plurality of N-type transistors and the input terminals of the first and second buffers by a control signal input to the control terminal. A mixer comprising: a switch that can be switched. The mixer according to claim 1, wherein
At least one of the first and second resistors is
A plurality of resistance elements connected in series or in parallel;
At least one switch connected in parallel or in series to at least one of the plurality of resistance elements and configured to be able to switch between a conductive state and a non-conductive state;
The mixer is configured such that a resistance value can be adjusted by switching between a conductive state and a non-conductive state by the switch. The mixer according to claim 1, wherein
A differential amplifier circuit for amplifying the IF signal;
A feedback resistor connected to provide negative feedback between the output terminal of the differential amplifier circuit and the input terminal of the differential amplifier circuit;
The bias voltage at the first output terminal is determined by the common voltage of the differential amplifier circuit, the feedback resistor, and the first resistor, and the common voltage of the differential amplifier circuit, the feedback resistor, and the second resistor are determined. A mixer, wherein a bias voltage at the second output terminal is determined by a resistor. The mixer according to any one of claims 1 to 5,
A mixer characterized by an IQ (In-Phase / Quadrature-Phase) orthogonal method. LNA (Low Noise Amplifier) that amplifies the input RF signal from the antenna;
The mixer according to any one of claims 1 to 6, wherein the LNA output signal is input to the first and second input terminals;
A VCO (Voltage Controlled Oscillator) that generates the first and second LO signals input to the first and second LO input terminals of the mixer;
A variable gain amplifier circuit for amplifying the IF signal output from the mixer;
An A / D (Analog to Digital) converter for digitally converting the analog output signal of the variable gain amplifier circuit;
A radio receiver comprising a DSP (Digital Signal Processor) for processing a digital signal output from the A / D converter.

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