JPWO2013021414A1 - Capacitance type input detection method - Google Patents

Capacitance type input detection method Download PDF

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JPWO2013021414A1
JPWO2013021414A1 JP2013527746A JP2013527746A JPWO2013021414A1 JP WO2013021414 A1 JPWO2013021414 A1 JP WO2013021414A1 JP 2013527746 A JP2013527746 A JP 2013527746A JP 2013527746 A JP2013527746 A JP 2013527746A JP WO2013021414 A1 JPWO2013021414 A1 JP WO2013021414A1
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元俊 南部
元俊 南部
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Abstract

【課題】入力操作体と検出電極間の静電容量から検出電極に対する入力操作体の入力操作を検出する静電容量式入力検出方式を提供する。【解決手段】検出電極と入力操作体間の静電容量を介して検出電極に表れる交流検出信号の受信レベルを検出する信号検出手段が、検出電極に表れる交流検出信号を交流検出信号の周期より充分に長い積分動作期間中に積分して出力する積分回路を有し、積分回路の出力の傾きから前記交流検出信号の受信レベルを拡大させて検出し、検出電極と入力操作体間の距離を求める。【選択図】図1An electrostatic capacity type input detection method for detecting an input operation of an input operation body with respect to a detection electrode from a capacitance between the input operation body and a detection electrode is provided. Signal detection means for detecting a reception level of an AC detection signal appearing on a detection electrode via a capacitance between the detection electrode and an input operation body converts the AC detection signal appearing on the detection electrode from an AC detection signal cycle. It has an integration circuit that integrates and outputs during a sufficiently long integration operation period, detects the reception level of the AC detection signal from the slope of the output of the integration circuit, and detects the distance between the detection electrode and the input operating body. Ask. [Selection] Figure 1

Description

本発明は、指などの入力操作体が接近して静電容量が増大する検出電極の配置位置から入力操作体の入力操作位置を検出する静電容量式入力検出方式に関する。   The present invention relates to a capacitance type input detection method for detecting an input operation position of an input operation body from an arrangement position of a detection electrode where an input operation body such as a finger approaches and the capacitance increases.

電子機器のディスプレーに表示されたアイコンなどを指示入力するポインティングデバイスとして静電容量式入力検出方式により入力操作や入力操作位置を検出する静電容量式タッチパネルが知られている。この静電容量式入力検出方式は、入力操作する入力操作体が接近する検出電極の浮遊容量(入力操作体と検出電極間の静電容量)が増大することに着目し、入力操作体との静電容量が変化する検出電極の配置位置から入力操作自体や入力操作体の入力操作位置を検出している。   2. Description of the Related Art A capacitive touch panel that detects an input operation and an input operation position by a capacitive input detection method is known as a pointing device that inputs an instruction displayed on a display of an electronic device. This capacitance type input detection method pays attention to the fact that the floating capacitance (capacitance between the input operation body and the detection electrode) of the detection electrode approaching the input operation body to be input increases. The input operation itself and the input operation position of the input operation body are detected from the position of the detection electrode where the capacitance changes.

しかしながら、入力操作体と検出電極間の静電容量は、例えば、入力操作体が指であるとして、検出電極から10cm離れた入力操作位置で約50fFと極めて微小であり、その静電容量から直接入力操作体の接近を検出することは困難であった。そこで、従来の入力検出方式は、多数のX側検出電極とY側検出電極を絶縁基板の表裏で交差するようにマトリックス状に形成し、入力操作体がいずれの位置にあっても、いずれかのX側検出電極とY側検出電極が近接するようにして、各検出電極の静電容量の変化を相対比較して入力操作位置を検出している(特許文献1)。   However, the capacitance between the input operation body and the detection electrode is extremely small, for example, about 50 fF at an input operation position 10 cm away from the detection electrode, assuming that the input operation body is a finger, and directly from the capacitance. It was difficult to detect the approach of the input operation body. Therefore, in the conventional input detection method, a large number of X-side detection electrodes and Y-side detection electrodes are formed in a matrix shape so as to intersect each other on the front and back of the insulating substrate, and the input operation body is in either position. The X-side detection electrode and the Y-side detection electrode are close to each other, and the input operation position is detected by relatively comparing the change in capacitance of each detection electrode (Patent Document 1).

この従来の入力検出方式では、入力操作面に沿って多数のX側検出電極とY側検出電極を配置し、背面側のディスプレーを目視できるように透明体で形成する必要があり、高価になると共に、入力操作位置の検出分解能を上げるには、より多数のX側検出電極とY側検出電極を密に配置する必要があり、全ての検出電極についての静電容量の変化を検出する走査時間を要し、短時間に入力位置を検出できなかった。   In this conventional input detection method, it is necessary to arrange a large number of X-side detection electrodes and Y-side detection electrodes along the input operation surface, and it is necessary to form a transparent body so that the display on the back side can be seen, which is expensive. In addition, in order to increase the detection resolution of the input operation position, it is necessary to arrange a larger number of X-side detection electrodes and Y-side detection electrodes densely, and a scanning time for detecting a change in capacitance for all the detection electrodes. The input position could not be detected in a short time.

そこで、入力操作面の周囲にのみ検出電極を配置し、入力操作体と検出電極間に高誘電率の誘電体を介在させ、大容量とした入力操作体と検出電極間の静電容量の変化から入力位置を検出する静電容量式入力検出方式が提案されている(特許文献2)。この特許文献2に記載の静電容量式入力検出方式は、高誘電率の誘電体からなる感触部材を入力操作面に沿った全体に配置し、入力操作位置と検出電極間の静電容量を、空気中に比べて誘電率の高い感触部材により拡大し、増大させた静電容量の変化から入力操作面上の入力操作位置を検出している。   Therefore, the detection electrode is arranged only around the input operation surface, and a dielectric having a high dielectric constant is interposed between the input operation body and the detection electrode, so that the capacitance changes between the input operation body and the detection electrode. An electrostatic capacitance type input detection method for detecting an input position from the above has been proposed (Patent Document 2). In the capacitance type input detection method described in Patent Document 2, a touch-sensitive member made of a dielectric material having a high dielectric constant is arranged along the input operation surface, and the capacitance between the input operation position and the detection electrode is determined. The input operation position on the input operation surface is detected from a change in capacitance that is enlarged by a touch member having a higher dielectric constant than in the air.

また、複数の検出電極を各検出電極毎に積分回路を接続し、積分回路の出力の勾配により、入力操作体が接触する検出電極を検出し、その検出電極の配置位置から入力操作位置を検出する位置検出装置も知られている(特許文献3)。この従来の位置検出装置では、積分回路の出力が、検出電極の抵抗値と検出電極についての浮遊容量を乗じた時定数に応じて変化し、入力操作体が接触した検出電極の浮遊容量は増大するので、一定時間後に積分回路の出力が所定値以下となる検出電極を入力操作体が接触した検出電極として、その検出電極の配置位置から入力操作位置を検出する。   In addition, an integration circuit is connected to each detection electrode for multiple detection electrodes, the detection electrode that the input operating body contacts is detected based on the gradient of the output of the integration circuit, and the input operation position is detected from the position of the detection electrode. A position detecting device is also known (Patent Document 3). In this conventional position detection device, the output of the integration circuit changes according to the time constant obtained by multiplying the resistance value of the detection electrode and the floating capacitance of the detection electrode, and the floating capacitance of the detection electrode that the input operating body contacts increases. Therefore, the input operation position is detected from the arrangement position of the detection electrode, using the detection electrode whose output from the integration circuit becomes a predetermined value or less after a certain time as the detection electrode with which the input operation body is in contact.

複数の検出電極の配置方向と直交方向の入力操作位置は、各検出電極の両端にそれぞれ積分回路を接続し、それぞれの積分回路の出力を比較して検出する。検出電極は、その長手方向に沿った距離に抵抗値が比例するように構成され、入力操作体の入力操作位置(接触位置)から各両端までの距離に検出電極の抵抗が比例するようにしている。これにより、それぞれの積分回路の出力も、その積分回路が接続する検出電極の一端から入力操作位置までの距離に応じて緩やかに上昇するので、それぞれの積分回路の出力を相対比較して検出電極の長手方向に沿った入力操作位置を検出する。   Input operation positions in a direction orthogonal to the arrangement direction of the plurality of detection electrodes are detected by connecting integration circuits to both ends of each detection electrode and comparing the outputs of the integration circuits. The detection electrode is configured such that the resistance value is proportional to the distance along the longitudinal direction, and the resistance of the detection electrode is proportional to the distance from the input operation position (contact position) of the input operation body to each end. Yes. As a result, the output of each integration circuit also rises gently according to the distance from one end of the detection electrode to which the integration circuit is connected to the input operation position. The input operation position along the longitudinal direction is detected.

特開2005−337773号公報JP 2005-337773 A 特開平8−171449号公報JP-A-8-171449 特許第3861333号公報Japanese Patent No. 3861333

特許文献1により開示されている静電容量式入力検出方式では、入力操作位置の検出精度を上げるために、入力操作面上に多数の検出電極を挟ピッチで配置する必要があり、多数の検出電極について走査する必要があるため、検出時間を要するとともに、背面側にディスプレーを配置する場合には、透明導電材料で形成しても完全な透明体ではないので、その背面側に配置されるディスプレーがみずらいという問題がある。   In the capacitance-type input detection method disclosed in Patent Document 1, in order to increase the detection accuracy of the input operation position, it is necessary to arrange a large number of detection electrodes on the input operation surface at a narrow pitch, and a large number of detections. Since it is necessary to scan the electrodes, detection time is required, and when the display is arranged on the back side, even if it is formed of a transparent conductive material, it is not a complete transparent body. There is a problem that it is difficult.

上記問題を解決するために入力操作面上に検出電極を配置しない構成とした特許文献2に開示された静電容量式入力検出方式であっても、入力操作面に平行に高誘電率の感触部材を配置するので、透過率低下の問題は解決できない。   In order to solve the above problem, even in the capacitance type input detection method disclosed in Patent Document 2 in which the detection electrode is not arranged on the input operation surface, a high dielectric constant feel parallel to the input operation surface Since the members are arranged, the problem of the decrease in transmittance cannot be solved.

また、指などの入力操作体を感触部材に触れて入力操作を行わなければ、入力操作体と検出電極間の静電容量が大幅に変化するので、感触部材に触れて入力操作を行う必要があり、入力操作面に平行な二次元の入力操作位置の検出に限られる。更に、感触部材に触れて入力操作を行うので、操作性が損なわれるとともに、入力操作体により透明体とする感触部材が汚れ、美観が損なわれたり、透過率が低下する問題がある。   In addition, if the input operation body such as a finger is not touched with the touch member and the input operation is not performed, the capacitance between the input operation body and the detection electrode changes significantly. Therefore, it is necessary to perform the input operation by touching the touch member. Yes, it is limited to the detection of a two-dimensional input operation position parallel to the input operation surface. Further, since the input operation is performed by touching the touch member, there is a problem that the operability is impaired, the touch member made transparent by the input operation body is soiled, the aesthetic appearance is impaired, and the transmittance is lowered.

特許文献3に記載の静電容量式入力検出方式は、入力操作体の入力操作による検出電極の抵抗値や浮遊容量の変化を積分回路の出力に拡大して、その出力から入力操作位置を検出するが、過渡現象によって上昇する積分回路への入力は、検出電極の浮遊容量や抵抗値に比例せず、積分回路の出力から検出電極の浮遊容量や抵抗値を直接得るものではないので、入力操作位置を精度よく検出することはできない。従って、検出電極の浮遊容量の変化から入力操作位置を検出する場合には、多数の検出電極の浮遊容量の変化を相対比較して、特定の検出電極の配置位置から入力操作位置を検出するものであり、特許文献1と同様に検出方向に沿って多数の検出電極を配置する必要がある。   The capacitance type input detection method described in Patent Document 3 expands the change in the resistance value and stray capacitance of the detection electrode due to the input operation of the input operation body to the output of the integration circuit, and detects the input operation position from the output. However, the input to the integration circuit, which rises due to a transient phenomenon, is not proportional to the stray capacitance or resistance value of the detection electrode, and does not directly obtain the stray capacitance or resistance value of the detection electrode from the output of the integration circuit. The operation position cannot be detected with high accuracy. Therefore, when the input operation position is detected from the change in the stray capacitance of the detection electrode, the input operation position is detected from the arrangement position of the specific detection electrode by relatively comparing the change in the stray capacitance of many detection electrodes. As in Patent Document 1, it is necessary to arrange a large number of detection electrodes along the detection direction.

また、検出電極についての浮遊容量は、非接触の入力操作体と検出電極間の静電容量が上述の通り極めて微小値であるため、特許文献3に記載の静電容量式検出方式では、これを検出せず、入力操作体が検出電極に接触することを前提とした入力操作体と接地電位間の静電容量を検出電極の浮遊容量として比較するものであり、検出電極に入力操作体を接触させる入力操作しか検出できない。   In addition, since the electrostatic capacitance between the non-contact input operation body and the detection electrode is extremely small as described above, the capacitance detection method described in Patent Document 3 has a stray capacitance for the detection electrode. The capacitance between the input operating body and the ground potential assuming that the input operating body is in contact with the detection electrode without comparing the detection potential is compared as the stray capacitance of the detection electrode. Only the input operation to contact can be detected.

本発明は、このような従来の問題点を考慮してなされたものであり、入力操作体と検出電極間の静電容量から検出電極に対する入力操作体の入力操作を検出する静電容量式入力検出方式を提供することを目的とする。   The present invention has been made in consideration of such conventional problems, and is a capacitance type input that detects an input operation of the input operation body with respect to the detection electrode from the capacitance between the input operation body and the detection electrode. The purpose is to provide a detection method.

また、入力操作面に接近するだけの非接触の入力操作の入力操作位置を検出可能な静電容量式入力検出方式を提供することを目的とする。   It is another object of the present invention to provide a capacitance type input detection method capable of detecting an input operation position of a non-contact input operation that only approaches the input operation surface.

上述の目的を達成するため、請求項1の静電容量式入力検出方式は、絶縁ケースに配置される検出電極と、入力操作体と検出電極との相対電位を変動させる交流検出信号を発信する発信手段と、検出電極と入力操作体間の静電容量を介して検出電極に表れる交流検出信号の受信レベルを検出する信号検出手段とを備え、検出電極に表れる交流検出信号の受信レベルから、検出電極と入力操作体間の距離を求め、入力操作体による入力操作を検出する静電容量式入力検出方式であって、信号検出手段は、前記検出電極に表れる交流検出信号を交流検出信号の周期より充分に長い積分動作期間中に積分して出力する積分回路を有し、積分回路の出力の傾きから前記交流検出信号の受信レベルを検出することを特徴とする。   In order to achieve the above-mentioned object, the capacitance type input detection system according to claim 1 transmits a detection electrode arranged in an insulating case and an AC detection signal for changing a relative potential between the input operation body and the detection electrode. A transmission means, and a signal detection means for detecting the reception level of the AC detection signal appearing on the detection electrode via the capacitance between the detection electrode and the input operation body, from the reception level of the AC detection signal appearing on the detection electrode, A capacitance type input detection method for obtaining a distance between a detection electrode and an input operation body and detecting an input operation by the input operation body, wherein the signal detection means converts an AC detection signal appearing on the detection electrode to an AC detection signal. An integration circuit that integrates and outputs during an integration operation period sufficiently longer than the cycle is provided, and the reception level of the AC detection signal is detected from the slope of the output of the integration circuit.

検出電極に表れる交流検出信号の受信レベルは、検出電極と入力操作体間の静電容量Cmに比例し、積分回路は、交流検出信号を交流検出信号の周期より充分に長い積分動作期間中に積分して出力するので、検出電極と入力操作体間の微小な静電容量Cmに比例する受信レベルが、積分回路の出力の傾きに拡大して表される。   The reception level of the AC detection signal appearing on the detection electrode is proportional to the capacitance Cm between the detection electrode and the input operating body, and the integration circuit converts the AC detection signal into an integration operation period sufficiently longer than the cycle of the AC detection signal. Since the signal is integrated and output, the reception level proportional to the minute capacitance Cm between the detection electrode and the input operation body is expanded and expressed in the inclination of the output of the integration circuit.

検出電極と入力操作体間の静電容量Cmは、検出電極と入力操作体間の距離をd、真空の誘電率をε0、空気の比誘電率εを約1、入力操作体と検出電極の対向面積をsとして、Cm=ε0・s/dで表され、その間の距離dに反比例するので、入力位置検出手段は、積分回路の出力の傾きで表される交流検出信号の受信レベルViから検出電極と入力操作体間の距離dが得られ、検出電極に入力操作体を接近させる入力操作やその入力操作位置を検出できる。   The capacitance Cm between the detection electrode and the input operation body is expressed as follows. The distance between the detection electrode and the input operation body is d, the dielectric constant of vacuum is ε0, the relative dielectric constant ε of air is about 1, and the input operation body and the detection electrode are Since the opposed area is s, it is expressed by Cm = ε0 · s / d, and is inversely proportional to the distance d between them, so that the input position detecting means is based on the reception level Vi of the AC detection signal expressed by the slope of the output of the integrating circuit. A distance d between the detection electrode and the input operation body is obtained, and an input operation for bringing the input operation body closer to the detection electrode and its input operation position can be detected.

請求項2の静電容量式入力検出方式は、積分回路が、検出電極の出力側に接続された積分用抵抗と、非反転入力端子の第1基準電圧に対して、検出電極から積分用抵抗を介して反転入力端子に入力される前記交流検出信号の入力電圧との差分を出力する積分用オペアンプと、積分用オペアンプの反転入力端子と出力端子間に接続された積分用コンデンサとからなり、信号検出手段は、更に、積分用オペアンプの反転入力端子と非反転入力端子間に発生するオフセット電圧を相殺するオフセット調整電圧を、積分用オペアンプの反転入力端子若しくは非反転入力端子に加えるオフセット調整手段を有することを特徴とする。   In the capacitance type input detection system according to claim 2, the integrating circuit has an integrating resistor connected to the output side of the detecting electrode and an integrating resistor connected from the detecting electrode to the first reference voltage of the non-inverting input terminal. An integration operational amplifier that outputs a difference from the input voltage of the AC detection signal that is input to the inverting input terminal via, and an integration capacitor connected between the inverting input terminal and the output terminal of the integration operational amplifier, The signal detection means further applies an offset adjustment voltage that cancels an offset voltage generated between the inverting input terminal and the non-inverting input terminal of the integrating operational amplifier to the inverting input terminal or the non-inverting input terminal of the integrating operational amplifier. It is characterized by having.

信号検出手段は、更に、積分用オペアンプの反転入力端子と非反転入力端子間に発生するオフセット電圧がオフセット調整電圧により相殺されるので、積分して積分用オペアンプから出力される出力信号にオフセット電圧が含まれず、検出電極と入力操作体間の微小な静電容量を表す交流検出信号のみを積分して積分用オペアンプから拡大した受信レベルとして出力できる。   In the signal detection means, the offset voltage generated between the inverting input terminal and the non-inverting input terminal of the integrating operational amplifier is canceled by the offset adjustment voltage, so that the offset voltage is integrated into the output signal output from the integrating operational amplifier. Is not included, and only the AC detection signal representing a minute capacitance between the detection electrode and the input operation body can be integrated and output as an expanded reception level from the integrating operational amplifier.

請求項3の静電容量式入力検出方式は、オフセット調整手段が、所定のオフセット調整期間中に第2基準電圧とした積分用抵抗の入力側に非反転入力端子が接続するとともに、積分用オペアンプの出力に反転入力端子が接続し、オフセット調整期間中に、非反転入力端子の第2基準電圧に対して、反転入力端子に入力される帰還用オペアンプの出力電圧との差分を出力する帰還用オペアンプと、帰還用オペアンプの出力と積分用オペアンプの非反転入力端子間に接続され、オフセット調整期間中に閉じ動作し、積分動作期間中に開動作するスイッチと、積分用オペアンプの非反転入力端子に接続し、オフセット調整期間中に帰還用オペアンプの出力電圧で充電されるオフセット調整電圧を、積分動作期間中に積分用オペアンプの非反転入力端子に加えるホールド用コンデンサとからなることを特徴とする。   The capacitance type input detection method according to claim 3 is characterized in that the offset adjusting means has a non-inverting input terminal connected to the input side of the integrating resistor which is set as the second reference voltage during the predetermined offset adjusting period, and the integrating operational amplifier. The inverting input terminal is connected to the output of the non-inverting input terminal during the offset adjustment period, and the difference between the output voltage of the feedback operational amplifier input to the inverting input terminal and the second reference voltage of the non-inverting input terminal is output. An operational amplifier, a switch that is connected between the output of the feedback operational amplifier and the non-inverting input terminal of the integrating operational amplifier, operates to close during the offset adjustment period, and opens during the integrating operation period, and the non-inverting input terminal of the integrating operational amplifier To the non-inverting input terminal of the integrating operational amplifier during the integration operation period. Characterized in that comprising a hold capacitor to be added to.

オフセット調整期間中は、積分用オペアンプの非反転入力端子に、第2基準電圧とその直前に積分用オペアンプから出力された出力電圧との差分が入力され、反転入力端子に第2基準電圧が入力される。積分用オペアンプから出力される出力電圧は、非反転入力端子の入力電圧と反転入力端子の入力電圧の差分にオフセット電圧加えた電圧を積分した値であり、帰還用オペアンプで出力電圧が非反転入力端子に負帰還されることにより、出力電圧はオフセット電圧に収束し、定電圧となる。このとき、帰還用オペアンプの出力電圧は、オフセット電圧を加えて積分用オペアンプの非反転入力端子と反転入力端子間の入力電圧の差分が0となるオフセット調整電圧で安定し、ホールド用コンデンサの充電電圧は、オフセット調整電圧となる。   During the offset adjustment period, the difference between the second reference voltage and the output voltage output from the integrating operational amplifier immediately before is input to the non-inverting input terminal of the integrating operational amplifier, and the second reference voltage is input to the inverting input terminal. Is done. The output voltage output from the integrating operational amplifier is the integrated value of the difference between the input voltage at the non-inverting input terminal and the input voltage at the inverting input terminal plus the offset voltage. By negative feedback to the terminal, the output voltage converges to the offset voltage and becomes a constant voltage. At this time, the output voltage of the feedback operational amplifier is stabilized by the offset adjustment voltage that adds the offset voltage and the difference in the input voltage between the non-inverting input terminal and the inverting input terminal of the integrating operational amplifier becomes 0, and the holding capacitor is charged. The voltage is an offset adjustment voltage.

積分動作期間中は、帰還用オペアンプの出力と積分用オペアンプの非反転入力端子間が遮断され、積分用オペアンプの非反転入力端子にホールド用コンデンサからオフセット調整電圧が加わる。その結果、積分動作期間中は、積分用オペアンプの出力にオフセット電圧が含まれず、交流検出信号の受信レベルのみが積分され拡大して表される。   During the integration operation period, the output of the feedback operational amplifier and the non-inverting input terminal of the integrating operational amplifier are disconnected, and an offset adjustment voltage is applied from the holding capacitor to the non-inverting input terminal of the integrating operational amplifier. As a result, during the integration operation period, the offset voltage is not included in the output of the integrating operational amplifier, and only the reception level of the AC detection signal is integrated and expanded.

請求項4の静電容量式入力検出方式は、絶縁ケースに互いに絶縁して配置される複数の検出電極と、複数の各検出電極を選択的に信号検出手段へ切り換え接続する切り換え手段とを備え、前記各検出電極についてそれぞれ信号検出手段が検出した交流検出信号の受信レベルと、各検出電極の配置位置とから、入力操作体の入力操作位置を検出することを特徴とする。   According to a fourth aspect of the present invention, there is provided a capacitance type input detection method comprising: a plurality of detection electrodes arranged in an insulating case insulated from each other; and a switching means for selectively switching and connecting each of the plurality of detection electrodes to the signal detection means. The input operation position of the input operation body is detected from the reception level of the AC detection signal detected by the signal detection means for each detection electrode and the arrangement position of each detection electrode.

複数の各検出電極について検出した交流検出信号の受信レベルから、各検出電極と入力操作体との距離が得られるので、検出電極から入力操作体が離れた非接触の入力操作であっても、その入力操作位置を検出できる。   Since the distance between each detection electrode and the input operation body is obtained from the reception level of the AC detection signal detected for each of the plurality of detection electrodes, even in a non-contact input operation in which the input operation body is separated from the detection electrode, The input operation position can be detected.

請求項1の発明によれば、指などの入力操作体を入力操作面へ接近させた微小な静電容量の変化を検出できるので、入力操作体を検出電極へ接近させるだけの入力操作や入力操作位置を検出できる。   According to the first aspect of the present invention, it is possible to detect a minute change in electrostatic capacitance when an input operation body such as a finger is brought close to the input operation surface. The operation position can be detected.

また、検出電極と入力操作体間の静電容量から両者の距離が得られるので、少ない検出電極で二次元若しくは三次元の入力操作位置を検出できる。   In addition, since the distance between the detection electrode and the input operation body can be obtained from the capacitance, the two-dimensional or three-dimensional input operation position can be detected with a small number of detection electrodes.

請求項2の発明によれば、入力操作体と検出電極間の数10fF程度の微小な静電容量に比例する交流検出信号の受信レベルを拡大させて検出でき、高誘電率の接触部材を介在させることなく、非接触で検出電極に接近する入力操作体との距離を検出できる。   According to the second aspect of the present invention, the reception level of the AC detection signal proportional to a small capacitance of about several tens of fF between the input operation body and the detection electrode can be expanded and detected, and a high dielectric constant contact member is interposed. The distance to the input operation body that approaches the detection electrode in a non-contact manner can be detected without causing the contact to occur.

請求項3の発明によれば、積分用アンプのオフセット電圧の影響を受けずに、交流検出信号の受信レベルを拡大させてその出力電圧波形の傾きに表すことができる。   According to the third aspect of the present invention, the reception level of the AC detection signal can be expanded and expressed in the slope of the output voltage waveform without being affected by the offset voltage of the integrating amplifier.

請求項4の発明によれば、複数の各検出電極について検出した交流検出信号の受信レベルから、各検出電極と入力操作体との距離が得られるので、限られた数の検出電極が平面上若しくは立体上の入力操作位置を検出できる。   According to the fourth aspect of the present invention, since the distance between each detection electrode and the input operation body can be obtained from the reception level of the AC detection signal detected for each of the plurality of detection electrodes, a limited number of detection electrodes are on the plane. Alternatively, it is possible to detect a three-dimensional input operation position.

本発明の第1実施の形態に係る静電容量式入力検出方式1を示す回路図である。It is a circuit diagram which shows the electrostatic capacitance type input detection system 1 which concerns on 1st Embodiment of this invention. 指示入力装置50の平面図である。3 is a plan view of an instruction input device 50. FIG. 図2のA−A線断面図である。It is the sectional view on the AA line of FIG. 静電容量式入力検出方式1を利用した指示入力装置50のブロック図である。It is a block diagram of the instruction | indication input device 50 using the electrostatic capacitance type input detection system. 指示入力装置50の電源回路の等価回路図である。3 is an equivalent circuit diagram of a power supply circuit of the instruction input device 50. FIG. 交流検出信号SGが流れる検出電極11の周囲の等価回路図である。It is an equivalent circuit diagram around the detection electrode 11 through which the AC detection signal SG flows. 積分処理回路14のオフセット調整期間中の動作を示すブロック図である。FIG. 6 is a block diagram showing an operation of the integration processing circuit 14 during an offset adjustment period. オフセット期間中のオフセット電圧ΔVと帰還用オペアンプ26の出力電圧Vfの算定値を示す説明図である。It is explanatory drawing which shows the calculated value of offset voltage (DELTA) V in the offset period, and the output voltage Vf of the operational amplifier 26 for feedback. 図1の(a)(b)(c)に示す各部の電圧波形図である。It is a voltage waveform diagram of each part shown in (a) (b) (c) of Drawing 1. 本発明の第2実施の形態に係る静電容量式入力検出方式の積分処理回路40を示すブロック図である。It is a block diagram which shows the integration process circuit 40 of the electrostatic capacitance type input detection system which concerns on 2nd Embodiment of this invention.

以下、本発明の第1実施の形態に係る静電容量式入力検出方式1を、図1乃至図9を用いて説明する。本実施の形態にかかる入力検出方式1は、入力操作データとなる入力操作体30の入力操作位置を検出するもので、検出した入力操作位置を含む操作データを上位処理装置へ出力し、ディスプレーに表示されるカーソルを移動制御する指示入力装置50に用いられる。   Hereinafter, the capacitance type input detection method 1 according to the first embodiment of the present invention will be described with reference to FIGS. 1 to 9. The input detection method 1 according to the present embodiment detects the input operation position of the input operation body 30 serving as input operation data, and outputs the operation data including the detected input operation position to the host processing device for display. It is used for the instruction input device 50 that controls the movement of the displayed cursor.

指示入力装置50の入力操作部は、図2に示すように、長方形枠状の絶縁ケース20の内方に横長長方形の窓孔21が形成され、窓孔21の開口面を操作体である指30を接近させて入力操作を行う入力操作面21aとしている。窓孔21に隣接する絶縁ケース20の内縁20aは、図3に示すように、窓孔21の中心に向かって下方に傾斜する傾斜面となっていて、互いに直交する4辺の内縁20aの表面に、それぞれX方向で対向する一組の検出電極X0、X1とY方向で対向する一組の検出電極Y0、Y1が一体に取り付けられている。   As shown in FIG. 2, the input operation unit of the instruction input device 50 has a horizontally long rectangular window hole 21 formed inside the rectangular frame-shaped insulating case 20, and the opening surface of the window hole 21 is a finger as an operating body. An input operation surface 21a is used for performing an input operation with 30 being approached. As shown in FIG. 3, the inner edge 20 a of the insulating case 20 adjacent to the window hole 21 is an inclined surface that is inclined downward toward the center of the window hole 21, and the surfaces of the four inner edges 20 a that are orthogonal to each other. In addition, a pair of detection electrodes X0, Y1 that face each other in the X direction and a pair of detection electrodes Y0, Y1 that face each other in the Y direction are integrally attached.

各検出電極11(X0、X1、Y0、Y1)は、それぞれ細長帯状に形成され、取り付けられる内縁20aに沿ったほぼ全体に配置される。これにより、入力操作面21aのいずれの位置に指30をおいても、指30が全ての検出電極11に対向するようになっている。ここでは、各検出電極11を上方に傾斜する内縁20aに沿って配置することにより、入力操作面21aの上方に指30が配置された際に、指30との対向面積が最大となり、後述する静電容量Cmを大きな値となるようにしている。   Each of the detection electrodes 11 (X0, X1, Y0, Y1) is formed in an elongated strip shape, and is disposed almost entirely along the inner edge 20a to be attached. As a result, the finger 30 faces all the detection electrodes 11 regardless of the position of the finger 30 at any position on the input operation surface 21a. Here, by arranging each detection electrode 11 along the inner edge 20a inclined upward, when the finger 30 is arranged above the input operation surface 21a, the area facing the finger 30 is maximized, which will be described later. The capacitance Cm is set to a large value.

図4に示すように、各検出電極11を含む入力検出方式1を構成する主要回路部品は、2種類の非振動側回路基板2と振動側回路基板3に分けて搭載されている。非振動回路基板2には、接地電位とした低圧基準電源線GNDと高圧基準電源線VCCとからなる基準電源回路4が配線され、低圧基準電源線GNDと高圧基準電源線VCC間に直流電圧Vccを印加するDC電源5が接続されている。これにより、非振動回路基板2に搭載されるインターフェース回路6等の各回路部品を基準電源回路4に接続し、DC電源5の出力電圧Vccにより駆動させている。   As shown in FIG. 4, the main circuit components constituting the input detection method 1 including the detection electrodes 11 are separately mounted on two types of the non-vibration side circuit board 2 and the vibration side circuit board 3. The non-vibration circuit board 2 is provided with a reference power supply circuit 4 including a low-voltage reference power supply line GND and a high-voltage reference power supply line VCC that are set to the ground potential, and a DC voltage Vcc between the low-voltage reference power supply line GND and the high-voltage reference power supply line VCC. Is connected to a DC power source 5. Thereby, each circuit component such as the interface circuit 6 mounted on the non-vibration circuit board 2 is connected to the reference power supply circuit 4 and driven by the output voltage Vcc of the DC power supply 5.

また、振動側回路基板3には、低圧振動電源線SGNDと高圧振動電源線SVCCとからなる振動電源回路7が配線されている。低圧振動電源線SGNDは低圧基準電源線GNDと、高圧振動電源線SVCCは高圧基準電源線VCCと、それぞれコイル8、9を介して接続している。コイル8とコイル9のインダクタンスは、いずれも後述する固有周波数fの交流検出信号SGに対してハイインピーダンスとなる値に設定され、ここでは、同一のインダクタンスLのコイル8、9を用いている。   Further, the vibration side circuit board 3 is provided with a vibration power circuit 7 including a low voltage vibration power line SGND and a high voltage vibration power line SVCC. The low-voltage vibration power supply line SGND is connected to the low-voltage reference power supply line GND, and the high-voltage vibration power supply line SVCC is connected to the high-voltage reference power supply line VCC via the coils 8 and 9, respectively. The inductances of the coil 8 and the coil 9 are both set to values having high impedance with respect to an AC detection signal SG having a natural frequency f described later. Here, the coils 8 and 9 having the same inductance L are used.

交流検出信号SGの固有周波数fを発信する発信手段となる発振回路15は、振動側回路基板3に搭載され、二股に分岐してそれぞれ直流電圧を遮断するキャパシタンスC’のコンデンサ17、18を介して交流検出信号SGを基準電源回路4の低圧基準電源線GNDと高圧基準電源線VCCに接続している。これにより、図4に示すように、基準電源回路4の低圧基準電源線GNDと高圧基準電源線VCCへ、固有周波数fの交流検出信号SGを同期させて出力すると、基準電源回路4の低圧基準電源線GNDが接地されて安定した電位にあるので、振動電源回路7の低圧振動電源線SGNDと高圧振動電源線SVCCの電位が同期して固有周波数fで変動し、両者間の電圧は、基準電源回路4と同じ直流出力電圧Vccとなる。交流検出信号SGの固有周波数fは、任意に調整することができるが、ここでは、187kHzの固有発振周波数の交流検出信号SGを出力する。   An oscillation circuit 15 serving as a transmission means for transmitting the natural frequency f of the AC detection signal SG is mounted on the vibration side circuit board 3 and is branched into two branches via capacitors 17 and 18 having a capacitance C ′ that cuts off the DC voltage. The AC detection signal SG is connected to the low-voltage reference power line GND and the high-voltage reference power line VCC of the reference power circuit 4. As a result, as shown in FIG. 4, when the AC detection signal SG having the natural frequency f is output to the low voltage reference power line GND and the high voltage reference power line VCC of the reference power circuit 4 in synchronization with each other, the low voltage reference of the reference power circuit 4 is output. Since the power supply line GND is grounded and at a stable potential, the potentials of the low-voltage vibration power supply line SGND and the high-voltage vibration power supply line SVCC of the vibration power supply circuit 7 fluctuate synchronously with the natural frequency f. The DC output voltage Vcc is the same as that of the power supply circuit 4. The natural frequency f of the AC detection signal SG can be arbitrarily adjusted. Here, the AC detection signal SG having a natural oscillation frequency of 187 kHz is output.

固有周波数fの交流検出信号SGが基準電源回路4と振動電源回路7に流れる場合に、低圧基準電源線GNDと高圧基準電源線VCC間及び低圧振動電源線SGNDと高圧振動電源線SVCC間が近接して配線され、固有周波数fの帯域でこれらの電源線間は短絡しているとすれば、基準電源回路4と振動電源回路7は、図5の等価回路図で示される。   When the AC detection signal SG having the natural frequency f flows in the reference power supply circuit 4 and the vibration power supply circuit 7, the low-voltage reference power supply line GND and the high-voltage reference power supply line VCC and the low-voltage vibration power supply line SGND and the high-voltage vibration power supply line SVCC are close to each other. If the power supply lines are short-circuited in the band of the natural frequency f, the reference power supply circuit 4 and the vibration power supply circuit 7 are shown in the equivalent circuit diagram of FIG.

図5に示すように、振動電源回路7側の発振回路15の出力と基準電源回路4間には、並列にキャパシタンスC’のコンデンサ17、18が接続されているので、その合成キャパシタンスは、2C’であり、また、基準電源回路4と振動電源回路7間に並列に接続されるコイル8、9の合成インダクタンスは、L/2となる。これらのキャパシタとインダクタは、固有周波数fの交流検出信号SGが流れる閉回路において直列に接続され、交流検出信号SGの振幅(レベル)をVsg、コイル8、9両端の基準電源回路4と振動電源回路7間の電圧をVs、2πfで表される角速度をω(rad/sec)とすれば、   As shown in FIG. 5, since capacitors 17 and 18 having a capacitance C ′ are connected in parallel between the output of the oscillation circuit 15 on the vibration power supply circuit 7 side and the reference power supply circuit 4, the combined capacitance is 2C. In addition, the combined inductance of the coils 8 and 9 connected in parallel between the reference power supply circuit 4 and the vibration power supply circuit 7 is L / 2. These capacitors and inductors are connected in series in a closed circuit in which an AC detection signal SG having a natural frequency f flows, and the amplitude (level) of the AC detection signal SG is Vsg, the reference power supply circuit 4 at both ends of the coils 8 and 9 and the vibration power supply. If the voltage between the circuits 7 is Vs, and the angular velocity represented by 2πf is ω (rad / sec),

Figure 2013021414
Figure 2013021414

で表される。
ここで、図4に示す回路は、ωLC’=1で直列共振し、そのときの周波数fは、
It is represented by
Here, the circuit shown in FIG. 4 resonates in series at ω 2 LC ′ = 1, and the frequency f 0 at that time is

Figure 2013021414
Figure 2013021414

となる。 It becomes.

つまり、(2)式関係から得られる共振周波数fを、交流検出信号SGの固有周波数fとすれば、交流検出信号SGのレベルに対して、(1)式から理論上振動電源回路7の電位が無限大で振動し、振動電源回路7に接続する各検出電極11の電位も無限大に振動させることができる。実際の入力検出方式1では、基準電源回路4と振動電源回路7のインダクタンス、浮遊容量などの影響から、(2)式から得る周波数fで共振せず、また、基準電源回路4と振動電源回路7に交流検出信号SGが流れる際のエネルギーロス等により、振動電源回路7は、交流検出信号SGのレベルVsgに対して有限倍率に拡大された振幅Vsで振動する。That is, if the resonance frequency f 0 obtained from the relationship of the expression (2) is the natural frequency f of the AC detection signal SG, the level of the AC detection signal SG is theoretically calculated from the expression (1) of the vibration power supply circuit 7. The potential vibrates at infinity, and the potential of each detection electrode 11 connected to the vibration power supply circuit 7 can be vibrated to infinity. In the actual input detection method 1, resonance does not occur at the frequency f 0 obtained from the equation (2) due to the influence of the inductance and stray capacitance of the reference power supply circuit 4 and the vibration power supply circuit 7. Due to energy loss or the like when the AC detection signal SG flows through the circuit 7, the vibration power supply circuit 7 vibrates with the amplitude Vs expanded to a finite magnification with respect to the level Vsg of the AC detection signal SG.

更に、操作者の指30が触れることのある各検出電極11に大電圧を加えることはできないので、交流検出信号SGの固有周波数fを共振周波数fの近傍で調整し、各検出電極11が相対的に振動する交流検出信号SGの出力レベルVsを任意に設定しでき、ここでは、出力レベルVsを5Vとしている。Furthermore, since a large voltage cannot be applied to each detection electrode 11 that the operator's finger 30 may touch, the natural frequency f of the AC detection signal SG is adjusted in the vicinity of the resonance frequency f 0 so that each detection electrode 11 The output level Vs of the AC detection signal SG that vibrates relatively can be arbitrarily set. Here, the output level Vs is set to 5V.

また、交流検出信号SGの固有周波数fについても、任意の周波数とすることができるが、商用交流電源線の周囲では、入力操作体30が定電位ではなく商用交流電源の周波数のコモンモードノイズが重畳することがあるので、各検出電極11から商用交流電源の周波数と識別して固有周波数fの交流検出信号SGを検出する必要があり、商用交流電源の周波数とその高調波を除く周波数とすることが好ましい。   Also, the natural frequency f of the AC detection signal SG can be set to an arbitrary frequency. However, around the commercial AC power supply line, the input operating body 30 is not at a constant potential, but common mode noise at the frequency of the commercial AC power supply is generated. Since it may be superposed, it is necessary to detect the AC detection signal SG of the natural frequency f from each detection electrode 11 as the frequency of the commercial AC power supply, and set the frequency excluding the frequency of the commercial AC power supply and its harmonics. It is preferable.

上述の各検出電極11は、振動電源回路7の低圧振動電源線SGNDと高圧振動電源線SVCCのいずれかの、ここでは高圧振動電源線SVCCに接続している。全ての各検出電極11が高圧振動電源線SVCCに接続することによって、交流検出信号SGの出力レベルVsで固有周波数fで振動する一方、足下などの一部が接地している操作者の指30の電位は定電位であるので、両者の間には、交流検出信号SGの出力レベルVsの電圧が発生し、指30が接近して指30との静電容量Cmが増大する検出電極11では、検出電極11から指30へ静電容量Cmを介して固有周波数fの交流検出信号SGがあらわれる。これを、固有周波数fで振動する振動電源回路7からみれば、定電位の検出電極11に対して入力操作体である指30が交流検出信号SGの固有周波数fで振動する。   Each of the detection electrodes 11 described above is connected to one of the low-voltage vibration power supply line SGND and the high-voltage vibration power supply line SVCC of the vibration power supply circuit 7, here the high-voltage vibration power supply line SVCC. When all the detection electrodes 11 are connected to the high-voltage vibration power supply line SVCC, the operator's finger 30 is vibrated at the natural frequency f at the output level Vs of the AC detection signal SG, while a part such as a foot is grounded. Is a constant potential, a voltage of an output level Vs of the AC detection signal SG is generated between the two, and the detection electrode 11 in which the finger 30 approaches and the capacitance Cm with the finger 30 increases. The AC detection signal SG having the natural frequency f appears from the detection electrode 11 to the finger 30 via the capacitance Cm. If this is seen from the vibration power supply circuit 7 that vibrates at the natural frequency f, the finger 30 as the input operating body vibrates at the natural frequency f of the AC detection signal SG with respect to the constant potential detection electrode 11.

各検出電極11と入力操作体30間の静電容量Cmは、検出電極と入力操作体間の距離をd、真空の誘電率をε0、空気の比誘電率εを約1、入力操作体30と検出電極11の対向面積をsとして、Cm=ε0・εr・s/dで表され、この静電容量Cmの交流検出信号に対するリアクタンスXcは、交流検出信号の固有周波数がfであるので、   The electrostatic capacitance Cm between each detection electrode 11 and the input operation body 30 is such that the distance between the detection electrode and the input operation body is d, the dielectric constant of vacuum is ε0, the relative dielectric constant ε of air is about 1, and the input operation body 30 And the detection electrode 11 is represented by Cm = ε0 · εr · s / d, and the reactance Xc of the capacitance Cm with respect to the AC detection signal is f because the natural frequency of the AC detection signal is f.

Figure 2013021414
から、
Figure 2013021414
From

Figure 2013021414
Figure 2013021414

で表される。 It is represented by

図6は、検出電極11に表れる交流検出信号SGの受信レベルViを検出する信号検出回路部全体の等価回路図であり、図中、Cpは、検出電極11と低圧振動電源線SGND間の浮遊容量、rpは、検出電極11の内部抵抗値、R4は、出力抵抗の抵抗値である。 図中の等価回路図では、   FIG. 6 is an equivalent circuit diagram of the entire signal detection circuit unit for detecting the reception level Vi of the AC detection signal SG appearing on the detection electrode 11, where Cp is a floating between the detection electrode 11 and the low-voltage vibration power supply line SGND. Capacitance, rp is the internal resistance value of the detection electrode 11, and R4 is the resistance value of the output resistance. In the equivalent circuit diagram in the figure,

Figure 2013021414
Figure 2013021414

Figure 2013021414
Figure 2013021414

Figure 2013021414
Figure 2013021414

Figure 2013021414
Figure 2013021414

の関係が成り立ち、(3)式乃至(6)式から、 From the equations (3) to (6),

Figure 2013021414
Figure 2013021414

の関係が得られる。 The relationship is obtained.

内部抵抗rpを0とし、R4がマルチプレクサ12と信号処理回路13を介して後述する積分用オペアンプA/D25に接続されるので無限大とすれば、(7)式は、   If the internal resistance rp is set to 0 and R4 is connected to an integration operational amplifier A / D25, which will be described later, via the multiplexer 12 and the signal processing circuit 13, it is assumed that it is infinite.

Figure 2013021414
Figure 2013021414

と置き換えられ、更に
数10pFの浮遊容量Cpに比べて静電容量Cmは数10fFと極めて小さいので、(7)式は、更に
Since the electrostatic capacitance Cm is extremely small, such as several tens of fF, compared to the stray capacitance Cp of several tens of pF, the equation (7)

Figure 2013021414
Figure 2013021414

で表され、受信レベルViは静電容量Cmに比例する。 The reception level Vi is proportional to the capacitance Cm.

上述の通り、入力操作体30と検出電極11のCmは、   As described above, Cm of the input operation body 30 and the detection electrode 11 is

Figure 2013021414
Figure 2013021414

で表されるので、これを(8)式に代入して変形すれば、 If it is transformed by substituting this into equation (8),

Figure 2013021414
となり、入力操作中に指30と検出電極11との対向面積sがほぼ変化しないものとして、(9)式中の(ε0・εr・s/Cp)は、定数であるので、これを1/kとおけば、検出電極11に表れる交流検出信号SGの受信レベルViは、
Figure 2013021414
Assuming that the facing area s between the finger 30 and the detection electrode 11 does not substantially change during the input operation, (ε0 · εr · s / Cp) in the equation (9) is a constant, so If k, the reception level Vi of the AC detection signal SG appearing on the detection electrode 11 is

Figure 2013021414
Figure 2013021414

で表され、指30との距離dが近い検出電極11ほど、受信レベルViが交流検出信号SGの出力レベルVsに近づく大きな値となる。ただし、指30が検出電極11に近接し、その間の静電容量Cmが数10pFの浮遊容量Cpに比べて無視できない程度に大きくなった場合には(10)式を適用できず、受信レベルViは最大で出力レベルVsとなる。 As the detection electrode 11 is closer to the finger 30 and the distance d is closer to the finger 30, the reception level Vi becomes a larger value that approaches the output level Vs of the AC detection signal SG. However, when the finger 30 is close to the detection electrode 11 and the electrostatic capacitance Cm therebetween becomes so large that it cannot be ignored compared to the stray capacitance Cp of several tens of pF, the equation (10) cannot be applied and the reception level Vi. Becomes a maximum output level Vs.

(10)式を用いれば、複数の各検出電極11に表れる交流検出信号の受信レベルViを比較して、指30と各検出電極11間の距離を比較することができ、本実施の形態では、各検出電極11(X0、X1、Y0、Y1)の配置位置と、各検出電極11(X0、X1、Y0、Y1)の受信レベルViとから、入力操作面21aに平行なXY方向の入力操作位置(x、y)と入力操作面21aに直交するZ方向の入力操作位置zの3次元の入力操作位置を検出する。   If the expression (10) is used, the reception level Vi of the AC detection signal appearing on each of the plurality of detection electrodes 11 can be compared, and the distance between the finger 30 and each detection electrode 11 can be compared. In this embodiment, The input in the XY direction parallel to the input operation surface 21a is determined from the arrangement position of each detection electrode 11 (X0, X1, Y0, Y1) and the reception level Vi of each detection electrode 11 (X0, X1, Y0, Y1). A three-dimensional input operation position between the operation position (x, y) and the input operation position z in the Z direction orthogonal to the input operation surface 21a is detected.

入力操作体である指30を検出電極11から10cm離れた位置へ入力操作を行ったとしたときの指30と検出電極11間の静電容量Cmは、指30と検出電極11との対向面積sを5・10−4(m)、真空の誘電率ε0を、8.854・10−12(F/m)、空気の比誘電率εを約1として、約44.27・10−15Fすなわち、44.27fFと極めて微小な値となる。The capacitance Cm between the finger 30 and the detection electrode 11 when the input operation is performed on the finger 30 that is the input operation body to a position 10 cm away from the detection electrode 11 is the facing area s between the finger 30 and the detection electrode 11. Is 5 · 10 −4 (m 2 ), the dielectric constant ε0 of vacuum is 8.854 · 10 −12 (F / m), and the relative dielectric constant ε of air is about 1, and about 44.27 · 10 −15. F, that is, a very small value of 44.27 fF.

このとき、検出電極11に表れる交流検出信号SGの受信レベルViは、(10)式において、比例定数kが、Cp/(ε0・εr・s)であることから、浮遊容量Cpを50pFとして1.13・10であり、交流検出信号SGの出力レベルVsを5V、dを10−1とすると、4.4mV程度と極めて微小な電圧変化で表される。At this time, the reception level Vi of the AC detection signal SG appearing on the detection electrode 11 is 1 when the stray capacitance Cp is 50 pF because the proportionality constant k is Cp / (ε0 · εr · s) in the equation (10). .13 - 10 4, and the output level Vs to 5V AC detection signal SG, when a d 10 -1, represented by a very small voltage change of about 4.4MV.

そこで、静電容量式入力検出方式1によって、この微小な受信レベルViを拡大し、拡大して表される受信レベルVoutから各検出電極11と指30との距離dを求め、入力操作位置(x、y、z)を検出する。   Therefore, the minute input level Vi is enlarged by the capacitance type input detection method 1, and the distance d between each detection electrode 11 and the finger 30 is obtained from the enlarged reception level Vout, and the input operation position ( x, y, z) are detected.

振動側回路基板3には、図1に示す静電容量式入力検出方式1を構成するアナログマルチプレクサ12、信号処理回路13、積分処理回路14、A/Dコンバータ19、MPU(マイクロプロセッサユニット)10及び発振回路15の各回路素子が搭載され、いずれも振動電源回路7の低圧振動電源線SGNDと高圧振動電源線SVCCに接続し、DC電源5から出力電圧Vccを受けて動作している。   The vibration side circuit board 3 includes an analog multiplexer 12, a signal processing circuit 13, an integration processing circuit 14, an A / D converter 19, and an MPU (microprocessor unit) 10 constituting the capacitance type input detection method 1 shown in FIG. Each of the circuit elements of the oscillation circuit 15 and the oscillation circuit 15 are mounted and connected to the low-voltage oscillation power supply line SGND and the high-voltage oscillation power supply line SVCC of the oscillation power supply circuit 7 and operate by receiving the output voltage Vcc from the DC power supply 5.

アナログマルチプレクサ12は、MPU10からの切り替え制御により、一定の周期、ここでは200msec毎に、各検出電極11を信号処理回路13へ切り換え接続し、各検出電極11に表れる交流検出信号SGを順に信号処理回路13へ出力している。   The analog multiplexer 12 switches and connects each detection electrode 11 to the signal processing circuit 13 at a constant period, here, every 200 msec by switching control from the MPU 10, and sequentially processes the AC detection signal SG appearing on each detection electrode 11. It is output to the circuit 13.

信号処理回路13は、交流検出信号の固有周波数fを中心とする周波数帯域の信号を通過させる共振回路23と、インピーダンス変換用の増幅回路24と、これらの間に直列に接続される第1アナログスイッチASW1とからなっている。共振回路23は、アナログマルチプレクサ12を介して接続する検出電極11に表れる信号から、直流信号等の低周波成分とコモンモードノイズ等の高周波ノイズをカットし、交流検出信号SGを後段の増幅回路24へ出力する。増幅回路24は、入力インピーダンスが無限大に近く、出力インピーダンスが微小値であるインピーダンス変換素子で、検出電極11に表れる微弱な交流検出信号SGであっても、その出力側に接続される積分処理回路14が動作するようにしている。   The signal processing circuit 13 includes a resonance circuit 23 that passes a signal in a frequency band centered on the natural frequency f of the AC detection signal, an amplifier circuit 24 for impedance conversion, and a first analog connected in series therebetween. The switch ASW1. The resonance circuit 23 cuts low-frequency components such as a DC signal and high-frequency noise such as common mode noise from the signal appearing on the detection electrode 11 connected via the analog multiplexer 12, and converts the AC detection signal SG into a subsequent amplification circuit 24. Output to. The amplifier circuit 24 is an impedance conversion element having an input impedance close to infinity and an output impedance of a minute value. Even if the weak AC detection signal SG appears on the detection electrode 11, an integration process connected to the output side of the amplification circuit 24. The circuit 14 is made to operate.

第1アナログスイッチASW1は、MPU10により開閉制御され、積分処理回路14が後述する積分動作を行っている積分動作期間(Tint)中に共振回路23と増幅回路24間を接続し、後述するオフセット調整期間(Tset)中に遮断する。これにより、オフセット調整期間(Tset)中に、交流検出信号SGが積分処理回路14に出力されないようにしている。   The first analog switch ASW1 is controlled to be opened and closed by the MPU 10, and connects the resonance circuit 23 and the amplifier circuit 24 during an integration operation period (Tint) in which the integration processing circuit 14 performs an integration operation described later, thereby adjusting an offset described later. Cut off during period (Tset). This prevents the AC detection signal SG from being output to the integration processing circuit 14 during the offset adjustment period (Tset).

積分処理回路14は、図1に示すように、積分用オペアンプ25と、信号処理回路14の出力と積分用オペアンプ25の反転入力端子間に接続された積分用抵抗R1と、積分用オペアンプ25の反転入力端子と出力端子間に接続された積分用コンデンサC1と、積分用コンデンサC1に並列に接続され、MPU10により開閉制御される第2アナログスイッチASW2を備えている。   As shown in FIG. 1, the integration processing circuit 14 includes an integration operational amplifier 25, an integration resistor R 1 connected between the output of the signal processing circuit 14 and the inverting input terminal of the integration operational amplifier 25, and the integration operational amplifier 25. An integrating capacitor C1 connected between the inverting input terminal and the output terminal, and a second analog switch ASW2 connected in parallel to the integrating capacitor C1 and controlled to be opened and closed by the MPU 10 are provided.

積分用オペアンプ25の反転入力端子に接続する積分用抵抗Rに入力される交流検出信号の電圧をVin、積分用オペアンプ25の出力端子から出力される電圧をVout、積分用抵抗R1の抵抗値をR、積分用コンデンサC1の容量をCとすれば、   The voltage of the AC detection signal input to the integrating resistor R connected to the inverting input terminal of the integrating operational amplifier 25 is Vin, the voltage output from the output terminal of the integrating operational amplifier 25 is Vout, and the resistance value of the integrating resistor R1 is R, if the capacitance of the integrating capacitor C1 is C,

Figure 2013021414
Figure 2013021414

で表され、積分用オペアンプ25の出力端子から入力電圧Vinを積分した電圧Voutが出力される。 The voltage Vout obtained by integrating the input voltage Vin is output from the output terminal of the integrating operational amplifier 25.

第2アナログスイッチASW2は、オフセット調整期間(Tset)開始後のわずかな時間、MPU10により閉じ制御され、積分処理回路14の積分動作期間(Tint)に積分用コンデンサC1に蓄積された電荷を速やかに放電させるもので、その直前の積分動作期間(Tint)に積分用コンデンサC1に充電された充電電圧が、後述する積分処理回路14のオフセット調整期間(Tset)のオフセット動作に影響しないようにしている。   The second analog switch ASW2 is controlled to be closed by the MPU 10 for a short time after the start of the offset adjustment period (Tset), so that the charge accumulated in the integrating capacitor C1 can be quickly transferred during the integration operation period (Tint) of the integration processing circuit 14. The charging voltage charged in the integration capacitor C1 during the immediately preceding integration operation period (Tint) does not affect the offset operation during the offset adjustment period (Tset) of the integration processing circuit 14 to be described later. .

この積分用オペアンプ25の反転入力端子と非反転入力端子間には、積分用オペアンプ25のオフセット電圧やその他の要因による直流成分の誤差があり、これらを合わせた誤差電圧をオフセット電圧Δvで表すと、(11)式は、   There is a DC component error between the inverting input terminal and the non-inverting input terminal of the integrating operational amplifier 25 due to the offset voltage of the integrating operational amplifier 25 and other factors, and the combined error voltage is represented by the offset voltage Δv. , (11)

Figure 2013021414
Figure 2013021414

で表され、オフセット電圧Δvは直流成分であるので、(12)式は、 Since the offset voltage Δv is a DC component, the equation (12) is

Figure 2013021414
Figure 2013021414

で表され、時間tの経過と共に、出力電圧Vout中のオフセット電圧Δvによる誤差が積分時間に比例して拡大する。 As time t elapses, the error due to the offset voltage Δv in the output voltage Vout increases in proportion to the integration time.

そこで、本実施の形態では、上記オフセット電圧Δvによる影響を実質的に解消させる目的で積分処理回路14に更にオフセット調整手段となるフィードバック回路部を設けている。このフィードバック回路部は、図1に示すように、帰還用オペアンプ26と、帰還用オペアンプ26の出力と積分用オペアンプ25の非反転入力端子間に接続された第3アナログスイッチASW3と、積分用オペアンプ25の非反転入力端子と接地間に接続され、帰還用オペアンプ26の出力電圧で充電されるホールド用コンデンサ27とから構成される。   Therefore, in the present embodiment, the integration processing circuit 14 is further provided with a feedback circuit section serving as an offset adjusting means in order to substantially eliminate the influence of the offset voltage Δv. As shown in FIG. 1, the feedback circuit section includes a feedback operational amplifier 26, a third analog switch ASW3 connected between the output of the feedback operational amplifier 26 and the non-inverting input terminal of the integrating operational amplifier 25, and an integrating operational amplifier. 25. A hold capacitor 27 connected between the 25 non-inverting input terminals and the ground and charged by the output voltage of the feedback operational amplifier 26.

帰還用オペアンプ26の非反転入力端子は、抵抗R2を介して積分用オペアンプ25の出力に接続され、反転入力端子は、積分用抵抗R1の入力側に接続している。帰還用オペアンプ26の反転入力端子と出力端子間に接続された抵抗R3と抵抗R2の抵抗値は等しく、従って、帰還用オペアンプ26は、第3アナログスイッチASW3が閉じ制御されている間、積分用オペアンプ25の反転入力端子に接続する積分用抵抗Rの入力側の電位を入力電圧Vinとし、入力電圧Vinに対する積分用オペアンプ25の出力電圧Voutの差分をゲイン−1で増幅し積分用オペアンプ25の非反転入力端子へ帰還するように作用する。   The non-inverting input terminal of the feedback operational amplifier 26 is connected to the output of the integrating operational amplifier 25 via the resistor R2, and the inverting input terminal is connected to the input side of the integrating resistor R1. The resistance values of the resistor R3 and the resistor R2 connected between the inverting input terminal and the output terminal of the feedback operational amplifier 26 are equal. Therefore, the feedback operational amplifier 26 is used for integration while the third analog switch ASW3 is closed and controlled. The potential on the input side of the integrating resistor R connected to the inverting input terminal of the operational amplifier 25 is set as the input voltage Vin, and the difference of the output voltage Vout of the integrating operational amplifier 25 with respect to the input voltage Vin is amplified by gain −1. It acts to return to the non-inverting input terminal.

MPU10により制御されるオフセット調整期間(Tset)中に、第3アナログスイッチASW3が閉じ制御されるとともに、積分用抵抗R1の入力と各検出電極11とは開制御される第1アナログスイッチASW1により遮断されるので、積分用抵抗R1の入力側には、交流検出信号SGが入力されることなく、積分用オペアンプ25の反転入力端子の電位は、一定の基準電圧である入力電圧Vinに保たれる。   During the offset adjustment period (Tset) controlled by the MPU 10, the third analog switch ASW3 is closed and controlled, and the input of the integrating resistor R1 and each detection electrode 11 are shut off by the first analog switch ASW1 controlled to open. Therefore, the AC detection signal SG is not input to the input side of the integrating resistor R1, and the potential of the inverting input terminal of the integrating operational amplifier 25 is maintained at the input voltage Vin that is a constant reference voltage. .

第1アナログスイッチASW1を開制御し、第3アナログスイッチASW3が閉じ制御したオフセット調整期間(Tset)中のフィードバック回路部は、図7に示すブロック図で示される。図7のVi(s)、Vo(s)、Vf(s)は、積分用オペアンプ25の入力電圧Vin、積分用オペアンプ25の出力電圧Vout及び帰還用オペアンプ26の出力電圧Vfを、それぞれ経過時間tの関数Vi(t)、Vo(t)、Vf(t)で表したそのラプラス変換値、G(s)、H(s)は、積分用オペアンプ25と帰還用オペアンプ26を含む各ブロックの伝達関数である。尚、sは、ラプラス演算子である。   The feedback circuit unit during the offset adjustment period (Tset) in which the first analog switch ASW1 is controlled to open and the third analog switch ASW3 is controlled to close is shown in the block diagram of FIG. In FIG. 7, Vi (s), Vo (s), and Vf (s) indicate the elapsed time of the input voltage Vin of the integrating operational amplifier 25, the output voltage Vout of the integrating operational amplifier 25, and the output voltage Vf of the feedback operational amplifier 26, respectively. The Laplace transform values G (s) and H (s) expressed by the functions Vi (t), Vo (t), and Vf (t) of t are the values of each block including the integrating operational amplifier 25 and the feedback operational amplifier 26. It is a transfer function. Note that s is a Laplace operator.

図7において、   In FIG.

Figure 2013021414
Figure 2013021414

及び as well as

Figure 2013021414
Figure 2013021414

であるので、
フィードバック回路部全体の伝達関数Vo(s)/Vi(s)は、
(14)式と(15)式から
So
The transfer function Vo (s) / Vi (s) of the entire feedback circuit unit is
From equations (14) and (15)

Figure 2013021414
Figure 2013021414

となる。 It becomes.

ここで伝達関数G(s)は、(11)式から、G(s)=−1/sCR
であり、伝達関数H(s)は、帰還用オペアンプ26のゲインAfであるので、(16)式は、
Here, the transfer function G (s) is expressed by G (s) = − 1 / sCR from the equation (11).
Since the transfer function H (s) is the gain Af of the feedback operational amplifier 26, the equation (16) is

Figure 2013021414
Figure 2013021414

で表され、システム安定性の定理より伝達関数の極Af/CRが負になれば、フィードバック回路部全体の制御系が安定する。 If the pole Af / CR of the transfer function becomes negative from the system stability theorem, the control system of the entire feedback circuit section is stabilized.

オフセット調整期間(Tset)中に一定の基準電圧とした入力電圧Vinを0Vとして、この制御系に積分用オペアンプ25により発生するオフセット電圧ΔVが入力されたものとすると、オフセット電圧ΔV(t)は、ステップ関数であるので、ラプラス変換すると、   Assuming that the input voltage Vin, which is a constant reference voltage during the offset adjustment period (Tset), is 0 V, and the offset voltage ΔV generated by the integrating operational amplifier 25 is input to this control system, the offset voltage ΔV (t) is Since it is a step function, Laplace transform

Figure 2013021414
Figure 2013021414

となり、これを(17)式のVi(s)として代入すると、 When this is substituted as Vi (s) in equation (17),

Figure 2013021414
Figure 2013021414

となる。 It becomes.

これを部分分数に展開すると、   When this is expanded into partial fractions,

Figure 2013021414
Figure 2013021414

となるので、等プラス逆変換すると、Vo(t)は、 Therefore, when the inverse plus transformation is performed, Vo (t) becomes

Figure 2013021414
Figure 2013021414

となる。 It becomes.

ここで、例えば、積分用抵抗R1の抵抗値Rを10kΩ、積分用コンデンサC1の容量Cを1000pF、積分用オペアンプ25のオフセット電圧ΔVを100mV、帰還用オペアンプ26のゲインAfを−1として、(15)式と(21)式を用いて、オフセット調整期間(Tset)開始後の経過時間tについて、積分用オペアンプ25の出力電圧Voutと帰還用オペアンプ26の出力電圧Vfを算出すると、図8に示すように、約30μs後に積分用オペアンプ25の出力Voutは、オフセット電圧Δvと逆極性の電圧に収束して安定する。この状態で、帰還用オペアンプ26の出力電圧Vf、すなわち積分用オペアンプ25の反転入力端子の入力電圧は、非反転入力端子の入力電圧Vinにオフセット電圧Δvを加えた電位に等しくなり、積分用オペアンプ25の出力電圧Voutにオフセット電圧Δvを積分した値が表れない。   Here, for example, the resistance value R of the integrating resistor R1 is 10 kΩ, the capacitance C of the integrating capacitor C1 is 1000 pF, the offset voltage ΔV of the integrating operational amplifier 25 is 100 mV, and the gain Af of the feedback operational amplifier 26 is −1. When the output voltage Vout of the integrating operational amplifier 25 and the output voltage Vf of the feedback operational amplifier 26 are calculated for the elapsed time t after the start of the offset adjustment period (Tset) using the equations (15) and (21), FIG. As shown, the output Vout of the integrating operational amplifier 25 converges to a voltage having a polarity opposite to that of the offset voltage Δv after about 30 μs and stabilizes. In this state, the output voltage Vf of the feedback operational amplifier 26, that is, the input voltage of the inverting input terminal of the integrating operational amplifier 25 becomes equal to the potential obtained by adding the offset voltage Δv to the input voltage Vin of the non-inverting input terminal. A value obtained by integrating the offset voltage Δv with the output voltage Vout of 25 does not appear.

(21)式は、帰還用オペアンプ26のゲインAfが大きいほど収束するまでの経過時間tが早くなることを示しているが、ゲインAfを大きくすると、積分用抵抗R1と積分用コンデンサC1による時定数RCより収束するまでの時間が大幅に短くなり、積分用オペアンプ25自体の遅延時間が無視できなくなる。   Equation (21) shows that the elapsed time t until convergence becomes faster as the gain Af of the feedback operational amplifier 26 increases. However, when the gain Af is increased, the time due to the integration resistor R1 and the integration capacitor C1 is increased. The time until convergence from the constant RC is significantly shortened, and the delay time of the integrating operational amplifier 25 itself cannot be ignored.

従って、オフセット調整期間(Tset)は、帰還用オペアンプ26のゲインAfと、積分用抵抗R1の抵抗値R及び積分用コンデンサC1の容量Cを考慮し、出力電圧Voutが安定して収束するまでの経過時間より充分に長い期間に設定する。   Therefore, the offset adjustment period (Tset) takes into account the gain Af of the feedback operational amplifier 26, the resistance value R of the integrating resistor R1, and the capacitance C of the integrating capacitor C1, until the output voltage Vout converges stably. Set a period sufficiently longer than the elapsed time.

オフセット調整期間(Tset)に、ホールド用コンデンサ27は帰還用オペアンプ26の出力電圧Vfで充電され、積分用オペアンプ25の出力Voutが安定した収束時のホールド用コンデンサ27の充電電圧は、その時の帰還用オペアンプ26の出力電圧Vf、すなわち、オフセット電圧Δvの影響を含めて非反転入力端子と反転入力端子間の差電圧を0とするオフセット調整電圧となっている。従って、ホールド用コンデンサ27は、積分用オペアンプ25の出力Voutが安定して収束する時に、少なくとも飽和するキャパシタのコンデンサを用いる。   During the offset adjustment period (Tset), the hold capacitor 27 is charged with the output voltage Vf of the feedback operational amplifier 26, and the charge voltage of the hold capacitor 27 when the output Vout of the integrating operational amplifier 25 is stabilized is the feedback at that time. This is an offset adjustment voltage that makes the difference voltage between the non-inverting input terminal and the inverting input terminal zero, including the influence of the output voltage Vf of the operational amplifier 26, that is, the offset voltage Δv. Therefore, as the hold capacitor 27, a capacitor that is at least saturated when the output Vout of the integrating operational amplifier 25 converges stably is used.

オフセット調整期間(Tset)の経過後、MPU10は、第1アナログスイッチASW1を閉じ制御すると共に、第3アナログスイッチASW3を開制御して、積分動作期間(Tint)に移行する。積分動作期間(Tint)では、第1アナログスイッチASW1を閉じ制御されることにより、アナログマルチプレクサ12で選択接続した検出電極11に表れる交流検出信号SGが積分用オペアンプ25の反転入力端子に入力される。また、第3アナログスイッチASW3が開制御されるので、オフセット調整期間(Tset)中に、ホールド用コンデンサ27に充電された上記オフセット調整電圧が積分用オペアンプ25の非反転入力端子に入力され、オフセット電圧Δvを含めた積分用オペアンプ25の非反転入力端子と反転入力端子間の差電圧が0となり、積分用オペアンプ25の出力Voutに(13)式に示すオフセット電圧Δvを積分した誤差−Δv・t/CRが含まれない。   After the elapse of the offset adjustment period (Tset), the MPU 10 controls to close the first analog switch ASW1, and controls to open the third analog switch ASW3, and shifts to the integration operation period (Tint). In the integration operation period (Tint), the first analog switch ASW1 is closed and controlled, so that the AC detection signal SG appearing on the detection electrode 11 selectively connected by the analog multiplexer 12 is input to the inverting input terminal of the integration operational amplifier 25. . In addition, since the third analog switch ASW3 is controlled to open, the offset adjustment voltage charged in the hold capacitor 27 is input to the non-inverting input terminal of the integrating operational amplifier 25 during the offset adjustment period (Tset). The difference voltage between the non-inverting input terminal and the inverting input terminal of the integrating operational amplifier 25 including the voltage Δv becomes 0, and an error −Δv · that is obtained by integrating the offset voltage Δv shown in the equation (13) into the output Vout of the integrating operational amplifier 25. t / CR is not included.

その結果、微小な交流検出信号SGの電圧Vinのみが積分して拡大され、積分用オペアンプ25の出力Voutとして表れる。MPU10は、積分動作期間(Tint)の開始時から各検出電極11について同一経過時間とした経過時間後であって、積分動作期間(Tint)が終了する直前の判定時t1に、判定時t1の出力Voutを後段に接続されたA/Dコンバータ19へ出力し、A/Dコンバータ19は、検出電極11毎に、判定時t1の積分用オペアンプ25の出力Voutを量子化してMPU10へ出力する。   As a result, only the voltage Vin of the minute AC detection signal SG is integrated and expanded, and appears as the output Vout of the integrating operational amplifier 25. The MPU 10 is at the determination time t1 after the elapsed time that is the same elapsed time for each detection electrode 11 from the start of the integration operation period (Tint) and immediately before the end of the integration operation period (Tint). The output Vout is output to the A / D converter 19 connected in the subsequent stage, and the A / D converter 19 quantizes the output Vout of the integrating operational amplifier 25 at the determination time t1 for each detection electrode 11 and outputs it to the MPU 10.

A/Dコンバータ19から出力される量子化データは、その積分動作期間(Tint)中にアナログマルチプレクサ12が選択接続した検出電極11に表れる交流検出信号SGの受信レベルViに比例するので、入力位置検出手段として作用するMPU10は、A/Dコンバータ19から出力される量子化データを検出電極11に表れる交流検出信号SGの受信レベルViとし、その検出電極11と指30との距離dを求める。また、交流検出信号SGの受信レベルViは、信号処理回路13と積分回路14を通して量子化データが受信レベルViのn倍に増幅されるので、MPU10は、A/Dコンバータ19から出力される量子化データを1/nとして交流検出信号SGの受信レベルViとし、検出電極11と指30との距離dを求めてもよい。   The quantized data output from the A / D converter 19 is proportional to the reception level Vi of the AC detection signal SG appearing on the detection electrode 11 selectively connected by the analog multiplexer 12 during the integration operation period (Tint). The MPU 10 acting as detection means uses the quantized data output from the A / D converter 19 as the reception level Vi of the AC detection signal SG appearing on the detection electrode 11 and obtains the distance d between the detection electrode 11 and the finger 30. Further, since the reception level Vi of the AC detection signal SG is amplified to n times the reception level Vi through the signal processing circuit 13 and the integration circuit 14, the MPU 10 receives the quantum output from the A / D converter 19. The distance d between the detection electrode 11 and the finger 30 may be obtained by setting the digitized data to 1 / n and the reception level Vi of the AC detection signal SG.

以下、上述の入力検出方式1により、各検出電極X0、X1、Y0、Y1についての交流検出信号SGの受信レベルVx0、Vx1、Vy0、Vy1を検出し、指30の入力操作位置(x、y、z)を検出する方法を説明する。   Hereinafter, the reception level Vx0, Vx1, Vy0, Vy1 of the AC detection signal SG for each of the detection electrodes X0, X1, Y0, Y1 is detected by the input detection method 1 described above, and the input operation position (x, y) of the finger 30 is detected. , Z) will be described.

入力操作位置を検出する間、MPU19は、図9に示す約200msecの周期でアナログマルチプレクサ12の接続を切り換え制御し、検出電極X0、X1、Y0、Y1の順に各検出電極11を信号処理回路13へ接続し、全ての検出電極X0、X1、Y0、Y1を個別に切り換え接続する一周期を繰り返す。各検出電極11毎に信号処理回路13へ接続する一期間は、上述のオフセット調整期間Tsetと積分動作期間Tintとからなり、MPU19は、オフセット調整期間Tsetの開始直後から一定期間、第2アナログスイッチASW2を閉じ制御し、その直前の積分動作期間Tint中に積分用コンデンサC1に蓄積された電荷を放電させる。   While detecting the input operation position, the MPU 19 switches and controls the connection of the analog multiplexer 12 at a cycle of about 200 msec shown in FIG. 9, and sets the detection electrodes 11 in the order of the detection electrodes X0, X1, Y0, and Y1 to the signal processing circuit 13. And one cycle of individually switching and connecting all the detection electrodes X0, X1, Y0, and Y1 is repeated. One period connected to the signal processing circuit 13 for each detection electrode 11 is composed of the above-described offset adjustment period Tset and integration operation period Tint. The MPU 19 performs the second analog switch for a certain period immediately after the start of the offset adjustment period Tset. The ASW 2 is closed and controlled, and the charge accumulated in the integrating capacitor C 1 during the immediately preceding integration operation period Tint is discharged.

オフセット調整期間Tset中は、第1アナログスイッチASW1が開制御、第3アナログスイッチASW3が閉じ制御され、これにより、積分用オペアンプ25の出力電圧Vo(c)は、ASW1が開制御され一定の基準電圧となる反転入力端子の入力電圧(a)とオフセット電圧Δvの電位差での電位に収束して安定し、一定電圧に安定したオフセット調整期間Tsetの終了時に、ホールド用コンデンサ27の充電電圧は、積分用オペアンプ25のオフセット電圧Δvを相殺するオフセット調整電圧となる。   During the offset adjustment period Tset, the first analog switch ASW1 is controlled to be opened, and the third analog switch ASW3 is controlled to be closed. As a result, the output voltage Vo (c) of the integrating operational amplifier 25 is controlled so that the ASW1 is opened and is constant. At the end of the offset adjustment period Tset that converges and stabilizes at the potential difference between the input voltage (a) of the inverting input terminal and the offset voltage Δv, and the charging voltage of the hold capacitor 27 is The offset adjustment voltage cancels the offset voltage Δv of the integrating operational amplifier 25.

続いて、MPU19は、第1アナログスイッチASW1を閉じ制御、第3アナログスイッチASW3を開制御し、積分動作期間Tintに移行する。第1アナログスイッチASW1を閉じ制御されることにより、その期間内にアナログマルチプレクサ12を介して接続された検出電極11に表れる交流検出信号SGが信号処理回路13から積分処理回路14へ入力される。また、第3アナログスイッチASW3が開制御されることにより、積分用オペアンプ25の非反転入力端子から、帰還用オペアンプ26の出力が切り離されると共に、ホールド用コンデンサ27の充電電圧が加わり、オフセット電圧Δvを加えた非反転入力端子と反転入力端子間の差電圧が0となる。   Subsequently, the MPU 19 closes the first analog switch ASW1, controls the third analog switch ASW3, and shifts to the integration operation period Tint. When the first analog switch ASW1 is closed and controlled, the AC detection signal SG appearing on the detection electrode 11 connected via the analog multiplexer 12 is input from the signal processing circuit 13 to the integration processing circuit 14 within that period. Further, when the third analog switch ASW3 is controlled to be opened, the output of the feedback operational amplifier 26 is disconnected from the non-inverting input terminal of the integrating operational amplifier 25, and the charging voltage of the holding capacitor 27 is added to the offset voltage Δv. The difference voltage between the non-inverting input terminal and the inverting input terminal to which is added is zero.

図9に示すように、積分動作期間Tint中は、積分用オペアンプ25の非反転入力端子にオフセット電圧Δvを反転入力端子との差電圧から相殺するホールド用コンデンサ27のオフセット調整電圧(b)が入力され、反転入力端子に入力される固有周波数187kHzの交流検出信号SGの入力電圧Vi(a)のみが経過時間tで積分され、反転して積分用オペアンプ25から出力(c)される。図中、反転入力端子に入力される交流検出信号SGは、その入力電圧Viが高くなるほど、階段状に表れる積分用オペアンプ25の出力波形の傾斜が大きくなる。   As shown in FIG. 9, during the integration operation period Tint, the offset adjustment voltage (b) of the hold capacitor 27 that cancels the offset voltage Δv from the difference voltage from the inverting input terminal is applied to the non-inverting input terminal of the integrating operational amplifier 25. Only the input voltage Vi (a) of the AC detection signal SG having a natural frequency of 187 kHz input to the inverting input terminal is integrated at the elapsed time t, inverted and output from the integrating operational amplifier 25 (c). In the figure, the AC detection signal SG input to the inverting input terminal has a larger slope of the output waveform of the integrating operational amplifier 25 that appears in a staircase pattern as the input voltage Vi increases.

本実施の形態では、積分動作期間Tintが終了する直前であって、積分動作期間Tintの開始時からの経過時間Tcが各検出電極11について同一となる判定時t1を設定し、この判定時t1の積分用オペアンプ25の出力Voutを、接続した検出電極11に表れる交流検出信号SGの受信レベルVx0、Vx1、Vy0、Vy1として、A/Dコンバータ19へ出力する。   In the present embodiment, a determination time t1 is set immediately before the end of the integration operation period Tint, and the elapsed time Tc from the start of the integration operation period Tint is the same for each detection electrode 11, and this determination time t1 The output Vout of the integrating operational amplifier 25 is output to the A / D converter 19 as reception levels Vx0, Vx1, Vy0, and Vy1 of the AC detection signal SG appearing at the connected detection electrode 11.

積分動作期間Tintの終了後、MPU10は、次の検出電極11を信号処理回路13へ接続するようにアナログマルチプレクサ12を切り換え制御し、その検出電極11について、同様にオフセット調整期間Tsetと積分動作期間Tintの制御を繰り返す。A/Dコンバータ19から入力された出力電圧Voutは、各検出電極に表れる交流検出信号SGの受信レベルViを同倍率で拡大したものなので、MPU10は、全ての検出電極X0、X1、Y0、Y1を接続した一周期の経過後に、各検出電極11についてA/Dコンバータ19から入力された出力電圧Voutを、その検出電極11についての交流検出信号SGの受信レベルViとして、指30の二次元の入力操作位置(x、y)若しくは三次元の入力操作位置(x、y、z)を検出する。   After the end of the integration operation period Tint, the MPU 10 switches and controls the analog multiplexer 12 so that the next detection electrode 11 is connected to the signal processing circuit 13, and the offset adjustment period Tset and the integration operation period are similarly detected for the detection electrode 11. Repeat Tint control. Since the output voltage Vout input from the A / D converter 19 is obtained by enlarging the reception level Vi of the AC detection signal SG appearing at each detection electrode at the same magnification, the MPU 10 has all the detection electrodes X0, X1, Y0, Y1. After the elapse of one cycle, the output voltage Vout input from the A / D converter 19 for each detection electrode 11 is used as the reception level Vi of the AC detection signal SG for the detection electrode 11 and the two-dimensional of the finger 30 An input operation position (x, y) or a three-dimensional input operation position (x, y, z) is detected.

検出電極X0、X1をアナログマルチプレクサ12が接続した際に、A/Dコンバータ19から出力される交流検出信号SGの受信レベルViをそれぞれVx0、Vx1、X方向で対向する一組の検出電極X0、X1間の距離をLxとし、指30が図3に示す入力操作位置P(x、z)にあったとすると、(10)式から、
検出電極X0について、
When the analog multiplexer 12 connects the detection electrodes X0 and X1, the reception level Vi of the AC detection signal SG output from the A / D converter 19 is set to a pair of detection electrodes X0 and Vx that face each other in the Vx0, Vx1, and X directions. If the distance between X1 is Lx and the finger 30 is at the input operation position P (x, z) shown in FIG.
About the detection electrode X0,

Figure 2013021414
Figure 2013021414

と、検出電極X1について、 And for the detection electrode X1,

Figure 2013021414
Figure 2013021414

が成り立ち、k、Lx、Vsが既知の値であるので、検出したVx0、Vx1を(22)式と(23)式に代入して、Lx−x、zが負ではないとの条件から、
検出電極X0からX方向の位置xと、入力操作面21aに直交するZ方向の位置zが得られる。
Since k, Lx, and Vs are known values, the detected Vx0 and Vx1 are substituted into the equations (22) and (23), and the condition that Lx−x and z are not negative is
A position x in the X direction from the detection electrode X0 and a position z in the Z direction orthogonal to the input operation surface 21a are obtained.

交流検出信号SGの出力レベルVsの検出が困難である場合には、例えば、検出電極X0の入力操作位置(x(0)、z(0))で検出電極X1についての交流検出信号SGの受信レベルVx1(0、0)を検出し、(10)式に代入し、   When it is difficult to detect the output level Vs of the AC detection signal SG, for example, reception of the AC detection signal SG for the detection electrode X1 at the input operation position (x (0), z (0)) of the detection electrode X0. Detect level Vx1 (0, 0) and substitute it into equation (10)

Figure 2013021414
Figure 2013021414

から得てもよい。 May be obtained from

同様に、Y方向についても、検出電極Y0、Y1をアナログマルチプレクサ12が接続した際に、A/Dコンバータ19から出力される交流検出信号SGの受信レベルViをそれぞれVy0、Vy1、Y方向で対向する一組の検出電極Y0、Y1間の距離をLyとし、指30が入力操作位置P(y、z)にあったとすると、(10)式から、
検出電極Y0について、
Similarly, in the Y direction, when the analog multiplexer 12 connects the detection electrodes Y0 and Y1, the reception level Vi of the AC detection signal SG output from the A / D converter 19 is opposed in the Vy0, Vy1, and Y directions, respectively. If the distance between the set of detection electrodes Y0 and Y1 is Ly and the finger 30 is at the input operation position P (y, z),
For the detection electrode Y0,

Figure 2013021414
Figure 2013021414

と、検出電極Y1について、 And for the detection electrode Y1,

Figure 2013021414
Figure 2013021414

が成り立ち、検出したVy0、Vy1を(24)式と(25)式に代入して、Ly−y、zが負ではないとの条件から、検出電極Y0からY方向の位置yと、入力操作面21aに直交するZ方向の位置zが得られる。 Substituting the detected Vy0 and Vy1 into the equations (24) and (25), and assuming that Ly-y and z are not negative, the position y in the Y direction from the detection electrode Y0 and the input operation A position z in the Z direction perpendicular to the surface 21a is obtained.

各検出電極X0、X1、Y0、Y1は、それぞれ矩形状の窓孔21の内縁の各辺全体に渡って配置されているので、少なくとも入力操作面21aの鉛直方向のいずれかを入力操作した指30は、X方向で検出電極X0、X1と、Y方向で検出電極Y0、Y1と対向するので、(22)式乃至(25)式から、指30の三次元の入力操作位置(x、y、z)を検出できる。   Since each of the detection electrodes X0, X1, Y0, Y1 is arranged over the entire inner edge of the rectangular window hole 21, the finger that has performed an input operation at least in the vertical direction of the input operation surface 21a. 30 faces the detection electrodes X0 and X1 in the X direction and the detection electrodes Y0 and Y1 in the Y direction, and therefore the three-dimensional input operation position (x, y) of the finger 30 from the equations (22) to (25). Z) can be detected.

特に、入力操作面21aへの入力操作に限り、二次元の入力操作位置(x、y)を検出する入力検出方式1とする場合には、X方向について、z=0とした(22)式と(23)式から、出力レベルVsを消去すれば、0≦x≦Lxから   In particular, in the case of the input detection method 1 for detecting the two-dimensional input operation position (x, y) only for the input operation on the input operation surface 21a, the equation (22) is set to z = 0 in the X direction. From equation (23), if the output level Vs is deleted, from 0 ≦ x ≦ Lx

Figure 2013021414
Figure 2013021414

が得られ、(26)式をxについて解けば、 And solving equation (26) for x,

Figure 2013021414
Figure 2013021414

となる。 It becomes.

同様に、Y方向についても、(24)式、(25)式から、   Similarly, from the formulas (24) and (25) in the Y direction,

Figure 2013021414
Figure 2013021414

が得られ、Vx0、Vx1、Vy0、Vy1から入力操作面21a上のXY方向の入力位置(x、y)が容易に得られる。 The input position (x, y) in the XY direction on the input operation surface 21a can be easily obtained from Vx0, Vx1, Vy0, Vy1.

MPU10で検出した入力操作位置(x、y、z)を含む入力操作データは、直流が絶縁された信号線16を介して、非振動回路基板2に搭載されるインターフェース回路6に出力され、インターフェース回路6からUSB通信、IC通信等で入力操作データを利用する上位機器に出力される。The input operation data including the input operation position (x, y, z) detected by the MPU 10 is output to the interface circuit 6 mounted on the non-vibration circuit board 2 via the signal line 16 in which the direct current is insulated. The data is output from the circuit 6 to a host device that uses input operation data by USB communication, I 2 C communication, or the like.

図10は、上述の積分処理回路14のフィードバック回路部を他の構成とした第2の実施の形態にかかる積分処理回路40のブロック図であり、以下、図10に示す他の実施の形態では、フィードバック回路部の構成のみが異なるので、図中の第1実施の形態と共通する構成は同一番号を付してその説明を省略する。   FIG. 10 is a block diagram of an integration processing circuit 40 according to the second embodiment in which the feedback circuit unit of the above-described integration processing circuit 14 has another configuration. Hereinafter, in the other embodiments shown in FIG. Since only the configuration of the feedback circuit section is different, the configuration common to the first embodiment in the figure is given the same number, and the description thereof is omitted.

積分処理回路40のフィードバック回路部は、非反転入力端子を積分用オペアンプ25の出力に、反転入力端子を基準電位(ここでは接地電位)とした帰還用オペアンプ41と、一側を基準電位とし、他側を第4アナログスイッチASW4を介して帰還用オペアンプ41の出力に接続させたホールド用コンデンサ42と、ホールド用コンデンサ42と第4アナログスイッチASW4の接続点を非反転入力端子に接続させた電圧フォロア43と、電圧フォロア43の出力と積分用オペアンプ25の反転入力端子間に接続された第2積分用抵抗R5で構成される。   The feedback circuit unit of the integration processing circuit 40 has a non-inverting input terminal as an output of the integrating operational amplifier 25, a feedback operational amplifier 41 having an inverting input terminal as a reference potential (here, ground potential), and one side as a reference potential. The holding capacitor 42 having the other side connected to the output of the feedback operational amplifier 41 via the fourth analog switch ASW4, and the voltage connecting the connection point of the holding capacitor 42 and the fourth analog switch ASW4 to the non-inverting input terminal The follower 43 includes a second integration resistor R5 connected between the output of the voltage follower 43 and the inverting input terminal of the integration operational amplifier 25.

すなわち、この第2の実施の形態にかかる積分処理回路40では、フィードバック回路部の出力を、第2積分用抵抗R5を介して積分用オペアンプ25の反転入力端子側に帰還させたもので、第2積分用抵抗R5を流れる帰還用オペアンプ41の出力で積分用オペアンプ25が安定動作させるように、出力インピーダンスがほぼ0の電圧フォロア43を介在させている。   That is, in the integration processing circuit 40 according to the second embodiment, the output of the feedback circuit unit is fed back to the inverting input terminal side of the integration operational amplifier 25 via the second integration resistor R5. 2 A voltage follower 43 having an output impedance of approximately 0 is interposed so that the integrating operational amplifier 25 operates stably with the output of the feedback operational amplifier 41 flowing through the integrating resistor R5.

オフセット調整期間Tset中に、第1アナログスイッチASW1を開制御、第4アナログスイッチASW4を閉じ制御すると、帰還用オペアンプ41の出力をVf、積分用抵抗R5の抵抗値をRとして、積分用オペアンプ25の出力電圧Voutは、   When the first analog switch ASW1 is controlled to be opened and the fourth analog switch ASW4 is controlled to be closed during the offset adjustment period Tset, the output of the feedback operational amplifier 41 is set to Vf, the resistance value of the integrating resistor R5 is set to R, and the integrating operational amplifier 25 The output voltage Vout of

Figure 2013021414
Figure 2013021414

で表され、積分用オペアンプ25は、入力電圧Vfを積分した電圧Voutを出力するように動作する。その結果、積分用オペアンプ25の出力電圧Voutは、反転入力端子の入力電圧、すなわち帰還用オペアンプ41の出力電圧Vfに収束して安定し、出力電圧Voutが安定したオフセット調整期間Tsetの終了時に、ホールド用コンデンサ42の充電電圧は、積分用オペアンプ25のオフセット電圧Δvを相殺するオフセット調整電圧となる。 The integrating operational amplifier 25 operates so as to output a voltage Vout obtained by integrating the input voltage Vf. As a result, the output voltage Vout of the integrating operational amplifier 25 converges and stabilizes at the input voltage of the inverting input terminal, that is, the output voltage Vf of the feedback operational amplifier 41, and at the end of the offset adjustment period Tset when the output voltage Vout is stable. The charging voltage of the holding capacitor 42 becomes an offset adjustment voltage that cancels the offset voltage Δv of the integrating operational amplifier 25.

第1アナログスイッチASW1を閉じ制御すると共に、第4アナログスイッチASW4を開制御して、積分動作期間(Tint)に移行すると、検出電極11に表れる交流検出信号SGにオフセット電圧Δvを相殺するオフセット調整電圧がホールド用コンデンサ42から加えられ、積分用オペアンプ25の反転入力端子に入力される。従って、非反転入力端子の基準電圧(接地電位)との差電圧には、オフセット電圧Δvが含まれず、交流検出信号SGの入力電圧Vinを積分した出力電圧Voutのみが出力される。   When the first analog switch ASW1 is controlled to be closed and the fourth analog switch ASW4 is controlled to be opened and the integration operation period (Tint) is started, the offset adjustment that offsets the offset voltage Δv to the AC detection signal SG that appears on the detection electrode 11 A voltage is applied from the holding capacitor 42 and input to the inverting input terminal of the integrating operational amplifier 25. Therefore, the difference voltage from the reference voltage (ground potential) of the non-inverting input terminal does not include the offset voltage Δv, and only the output voltage Vout obtained by integrating the input voltage Vin of the AC detection signal SG is output.

上述の実施の形態では、検出電極11を入力操作体30に対して交流検出信号SGの出力レベルVsで振動させ、両者の間に出力レベルVsの相対電位を発生させたが、検出電極11側を定電位として、入力操作体30の電位を交流検出信号SGの出力レベルVsで変動させてもよい。   In the above-described embodiment, the detection electrode 11 is vibrated at the output level Vs of the AC detection signal SG with respect to the input operating body 30, and the relative potential of the output level Vs is generated between them. May be set to a constant potential, and the potential of the input operating body 30 may be varied with the output level Vs of the AC detection signal SG.

また、入力操作体30は、操作者が入力操作を行う指30で説明したが、操作者が握る専用入力ペンなど操作者と別の操作体であってもよい。   Moreover, although the input operation body 30 was demonstrated with the finger | toe 30 which an operator performs input operation, you may be an operation body different from an operator, such as a dedicated input pen which an operator holds.

積分回路の出力電圧Voutの傾きから交流検出信号の受信レベルViを得る方法として、上述の実施の形態では、一定の積分時間が経過した時点での出力電圧Voutから受信レベルViを得たが、出力電圧Voutが一定値となるまでの積分時間から受信レベルViを得てもよい。   As a method for obtaining the reception level Vi of the AC detection signal from the slope of the output voltage Vout of the integration circuit, the reception level Vi is obtained from the output voltage Vout when a certain integration time has elapsed in the above-described embodiment. The reception level Vi may be obtained from the integration time until the output voltage Vout becomes a constant value.

また、上述の実施の形態では、複数の検出電極11についての受信レベルViを比較して入力操作体30の入力操作位置を検出する例で説明したが、特定の検出電極11についての受信レベルViが一定レベルを越えることから、その検出電極11に入力操作体30を接近させる入力操作を検出する用途にも採用できる。   In the above-described embodiment, the example in which the input operation position of the input operation body 30 is detected by comparing the reception levels Vi for the plurality of detection electrodes 11 has been described. However, the reception level Vi for the specific detection electrode 11 is described. Since this exceeds a certain level, it can also be used for detecting an input operation in which the input operating body 30 is brought close to the detection electrode 11.

本発明は、非接触で入力操作を検出する静電容量式タッチパネルに用いる入力検出方式に適している。   The present invention is suitable for an input detection method used for a capacitive touch panel that detects an input operation without contact.

1 静電容量式入力検出方式
10 MPU
11 検出電極
14 積分処理回路(信号検出手段)
15 発振回路(発信手段)
30 指(入力操作体)
Cm 静電容量
SG 交流検出信号
Vs 交流検出信号の出力レベル
Vi 交流検出信号の受信レベル
1 Capacitance type input detection method 10 MPU
11 detection electrode 14 integration processing circuit (signal detection means)
15 Oscillator circuit (transmitting means)
30 fingers (input operation body)
Cm Capacitance SG AC detection signal Vs Output level of AC detection signal Vi Reception level of AC detection signal

Claims (4)

絶縁ケースに配置される検出電極と、
入力操作体と検出電極との相対電位を変動させる交流検出信号を発信する発信手段と、
検出電極と入力操作体間の静電容量を介して検出電極に表れる交流検出信号の受信レベルを検出する信号検出手段とを備え、
検出電極に表れる交流検出信号の受信レベルから、検出電極と入力操作体間の距離を求め、入力操作体による入力操作を検出する静電容量式入力検出方式であって、
信号検出手段は、前記検出電極に表れる交流検出信号を交流検出信号の周期より充分に長い積分動作期間中に積分して出力する積分回路を有し、積分回路の出力の傾きから前記交流検出信号の受信レベルを検出することを特徴とする静電容量式入力検出方式。
A sensing electrode disposed in an insulating case;
Transmitting means for transmitting an AC detection signal for changing the relative potential between the input operation body and the detection electrode;
Signal detecting means for detecting the reception level of the AC detection signal appearing on the detection electrode via the capacitance between the detection electrode and the input operation body,
From the reception level of the AC detection signal appearing on the detection electrode, the distance between the detection electrode and the input operation body is obtained, and the capacitance type input detection method for detecting the input operation by the input operation body,
The signal detection means has an integration circuit that integrates and outputs the AC detection signal appearing on the detection electrode during an integration operation period sufficiently longer than the cycle of the AC detection signal, and the AC detection signal is obtained from the slope of the output of the integration circuit. Capacitance type input detection method characterized by detecting the reception level.
積分回路は、検出電極の出力側に接続された積分用抵抗と、非反転入力端子の第1基準電圧に対して、検出電極から積分用抵抗を介して反転入力端子に入力される前記交流検出信号の入力電圧との差分を出力する積分用オペアンプと、積分用オペアンプの反転入力端子と出力端子間に接続された積分用コンデンサとからなり、
信号検出手段は、更に、積分用オペアンプの反転入力端子と非反転入力端子間に発生するオフセット電圧を相殺するオフセット調整電圧を、積分用オペアンプの反転入力端子若しくは非反転入力端子に加えるオフセット調整手段を有することを特徴とする請求項1に記載の静電容量式入力検出方式。
The integration circuit is configured to detect the AC detection input from the detection electrode to the inverting input terminal via the integration resistor with respect to the integration resistor connected to the output side of the detection electrode and the first reference voltage of the non-inverting input terminal. It consists of an integration operational amplifier that outputs the difference from the signal input voltage, and an integration capacitor connected between the inverting input terminal and the output terminal of the integration operational amplifier.
The signal detection means further applies an offset adjustment voltage that cancels an offset voltage generated between the inverting input terminal and the non-inverting input terminal of the integrating operational amplifier to the inverting input terminal or the non-inverting input terminal of the integrating operational amplifier. The electrostatic capacitance type input detection system according to claim 1, wherein:
オフセット調整手段は、所定のオフセット調整期間中に第2基準電圧とした積分用抵抗の入力側に非反転入力端子が接続するとともに、積分用オペアンプの出力に反転入力端子が接続し、オフセット調整期間中に、非反転入力端子の第2基準電圧に対して、反転入力端子に入力される帰還用オペアンプの出力電圧との差分を出力する帰還用オペアンプと、帰還用オペアンプの出力と積分用オペアンプの非反転入力端子間に接続され、オフセット調整期間中に閉じ動作し、積分動作期間中に開動作するスイッチと、積分用オペアンプの非反転入力端子に接続し、オフセット調整期間中に帰還用オペアンプの出力電圧で充電されるオフセット調整電圧を、積分動作期間中に積分用オペアンプの非反転入力端子に加えるホールド用コンデンサとからなることを特徴とする請求項2に記載の静電容量式入力検出方式。 The offset adjusting means has a non-inverting input terminal connected to the input side of the integrating resistor used as the second reference voltage during a predetermined offset adjusting period, and an inverting input terminal connected to the output of the integrating operational amplifier. A feedback operational amplifier that outputs a difference between the output voltage of the feedback operational amplifier input to the inverting input terminal with respect to the second reference voltage of the non-inverting input terminal, and the output of the feedback operational amplifier and the integrating operational amplifier. Connected between the non-inverting input terminals, closed during the offset adjustment period, opened during the integration operation period, and connected to the non-inverting input terminal of the integrating operational amplifier, and fed back to the feedback operational amplifier during the offset adjustment period. From the hold capacitor that applies the offset adjustment voltage charged by the output voltage to the non-inverting input terminal of the integration operational amplifier during the integration operation period Capacitive input detection method according to claim 2, characterized in Rukoto. 絶縁ケースに互いに絶縁して配置される複数の検出電極と、
複数の各検出電極を選択的に信号検出手段へ切り換え接続する切り換え手段とを備え、
前記各検出電極についてそれぞれ信号検出手段が検出した交流検出信号の受信レベルと、各検出電極の配置位置とから、入力操作体の入力操作位置を検出することを特徴とする請求項1乃至3のいずれか1項に記載の静電容量式入力検出方式。
A plurality of detection electrodes arranged insulated from each other in an insulating case;
Switching means for selectively switching and connecting each of the plurality of detection electrodes to the signal detection means,
The input operation position of the input operation body is detected from the reception level of the AC detection signal detected by the signal detection means for each detection electrode and the arrangement position of each detection electrode. The capacitance-type input detection method according to any one of the above.
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