JPWO2013018218A1 - Synchronous control device, arithmetic processing device, parallel computer system, and synchronous control device control method - Google Patents

Abstract

The synchronization control device (17) detects the rising or falling edge of the divided clock signal obtained by dividing the clock signal by 1 / N by the CD (4). Further, the synchronization control device (17) monitors the second timing for updating the STICK register (15) of the CPU (10) by monitoring the elapsed time from the rising or falling edge of the divided clock signal. The synchronous control device (17) generates a control clock obtained by multiplying the divided clock signal obtained by dividing the CD (4) by N times. The synchronization control device (17) receives a synchronization request from another CPU via the XB (26). And a synchronous control apparatus (17) outputs the produced | generated control clock, when the synchronous request | requirement from another CPU is received and a 2nd timing is detected.

Description

  The present invention relates to a synchronous control device, an arithmetic processing device, a parallel computer system, and a control method for the synchronous control device.

  Conventionally, a parallel computer system having a plurality of CPUs (Central Processing Units) is known. As an example of such a parallel computer system, a technique is known in which values stored in a system TICK register (hereinafter referred to as a STICK register) of each CPU are aligned to synchronize processing executed by each CPU. ing.

  FIG. 21 is a diagram for explaining an example of a conventional parallel computer system. In the example illustrated in FIG. 21, the parallel computer system 70 includes an oscillator 71, a reference signal generation unit 72, a plurality of CPUs 73 to 73 e, a plurality of crossbar chips (hereinafter referred to as XB) 74 to 74 b, and a bus 75.

  The CPU 73 has a plurality of cores 76 and 79, and has STICK registers 77 and 80 for executing processing in synchronization with the other CPUs 73 a to 73 e inside each of the cores 76 and 79. The CPU also includes a synchronization control mechanism 90 for synchronizing the value stored in the STICK register with other CPUs. Note that the CPUs 73a to 73e perform the same functions as the CPU 73, and the following description is omitted.

  The reference signal generator 72 included in the parallel computer system 1 counts the values stored in the STICK registers 77 to 77e and 80 to 80e included in the CPUs 73 to 73e in accordance with the signal input from the oscillator 71. A reference signal to be raised is generated. Then, the reference signal generation unit 72 supplies the generated reference signal to each of the CPUs 73 to 73e with a minimum skew through a transmission path in which signal transmission characteristics such as the length of the connection line are managed. That is, the reference signal generation unit 72 supplies reference signals having the same phase to the CPUs 73 to 73e.

  FIG. 22 is a diagram for explaining a conventional CPU. As shown in FIG. 22, the CPU 73 includes a core 76, a core 79, and a synchronization control mechanism 90. The core 76 includes a STICK register 77 and an IU (Instruction Control Unit) 78, and the core 79 includes a STICK register 80 and an IU 81. Have Such a CPU 73 supplies the reference signal supplied from the reference signal generator 72 to the synchronization control mechanism 90 via the path shown in FIG.

  Further, when the software being executed requests synchronization of processing executed by the CPUs 73 to 73e, the IUs 78 and 81 send the CPUs 73 to 73 to the synchronization control mechanism 90 as shown in FIG. Requests synchronization of processing executed by 73e. In such a case, as shown in (C ′) in FIG. 22, the synchronization control mechanism 90 synchronizes the CPUs 73 to 73e including itself with a synchronization request indicating the count start or count stop of the STICK register. Broadcast transmission to the control mechanisms 90-90e.

  Here, the CPUs 73 to 73e, the XBs 74 to 74b, and the bus 75 are connected by a parallel bus in which signal transmission characteristics are managed and a constant latency can be expected. Therefore, each of the synchronization control mechanisms 90 to 90e receives the synchronization request broadcasted as shown in (C) in FIG. 22 at the same timing. Then, as shown in FIG. 22D, the synchronization control mechanism 90 starts or stops counting the values stored in the STICK registers 77 and 80 based on the timing at which the synchronization request is received.

  By executing such processing, the synchronization control mechanisms 90 to 90e start counting up the values stored in the STICK registers 77 to 77e and 80 to 80e at the same timing, and are executed by the CPUs 73 to 73e. Synchronize the processing to be performed.

  Hereinafter, an example of each of the synchronization control mechanisms 90 to 90e will be described with reference to the drawings. FIG. 23 is a diagram for explaining a conventional synchronization control mechanism. For example, the synchronization control mechanism 90 includes a synchronizer 91, an up-edge detector 92, a phase counter 93, a setting register 94a, a comparator 94b, a setting register 95a, a comparator 95b, a control packet transmitter 96, and a control packet receiver 97. The control packet transmission unit 96 includes a transmission buffer 96a, an output circuit 96b, and an encoder 96c. In addition, the control packet receiving unit 97 includes a decoder 97a, a reception buffer 97b, and an update circuit 97c. Note that routes (A) to (D) shown in FIG. 23 correspond to routes (A) to (D) in FIG.

  The synchronizer 91 synchronizes the reference signal received via the path shown in FIG. 23A with the core clock of the core 73. The up edge detector 92 detects the up edge of the reference signal synchronized with the core clock. The phase counter 93 counts the number of core clock cycles, and resets the counted number of core clock cycles each time the up-edge detector 92 detects an up-edge. That is, the phase counter 93 measures the time elapsed from the up edge of the reference signal using the core clock.

  Here, predetermined values are set in advance in the setting register 94a and the setting register 95a. The comparator 94b outputs an enable signal to the output circuit 96b when the value of the phase counter 93 becomes equal to the value set in the setting register 94a. In the comparison period 95b, when the value of the phase counter 93 becomes the same as the value set in the setting register 95b, an enable signal is output to the update circuit 97c.

  That is, the comparator 94b outputs an enable signal to the output circuit 96b when the time set in the setting register 94a has elapsed from the up edge of the reference signal. Further, the comparator 95b outputs an enable signal to the update circuit 97c when the time set in the setting register 95a elapses from the up edge of the reference signal. In the following description, the timing at which the comparator 94b transmits the enable signal is described as “XBC Timing”, and the timing at which the comparator 95b outputs the enable signal is described as “REG-WR Timing”.

  When receiving a synchronization request from the IU 78 via the path shown in FIG. 23B, the control packet transmission unit 96 stores the received synchronization request in the transmission buffer 96a. Then, when the enable signal is input to the output circuit 96b, that is, when the time measured by the phase counter 93 becomes “XBC Timing”, the control packet transmitting unit 96 executes the following processing. That is, the control packet transmission unit 96 packetizes the synchronization request using the encoder 96c, and broadcasts the synchronization request packet via the path and the XB 75 shown in (C ') in FIG.

  On the other hand, when receiving the synchronization request packet via the path shown in FIG. 23C, the control packet receiving unit 97 decodes the packet using the decoder 97a and sends the synchronization request to the reception buffer 97b. Store. Then, when the enable signal is input, that is, when the time measured by the phase counter 93 becomes “REG-WR Timing”, the update circuit 97c executes the following processing.

  That is, the update circuit 97c stores “0” in the control register 98 when the synchronization request stored in the reception buffer 97b indicates the count start of each CPU. As a result, the synchronization control mechanism 90 outputs the reference signal to the STICK register 77 via the path indicated by (D) in FIG. That is, immediately after receiving the synchronization request, the synchronization control mechanism 90 starts counting the STICK register at the timing when the phase counting circuit indicates “REG-WR Timing”.

  FIG. 24 is a diagram for explaining the timing for starting the count of the STICK register. 24 includes a reference signal received via (A) in FIG. 23, a synchronization request received via (B) in FIG. 23, a packet received via (C) in FIG. The reference signal output via D) is described. FIG. 24 shows the timing at which each of the CPUs 73 to 73e receives the packet, and the timing at which each of the CPUs 73 to 73e counts the STICK register. First, as shown in (E) of FIG. 23, when the synchronization control mechanism 90 receives a synchronization request from the IU 78, the synchronization request is stored by “XBC Timing” shown in (F) of FIG. 24. The packet is broadcasted to each of the CPUs 73 to 73e.

  Then, the CPUs 73 to 73e, the XBs 74 to 74b, and the bus 75 are connected by a parallel bus with guaranteed latency. A packet in which a synchronization request is stored is received. Thereafter, each of the motivation control mechanisms 90 to 90e starts counting of the STICK register at “REG-WR Timing” shown in FIG.

Japanese Patent Laid-Open No. 10-233766 Japanese Patent Laid-Open No. 10-244383

  However, in the technique of broadcasting the above-described synchronization request, the control signal and the data are transmitted through one signal line instead of the parallel bus in which the control signals and the data to be controlled by the control signals are separated between the CPUs. When the transmission latency of a serial link or the like is connected in a manner that is not constant, there is a problem that proper synchronization control cannot be performed.

  FIG. 25 is a diagram for explaining a case where the timing for starting counting of the STICK register is not uniform among CPUs when the transmission latency between the CPUs is not constant. In the example shown in FIG. 25, the CPUs 73 to 73a are connected by a serial link. 25 (E) shows the timing of receiving a synchronization request from the IU 79, as in (E) in FIG. 24. (F) in FIG. 25 is similar to (F) in FIG. Timing ". Further, (G) in FIG. 25 indicates “REG-WR Timing” as in (G) in FIG. 24. FIG. 25 shows the timing at which the CPUs 73 to 73e receive the packet, and the timing at which the CPUs 73 to 73e count the STICK register, as in FIG.

  For example, as shown in (E) of FIG. 25, when the IU 78 issues a synchronization request, the CPU 62 broadcasts the synchronization request to each of the CPUs 73 to 73e by “XBC Timing” shown in (F) of FIG. To do. Here, in the serial link, by allowing the occurrence of a transmission error with a certain probability, the throughput between the CPUs 73 to 73e is made higher than when the occurrence of the transmission error is not allowed. That is, in a serial link that allows the occurrence of a transmission error with a certain probability, if a transmission error occurs, the transmission error is remedied by retransmitting the data, so that the transmission latency is higher than when the transmission error is not allowed. Will increase. Therefore, unlike signal transmission that does not allow the occurrence of transmission errors, transmission latency is not constant in signal transmission using a serial link.

  For this reason, as shown in (I) in FIG. 25, when a transmission error occurs in the CPUs 73a, 73b, 73e, the CPUs 62 to 69 receive the broadcast synchronization requests at different timings. As a result, the CPU starts counting the STICK register at “REG-WR Timing” shown in FIG. 25G and the STICK register starts counting at “REG-WR Timing” shown in FIG. CPU will be mixed. In the example illustrated in FIG. 25, the CPU 73a and the CPU 73b start counting at timings different from those of the other CPUs 73 and 73c to 73e. That is, there are CPUs that start counting the STICK register at different timings.

  As a result, each of the CPUs 73 to 73e cannot prepare the values stored in the respective STICK registers 77 to 77e and 80 to 80e, so that there is a problem that the processes cannot be executed synchronously.

  In one aspect, an object of the present invention is to enable synchronous control when CPUs are connected in a manner in which transmission latency such as a serial link is not constant.

  In one aspect, a synchronization control device included in an arithmetic processing device connected to another arithmetic processing device via a data transfer device, which is connected to a clock frequency divider that divides an input clock signal by 1 / N. The synchronization control device also detects a rising edge or falling edge of the divided clock signal divided by the clock divider, and an elapsed time from the rising edge or falling edge of the divided clock signal detected by the detection section. A monitoring unit for monitoring; Here, the monitoring unit monitors a first timing for transmitting a synchronization request to the data transfer device and a second timing for updating a synchronization register included in the arithmetic processing device. In addition, the synchronization control device includes a clock generation unit that generates a control clock obtained by multiplying the divided clock signal divided by the clock divider by N times. In addition, the synchronization control device includes a synchronization request receiving unit that receives synchronization requests from other arithmetic processing devices via the data transfer device. The synchronization control device outputs the control clock generated by the clock generation unit when the synchronization request reception unit receives a synchronization request from another arithmetic processing unit and the monitoring unit detects the second timing. A clock control unit. In addition, the synchronization control device includes a synchronization request transmission unit that transmits a synchronization request to another arithmetic processing device via the data transfer device when the monitoring unit detects the first timing.

  In one embodiment, synchronization control can be performed when the CPUs are connected by a method such as a serial link in which the transmission latency is not constant.

FIG. 1 is a diagram for explaining an example of a parallel computer system according to the first embodiment. FIG. 2 is a schematic diagram illustrating an example of a CPU according to the first embodiment. FIG. 3 is a diagram for explaining an example of the synchronization control mechanism according to the first embodiment. FIG. 4 is a diagram for explaining an example of a control packet storing a synchronization request. FIG. 5A is a diagram for explaining an example of the synchronization control mechanism according to the first embodiment. FIG. 5B is a diagram (1) for explaining an example of the operation of the synchronization control mechanism. FIG. 5c is a diagram (2) for explaining an example of the operation of the synchronization control mechanism. FIG. 5d is a diagram (3) for explaining an example of the operation of the synchronization control mechanism. FIG. 6 is a time chart for explaining the timing for starting the count of the STICK register according to the first embodiment. FIG. 7 is a diagram for explaining an example of a parallel computer system according to the second embodiment. FIG. 8 is a schematic diagram illustrating an example of a CPU according to the second embodiment. FIG. 9 is a diagram for explaining the synchronization control mechanism according to the second embodiment. FIG. 10 is a diagram for explaining an example of the synchronization control mechanism according to the second embodiment. FIG. 11 is a time chart for explaining the timing for starting the count of the STICK register according to the second embodiment. FIG. 12 is a schematic diagram illustrating an example of a parallel computer system according to the third embodiment. FIG. 13 is a diagram for explaining a part of the parallel computer system according to the third embodiment. FIG. 14 is a schematic diagram illustrating an example of a component according to the third embodiment. FIG. 15 is a diagram for explaining the synchronization control mechanism according to the third embodiment. FIG. 16 is a diagram for explaining the BC pipeline mechanism according to the third embodiment. FIG. 17 is a diagram for explaining an example of the BC pipeline mechanism. FIG. 18 is a time chart for explaining the timing at which the synchronization control mechanism transmits a control packet to the BC pipeline mechanism. FIG. 19 is a time chart for explaining the timing at which the BC pipeline mechanism broadcasts a control packet. FIG. 20 is a time chart for explaining the timing at which the synchronization control mechanism outputs a synchronization signal to the STICK register. FIG. 21 is a diagram for explaining an example of a conventional parallel computer system. FIG. 22 is a diagram for explaining a conventional CPU. FIG. 23 is a diagram for explaining a conventional synchronization control mechanism. FIG. 24 is a diagram for explaining the timing for starting the count of the STICK register. FIG. 25 is a diagram for explaining a case where the timing for starting counting of the STICK register is not uniform among CPUs when the transmission latency between the CPUs is not constant.

  A control method for a synchronous control device, an arithmetic processing device, a parallel computer system and a synchronous control device according to the present application will be described below with reference to the accompanying drawings.

  In the following embodiment 1, an example of a parallel computer system will be described with reference to FIG. FIG. 1 is a diagram for explaining an example of a parallel computer system according to the first embodiment. As shown in FIG. 1, the parallel computer system 1 includes a plurality of structural units 2 to 2 b and a bus 7.

  The structural unit 2 includes an oscillator 3, a CD (Clock Distributor) 4, a CPU 10, a CPU 18, and an XB 26. In addition, each structural unit 2a, 2b has the oscillator 3a, 3b, CD4a, 4b, CPU10a, 10b, CPU18a, 18b, XB26a, XB26b similarly to the structural unit 2. The bus 7 is a connection path that is used in common by each unit of the parallel computer system 1 such as, for example, Inter Connect. The CPUs 11 to 11b, 18 to 18b, XBs 26 to 26b, and the bus 7 are connected by a serial link.

  The CPU 10 includes a core 11, a core 14, and a synchronization control mechanism 17. The core 11 has STICK registers 12 and 13 for each strand, and the core 14 similarly has STICK registers 15 and 16 for each strand. The CPU 18 includes a core 19, a core 22, and a synchronization control mechanism 25. The core 19 has STICL registers 20 and 21, and the core 22 has STICK registers 223 and 24.

  In the following description, the CPUs 10a to 10b and the CPUs 18 to 18b execute the same processing as the CPU 10, and the description thereof is omitted. The XBs 26a to 26b execute the same processing as the XB 26, and a description thereof is omitted.

  Hereinafter, processing executed by the oscillator 3, the CD 4, the CPU 10, and the XB 26 included in the structural unit 2 will be described. Each of the CDs 4 to 4b is a clock device that supplies frequency-divided signals having the same phase and the same frequency to the CPUs 10 to 10b and 18 to 18b. Specifically, each of the CDs 4 to 4b is connected to an oscillator 3 to 3b that generates a reference signal having the same frequency. Each of the CDs 4 to 4b is connected to each other via a transmission path in which signal transmission characteristics such as the length of the connection line are managed, and any one CD is used as a master and is a reference with respect to other CDs. Send a signal.

  For example, when the CD 4 is connected to the other CDs 4a and 4b as a master, the CD 4 acquires the reference signal generated by the oscillator 3, and the acquired reference signal is 1 / N (N is a number greater than 1). Frequency) to a frequency-divided signal. Then, the CD 4 supplies the frequency-divided signal with the minimum skew to the other CDs 4a and 4b. Further, the CD 4 transmits the frequency-divided signal to the synchronization control mechanism 17 included in the CPU 10 and the synchronization control mechanism 25 included in the CPU 18 at a timing in consideration of the latency of the frequency-divided signal transmitted to the other CDs 4a and 4b. .

  On the other hand, when the CD 4a receives the frequency-divided signal from the CD 4, the CD 4a supplies the received signal to the synchronization control mechanism 17a included in the CPU 10a and the synchronization control mechanism 25a included in the CPU 18a. Similarly, when the CD4b receives a frequency-divided signal from the CD4, the received signal is supplied to the synchronization control mechanisms 17b and 25b. Each of the CDs 4 to 4b can also operate as a master, and an arbitrary CD can be used as a master depending on the configuration of the parallel computer system 1 or the like.

  As a method for dividing the reference signal by the CDs 4 to 4b, any dividing method can be applied. For example, the CDs 4 to 4b may divide the reference signal using a frequency divider such as a synchronous counter and generate the divided reference signal, that is, the divided signal. In this way, each of the CDs 4 to 4b supplies a frequency-divided signal having a period N times that of the reference signal to each of the synchronization control mechanisms 17 to 17b and 25 to 25b while adjusting the same phase.

  The CPU 10 is an arithmetic processing unit that executes processing assigned to itself. Further, the CPU 10 synchronizes the values stored in the STICK registers 12, 13, 15, and 16 with the STICK registers of other CPUs. And CPU10 performs a process synchronizing with other CPU10a, 10b, 18-18b by performing a process according to the value stored in STICK register 12,13,15,16.

  The synchronization control mechanism 17 receives the frequency-divided signal from the CD 4 via the path indicated by (K) in FIG. In addition, the synchronization control mechanism 17 generates a control signal obtained by multiplying the received divided signal by N times, and monitors the rising time of the divided signal or the elapsed time from the falling edge. When the application executed by the CPU 10 issues a synchronization request requesting synchronization with other processes executed by the CPUs 10a, 10b, and 18 to 18b, the application executed by the CPU 10 Execute the process.

  That is, the synchronization control mechanism 17 broadcasts a control packet storing a synchronization request to each of the CPUs 10 to 10b and 18 to 18b including itself via the path indicated by (M) in FIG. In addition, when the synchronization control mechanism 17 receives a control packet storing a synchronization request via the path indicated by (N) in FIG. 1, the synchronization control mechanism 17 executes the following processing. That is, the synchronization control mechanism 17 supplies a control signal to each of the STICK registers 12, 13, 15, and 16 via the path indicated by (O) in FIG. 1 according to the timing indicated by the frequency-divided signal received from the CD4.

  Hereinafter, the process executed by the CPU 10 will be described in detail. FIG. 2 is a schematic diagram illustrating an example of a CPU according to the first embodiment. 2 correspond to the paths indicated by (K), (M), (N), and (O) in FIG. 1. The paths indicated by (K), (M), (N), and (O) in FIG. . In the example illustrated in FIG. 2, the structural unit 2 includes an SCF (System Control Facility) 5 that is a system control unit that controls communication between the CPUs 10 and 18.

  In the example illustrated in FIG. 2, the CPU 10 includes a core 11, a core 14, an SX (Secondary Cache and External Access Unit) 101, and a serial IO (Input Output) 102. The core 11 has an IU (Instruction Control Unit) 110, a strand T111 having a STICK register 12, and a strand T112 having a STICK register 13. The serial IO is an input / output device that transmits and receives data to and from the XB 26 via the transaction layer, the data link layer, and the physical layer.

  Similarly, the core 14 has the STICK register 15 in the IU 140 and the strand T141, and the STICK register 16 in the strand T142. The SX 101 includes an arbiter 103 and a synchronization control mechanism 17. In the following description, the core 14 performs the same processing as the core 11 and will not be described in detail.

  When the IU 110 receives a read request for the STICK register 12 or the STICK register 13 from the arbiter 103, the IU 110 reads the value stored in the STICK register 12 or the STICK register 13. Then, the IU 110 transmits the read value to the arbiter 103. When the IO 110 receives a value to be written together with a register write request from the arbiter 103, the IO 110 writes the received value to the STICK register 12 or the STICK register 13.

  When the program executed by the CPU 10 requests reading of the value stored in the SITCK register 12 or the STICK register 13, the arbiter 103 transmits a register reading request to the IU 110. Further, when the program being executed by the CPU 10 requests an update of the value stored in the STICK register 12 or the STICK register 13, the arbiter 103 sends a write value to the IU 110 together with a register write request. Send.

  Similarly, the arbiter 103 transmits a write request and a read request to the STICK registers 13 and 16 to the IU 140. Further, the arbiter 103 issues a synchronization request when a program executed by the CPU 10 requests synchronization of processing executed by each of the CPUs 10 to 10b and 18 to 18b, and a route indicated by (L) in FIG. To the synchronization control mechanism 17.

  The synchronization control mechanism 17 receives a frequency-divided signal obtained by frequency-dividing the reference signal at a frequency of 1 / N from the CD 4 via a path indicated by (K) in FIG. Further, the synchronization control mechanism 17 generates a control signal obtained by multiplying the received divided signal by N times. Here, the control signal is a signal indicating the timing for counting up the values stored in the respective STICK registers 12, 13, 15, and 16. Further, the synchronization control mechanism 17 detects the rising or falling edge of the frequency-divided signal and monitors the elapsed time from the detected rising or falling edge.

  When the synchronization control mechanism 17 receives the synchronization request from the arbiter 103 and the monitored elapsed time becomes “XBC Timing”, the synchronization request is transmitted via the path indicated by (M) in FIG. Is transmitted to the Serial IO 102. In addition, the synchronization control mechanism 17 receives a synchronization request from the Serial IO 102 via the path indicated by (N) in FIG. 2 and when the monitored elapsed time becomes “REG-WR Timing”, The following processing is executed. That is, the synchronization control mechanism 17 counts up the value stored in the STICK register by supplying a control signal to each of the STICK registers 12, 13, 15 and 16 via the path indicated by (O) in FIG. I do. That is, the control signal is a signal for incrementing the value stored in each STICK register 12, 13, 15, 16.

  Further, the synchronization control mechanism 17 receives setting information indicating the elapsed time to be “SBC Timing” or the elapsed time to be “REG-WR Timing” via the path indicated by (P) in FIG. In such a case, the synchronization control mechanism 17 sets the elapsed time that becomes “SBC Timing” or the elapsed time that becomes “REG-WR Timing” to the elapsed time indicated by the received setting information.

  Further, the synchronization control mechanism 17 transfers the received setting information to the synchronization control mechanism 25 included in the CPU 18 via the route indicated by (Q) in FIG. Further, the synchronization control mechanism 17 transmits a signal indicating whether or not the control signal is supplied to each of the STICK registers 12, 13, 15, and 16 to the arbiter 103 via the path indicated by (R) in FIG. 2. .

  Similar to the CPU 10, the CPU 18 includes a core 19, a core 22, an SX 181, and a serial IO 182. The core 19, the core 22, the SX181, and the serial IO 182 included in the CPU 18 execute the same processing as the core 11, the core 14, SX101, and the serial IO 102 included in the CPU 10, respectively, and detailed description thereof is omitted.

  Next, an example of the synchronization control mechanism 17 will be described with reference to FIG. FIG. 3 is a diagram for explaining an example of the synchronization control mechanism according to the first embodiment. Note that the paths indicated by (K), (L), (M), (N), and (O) in FIG. 3 are (K), (L), (M), (N), and (O) in FIG. Corresponding to the route shown in FIG.

  In the example shown in FIG. 3, the synchronization control mechanism 17 includes a synchronizer 30, an up-edge detector 31, a phase counter 32, a setting register 33a, a comparator 33b, a setting register 34a, a comparator 34b, a control packet transmission unit 35, and a control packet reception. Part 36. The synchronization control mechanism 17 includes a control register 37, an n pulse generation unit 50, and an AND gate 60. Further, the control packet transmission unit 35 includes a transmission buffer 35a, an output circuit 35b, and an encoder 35c. The control packet receiving unit 36 includes a decoder 36a, a reception buffer 36b, and an update circuit 36c.

  The n pulse generation unit 50 includes an adder 51, a period register 52, a divider 53, a sub period register 54, a sub phase counter 55, a first comparator 56, a residual pulse counter 57, a second comparator 58, and an AND gate 59. Have.

  For example, the synchronization control mechanism 17 inputs the received frequency-divided signal to the synchronizer 30 when the frequency-divided signal generated by the CD 4 is received from the path indicated by (K) in FIG. The synchronizer 30 synchronizes the phase of the frequency-divided signal with the core clock of the CPU 10 and inputs the frequency-divided signal whose phase is synchronized with the core clock to the up-edge detector 31.

  The up edge detector 31 detects the rising edge of the frequency-divided signal input from the synchronizer 30. When the up edge detector 31 detects the rising edge of the divided signal, the up edge detector 31 inputs a pulse signal to the phase counter 32, the period register 52, the sub-phase counter 55, and the residual pulse counter 57.

  In the example shown in FIG. 3, a down edge detector that detects the falling edge of the divided signal may be installed instead of the up edge detector 31. Such a down-edge detector inputs a pulse signal to the phase counter 32, the period register 52, the sub-phase counter 55, and the residual pulse counter 57 when it detects the falling edge of the frequency-divided signal.

  The phase counter 32 monitors the core clock of the CPU 10 and counts the number of core clock cycles. The phase counter 32 resets the counted number of core clock cycles to “0” every time the up-edge detector 31 detects the up-edge of the divided signal. That is, the phase counter 32 measures the time elapsed since the up edge of the divided signal was detected by measuring how many cycles of the core clock have occurred since the up edge of the divided signal was detected.

  The setting register 33a is a register for setting “XBC Timing”. Specifically, the setting register 33a stores a value indicating the time from the up edge of the frequency-divided signal to “XBC Timing” in units of the core clock period. For example, the setting register 33a stores the value “5” when the timing when the time corresponding to the period of the core clock “5” has elapsed from the up edge of the divided signal is “XBC Timing”.

  The comparator 33b compares the number of core clock cycles counted by the phase counter 32 with the value stored in the setting register 33a. If the number of core clock cycles counted by the phase counter 32 matches the value stored in the setting register 33a, the comparator 33b sends an enable signal to the output circuit 35b of the control packet transmitter 35. Send. That is, when the predetermined time has elapsed from the up edge of the frequency-divided signal, the comparator 33b determines that it is “XBC Timing” and outputs an enable signal to the output circuit 35b.

  The setting register 34a is a register for setting “REG-WR Timing”. That is, as in the setting register 33a, the setting register 34a stores a value indicating the time from the up edge of the frequency-divided signal to “REG-WR Timing” in units of the core clock period. Similarly to the comparator 33b, the comparator 34b compares the number of core clock cycles counted by the phase counter 32 with the value stored in the setting register 34a.

  When the number of core clock cycles counted by the phase counter 32 matches the value stored in the setting register 34a, the comparator 33b sends an enable signal to the update circuit 36c included in the control packet receiver 36. Is output. That is, the comparator 34b determines that it is “REG-WR Timing” by the phase counter 32 when a predetermined time has elapsed from the up edge of the divided signal, and outputs an enable signal to the update circuit 36c. .

  Further, when the synchronization control mechanism 17 receives a synchronization request issued by an application from the arbiter 103 via (L) in FIG. 3, the synchronization control mechanism 17 stores the received synchronization request in the transmission buffer 35a. Here, the synchronization control mechanism 17 receives a synchronization request indicating “0” from the arbiter 103 when the application requests the CPU 10 to 10 b and 18 to 18 b to start the synchronization process. Further, the synchronization control mechanism 17 receives a synchronization request indicating “1” from the arbiter 103 when the application requests the CPUs 10 to 10 b and 18 to 18 b to stop the synchronization processing.

  Further, when receiving an enable signal from the comparator 33b, the output circuit 35b transmits the synchronization request stored in the transmission buffer 35a to the encoder 35c. When the encoder 35c receives the synchronization request from the output circuit 35b, the encoder 35c generates a control packet storing the synchronization request, and transmits the generated packet to the XB 26 via the path indicated by (M) in FIG. , Broadcast to each of the CPUs 10 to 10b and 18 to 18b. That is, when the synchronization request is issued and the time “XBC Timing” has elapsed since the rising of the frequency-divided signal, the control packet transmitter 35 broadcasts the control packet storing the synchronization request.

  Here, FIG. 4 is a diagram for explaining an example of a control packet storing a synchronization request. As shown in FIG. 4, the encoder 35c generates a packet storing STP (Start TLP character), SEQ # (Sequence Number), VCID (Virtual Channel ID), S (Packet Size), and DID (Destination ID). To do. The encode 35c includes PID (Partition ID), OPC (Operation Code), RQID (Request ID), W (Write Data), a plurality of CRC (Cyclic Redundancy Check) 3 to 0, END (End character), PAD ( A control packet storing Padding character is generated.

  Here, a code indicating the start of TLP is stored in STP. SEQ # stores the sequence number of the packet. In addition, information indicating the virtual channel ID is stored in the VICD. In S, the size of the packet is stored. In the DID, information indicating broadcast or the number of the destination CPU is stored. The PID stores a partition ID. Further, the request ID is stored in the RQID. Each CRC stores a signal for cyclic redundancy check. In END, a code indicating the end of TLP is stored. The PAD stores a code for filling in the fraction of the packet.

  Here, in W, information indicating the operation contents of STICK is stored. That is, when “1” is stored in the W area of the packet shown in FIG. 4, the control packet transmitter 35 requests the CPUs 12, 13, 15, and 16 to stop synchronization and stores “0”. In such a case, the CPU 12, 13, 15, 16 is requested to start synchronization.

  Returning to FIG. 3, the synchronization control mechanism 17 receives a packet broadcast from the XB 26 by each of the synchronization control mechanisms 17 to 17 b and 25 to 25 b including itself via the route indicated by (N) in FIG. 3. The received packet is transmitted to the decoder 36a. When receiving the packet, the decoder 36a decodes the received packet and stores the synchronization request stored in the packet in the reception buffer 36b.

  When the update circuit 36c receives the enable signal from the comparator 34b, the update circuit 36c stores the synchronization signal stored in the reception buffer 36b in the control register 37. That is, the update circuit 36 c stores “0” in the control register 37 when the application requests the CPU 10 to 10 b and 18 to 18 b to start the synchronization process. Further, the update circuit 36 c stores “1” in the control register 37 when the application requests the CPU 10 to 10 b and 18 to 18 b to stop the synchronization process. That is, when the control packet receiving unit 36 receives the control packet storing the synchronization request and the time elapsed from the rising edge of the divided signal becomes “REG-WR Timing”, the control signal is transmitted to the control register. 37.

  Here, the inverted signal of the value stored in the control register 37 is input to the AND gate 60. For this reason, when “0” is set in the control register 37, the AND gate 60 sends a control signal, which is an output from an n-pulse generator 50, which will be described later, via a path indicated by (O) in FIG. Output to the STICK registers 12, 13, 15, and 16. The AND gate 60 stops outputting the control signal when “1” is input to the control register 37. For this reason, the synchronization control mechanism 17 receives the control packet storing the synchronization request, and outputs and stops the control signal at the timing when the time elapsed from the rising edge of the divided signal becomes “REG-WR Timing”. It can be performed.

  Next, each part 51-59 which the n pulse generation part 50 has is demonstrated. The adder 51 calculates a value obtained by adding 1 to the number of core clock cycles counted by the phase counter 32, and transmits the calculated value to the period register 52. That is, the adder 51 transmits to the period register 52 a value indicating the phase of the divided signal by the number of core clock cycles.

  The period register 52 holds the value transmitted by the adder 51 at the timing when the pulse signal transmitted by the up-edge detector 31 is received. Here, the up-edge detector 31 transmits a pulse signal to the period register 31 when detecting the rising edge of the divided signal. For this reason, the period register 52 holds a value indicating the period of the frequency-divided signal by the number of periods of the core clock. For example, when the period of the divided signal is T times the core clock, the period register 52 holds the value “T”.

  The divider 53 calculates a value obtained by dividing the value held in the period register 52 by the division ratio used when the CD 4 generates the divided signal. For example, when the value “T” is held in the period register 52 and the CD 4 generates a divided signal obtained by multiplying the period of the reference signal by “N” times, the divider 53 quotient of the value “T / N”. And the remainder are output. That is, the divider 53 calculates the period of the reference signal that is the source of the divided signal by dividing the value indicating the period of the divided signal by the division ratio.

  The sub-period register 54 holds a value output from the divider 53 at the timing when an AND gate 59 described later outputs a control signal. That is, the subperiod register 54 holds a value indicating the cycle of the reference signal by the number of cycles of the core clock of the CPU 10. In other words, the subperiod register 54 holds a value indicating the cycle of the control signal. For example, when the cycle of the control signal is 8 times the cycle of the core clock of the CPU 10, a numerical value “8” is stored in the subperiod register 54.

  The sub-phase counter 55 is a counter that indicates the phase of the control signal by the number of core clock cycles of the CPU 10. Specifically, the sub-phase counter 55 increments its value in accordance with a pulse signal output from a second comparator 58 described later. When the sub-phase counter 55 receives a pulse signal from the up-edge detector 31, or when the value obtained by adding 1 to the count value becomes equal to the value of the sub-period register 54, the sub-phase counter 55 counts the counted value. Is reset to “0”. That is, the sub-phase counter 55 resets the value counted at the same cycle as the reference signal to “0”.

  The first comparator 56 is a comparator that outputs a signal “1” to the AND gate 59 when the value of the sub-phase counter 55 is “0”. That is, the first comparator outputs a pulse signal with the same cycle as the reference signal.

  The remaining pulse counter 57 counts the remaining number of pulse signals generated as control signals. Specifically, the residual pulse counter 57 is set every time a pulse signal is received from the up-edge detector 31 and a predetermined value “N” is set, and the control signal is output from the AND gate 59. Decrement the value. The residual pulse counter 57 holds its value when it has not received a pulse signal from the up-edge detector 31 and has not received a control signal. The second comparator 58 outputs a signal “1” when the value set in the residual pulse counter 57 is not “0”.

  The AND gate 59 outputs a signal “1” when the first comparator 56 and the second comparator 58 output a signal “1”. That is, the AND gate 59 is a signal that becomes “1” for one cycle of the core clock when the value of the residual pulse counter 57 is other than “0” and the value of the sub-phase counter 55 is “0”, that is, the control signal. Is output.

  When “0” is set in the control register 37, the AND gate 60 outputs a control signal to the STICK registers 12, 13, 15, and 16 through the path indicated by (O) in FIG.

  In other words, the n pulse generation unit 50 complements the frequency-divided signal received from the CD 4 and generates a control signal having the same frequency as the reference signal before frequency division. When the synchronization control mechanism 17 receives the synchronization request and the phase of the frequency-divided signal indicated by the phase counter 32 is “REG-WR Timing”, the synchronization control mechanism 17 generates the control signal generated by the n-pulse generation unit 50. Output to each CTICK register 12, 13, 15, 16. Therefore, the synchronization control mechanism 17 can appropriately synchronize the CPUs 11 to 18 even when the synchronization process is started in accordance with the timing indicated by the divided signal obtained by dividing the reference signal.

  The n pulse generation unit 40 can be realized with a relatively small number of FFs (Flip Flops), so that the cost is low and the mounting is easy. In addition, the n pulse generation unit 40 is configured by a digital logic circuit as compared with a PLL (Phase Locked Loop) that is an analog circuit. For this reason, the n-pulse generator 40 can operate normally without mistaking the number of pulses to be output, even for large frequency fluctuations that are difficult to follow with a PLL. Note that the n pulse generation unit 40 can also be implemented by a normal PLL.

  Hereinafter, an example of the synchronization control mechanism 17 will be described with reference to FIG. FIG. 5A is a diagram for explaining an example of the synchronization control mechanism according to the first embodiment. Note that the synchronization control mechanism 17 illustrated in FIG. 5A is merely an example, and the units 30 to 37 and 50 to 60 included in the synchronization control mechanism 17 can be replaced with circuits or the like having equivalent functions.

  In the example illustrated in FIG. 5A, the core clock of the CPU 10 is set as “core clk”, the synchronization signal supplied from the CD 4 is set as “stick sync”, and the synchronization request input from the application via the arbiter 103 is set as “stick ctl req”. Further, the control signal generated by the n pulse generation unit 50 is referred to as stick clk. Further, the routes shown in (K) to (O) in FIG. 5a are the same routes as (K) to (O) shown in FIG.

  In the example shown in FIG. 5a, the synchronizer 30 uses a plurality of D-type flip-flops (hereinafter referred to as D-FFs) and the core sync acquired via the core clk and the path shown in FIG. 5A (K). Align the phase with the signal. The up-edge detector 31 connects two D-FFs having core clk as a clock in series, and when the output of the preceding D-FF is “1” and the output of the subsequent D-FF is “0”, By outputting “1”, the up edge of stick sync is detected. In the following description, the output of the up-edge detector 31 is referred to as stick sync upload. The stick sync upload is input to the multiplexer S1 as a selection control signal. When the stick sync upload is “1”, the signal output from the adder 51 is looped back to the phase counter 32, and “0” is input otherwise.

  The phase counter 32 holds the signal from the multiplexer S1. That is, the value held in the phase counter 32 is reset to 0 when the stick sync upload is “1”, and is counted up by the adder 51 when the stick sync update is “0”.

  The period register 52 latches the output of the adder 51 when the stick sync upload is “1”. The divider 53 outputs a value obtained by dividing the output of the period register 52 by the value “N” stored in the config register # 0 set in advance. The comparator # 0 outputs “1” when the value of the rest pulse counter 57 is equal to or less than the remainder value output from the terminal R by the divider, and sets the value of the period register to “N + 1” in the subperiod register 54. Outputs a signal that sets the divided value. This is a signal for correcting the value stored in the sub-period register 54 when the value of the period register 52 is not divisible by N.

  The adder # 1 adds 1 to the quotient output from the terminal Q of the divider 53 and inputs the quotient to the multiplexer S2. The multiplexer S2 uses the output of the comparator # 0 as the selection control signal, the adder # 1, or The quotient output from the divider 53 is input to the subperiod register 54. That is, the multiplexer S2 corrects the value stored in the sub-period register 54 when the value of the period register 52 is not divisible by N using the output of the comparator # 0.

  The subperiod register 54 holds the output of the multiplexer S2. Comparator # 1 compares the value held in subperiod register 54 with the value obtained by adding 1 to the value held in subphase counter 55 by adder # 2. When the value held in the sub-period register 54 and the value obtained by adding 1 to the value held in the sub-phase counter 55 are the same value, the comparator # 1 calculates the logical value of the stick sync upload. "1" is output to the OR gate that takes the sum.

  The output of the or gate is a logical OR selection control signal of the multiplexer S3. The multiplexer S3 subtracts "0" when the stick sync upload is "1" or when the value held in the subperiod register 54 is the same as the value obtained by adding 1 to the value of the subphase counter 55. Output to the phase counter 55. In other cases, the multiplexer S 3 inputs the output of the adder # 2, that is, the value obtained by adding 1 to the value of the sub-phase counter 55 to the sub-phase counter 55. The sub-phase counter 55 indicates the output of the multiplexer S3, that is, the phase of the control signal as the number of core clock cycles of the CPU 10.

  The adder # 2 inputs a value obtained by adding 1 to the output of the sub-phase counter 55 to the comparator # 1 and the multiplexer S3. The residual pulse counter 57 is set to “N” by the comparator S0 when the stick sync upload = 1 and the value of the residual pulse counter 57 is 1, and is decremented by the subtractor # 0 when the regenerated stick clk is “1”. The In neither case, the stored pulse counter 57 holds the stored value.

  Here, as the selection control signal of the comparator S0, the rest pulse counter val generated by the core clk and the stick sync upload is input. This restart pulse counter val is a signal that prevents the output of a regenerated stick clk whose period is not fixed immediately after the start of the operation of the n-pulse generator 50.

  Further, the first comparator 56 outputs “1” to the AND gate 59 when the value of the sub-phase counter 55 is “0”, and the second comparator 58 when the value of the residual pulse counter 57 is not “0”. Then, “1” is input to the AND gate 59. The AND gate 59 inputs an output corresponding to the outputs of the first comparator 56 and the second comparator 58 to the D-FF, and outputs a regenerated stick clk. In other words, the regenerated stick clk is a signal that is “1” for one core clock when the value of the residual pulse counter 57 is not “0” and the value of the sub-phase counter 55 is “0”. is there. In this way, the n pulse generation unit 50 generates a regenerated stick clk, and transmits the generated regenerated stick clk to the STICK registers 12, 13, 15, and 16 via the path indicated by (O) in FIG.

  Next, processing for setting “XBC Timing” and “REG-WR Timing” will be described. For example, the synchronization control mechanism 17 acquires a Scan In signal from the SCF 5 via a path indicated by (P) in FIG. In the synchronization control mechanism 17, “N” is set in the config register # 0 included in the n pulse generation unit 50 by the Scan In signal.

  Further, the synchronization control mechanism 17 sets the value of the phase counter 32 to be “XBC Timing” in the setting register 33a and sets the value of the phase counter 32 to be “REG-WT Timing” in the setting register 34a by the Scan In signal. Set. In addition, the synchronization control mechanism 17 transmits a Scan Out signal to the synchronization control mechanism 25 via a path indicated by (Q) in FIG. Similarly, the synchronization control mechanism 25 sets “XBC Timing” and “REG-WR Timing” by the Scan In signal, and then transmits the Scan Out signal to the SCF 5.

  The comparator 33 outputs “1” when the value stored in the setting register 33 a matches the value of the phase counter 32. Further, the comparator 34 outputs “1” when the value stored in the setting register 34 a matches the value of the phase counter 32.

  Next, an example of the control packet transmitter 35 and the control packet receiver 36 will be described. In the example illustrated in FIG. 5A, when the control ctl req is “1”, the control packet is broadcast. For example, the control packet transmission unit 35 acquires stick ctl req from the arbiter 103 via (L) in FIG. 5a, and stores the value of stick ctl req in the transmission buffer 35a.

  When the comparator 33 determines that the value stored in the setting register 33a matches the value of the phase counter 32, the value stored in the transmission buffer 35a is output by the output circuit 35b that is a three-state buffer. It is transmitted to the encoder 35c. That is, the value stored in the transmission buffer 35 a is stored in the control packet when the comparator 33 outputs “1”, that is, “XBC Timing”, and passes through the path indicated by (M) in FIG. Thus, it is broadcast to each of the CPUs 10 to 10b and 18 to 18b.

  Further, the decoder 36a included in the control packet receiving unit 36 receives the control packet from the route indicated by (N) in FIG. 5a, and acquires information indicating the operation contents of the STICK stored in W among the received packets. . Specifically, the decoder 36a acquires “0” indicating the start of STICK synchronization or “1” indicating the stop of STICK synchronization. Then, the decoder 36a outputs a packet valid indicating that the packet has been received and “0” or “1” which is the packet data.

  The reception buffer 36b holds “0” or “1” that is packet data output from the decoder. The update circuit 36 c is a three-state buffer, and stores the value stored in the reception buffer 36 b in the control register 37 when the comparator 36 c outputs “1”, that is, at “REG-WR Timing”. . Here, the value stored in the control register 37 is inverted and input to the AND gate 60. Therefore, when “0” is stored in the control register 37, the stick clk is supplied to the STICK registers 12, 13, 15 and 16, and when “1” is stored in the control register 37, the stick clk is supplied. The supply of clk stops.

  The setting registers 33a and 34a and config register # 0 shown in FIG. 5a are set by a mechanism independent of STICK such as JTAG (Joint Test Action Group) or I2C (Inter Integrated Circuit). In the example shown in FIG. 5a, the scan signal is set by JTAG.

  Next, an example of a signal waveform output by the circuit shown in FIG. 5a and a value stored in each counter will be described with reference to FIGS. 5b to 5d. FIG. 5B is a diagram (1) for explaining an example of the operation of the synchronization control mechanism. FIG. 5c is a diagram (2) for explaining an example of the operation of the synchronization control mechanism. FIG. 5d is a diagram (3) for explaining an example of the operation of the synchronization control mechanism. 5b to 5d show waveforms obtained by dividing a signal waveform showing an example of the operation of the synchronization control mechanism into three. In the example shown in FIGS. 5b to 5d, the period of stick_sync is four times the period of stick_clk, which is the reference signal before CD4 to 4b divide, and N = 4. Note that the numerical values shown in FIGS. 5b to 5d are numerical values obtained by hexadecimal representation of the values counted by the respective counters and the values stored in the respective registers.

  As shown in FIG. 5b, when stick_sync having a period four times that of stick_clk is output, stick_sync_upedge is output, and the value of phase_counter is reset. Further, with stick_sync_upload as a trigger, a value obtained by adding “1” to the value immediately before phase_counter is stored in period_register 52, and “0” is stored in sub_phase_counter.

  Next, as shown in FIG. 5c, when the next stic_sync_upload is detected, the period_register stores "20" in hexadecimal ("32" in decimal), and stores "4" in hexadecimal in the rest_pulse_counter. Is done. Also, sub_period_counter stores “8” in hexadecimal. As a result, sub_phase_counter counts values from 0 to 7. As a result, regenerated_stick_clk is output with a period of eight core clocks.

  Further, as shown in FIG. 5d, the n pulse generating unit 50 continues to output regenerated_stick_clk having a period corresponding to eight core clocks. Then, the synchronization control mechanism 17 supplies the pulse signal generated by the n pulse generation unit 50 to each of the STICK registers 12, 13, 15 and 16 by “REG-WR Timing”.

  Next, the timing when each of the CPUs 10 to 10b and 18 to 18b starts synchronization will be described with reference to FIG. FIG. 6 is a time chart for explaining the timing for starting the count of the STICK register according to the first embodiment. In the example shown in FIG. 6, time advances from the left side to the right side in the figure. FIG. 6 shows the waveform of the reference signal, stick_sync, which is a frequency-divided signal acquired from the path shown in FIG. 5A, and the waveform of regenerated stick_clk generated by the n-pulse generator. Moreover, the waveform of the signal which flows through the path | route shown to (L), (M), (O) in FIG. 5a, and the value stored in each STICK register of each CPU10-10b and 18-18b are shown. In the example illustrated in FIG. 6, each of the CPUs 10 to 18 b receives a packet at the timing indicated by the dotted line, and the waveform of a signal received by each of the CPUs 10 to 18 b is simplified.

  For example, when the application transmits a synchronization request at the timing shown in (S) of FIG. 6 via the route shown in (L) of FIG. 5A, the control packet is sent to each of the CPUs 10 to 10b by the next “XBC_Timing”. , 18 to 18b. Here, “XBC_Timing” is the timing at which the number of core clock cycles stored in the setting register 33a has elapsed from the up edge of the stick_sync.

  Here, the CPUs 10 to 10b, 18 to 18b, the XBs 26 to 26b, and the bus 7 are connected by a serial link whose transmission latency is not constant. For this reason, as shown in FIG. 6, each CPU10a, 10b, 18-18b acquires a control packet at a respectively different timing. Also, the CPU 10 acquires the control packet broadcast by itself from the route indicated by (N) in FIG.

  After that, each of the CPUs 10 to 10b and 18 to 18b starts outputting regenerated_stick_clk with “REG-WR_Timing”. Here, “REG-WR_Timing” is the timing at which the number of core clock cycles stored in the setting register 34a has elapsed from the up edge of stick_sync.

  As described above, each of the CPUs 10 to 10b and 18 to 18b transmits the control packet and outputs the regenerated_stick_clk in accordance with “XBC_Timing” and “REG-WT_Timing” indicated by the frequency-divided signal obtained by dividing the reference signal. Here, stick_sync has a cycle that is N times longer than the reference signal. For this reason, “XBC_Timing” and “REG-WT_Timing” indicated by stick_sync have longer intervals than “XBC_Timing” and “REG-WT_Timing” indicated by the reference signal.

  As a result, each of the CPUs 10 to 10b and 18 to 18b can absorb the variation in transmission latency, and thus can start supplying the regenerated_stick_clk at the same time even when the control packets are received at different timings. As a result, each of the CPUs 10 to 10b and 18 to 18b can execute the processing in synchronization with the values stored in the respective STICK registers.

[Effect of Example 1]
As described above, the synchronization control mechanism 17 receives the frequency-divided signal obtained by frequency-dividing the reference signal at a low frequency. Further, when the CPU 11 synchronizes with each of the CPUs 12 to 18, the synchronization control mechanism 17 broadcasts a control packet storing a synchronization request destined for each of the CPUs 10 to 10 b and 18 to 18 b. When the synchronization control mechanism 17 receives a control packet transmitted by itself or another synchronization control mechanism 17a, 17b, or 25-25b, it starts synchronization control according to the timing indicated by the received divided signal. To do. For this reason, the synchronization control mechanism 17 can start synchronization at an appropriate timing even when the CPUs 10 to 10b and 18 to 18b are connected in a manner in which the transmission latency is not constant.

  That is, each of the CPUs 10 to 10b and 18 to 18b determines the timing of “REG-WR Timing” according to the frequency-divided signal having a longer period than the reference signal, and starts the synchronization control at the determined timing. For this reason, each of the CPUs 10 to 10b and 18 to 18b can secure tolerance against variations in the transmission latency of the synchronization request.

  Further, even when the CPUs 10 to 10b and 18 to 18b are connected by a connection method in which the simultaneous reachability of the synchronization request is not guaranteed as in the serial link method, the CPUs 11 to 18 are appropriately synchronized. Can be made. Further, each of the CPUs 10 to 10b and 18 to 18b can simultaneously transmit arbitrary control instructions to the respective CPUs 11 to 18 by using a mechanism for issuing a synchronization request to each of the CPUs 11 to 18. .

  Further, the synchronization control mechanism 17 includes an n pulse generation unit 50 that generates a control signal having the same frequency as the reference signal before frequency division based on the frequency division signal. When receiving the synchronization request, the synchronization control mechanism 17 supplies the control signal to each of the STICK registers 12, 13, 15, and 16 according to the timing indicated by the frequency-divided signal. For this reason, the synchronization control mechanism 17 can appropriately synchronize the processing. That is, since the synchronization control mechanism 17 appropriately synchronizes the values stored in the STICK registers 12, 13, 15, and 16, the CPUs 10 and 18 can be appropriately synchronized.

  Thus, the frequency-divided signal is input to each of the CPUs 10 to 10b and 18 to 18b with the minimum skew, and each of the synchronization control mechanisms 17 to 17b and 26 to 26b receives the control signal having the same frequency as the reference signal. Generate a control signal to each STICK register. For this reason, the parallel computer system 1 can appropriately synchronize the processes executed by the CPUs 10 to 10b and 18 to 18b.

  In Example 2 below, an example of a parallel computer system will be described with reference to FIG. FIG. 7 is a diagram for explaining an example of a parallel computer system according to the second embodiment. In the example illustrated in FIG. 7, the same reference numerals are given to components that exhibit the same functions as the units included in the parallel computer system 1 according to the first embodiment, and description thereof is omitted. As shown in FIG. 7, the parallel computer system 1a includes a plurality of structural units 2c to 2e and a plurality of buses 7 and 7a. The structural units 2d and 2e are assumed to perform the same function as the structural unit 2c, and the description thereof is omitted.

  The structural unit 2c includes an oscillator 3, a CD4, a CPU 10c, a CPU 18c, an XB 26c, and an XB 26d. The CPU 10c is connected to the bus 7 through the XB 26c, and the CPU 18c is connected to the bus 27 through the XB 26d. It is assumed that the CPU 10c, XB 26c, and bus 7 are connected by a serial link. The CPU 18c, XB 26d, and bus 7a are connected by a serial link.

  The bus 7 is a bus that connects the CPUs 10c, 10d, and 10e via the XBs 26c, 26e, and 26g. The bus 7a is a bus that connects the CPUs 18c, 18d, and 18e via the XBs 26d, 26f, and 26h. The CPUs 10c and 18c included in the structural unit 2c are connected to each other.

  That is, in the parallel computer system 1a, the two CPUs included in the structural units 2c to 2e are set as different groups, and the buses of different systems are connected to the groups. Of the CPUs in each group, CPUs 10c to 10e are connected via a bus 7, and CPUs 18c to 18e are connected via a bus 7a.

  Each of the CPUs 10c to 10e and 18c to 18e includes synchronization control mechanisms 17c to 17e and 25c to 25e. In the following description, the synchronization control mechanisms 17d, 17e, and 25c to 25e execute the same processing as the synchronization control mechanism 17c, and the description thereof is omitted. Moreover, about XB26c-26h, description is abbreviate | omitted as what demonstrates the function similar to XB26 which concerns on Example 1. FIG.

  When synchronizing the processing executed by each of the CPUs 10c to 10e and 18c to 18e, the synchronization control mechanism 17c stores a control packet in which the synchronization request is stored in the synchronization control mechanism 25c via the path indicated by (T) in FIG. Send. After that, the synchronization control mechanism 17c receives a control packet from the synchronization control mechanism 25c via the path indicated by (U) in FIG. 7, or a predetermined time has elapsed since the transmission of the control packet. In the case, the following processing is executed. That is, the synchronization control mechanism 17c broadcasts a control packet storing a synchronization request to each of the CPUs 10c to 10e connected to the bus 7.

  Here, when receiving the control packet storing the synchronization request from the synchronization control mechanism 17c, the synchronization control mechanism 25c executes the following processing. That is, the synchronization control mechanism 25c broadcasts the control packet to the CPUs 18c to 18e at the same time as the synchronization control mechanism 17c broadcasts the control packet to the CPUs 10c to 10e.

  Thereafter, each of the synchronization control mechanisms 17c to 17e and 25c to 25e receives the control packet transmitted by broadcast. And each synchronous control mechanism 17c-17e, 25c-25e is with respect to each STICK register which each CPU10c-10e, 18c-18e has by "REG-WR Timing" when predetermined time passed from the up edge of the frequency-divided signal. Supply a control signal.

  That is, the synchronization control mechanism 17c synchronizes with the other synchronization control mechanism 25c included in the same structural unit 2c as itself, and then broadcasts a control packet to each of the CPUs 10c to 10e connected to the bus 7. The synchronization control mechanism 17c also broadcasts the control packet to each of the CPUs 10c to 10e connected to the bus 7 even when the control packet is received from the synchronization control mechanism 25c.

  As described above, when the CPUs 10c to 10e and 18c to 18e are connected to different buses, the synchronization control mechanisms 17c to 17e and 25c to 25e have a CPU connected to a bus different from the CPU having itself. A synchronization request is transmitted to the synchronization control mechanism. Then, the synchronization control mechanisms 17c to 17e and 25c to 25e transmit a synchronization request to a CPU connected to the same bus as the CPU having itself. As described above, the synchronization control mechanisms 17c to 17e and 25c to 25e transmit the synchronization requests to the CPUs 10c to 10e and 18c to 18e step by step.

  Thereafter, each of the synchronization control mechanisms 17c to 17e and 25c to 25e is “REG-WR Timing” in which a predetermined time has elapsed from the up edge of the frequency-divided signal, and each of the CPUs 10c to 10e and 18c to 18e has its STICK register. Output sync signal. For this reason, the parallel computer system 1a can synchronize the processes executed by the CPUs 10c to 10e and 18c to 18e.

  FIG. 8 is a schematic diagram illustrating an example of a CPU according to the second embodiment. In addition, about the part which attaches | subjects the code | symbol same as each part shown in FIG. 2 among each part shown in FIG. 8, description is abbreviate | omitted as what performs the process similar to each part which concerns on Example 1. FIG. Note that the routes shown in (K) to (R) in FIG. 8 are the same as the routes shown in (K) to (R) in FIG.

  When the application issues a synchronization request via the arbiter 103, the synchronization control mechanism 17a sends the control packet storing the synchronization request via the path indicated by (T) in FIG. To 25c. In addition, the synchronization control mechanism 17a acquires a synchronization request issued by the application, and when the synchronization control mechanism 25c transmits a control packet, the synchronization control mechanism 25c transmits a control packet via the path (U) illustrated in FIG. Receive control packets.

  The synchronization control mechanism 17a is connected to the bus 7 when a certain period of time has elapsed since the transmission of the control packet or when the control packet transmitted by the synchronization control mechanism 25c is received. A control packet is broadcasted to the CPUs 10c to 10e. Thereafter, the synchronization control mechanism 17c supplies a control signal to each of the STICK registers 12, 13, 15 and 16 by “REG-WR Timing”, as in the synchronization control mechanism 17 according to the first embodiment.

  Next, the synchronization control mechanism 17c will be described with reference to FIG. FIG. 9 is a diagram for explaining the synchronization control mechanism according to the second embodiment. In addition, the path | route shown to (K)-(O) in FIG. 9 shall be the same path | route as (K)-(O) shown in FIG. Further, the routes shown in (T) and (U) in FIG. 9 are the routes shown in (T) and (U) in FIG. In addition, among the units illustrated in FIG. 9, those that perform the same processing as in FIG. 3 are denoted by the same reference numerals, and description thereof is omitted.

  As shown in FIG. 9, the synchronization control mechanism 17c includes a synchronizer 30, an up-edge detector 31, a phase counter 32, a comparator 33, a setting register 33a, a comparator 34, a setting register 34a, a control packet transmission unit 35d, and a control packet reception. It has a portion 36d. The synchronization control mechanism 17c includes a control register 37, a comparator 38, a setting register 38a, a delay circuit 39, an n pulse generation unit 50, and an AND gate 60.

  The control packet transmitter 35d includes a first transmission buffer 35e, an output circuit 35f, an encoder 35g, a second transmission buffer 35h, an output circuit 35i, and an encoder 35j. The control packet receiving unit 36d includes a decoder 36e, a first reception buffer 36f, a decoder 36g, a second reception buffer 36h, and an update circuit 36i.

  The first transmission buffer 35e and the second transmission buffer 35 are the same as the transmission buffer 35a shown in FIG. 3, the output circuit 35f and the output circuit 35i are the output circuit 35b, and the encoder 35g and the encoder 35j are the same as the encoder 35c. It shall function. The decoder 36e and the decoder 36g are assumed to perform the same functions as the decoder 36a, the first reception buffer 36f and the second reception buffer 36h, the reception buffer 36b, and the update circuit 36i.

  The output of the comparator 33 is input to the output circuit 35i, the output from the comparator 34 is input to the update circuit 36i, and the output of the comparator 38 is input to the output circuit 35f. Shall. Similarly to the first embodiment, the setting register 33a stores a numerical value indicating how many "XBC Timing" is the core clock period from the up edge of the divided signal. The setting register 34a stores a numerical value indicating how many "REG-WR Timing" are in the core clock period from the up edge of the divided signal.

  When the application executed by the CPU 10c issues a synchronization request, the synchronization control mechanism 17c receives the synchronization request from the path shown in (L) in FIG. 9 and controls the control packet storing the synchronization request synchronously. Transmit to mechanism 25c. In the following description, the timing at which the synchronization control mechanism 17c transmits a control packet to the synchronization control mechanism 25c connected to a bus different from itself is referred to as “SBC Timing”.

  In other words, the setting register 38a stores a value indicating how many "SBC Timing" are in units of the core clock period from the up edge of the frequency-divided signal. The comparator 38 outputs a signal to the output circuit 35f when the value of the phase counter 32 matches the value of the setting register 38a. When receiving a signal from the comparator 38, that is, when “SBC Timing” occurs, the output circuit 35f outputs the synchronization signal stored in the first transmission buffer 35e to the encoder 35g.

  The encoder 35g generates a control packet in which the received synchronization signal is stored, and transmits the generated control packet to the synchronization control mechanism 35c via the path indicated by (T) in FIG. The encoder 35g also transmits the generated packet to the delay circuit 39. The packet generated by the encoder 35g is the same packet as the packet generated by the encoder 35c according to the first embodiment. In addition, when receiving the control packet generated by the encoder 35g, the delay circuit 39 outputs the received control packet after a predetermined time has elapsed.

  Further, the synchronization control mechanism 17c transmits the control packet transmitted by the synchronization control mechanism 25c or the control packet output by the delay circuit 39 to the control packet receiving unit 36d via the path indicated by (U) in FIG. To do. Similar to the control packet receiver 36 according to the first embodiment, the control packet receiver 36d decodes the control packet by the decoder 36e and stores the synchronization request in the first reception buffer 36f. The control packet receiver 36 transmits the synchronization request stored in the first reception buffer 36 to the second transmission buffer 35h of the control packet transmitter 35d.

  When the second transmission buffer 35h receives the synchronization request and the output circuit 35i receives a signal from the comparator 33, that is, when it becomes “XBC Timing”, the control packet transmitter 35d Execute the process. That is, the control packet transmitter 35d uses the encoder 35j to generate a control packet that stores the synchronization request stored in the second transmission buffer 35h. Then, the control packet transmission unit 35d broadcasts the generated control packet to each of the CPUs 10c to 10e via the route indicated by (M) in FIG.

  When the synchronization control mechanism 17c receives a control packet broadcasted by itself from the XB 26c or a control packet broadcasted by the other synchronization control mechanisms 26e and 26g, the synchronization control mechanism 17c indicates a route indicated by (N) in FIG. A control packet is received via Also, the synchronization control mechanism 17c decodes the received control packet by the decoder 36g of the control packet receiving unit 36d, and stores the stored synchronization request in the second reception buffer 36h. Here, similarly to the update circuit 36c according to the first embodiment, the update circuit 36i receives the signal from the comparator 34, that is, when “REG-WR Timing” occurs, the second reception buffer 36h. Is stored in the control register 37.

  Next, an example of the synchronization control device 17c according to the second embodiment will be described with reference to FIG. FIG. 10 is a diagram for explaining an example of the synchronization control mechanism according to the second embodiment. Note that the synchronization control mechanism 17c illustrated in FIG. 10 is merely an example, and the units 30 to 38a and 50 to 60 included in the synchronization control mechanism 17c can be replaced with circuits or the like having equivalent functions.

  The synchronization control mechanism 17c shown in FIG. 10 adds a comparator 38, a setting register 38a, and a delay circuit 39 to the synchronization control mechanism 17 shown in FIG. 5a, and sends the control packet transmitter 35 to the control packet 35d. The receiving unit 36 is a control packet receiving unit 36d.

  As illustrated in FIG. 10, the first transmission buffer 35 e receives the stick ctl req issued by the application from the arbiter 103 via the path illustrated in (L) in FIG. 10, and holds the received stick ctl req. The output circuit 35f is a three-state buffer, and when the comparator 38 outputs “1”, the stick ctl req stored in the first transmission buffer 35e is transmitted to the encoder 35g. The encoder 35g generates a control packet storing stick ctl req, and transmits the generated control packet to the synchronization control mechanism 25c via the path indicated by (T) in FIG.

  Also, the decoder 36e of the control packet receiving unit 36d receives a control packet from the synchronization control mechanism 25c via the path shown in FIG. 10 (U), or receives a control packet delayed by the delay circuit 39. The following processing is executed. That is, the packet decoder 36e decodes the received packet and extracts a synchronization request. Then, the extracted synchronization request is stored in the first reception buffer 36f.

  The synchronization request stored in the first reception buffer 36f is transmitted to and stored in the second transmission buffer 35h included in the control packet transmission unit 35h. Next, similarly to the output circuit 35b, when the output circuit 35i receives a signal from the comparator 33 by "XBC Timing", the output circuit 35i outputs the synchronization request stored in the second transmission buffer 35h to the encoder 35j. Similarly to the encoder 35c, the encoder 35j generates a control packet storing a synchronization request, and broadcasts the generated control packet to each of the CPUs 10c to 10e via a path indicated by (M) in FIG.

  Further, when the control packet receiving unit 36d receives the control packet transmitted by broadcast via the route indicated by (N) in FIG. 10, the control packet receiving unit 36d performs the same processing as the control packet receiving unit 36 according to the first embodiment. Do. That is, the control packet receiving unit 36d extracts a synchronization request of “0” or “1” from the control packet using the decoder 36, and stores the extracted synchronization request in the second reception buffer 36h. Then, in the case of “REG-WR Timing”, the control packet receiving unit 36d starts or stops the supply of stick clk by holding the value stored in the second reception buffer 36 in the control register 37. I do.

  Next, a process in which the CPUs 10c to 10e and 18c to 18e are synchronized will be described with reference to FIG. FIG. 11 is a time chart for explaining the timing for starting the count of the STICK register according to the second embodiment. In the example shown in FIG. 11, it is assumed that time advances from the left side to the right side in the figure. Further, FIG. 11 shows the waveform of the reference signal, the waveform of the stick sync that is the frequency-divided signal obtained from the path indicated by (K) in FIG. 10, and the reflected stick clk generated by the n-pulse generator. Waveform is shown. Moreover, the waveform of the signal which flows through the path | route shown to (L), (U), (N), (O) in FIG. 10, and the value stored in each CPU10c-10e, 18c-18e are shown. In the example illustrated in FIG. 11, each of the CPUs 10 c to 18 e receives a packet at the timing indicated by the dotted line of the arrow, and the waveform of the signal received by each of the CPUs 10 c to 18 e is simplified.

  For example, when the application transmits a synchronization request at the timing shown in (S) of FIG. 11 via the route shown in (L) of FIG. 10, the synchronization control mechanism 17c performs the next “SBC Timing”. Then, a control packet is transmitted to the synchronization control mechanism 25c. Note that “SBC Timing” is the timing at which the number of core clock cycles stored in the setting register 38a has elapsed from the up edge of stick sync.

  Further, the synchronization control mechanism 17c, when receiving the control packet output from the delay circuit 39 or the control packet from the synchronization control mechanism 25c via (U) in FIG. 10, performs the control packet with “XBC Timing”. Is broadcasted to the CPUs 10c to 10e. Here, the synchronization control mechanism 25c broadcasts a control packet to the CPUs 18c to 18e using the same “XBC Timing” as the synchronization control mechanism 17c.

  Thereafter, each of the synchronization control mechanisms 17c to 17e and 25c to 25e receives the control packet transmitted by broadcast, and outputs stick-clk to the STICK register at the next “REG-WT Timing”. Therefore, the CPUs 10c to 10e and 18c to 18e can execute processing synchronously because the values stored in the STICK registers match.

[Effect of Example 2]
As described above, when the application issues a synchronization request, the synchronization control mechanism 17c transmits the synchronization request to the synchronization control mechanism 25c of the CPU 18c associated as the structural unit 2a. Then, when a predetermined time has elapsed since the transmission of the synchronization request or when the synchronization control mechanism 17c receives the synchronization request from the synchronization control mechanism 25c, the synchronization control mechanism 17c uses “XBC Timing” indicated by the frequency division signal, The control packet is broadcasted to the CPUs 10c to 10e.

  At this time, the synchronization control mechanism 25c broadcasts the control packet to the CPUs 18c to 18e at the same timing as the synchronization control mechanism 17c broadcasts the control packet. After that, the synchronization control mechanism 17c executes the following processing when a predetermined time has elapsed from the up edge of the frequency-divided signal after receiving the control packet transmitted by broadcast. To do. That is, the synchronization control mechanism 17c supplies a control signal to the STICK registers 12, 13, 15, 16 of the CPU 10c. As a result, the synchronization control mechanism 17c can appropriately synchronize the processes executed by the CPUs 10c to 10e and 18c to 18e even when the CPUs 10c to 10e and the CPUs 18c to 18e are connected to different buses.

  In addition, the synchronization control mechanisms 17c to 17e and 25c to 25e are connected to each of the CPUs 11 to 11 at a timing when “REG-WR Timing” has elapsed after a predetermined time has elapsed from the up edge of the frequency-divided signal having a longer period than the reference signal. A synchronization signal is output to 18 STICK registers. For this reason, the parallel computer system 1a performs processing executed by each of the CPUs 10c to 10e and 18c to 18e even when the CPUs 10c to 10e and 18c to 18e are connected by a method in which transmission latency such as a serial link is not constant. It can be synchronized properly.

  The synchronization control mechanism 17c can appropriately synchronize the processes executed by the CPUs 10c to 10e and 18c to 18e even when the parallel computer system 1a has a configuration other than the configuration shown in FIG. That is, the synchronization control mechanism 17c includes a plurality of CPUs connected to one bus as one set, and when the CPU in which the synchronization control mechanism 17c is installed is connected to a different set of CPUs, the connected CPUs A control packet storing a synchronization request is transmitted to

  The synchronization control mechanism 17c transmits a control packet to each set of CPUs, and then broadcasts the control packet to the set of CPUs on which the synchronization control mechanism 17c is installed. In this way, by transmitting the control packet to the CPUs 10c to 10e and 18c to 18e in multiple stages, the synchronization control mechanism 17c can appropriately synchronize the processes executed by the CPUs.

  In the following third embodiment, an example of the parallel computer system 1b will be described using a plurality of diagrams. FIG. 12 is a diagram for explaining an example of the parallel computer system according to the third embodiment. As shown in FIG. 12, the parallel computer system 1b is a system in which a plurality of structural units 2f to 2i, 5f to 5i, 6f to 6i, and 7f to 7i are connected in a two-dimensional mesh shape in the x-axis direction and the y-axis direction. It is.

  Specifically, the structural units 2f to 7f, 2g to 7g, 2h to 7h, 2i to 7i are connected in the x-axis direction, and the structural units 2f to 2i, 5f to 5i, 6f to 6i, and 7f to 7i are the y axis. Connected in the direction. Although omitted in FIG. 12, the parallel computer system 1b further includes a plurality of structural units connected in a mesh shape. In the following description, the process executed by the structural unit 2f will be described, and the other structural units 2g to 2i, 5f to 5i, 6f to 6i, and 7f to 7i execute the same process as the structural unit 2f. As an example, the description is omitted.

  FIG. 13 is a diagram for explaining a part of the parallel computer system according to the third embodiment. Note that FIG. 13 illustrates each part included in the structural units 2f, 5f, and 7f connected in the x-axis direction. Moreover, about what exhibits the same function as each part which concerns on Example 1, the same code | symbol is attached | subjected and the following description is abbreviate | omitted. In addition, the routes indicated by (K) and (O) in FIG. 13 are the same as the routes indicated by (K) and (O) in FIG.

  Similar to the structural unit 2 according to the first embodiment, the structural unit 2f includes the oscillator 3, the CD4, the CPU 10, the CPU 18, and the XB 26i. Further, the XB 26 i has a BC (broadcast) pipeline mechanism 61. As shown in FIG. 13 (V), the frequency-divided signal generated by the CD 4 is also supplied to the BC pipeline mechanism 61.

  The synchronization control mechanism 17f executes the same processing as that of the synchronization control mechanism 17 according to the first embodiment. Also, the synchronization control mechanism 17f transmits a control packet to the BC pipeline mechanism 61 at “XBC0 Timing” after a predetermined time has elapsed from the up edge of the frequency-divided signal. The BC pipeline mechanism 61 receives a control packet from the synchronization control mechanism 17f via the path indicated by (W) in FIG.

  Here, when the parallel computer system 1b is larger than a certain scale, each of the structural units 2f to 7i before the “REG-WR Timing” after a predetermined time elapses from the rising edge of the divided signal. In some cases, the control packet does not reach the CPU of the. Therefore, when the BC pipeline mechanism 61 receives a control packet from the CPU 10, the BC pipeline mechanism 61 broadcasts the control packet to the structural unit 2f having the CPU 10 and the structural units 5f to 7f connected in the x-axis direction. Send.

  In addition, the BC pipeline mechanism 61 controls when a certain time has elapsed since the control packet was broadcasted to the x-axis direction structural units 2f, 5f-7f, or when any of the structural units 5f-7f transmitted. When a packet is received, the following processing is executed. That is, the BC pipeline mechanism 51 broadcasts a control packet to the structural unit 2b having the CPU 11 and the structural units 2g to 2e connected in the y-axis direction.

  In addition, the BC pipeline mechanism 51 is configured to transmit a control packet to each of the structural units 2g to 2e connected to the structural unit 2f in the y-axis direction, or when the certain time has elapsed or from each of the structural units 2g to 2e. When a control packet is received, the following processing is executed. That is, the BC pipeline mechanism 51 transmits the received control packet to the synchronization control mechanism 17f via the path shown in FIG. In addition, the BC pipeline mechanism 51 transmits a control packet to the synchronization control mechanism 25. After that, when receiving the control packet from the BC pipeline mechanism 51, the synchronization control mechanisms 17f and 25f supply the synchronization signal to each STICK register by “REG-WR Timing” indicated by the divided signal.

  In the above example, the CPU 11 has the synchronization control mechanisms 17f and 25f, and the XB 26i has the BC pipeline mechanism 61. However, the functions of the BC pipeline mechanism 51 are integrated into the synchronization control mechanism 17f. Also good. Further, the function of the BC pipeline mechanism 61 may be provided at an arbitrary place other than the XB 26i.

  Next, the position where the BC pipeline mechanism 61 is installed will be described with reference to FIG. FIG. 14 is a schematic diagram illustrating an example of a component according to the third embodiment. 14 having the same functions as those shown in FIG. 2 are denoted by the same reference numerals, and the following description is omitted. Further, (K), (O), (V), (W), and (b) in FIG. 14 are the same as (K), (O), (V), (W), and (b) in FIG. It is a route. In the example shown in FIG. 14, (K), (L), (O) to (R) in FIG. 2 through the paths indicated by (K), (L), and (O) to (R) in FIG. 14. It is the same route as shown in FIG.

  That is, the synchronization control mechanism 17f transmits and receives signals similar to those of the synchronization control mechanism 17 according to the first embodiment via the paths indicated by (K), (L), and (O) to (R) in FIG. The following description is omitted. Further, the control packet transmitted by the synchronization control mechanism 17f with “XBC0 Timing” is input to the BC pipeline mechanism 61 via the path indicated by (W) in FIG. That is, “XBC0 Timing” is a timing at which the synchronization control mechanism 17 f stores the control packet in the BC pipeline mechanism 61.

  The BC pipeline mechanism 61 acquires the frequency-divided signal from the CD 4 via the path (V) in FIG. 14, and performs the same processing as that of the synchronous control mechanism 17 according to the first embodiment, thereby increasing the frequency-divided signal. The time elapsed from the edge is measured. Further, the BC pipeline mechanism 61 receives the control packet transmitted by the synchronization control mechanism 17f by “XBC0 Timing” via the path shown in FIG.

  Then, the BC pipeline mechanism 61 receives the control packet from the synchronization control mechanism 17f, and when it becomes “XBC1 Timing” that is a timing when a predetermined time has elapsed from the up edge of the frequency-divided signal, Execute the process. That is, the BC pipeline mechanism 61 broadcasts the received control packet to the structural units 2f, 5f to 7f via the path indicated by (X) in FIG. That is, “XBC1 Timing” is a timing at which a control packet is transmitted to structural units connected in the x-axis direction.

  Further, the BC pipeline mechanism 61 receives the control packet broadcasted to the structural units 2f, 5f to 7f via the route indicated by (Y) in FIG. In such a case, the BC pipeline mechanism 61 executes the following processing when “XBC2 Timing” is reached, which is a timing at which a predetermined time has elapsed from the up edge of the frequency-divided signal. That is, the BC pipeline mechanism 61 broadcasts a control packet to each of the structural units 2f to 2i connected in the y-axis direction via the path indicated by (Z) in FIG. That is, “XBC2 Timing” is a timing for transmitting a control packet to a structural unit connected in the y-axis direction.

  Further, when the BC pipeline mechanism 61 receives a control packet broadcast to each of the structural units 2f to 2i via the route shown in FIG. 14A, the BC pipeline mechanism 61 executes the following processing. That is, when the BC pipeline mechanism 61 becomes “SBC Timing”, which is a timing at which a predetermined time has elapsed from the up edge of the frequency-divided signal, the control packet is routed through the route shown in FIG. To the synchronization control mechanism 17f. That is, “SBC Timing” is a timing at which a control packet is transmitted to the synchronization control mechanism 17f.

  Next, the synchronization control mechanism 17f according to the third embodiment will be described with reference to FIG. FIG. 15 is a diagram for explaining the synchronization control mechanism according to the third embodiment. In addition, about each part which shows the function similar to each part shown in FIG. 3 among each part shown in FIG. 15, the same code | symbol is attached | subjected and description is abbreviate | omitted.

  The setting register 33b is a register for setting “XBC0 Timing”. Specifically, the setting register 33a stores a value indicating the time from the up edge of the frequency-divided signal to “XBC0 Timing” in units of the core clock period. In other words, the synchronization control mechanism 17f transmits the control packet to the BC pipeline mechanism 61 of the XB 26i with “XBC0 Timing” instead of “XBC Timing”. When the control packet is received from the BC pipeline mechanism 61 of the XB 26i, the synchronization control mechanism 17f uses the “REG-WR Timing” and the STICK registers 12, 13, 15, Supply of control signals to 16 is started.

  Next, processing executed by the BC pipeline mechanism 61 will be described with reference to FIG. FIG. 16 is a diagram for explaining the BC pipeline mechanism according to the third embodiment. In addition, the path | route shown to (X)-(Z), (a), (b) in FIG. 16 is a path | route shown to (X)-(Z), (a), (b) in FIG. And

  In the example shown in FIG. 16, the BC pipeline mechanism 61 includes a synchronizer 62, an up-edge detector 63, a phase counter 64, comparators 65 to 67, setting buffers 65a to 67a, a BC control packet receiving unit 68, and a BC control packet transmitting unit. 69. The BC control packet receiving unit 68 includes a plurality of decoders 68a, 68c, 68e, a first reception buffer 68b, a second reception buffer 68d, and a third reception buffer 68f. The BC control packet transmitter 69 includes a first transmission buffer 69a, a second transmission buffer 69d, a third transmission buffer 69g, a plurality of output circuits 69b, 69e, and 69h, and a plurality of encoders 69c, 69f, and 69i.

  Note that the synchronizer 62, the up edge detector 63, and the phase counter 64 shown in FIG. 16 perform the same processing as the synchronizer 30, the up edge detector 31, and the phase counter 32 shown in FIG. The setting buffer 65a stores a value indicating how many "XBC0 Timing" are set in the core clock cycle unit from the up edge of the divided signal.

  The setting buffer 66a stores a value indicating how many "XBC1 Timing" are set in the core clock period from the up edge of the divided signal. The setting buffer 67a stores a value indicating how many "XBC2 Timing" are set in the core clock cycle unit from the up edge of the divided signal.

  Further, the decoders 68a, 68b, and 68e included in the BC control packet receiving unit 68 exhibit the same functions as the decoder 36a shown in FIG. Further, the encoders 69c, 69f, and 69i included in the BC control packet transmission unit 69 exhibit the same functions as the encoder 35c shown in FIG. The first buffer 68a, the second buffer 68d, and the third buffer 68f are buffers that store synchronization requests acquired from the control packets by the decoders 68a, 68c, and 68e.

  The first transmission buffer 69a, the second transmission buffer 69a, and the third transmission buffer 69g receive and store the control packets stored in the first reception buffer 68b, the second reception buffer 68d, and the third reception buffer 68f, respectively. It is a buffer. When the output circuit 69b receives a signal from the comparator 65, the output circuit 69b outputs the synchronization request stored in the first transmission buffer 69a to the encoder 69c. When receiving a signal from the comparator 66, the output circuit 69e stores the synchronization signal stored in the second transmission buffer 69d in the encoder 69f. When receiving the signal from the comparator 65, the output circuit 69h stores the synchronization signal stored in the third transmission buffer 69g in the encoder 69i.

  Such a BC pipeline mechanism 61 receives a control packet from the synchronization control mechanism 17f via the path shown in FIG. Then, the BC pipeline mechanism 61 decodes the control packet and acquires the synchronization request stored in the control packet. Then, the BC pipeline mechanism 61 executes the following processing when the time elapsed from the up edge of the divided signal becomes “XBC1 Timing”. That is, the BC pipeline mechanism 61 generates a control packet storing the synchronization request, and transmits the control packet to the structural units 2f, 5f to 7f connected in the x-axis direction via the path indicated by (X) in FIG. Broadcast. Further, the BC pipeline mechanism 61 inputs a control packet to the delay circuit 39.

  Further, the BC pipeline mechanism 61 receives the control packet broadcasted in the x-axis direction via the route indicated by (Y) in FIG. 16, or the delay circuit 39 outputs the control packet. In the case, the following processing is executed. That is, the BC pipeline mechanism 61 acquires the synchronization request from the control packet, and executes the following processing when the time elapsed from the up edge of the frequency-divided signal becomes “XBC2 Timing”. That is, the BC pipeline mechanism 61 broadcasts the control packet storing the synchronization request to the constituent units 2f to 2i in the y-axis direction via the path indicated by (Z) in FIG. The BC pipeline mechanism 61 inputs the control packet to the delay circuit 39a.

  Further, the BC pipeline mechanism 61 meets the route shown in FIG. 16A and receives a control packet broadcast to the constituent units 2f to 2i in the y-axis direction, or is controlled by the delay circuit 39a. When a packet is output, the following processing is executed. That is, the BC pipeline mechanism 61 acquires the synchronization request from the control packet, and executes the following processing when the time elapsed from the up edge of the frequency-divided signal becomes “SBC Timing”. That is, the BC pipeline mechanism 61 outputs the control packet storing the synchronization request to the synchronization control mechanism 17f via the path shown in FIG.

  Thereafter, the synchronization control mechanism 17f that has received the synchronization request from the BC pipeline mechanism 51 generates the n pulse generation unit 40 when the time elapsed from the edge of the frequency division signal becomes “REG-WR Timing”. The synchronized signal is output to each STICK register.

  FIG. 17 is a diagram for explaining an example of the BC pipeline mechanism. As shown in FIG. 17, the setting registers 65a, 66a, and 67a store values indicating timings of “XBC1 Timing”, “XBC2 Timing”, and “SBC Timing”, respectively, according to the Scan in signal. .

  The comparator 65 compares the value stored in the setting register 65a with the value of the phase counter 64, and outputs a signal to the output circuit 69b that is a three-state buffer when the values match. The comparator 66 compares the value stored in the setting register 66a with the value of the phase counter 64, and outputs a signal to the output circuit 69e that is a three-state buffer when the values match. The comparator 67 compares the value stored in the setting register 67a with the value of the phase counter 64, and outputs a signal to the output circuit 69h that is a three-state buffer when the values match. As described above, the BC pipeline mechanism 61 can be realized by the same components as the synchronous control mechanism 17 shown in FIG. 5A, and is low in cost and easy to mount.

  Next, processing for synchronizing CPUs included in the parallel computer system 1b will be described with reference to FIGS. FIG. 18 is a time chart for explaining the timing at which the synchronization control mechanism transmits a control packet to the BC pipeline mechanism. 18 shows a reference signal, a stick sync, a regenerated stick clk, a signal flowing through the path shown in (L) in FIG. 15, and a signal flowing through the paths shown in (W), (X), and (Y) in FIG. Indicates. FIG. 18 shows the timing at which each BC pipeline mechanism 61-61b receives a control packet. In the example shown in FIG. 18, it is assumed that each CPU 10 and BC pipeline mechanisms 61-61b receive a packet at the timing indicated by the dotted line of the arrow, and the waveforms of signals received by each CPU 10 and BC pipeline mechanisms 61-61b. About simplified.

  In the example illustrated in FIG. 18, when the synchronization control mechanism 17 f included in the CPU 10 receives the synchronization request from the application at the timing illustrated in FIG. 18C, the control packet storing the synchronization request is “XBC0 Timing”. Then, the data is transmitted to the BC pipeline mechanism 61. For this reason, the BC pipeline mechanism 61 receives the control packet at the timing shown in FIG. Next, as shown in FIG. 18E, the BC pipeline mechanism 61 executes the following processing when the time elapsed from the up edge of the stck sync reaches “XBC1 Timing”.

  That is, the BC pipeline mechanism 61 broadcasts the control packet to the BC pipeline mechanisms 61 to 61b included in the structural units 2f and 5f to 7f in the x-axis direction. Thereafter, the BC pipeline mechanism 61 receives the control packet at the timing shown in FIG.

  FIG. 19 is a time chart for explaining the timing at which the BC pipeline mechanism broadcasts a control packet. In the example shown in FIG. 19, the reference signal, a stick sync acquired from the route shown in FIG. 16 (V), a regenerated stick clk, a signal flowing through the route shown in FIG. 16 (Z), and the signal shown in FIG. Indicates a signal that can be routed. In the example illustrated in FIG. 19, the BC pipeline mechanisms 61 to 61b, the CPUs 10 to 10b, and the CPUs 18 to 18b receive the control packets.

  In the example illustrated in FIG. 19, the BC pipeline mechanism 61 c included in the structural unit 2 g, the CPUs 10 f to 10 h and the CPUs 18 f to 18 h included in the structural unit 2 g are illustrated as receiving timings. In the example illustrated in FIG. 19, the BC pipeline mechanism 61f, the CPUs 10i to 10k, and the CPUs 18i to 18k included in the structural unit 7i receive the control packets. In the example shown in FIG. 19, the CPUs 10 to 10 k and the BC pipeline mechanisms 61 to 61 f receive the packets at the timing indicated by the dotted lines, and the CPUs 10 to 10 k and the BC pipeline mechanisms 61 are received. The waveform of the signal received by ~ 61f is simplified.

  In the example illustrated in FIG. 19, when the time elapsed from the edge of the frequency-divided signal becomes “XBC2 Timing”, the BC pipeline mechanisms 61 to 61 b, as illustrated in FIG. A control packet is transmitted to the constituent unit in the y-axis direction via the path shown in the middle (Z). Then, the control packet is distributed to each of the structural units 2f to 2i and 5f to 7i included in the parallel computer system 1b. Thereafter, each of the BC pipeline mechanisms 61 to 61f is “SBC Timing”, and, as shown in (h) of FIG. 19, the control packet is sent to each of the structural units 2f to 2 through the path shown in FIG. It transmits to CPU10-10k, 18-18k which 2i, 5f-7i has.

  FIG. 20 is a time chart for explaining the timing at which the synchronization control mechanism outputs a synchronization signal to the STICK register. FIG. 20 shows a reference signal, a stick sync acquired from the path indicated by (K) in FIG. 15, a regenerated stick slk to be generated, and a stick slk output from the path indicated by (O) in FIG. 15. FIG. 20 shows values stored in the STICK registers of the CPUs 10 to 10k and 18 to 18k. In the example shown in FIG. 20, it is assumed that each of the CPUs 10 to 10k and 18 to 18k has already received the control packet.

  As illustrated in FIG. 20, each synchronization control mechanism included in the parallel computer system 1 b stores the synchronization request stored in the control packet in the control register 37 by “REG WR Timing”. Therefore, each of the CPUs 10 to 10k and 18 to 18k can start the input of the regenerated stick clk to the STICK register at the same time, so that the values input to the STICK registers can be aligned. As a result, the parallel computer system 1b can synchronize the processes executed by the CPUs 10 to 10k and 18 to 18k.

[Effect of Example 3]
As described above, the synchronization control mechanism 17f and the BC pipeline mechanism 61 broadcast the synchronization request to the structural units 5f to 7f connected to the structural unit 2f in the x-axis direction, and then connected to the y-axis direction. The synchronization request is broadcasted to the constituent units 2g to 2i. When the synchronization control mechanism 17f receives the broadcast-synchronized synchronization request and the frequency division signal indicates “REG-WR Timing” for updating the STICK register, each of the CPUs 10 to 10b, 18 to The synchronization signal is started to be output to the STICK register of 18b. For this reason, the parallel computer system 1b can appropriately synchronize the processes executed by the CPUs 10 to 10k and 18 to 18k.

  That is, in the parallel computer system 1b, when there are a large number of CPUs to be synchronized and the synchronization signal cannot be broadcasted to each CPU within a time shorter than the period in which the frequency-divided signal indicates “REG-WR Timing”, it is sent to each CPU. In contrast, a synchronization request is transmitted step by step. The parallel computer system 1b then synchronizes the processing executed by each CPU when the synchronization request is distributed to each CPU and the divided signal becomes “REG-WR Timing”. For this reason, the parallel computer system 1b appropriately performs the processing executed by each CPU even when the synchronization signal cannot be broadcast to each CPU within a time shorter than the period in which the frequency-divided signal indicates “REG-WR Timing”. Can be synchronized.

  Further, the synchronization control mechanism 17f starts outputting the synchronization signal according to the timing indicated by the frequency-divided signal having a long cycle obtained by frequency-dividing the reference signal. For this reason, the parallel computer system 1b performs processing executed by the CPUs 10 to 10k and 18 to 18k even when the CPUs 10 to 10k and 18 to 18k are connected by a method such as a serial link in which the transmission latency is not constant. Can be synchronized.

  Although the embodiments of the present invention have been described so far, the embodiments may be implemented in various different forms other than the embodiments described above. Accordingly, another embodiment included in the present invention will be described below as a fourth embodiment.

(1) Constituent Units of Parallel Computer System The parallel computer system 1 described above has constituent units 2 to 2b connected by a serial bus. The parallel computer system 1a has structural units 2c to 5e connected by a serial bus. However, the embodiment is not limited to this, and the parallel computer system 1 and the parallel computer system 1a may have any number of constituent units.

  Each of the structural units 2c to 2e has two CPUs. However, the embodiment is not limited to this, and each of the structural units 2c to 2e may have an arbitrary number of CPUs. In such a case, the synchronization control mechanism 17c transmits a synchronization request to each CPU included in the same structural unit as the CPU 10c, and then another structural unit 2c via the bus to which each CPU is connected. The synchronization request is transmitted to each CPU of .about.2e.

  The parallel computer system 1b has two CPUs, and has a plurality of structural units 2f to 2i and 5f to 7i connected in a mesh shape in the x-axis direction and the y-axis direction. However, the embodiment is not limited to this. For example, the parallel computer system 1b may have a plurality of structural units connected in three dimensions in the x-axis direction, the y-axis direction, and the z-axis direction. In the case of having such a plurality of structural units, each synchronization control mechanism and XB execute the following processing. That is, when a synchronization request is transmitted in a multistage manner to the constituent units in each axial direction, and the synchronization request is transmitted to all the constituent units, the synchronization signal is sent to the STICK counter of each CPU according to the timing indicated by the divided signal. Is output.

  The parallel computer system 1b may include structural units 2f to 2i and 5f to 7i each having an arbitrary number of CPUs. For example, the parallel computer system 1b may include structural units 2f to 2i and 5f to 7i each having one CPU. That is, the parallel computer system 1b may have a plurality of CPUs connected in the x-axis direction and the y-axis direction. In such a case, each synchronization control mechanism transmits a synchronization request to the CPU connected in the x-axis direction, and then transmits the synchronization request to the CPU connected in the y-axis direction. Each synchronization control mechanism then outputs a synchronization signal to the STICK register of each CPU at the timing indicated by the divided signal.

  As described above, the parallel computer system transmits a synchronization request to the synchronization control device of each CPU included in the parallel computer system, and thereafter, starts processing executed by each CPU at the timing indicated by the divided signal. For this reason, the parallel computer system can properly synchronize the processes executed by the CPUs even when the CPUs are connected by a method such as a serial link where the transmission latency is not constant.

(2) Transmission destination of synchronization request The parallel computer system 1b described above broadcasts a synchronization request to the constituent units connected in the x-axis direction, and then broadcasts the synchronization request to the constituent units connected in the y-axis direction. It was. However, the embodiment is not limited to this. For example, the parallel computer system 1b does not transmit the synchronization request to the structural units connected in the respective axial directions at once, but transmits the synchronous request to the structural units connected in the respective axial directions. May be executed in multiple stages.

  That is, the parallel computer system uses an arbitrary method to transmit a synchronization request to each CPU, and then, based on the timing indicated by the divided signal having a cycle longer than the reference signal, What is necessary is just to start a synchronization. The parallel computer system can design an appropriate route for sending a synchronization request to each CPU according to various conditions such as the scale of the system and the latency of the transmission route.

1, 1a, 1b Parallel computer system 2-2i, 5f-5i, 6f-6i, 7f-7i Configuration unit 3 Oscillator 4 CD
7, 7a bus 10-10k, 18-18k CPU
26-26k XB
50 n pulse generator 61-61b BC pipeline mechanism

Claims (9)

In a synchronous control device included in an arithmetic processing device connected to another arithmetic processing device via a data transfer device, which is connected to a clock frequency divider that divides the input clock signal by 1 / N,
A detection unit for detecting a rising edge or a falling edge of the divided clock signal divided by the clock divider;
Monitoring the elapsed time from the rise or fall of the frequency-divided clock signal detected by the detection unit, and transmitting a synchronization request to the data transfer device; and a synchronization register included in the arithmetic processing unit. A monitoring unit for monitoring the second timing to be updated;
A clock generator for generating a control clock obtained by multiplying the divided clock signal divided by the clock divider by N times;
A synchronization request receiving unit that receives a synchronization request from the other arithmetic processing unit via the data transfer device;
A clock that outputs a control clock generated by the clock generation unit when the synchronization request reception unit receives a synchronization request from the other arithmetic processing unit and the monitoring unit detects the second timing. A control unit;
A synchronization control device comprising: a synchronization request transmission unit configured to transmit a synchronization request to the other arithmetic processing device via the data transfer device when the monitoring unit detects the first timing. In the synchronous control device,
The monitoring unit further monitors the period of the divided clock signal,
The clock generator is
A first cycle holding circuit for holding a cycle of the divided clock signal detected by the monitoring unit;
A second period holding circuit that holds a period of 1 / N of the period of the divided clock;
A division circuit that divides the period of the divided clock held in the first period holding circuit by N and holds a period of 1 / N of the period of the divided clock in the second period holding circuit;
A first counting circuit for subtracting a value to be held from N by 1;
An N detection circuit for detecting that the value held by the first counting circuit is other than 0;
A second counting circuit that increments a value to be held by 1 from 0 based on a period of 1 / N of the period of the divided clock;
A zero detection circuit for detecting that the value held by the second counting circuit is 0;
2. The synchronous control device according to claim 1, further comprising a logical product circuit that outputs a logical product of the zero detection circuit and the one detection circuit. The monitoring unit
An elapsed time monitoring unit that monitors an elapsed time from the rise or fall of the divided clock signal detected by the detection unit;
A first setting register for storing a time value for detecting the first timing;
A second setting register for storing a time value for detecting the second timing;
If the value stored in the first setting register matches the time monitored by the elapsed time monitoring unit, the synchronization request transmitting unit is notified that the first timing has been detected, and the second setting A timing detection unit that notifies the clock control unit that the second timing has been detected when the value stored in the register matches the time monitored by the elapsed time monitoring unit. The synchronous control device according to claim 1 or 2. The monitoring unit further monitors a third timing for transmitting a synchronization request to another arithmetic processing device associated with the arithmetic processing device and connected to a different path from the arithmetic processing device,
The synchronization request transmission unit transmits a synchronization request to the other arithmetic processing unit when the monitoring unit detects the third timing, and a predetermined time has elapsed after the transmission of the synchronization request and the monitoring When the unit detects the first timing, or when receiving a synchronization request from the other arithmetic processing unit and the monitoring unit detects the first timing, The synchronization control device according to claim 1, wherein the synchronization request is transmitted to the other arithmetic processing device. When a plurality of arithmetic processing devices are connected in a two-dimensional mesh shape in the x-axis direction and the y-axis direction,
The monitoring unit transmits a synchronization request to another arithmetic processing device connected in the x-axis direction, and a fourth timing transmits a synchronization request to another arithmetic processing device connected in the y-axis direction. To further monitor timing,
When the monitoring unit detects the fourth timing, the synchronization request transmission unit transmits a synchronization request to another arithmetic processing device connected in the x-axis direction. When time elapses and the monitoring unit detects the fifth timing, or when a synchronization request is received from another arithmetic processing device connected in the x-axis direction and the monitoring unit receives the fifth timing Is detected, the synchronization request is transmitted to the other arithmetic processing devices connected in the y-axis direction via the data transfer device,
The clock control unit has passed a predetermined time after the synchronization request receiving unit has transmitted a synchronization request to the arithmetic processing unit connected in the y-axis direction, and the monitoring unit has detected the second timing. The control clock generated by the clock generator when receiving a synchronization request from another arithmetic processing unit connected in the y-axis direction and when the monitoring unit detects the second timing. The synchronous control device according to claim 1, wherein the synchronous control device outputs the synchronous control device. The structural units having a plurality of the arithmetic processing units are connected in a two-dimensional mesh shape in the x-axis direction and the y-axis direction,
The synchronization request transmission unit transmits a synchronization request to another structural unit connected in the x-axis direction when the monitoring unit detects the fourth timing, and then a predetermined time has elapsed. And when the monitoring unit detects the fifth timing, or receives a synchronization request from another structural unit connected in the x-axis direction, and the monitoring unit receives the fifth timing. Is detected, the synchronization request is transmitted to the other structural unit connected in the y-axis direction via the data transfer device,
The clock controller receives a synchronization request from the synchronization request receiver to the constituent unit connected in the y-axis direction, and the monitoring unit detects the second timing. Control generated by the clock generator when receiving a synchronization request from another structural unit connected in the y-axis direction and when the monitoring unit detects the second timing 6. The synchronization control apparatus according to claim 5, wherein a clock is output. In an arithmetic processing device connected to another arithmetic processing device via a data transfer device,
An arithmetic processing unit for performing arithmetic processing;
A clock controller that receives the divided clock signal obtained by dividing the input clock signal by 1 / N by a clock divider and includes a synchronization control device that performs synchronization control between the arithmetic processing device and the other arithmetic processing device;
The synchronization control device includes:
A detector for detecting the rising or falling edge of the input divided clock signal;
A first timing for monitoring the elapsed time from the rise or fall of the divided clock signal detected by the detection unit, and transmitting a synchronization request; and a second timing for updating a synchronization register included in the arithmetic processing unit. A monitoring unit for monitoring
A clock generator for generating a control clock obtained by multiplying the divided clock signal divided by the clock divider by N times;
A synchronization request receiving unit that receives a synchronization request from the other arithmetic processing unit via the data transfer device;
When the synchronization request receiving unit receives a synchronization request from the other arithmetic processing unit and the monitoring unit detects the second timing, the synchronization register is updated, and the clock generation unit generates A clock control unit for outputting a control clock to the arithmetic processing unit;
A synchronization request transmission unit that transmits a synchronization request to the other arithmetic processing unit via the data transfer device when the monitoring unit detects the first timing;
An arithmetic processing apparatus comprising: A parallel computer system having a clock divider that divides an input clock signal by 1 / N and a plurality of arithmetic processing devices connected to another arithmetic processing device via a data transfer device,
The arithmetic processing device has a synchronous control device for executing processing in synchronization with the other arithmetic processing device,
The synchronization control device includes:
A detection unit for detecting a rising edge or a falling edge of the divided clock signal divided by the clock divider;
Monitoring the elapsed time from the rise or fall of the frequency-divided clock signal detected by the detection unit, and transmitting a synchronization request to the data transfer device; and a synchronization register included in the arithmetic processing unit. A monitoring unit for monitoring the second timing to be updated;
A clock generator for generating a control clock obtained by multiplying the divided clock signal divided by the clock divider by N times;
A synchronization request receiving unit that receives a synchronization request from the other arithmetic processing unit via the data transfer device;
A clock that outputs a control clock generated by the clock generation unit when the synchronization request reception unit receives a synchronization request from the other arithmetic processing unit and the monitoring unit detects the second timing. A control unit;
A parallel computer system comprising: a synchronization request transmission unit configured to transmit a synchronization request to the other arithmetic processing unit via the data transfer device when the monitoring unit detects the first timing. . A control method executed by a synchronous control device included in an arithmetic processing device connected to another arithmetic processing device via a data transfer device, which is connected to a clock frequency divider that divides an input clock signal by 1 / N. ,
Detecting the rising or falling edge of the divided clock signal divided by the clock divider;
Monitoring the elapsed time from the rising or falling edge of the detected frequency-divided clock signal, a first timing for transmitting a synchronization request to the data transfer device, and a updating of a synchronization register included in the arithmetic processing unit. 2 timing is monitored,
Generating a control clock obtained by multiplying the frequency-divided clock signal by N times;
Receives a synchronization request from the other arithmetic processing device via the data transfer device,
When receiving a synchronization request from the other arithmetic processing unit and detecting the second timing, the generated control clock is output,
A control method for a synchronization control device, comprising: executing processing for transmitting a synchronization request to the other arithmetic processing device via the data transfer device when the first timing is detected.

Images