JPWO2012133366A1 - Parallel processing apparatus and parallel processing system - Google Patents

Abstract

A parallel processing device that prevents a response from being delayed due to temporary concentration of access is provided. A parallel processing apparatus connected to a network, wherein a plurality of CPUs, means for receiving data from the network, and means for allocating tasks related to the received data to waiting CPUs among the plurality of CPUs And a parallel processing device.

Description

  The present invention relates to a parallel processing device and a parallel processing system.

  Conventionally, as a system that intensively processes predetermined processes that occur randomly on the network, only the identification information is stored in the boarding medium, and the boarding information that is necessary for the entrance process, the exit process, etc. is the identification information. A station affairs system that is associated and managed centrally by a host server has been proposed (see Patent Document 1).

JP 2011-8588 A

  However, in the conventional system, the server response may be delayed due to temporary concentration of access. If the gate is closed after passing through the ticket gate at the usual speed, it will not take much time. There was a problem that the processing did not proceed as expected by the user because the stock buying and selling order that had been thought was not processed easily.

  Accordingly, an object of the present invention is to provide a parallel processing device and a parallel processing system that prevent a response from being delayed due to temporary concentration of access.

  According to the present invention, the above problem is solved by the following means.

  The present invention is a parallel processing apparatus connected to a network, wherein a plurality of CPUs, a means for receiving data from the network, and a task related to the received data are in a waiting state among the plurality of CPUs. And a means for distributing to a CPU.

  The present invention further includes a memory and means for assigning an area in the address space of the memory to a CPU that assigns the task each time the task is assigned. Device.

  Further, the present invention is characterized by comprising a bus for connecting the plurality of CPUs and the memory, and means for connecting and disconnecting the bus so that one CPU is connected to the memory. The parallel processing device described above.

  In addition, the present invention is characterized by comprising means for transmitting, when data on the memory is rewritten, the rewritten data to another parallel processing device connected to the network. This is a parallel processing device.

  Further, the present invention is the parallel processing apparatus described above, wherein the parallel processing apparatus is connected to a ticket gate installed at a station via the network.

  The present invention is the parallel processing apparatus described above, wherein the parallel processing apparatus is connected to a stock trading terminal via the network.

  The present invention is also a parallel processing system in which the parallel processing device and a plurality of terminal devices are connected by a network.

  ADVANTAGE OF THE INVENTION According to this invention, the parallel processing apparatus and parallel processing system which prevent that a response becomes slow by temporary concentration of access can be provided.

It is a figure which shows the parallel processing system which concerns on embodiment of this invention. It is a figure which shows the structural example of the parallel processing apparatus which concerns on embodiment of this invention. It is a figure which shows the structural example of the table used by embodiment of this invention. It is a figure which shows the operation example of the parallel processing apparatus which concerns on embodiment of this invention. It is a figure which compares the process by Example 1 of this invention with the process of Comparative Examples 1 and 2, (a) is a figure which shows the process which concerns on Example 1 of this invention, (b) is a comparison. It is a figure which shows the process which concerns on Example 1, (c) is a figure which shows the process which concerns on the comparative example 2. FIG.

  EMBODIMENT OF THE INVENTION Below, the form for implementing this invention is demonstrated, referring attached drawing.

  FIG. 1 is a diagram showing a parallel processing system according to an embodiment of the present invention.

  As shown in FIG. 1, a parallel processing system 1 according to an embodiment of the present invention is a computer system in which a plurality of parallel processing devices 10 and a plurality of terminal devices 20 are connected via a network 30.

  In the parallel processing system 1 according to the embodiment of the present invention, the parallel processing device 10 and a plurality of terminal devices 20 are arranged for each of the areas 1a, 1b, 1c, and 1d divided based on geography, trade area, and the like.

  The parallel processing device 10 in each area can process a transaction for all the terminal devices 20 connected to the network 30. However, in the embodiment of the present invention, the parallel processing device 10 in each area can be used in the event of a disaster or failure. Other than the above, a transaction related to the terminal device 20 belonging to its own area is processed.

[Parallel processing device]
FIG. 2 is a diagram illustrating a configuration example of the parallel processing device according to the embodiment of the present invention.

  As shown in FIG. 2, the parallel processing device 10 according to the embodiment of the present invention includes a plurality of CPUs (P1) to (P3), a control unit 11, a bus switch unit 12, and a memory 13 on a bus. It is a connected computer. Note that the bus is configured by a data bus, an address bus, or the like, but in FIG. 2, these buses are simplified and described as appropriate in order to facilitate understanding of the present invention.

  The control unit 11 is connected to the network 30 and receives data from the network 30. In addition, the control unit 11 distributes tasks related to the received data to the CPUs in the waiting state among the plurality of CPUs (P1) to (P3). Further, the control unit 11 assigns an area in the address space of the memory 13 to the CPU to which the task is assigned every time the task is assigned to the CPU in the waiting state.

  The plurality of CPUs (P1) to (P3) and the control unit 11 access the memory 13 via the bus switch unit 12. The bus switch unit 12 connects and disconnects the bus so that one of the CPUs (P1) to (P3) or the control unit 11 is connected to the memory 13.

  The bus switch unit 12 monitors data on the memory 13, and when these are rewritten, the bus switch unit 12 transmits the rewritten data to the parallel processing devices 10 belonging to other areas connected to the network 30. As a result, the data on the memory 13 is synchronized among the plurality of parallel processing devices 10, and data redundancy is ensured.

  As the terminal device 20, for example, a ticket gate or a stock trading terminal installed at a station can be used.

[table]
FIG. 3 is a diagram showing a configuration example of a table used in the embodiment of the present invention.

  As shown in FIG. 3, in the embodiment of the present invention, a data management table (a) and a CPU management table (b) stored in the control unit 11 and an address conversion management table (c) stored in the bus switch unit 12. ) And are used.

(Data management table)
The data management table has a “user” field, a “terminal” field, an “address” field, and a “date_and_time” field.

“User” field The “user” field stores a user ID. The card ID of the non-contact ID card, the user name used for stock trading, etc. are examples of the user ID.

“Terminal” field In the “terminal” field, a terminal ID for identifying a terminal device is stored.

“Address” field The “address” field stores the upper n bits (8 bits in this embodiment) of the memory address in the address space.

“Date_and_time” field The “date_and_time” field stores data indicating the date and time.

(CPU management table)
The CPU management table has a “cpu” field and a “user” field.

“Cpu” field The “cpu” field stores a CPU ID for identifying a CPU.

“User” field The “user” field stores a user ID.

(Address translation management table)
The address conversion management table has a “cpu” field and an “address” field.

“Cpu” field The “cpu” field stores a CPU ID for identifying a CPU.

“Address” field The “address” field stores the upper n bits (8 bits in this embodiment) of the memory address in the address space.

[Operation example]
FIG. 4 is a diagram illustrating an operation example of the parallel processing device according to the embodiment of the present invention.

(Step S1)
First, the control unit 11 receives a user ID and a terminal ID from the terminal device 20. Note that the terminal device 20 acquires a user ID by reading from a non-contact IC card (not shown) or input from a user.

(Step S2)
Next, the control unit 11 stores the received user ID and terminal ID in the “user” field and the “terminal” field in the data management table of FIG.

(Step S3)
Next, the control unit 11 accesses the CPU management table of FIG. 3B to identify a record in which nothing is stored in the “user” field, and stores it in the “cpu” field of the specified record. CPU ID is acquired. As a result, the task related to the received user ID is distributed to the waiting CPU. Here, P2 for identifying the CPU (P2) is acquired as the CPUID.

(Step S4)
Next, the control unit 11 secures an area on the address space for the received user ID. More specifically, the control unit 11 determines the upper n bits (for example, AAAAAAAA) of the memory address in the reserved address space, and stores this in the “address” field in the data management table of FIG. To do. Thereby, an area (for example, AAAAAAAAA00000000-AAAAAAAAA11111111) in the address space having the determined upper n bits (for example, AAAAAAAAA) as a memory address is reserved for the received user ID. “A” is 0 or 1.

(Step S5)
Next, the control unit 11 accesses the memory 13 via the bus switch unit 12, and in a predetermined area (for example, the head area AAAAAAAA00000000) in the address space indicated by the upper n bits (for example, AAAAAAAA) determined in step S4. Write a command to the CPU (P2).

(Step S6)
Next, the control unit 11 accesses the bus switch unit 12 and converts the CPUID “P2” and the upper n bits (for example, AAAAAAAA) of the memory address determined in step S4 into the address conversion of FIG. Stored in the “cpu” field and the “address” field in the management table, respectively. As a result, an area in the address space is assigned to the CPU that distributes the task each time the task is distributed.

(Step S7)
Next, the control unit 11 outputs a start command to the CPU (P2).

(Step S8)
Next, the CPU (P2) accesses the memory 13 via the bus switch unit 12, and reads an instruction from a predetermined area (for example, the head area AAAAAAAA00000000) in the address space allocated to the CPU (P2).

  More specifically, in the embodiment of the present invention, the address space from XXXXXXXXX000000000000 to XXXXXXXXX11111111 is fixedly assigned to the CPU (P2), and the CPU (P2) accesses the memory 13 to access the bus switch unit. 12 outputs a memory address in the range of XXXXXXXXX000000000000 to XXXXXXXXX11111111. “X” is 0 or 1.

  When there is an access from the CPU (P2), the bus switch unit 12 switches the CPU connected to the memory 13 to the CPU (P2). At this time, in the address conversion management table of FIG. "P2" is specified in the "" field, and the upper n bits (for example, AAAAAAAA) of the memory address are acquired from the "address" field of the specified record.

  Then, the bus switch unit 12 outputs the upper n bits (XXXXXXX) of the memory address in the range of XXXXXXXXX000000000000 to XXXXXXXXX output from the CPU (P2) from the address conversion management table of FIG. 3C. Rewrite with n bits (for example, AAAAAAAA).

  In this way, the CPU (P2) can access the area in the address space reserved for the received user ID (for example, AAAAAAAA00000000-AAAAAAAAA11111111).

(Step S9)
Next, the CPU (P2) performs a process based on the instruction read from the memory 13, and writes the result into the memory 13 via the bus switch unit 12.

(Step S10)
Next, the bus switch unit 12 outputs a memory address (for example, AAAAAAAAA00000000-AAAAAAAAA11111111) in an area in the address space where data is written to the control unit 11.

(Step S11)
Next, the control unit 11 accesses the memory 13 via the bus switch unit 12 and reads data from an area on the address space having the output memory address (for example, AAAAAAAA00000000-AAAAAAAAA11111111).

(Step S12)
Next, the control unit 11 specifies a record in which the upper n bits (for example, AAAAAAAAA) of the address space in which the data is written is stored in the data management table of FIG. The user ID stored in the field and the data read in step S11 are transmitted to the parallel processing devices 10 belonging to other areas.

  As a result, when the data on the memory 13 is rewritten, the rewritten data is transmitted to the other parallel processing devices 10 connected to the network 30, and the data on the memory 13 is exchanged between the plurality of parallel processing devices 10. It becomes possible to synchronize the data.

  Note that the parallel processing device 10 belonging to another area performs a task of writing the received user ID and data in the memory 13 provided in the parallel processing device 10 in the same manner as when receiving data from the terminal device 20 among a plurality of CPUs. Assign to the waiting CPU. In this case, in the other parallel processing devices 10, the parallel processing device 10 that has transmitted the data is regarded as a terminal device.

(Step S13)
Next, the CPU (P2) outputs a processing completion notification to the control unit 11.

(Step S14)
Next, the control unit 11 accesses the CPU management table shown in FIG. 3B, identifies a record in which the CPU ID “P2” is stored in the “cpu” field, and enters the “user” field of the identified record. The stored user ID is deleted.

(Step S15)
Next, the control unit 11 accesses the data management table of FIG. 3A, identifies the record in which the CPU ID “P2” is stored in the “cpu” field, and sets the “terminal” field of the identified record The terminal ID stored in the “address” field and the upper n bits (eg, AAAAAAAA) of the memory address are acquired, and the date and time when step S15 is executed in the “date_and_time” field of the specified record Store the data shown.

(Step S16)
Next, the control unit 11 accesses the memory 13 via the bus switch unit 12, and reads data from the area on the address space indicated by the upper n bits (for example, AAAAAAAA) acquired in step S15.

(Step S17)
Next, the control unit 11 transmits the data read out in step S16 to the terminal device 20 based on the terminal ID acquired in step S15.

  The control unit 11 reads the data stored in the “date_and_time” field of the data management table in FIG. 3A at a predetermined time interval, and the date and time indicated by the read data is more predetermined than the date and time when reading is performed. If it is before the time, the record in which the read data is stored is deleted. As a result, the address space is released for user IDs that do not respond even after a certain period of time (timed-out user IDs).

  In the above description, the control unit 11 performs processing related to synchronization and processing related to timeout. However, these processing can also be performed by means different from the control unit 11. The separate means in this case can be constituted by hardware or software.

  In the above-described embodiment, an example in which the memory 13 is accessed via the bus switch unit 12 has been described. However, the access to the memory 13 may be performed via a cache memory.

  Next, referring to FIG. 5, the processing according to the first embodiment of the present invention and the processing according to the first and second comparative examples are compared.

  FIG. 5 is a diagram comparing the process according to the first embodiment of the present invention with the processes according to the first and second comparative examples. FIG. 5A is a diagram illustrating the process according to the first embodiment of the present invention. ) Is a diagram illustrating a process according to Comparative Example 1, and (c) is a diagram illustrating a process according to Comparative Example 2. FIG.

  In the first embodiment of the present invention, one transaction is composed of four tasks, and each task is processed by a CPU in a waiting state among a plurality of CPUs.

  According to the first embodiment of the present invention, for example, as shown in FIG. 5A, each task is sequentially processed by a waiting CPU (in the example shown in FIG. 5, CPU (P1), CPU (P3) ), CPU (P2) and CPU (P1) are sequentially processed), and one transaction is completed almost without waiting.

[Comparative Example 1]
In the first comparative example, as in the first embodiment of the present invention, one transaction is assumed to be composed of four tasks. However, in the first comparative example, unlike the first embodiment of the present invention, it is assumed that one CPU (P) performs time sharing by a plurality of transactions.

  According to Comparative Example 1, for example, as shown in FIG. 5B, one CPU (P) is time-shared by a plurality of transactions. A certain amount of time is required until the processing of the task is started, and the transaction is not easily completed.

[Comparative Example 2]
In Comparative Example 2, as in Example 1 of the present invention, one transaction is assumed to be composed of four tasks. However, in the second comparative example, unlike the first embodiment of the present invention, one CPU (P) is exclusively used by one transaction.

  According to the second comparative example, as shown in FIG. 5C, for example, the CPU is not empty until all tasks related to other transactions are completed, so the transaction is not easily completed.

  As mentioned above, although embodiment and the Example of this invention were described, these description is related to an example of this invention, and this invention is not limited at all by these description.

DESCRIPTION OF SYMBOLS 1 Parallel processing system 1a, 1b, 1c, 1d Area 10 divided based on geography, trade area, etc. Parallel processing unit 11 Control unit 12 Bus switch unit 13 Memory 20 Terminal device 30 Network P1, P2, P3 CPU

Claims (7)

A parallel processing device connected to a network,
Multiple CPUs;
Means for receiving data from the network;
Means for distributing a task related to the received data to a CPU in a waiting state among the plurality of CPUs;
A parallel processing apparatus comprising: Memory,
Means for allocating an area on the address space of the memory to a CPU for distributing the task each time the task is distributed;
The parallel processing apparatus according to claim 1, further comprising: A bus connecting the plurality of CPUs and the memory;
Means for connecting and disconnecting the bus so that one CPU is connected to the memory;
The parallel processing apparatus according to claim 2, further comprising:   4. The apparatus according to claim 2, further comprising means for transmitting the rewritten data to another parallel processing device connected to the network when the data on the memory is rewritten. The parallel processing device according to 1.   The parallel processing apparatus according to any one of claims 1 to 4, wherein the parallel processing apparatus is connected to a ticket gate installed at a station via the network.   The parallel processing apparatus according to any one of claims 1 to 4, wherein the parallel processing apparatus is connected to a stock trading terminal via the network. The parallel processing system according to claim 1, wherein the parallel processing device according to claim 1 and a plurality of terminal devices are connected via a network.

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