JPWO2010095635A1 - Circuit design support device, circuit design support method, and program - Google Patents

Abstract

The circuit design support device (100) includes an on-chip debug unit (110) and a simulation unit (130). The on-chip debug unit (110) operates the electronic circuit (47) on the integrated circuit until the operation of the electronic circuit (47) reaches the switching stage, and when the operation of the electronic circuit (47) reaches the switching stage, Data in the circuit (47) is extracted. The simulation unit (130) reproduces the electronic circuit (47) at the switching stage using the simulation code (121) representing the electronic circuit (47) and the data extracted by the on-chip debug unit (110). The operation of the electronic circuit (47) after the switching stage is simulated.

Description

  The present invention relates to a circuit design support apparatus and circuit design support method suitable for efficiently debugging an electronic circuit, and a computer-readable recording medium storing a program for realizing these on a computer.

Using a so-called circuit simulator, reconfigurable devices such as FPGA (Field Programmable Gate Array) and DRP (Dynamically Reconfigurable Processor) and ASIC (Application Specific Integration) are known for executing the design of Application Specific Integration (CIRCUIT). The circuit simulator can execute a simulation according to the design stage.
For example, the circuit simulator executes C level simulation for the behavior level description described in C language or the like. Also, the circuit simulator can be used for RTL (Register Transfer Level (register transfer level)) description obtained by behavioral synthesis of behavior level description described in C language or the like, or for RTL description directly described in RTL description language. , RTL simulation is executed.
The circuit simulator executes block level simulation for a netlist obtained by logical synthesis or technology mapping of the RTL description.
Further, the circuit simulator executes a hardware model simulation for the configuration code obtained by the placement / wiring design based on the net list.

  However, when a complex circuit is simulated using a circuit simulator or a circuit is simulated using a large amount of test data, the time required for the simulation is enormous. In particular, when a hardware model simulation is executed using a circuit simulator, it is possible to debug in detail, but a great deal of time is spent on debugging.

  On the other hand, a technique for debugging a reconfigurable device or ASIC using an on-chip debugger instead of using a circuit simulator is also known. The on-chip debugger operates the reconfigurable device and the ASIC itself, and outputs the values of the internal registers and memories of these devices to the outside of the device.

  However, in debugging using an on-chip debugger, unlike simulation using a circuit simulator, a signal other than a signal stored in a register or memory at a clock edge, for example, a signal input to a computing unit or a middle The signal output from the computing unit could not be observed.

  As a technique for solving such a problem, for example, in Patent Document 1, the electronic circuit to be debugged is stopped using resources such as a register, a memory, an external port, and a wiring that are not used in the reconfigurable device. A data processing system for inserting a conditional circuit is disclosed. In this data processing system, when the stop condition circuit determines that the desired stop condition is met, the operation of the electronic circuit to be debugged is stopped, etc. Or output to a port.

JP 2007-179567 A

  However, the technique disclosed in Patent Document 1 has a limitation that it cannot be used when there are not enough resources such as registers, memories, external ports, and wiring. Also, the electronic circuits in the reconfigurable device are generally densely arranged at predetermined positions by optimization. Therefore, it is common that an additional circuit is generated at a position away from the electronic circuit. For this reason, the additional circuit becomes a critical path, which may limit the operation speed of the reconfigurable device.

As described above, although the circuit simulator can perform detailed debugging, the time required for debugging is enormous. On the other hand, the on-chip debugger has a short time required for debugging but is not suitable for detailed debugging.
For this reason, it has been desired to develop an easy-to-use circuit design support apparatus that enables detailed debugging while reducing the time required for debugging.

  The present invention has been made in view of the above problems, and an object thereof is to provide a circuit design support apparatus and the like suitable for efficiently debugging an electronic circuit.

In order to achieve the above object, a circuit design support apparatus according to a first aspect of the present invention provides:
An on-chip debug unit for operating an electronic circuit mounted on the integrated circuit on the integrated circuit and extracting data in the electronic circuit;
A simulation unit for simulating the operation of the electronic circuit using a simulation code representing the electronic circuit;
An abnormality detection unit that detects an operation abnormality of the electronic circuit and identifies a time point when the operation abnormality is detected, and
When the operation abnormality is detected, the on-chip debug unit re-operates the electronic circuit until a switching stage that is a predetermined number of cycles before the specified time, and further, the data in the electronic circuit Extract
The simulation unit reproduces the state of the electronic circuit in the switching stage using the simulation code and the data extracted by the on-chip debugging unit, and then performs an operation of the electronic circuit after the switching stage. To simulate,
It is characterized by that.

In order to achieve the above object, a circuit design support method according to another aspect of the present invention includes:
An on-chip debug step for operating an electronic circuit mounted on the integrated circuit on the integrated circuit and extracting data in the electronic circuit;
A simulation step for simulating the operation of the electronic circuit using a simulation code representing the electronic circuit;
An abnormality detection unit that detects an operation abnormality of the electronic circuit and identifies an abnormality detection step that detects the operation abnormality; and
In the on-chip debugging step, when the operation abnormality is detected, the on-chip debugging unit re-operates the electronic circuit until a switching stage that is a predetermined number of cycles before the identified time point, and Extracting the data in the electronic circuit,
In the simulation step, the simulation unit reproduces the state of the electronic circuit in the switching stage using the simulation code and the data extracted by the on-chip debugging unit, and then performs the switching after the switching stage. Simulate the operation of electronic circuits,
It is characterized by that.

In order to achieve the above object, a computer-readable recording medium according to another aspect of the present invention provides:
On the computer,
An on-chip debug step for operating an electronic circuit mounted on the integrated circuit on the integrated circuit and extracting data in the electronic circuit;
A simulation step of simulating the operation of the electronic circuit using a simulation code representing the electronic circuit;
An abnormality detection step for detecting an operation abnormality of the electronic circuit and specifying a time point when the operation abnormality is detected, and a program for executing
In the on-chip debugging step, when the operation abnormality is detected, the electronic circuit is re-operated until a switching stage that is a predetermined number of cycles before the specified time, and the data in the electronic circuit is further operated. Extract
In the simulation step, the state of the electronic circuit in the switching stage is reproduced using the simulation code and the data extracted by the on-chip debugging unit, and then the operation of the electronic circuit after the switching stage is performed. To simulate,
A program characterized by this is recorded.

  According to the present invention, it is possible to provide a circuit design support apparatus and the like suitable for efficiently debugging an electronic circuit.

It is a block diagram which shows the structure of the circuit design assistance apparatus which concerns on the 1st-4th embodiment of this invention. It is a block diagram which shows the structure of a target substrate. It is a figure for demonstrating the data which a data reading part can acquire, and the data which cannot be acquired. It is a figure for demonstrating the function of the circuit design support apparatus which concerns on the 1st-4th embodiment of this invention. It is a flowchart which shows the code | cord | chord generation process which the circuit design assistance apparatus which concerns on the 1st-4th embodiment of this invention performs. It is a flowchart which shows the circuit design assistance process which the circuit design assistance apparatus which concerns on the 1st Embodiment of this invention performs. It is a figure for demonstrating operation | movement of a multi-cycle arithmetic unit. It is a flowchart which shows the circuit design assistance process which the circuit design assistance apparatus which concerns on the 2nd Embodiment of this invention performs. It is a flowchart which shows the circuit design support process which the circuit design support apparatus which concerns on the 3rd Embodiment of this invention performs. It is a flowchart which shows the circuit design support process which the circuit design support apparatus which concerns on the 4th Embodiment of this invention performs.

  Hereinafter, a circuit design support apparatus according to an embodiment of the present invention will be described with reference to the drawings. Here, the circuit design support apparatus is an apparatus for detecting a design bug present in an electronic circuit mounted on an integrated circuit such as DRP or FPGA. Specifically, the circuit design support device enables on-chip debugging of a user's electronic circuit by reading a register or memory value of the electronic circuit while actually operating the electronic circuit mounted on the integrated circuit. Has a function as a debugger. Furthermore, the circuit design support apparatus has a function as a simulator for simulating an electronic circuit by executing a program (simulation code) representing the electronic circuit mounted on the integrated circuit on a computer.

(First embodiment)
First, the configuration of the circuit design support apparatus according to the first embodiment of the present invention will be described with reference to FIG. Here, the circuit design support apparatus according to the present embodiment includes a compile function for generating a configuration code to be written in an integrated circuit by compiling a circuit description (source program) of a predetermined description level, and a generated configuration code. A writer function for writing into the integrated circuit and a simulation code generation function for generating a simulation code by converting a circuit description at a predetermined description level are further provided.

  As shown in FIG. 1, the circuit design support apparatus 100 physically includes a CPU (Central Processing Unit) 11, a ROM (Read Only Memory) 12, a RAM (Random Access Memory) 13, a hard disk device 14, and the like. A display control unit 15 and an interface 16. Each component included in the circuit design support apparatus 100 is connected via the bus 10. The circuit design support apparatus 100 can be configured by a personal computer, a workstation, or the like. As illustrated in FIG. 1, the circuit design support system 1000 includes a circuit design support device 100, a display device 20, an input device 30, and a target substrate 40. The circuit design support device 100 may be configured to include the display device 20, the input device 30, the target substrate 40, and the like.

  The CPU 11 controls the operation of the entire circuit design support apparatus 100 according to a control program stored in the hard disk device 14. The CPU 11 exchanges control signals and data with each component via the bus 10.

  The ROM 12 stores an IPL (Initial Program Loader) that is executed immediately after the power is turned on. After the IPL is executed, the CPU 11 reads out the control program stored in the hard disk device 14 to the RAM 13 and executes it.

  The RAM 13 temporarily stores control programs and data. The RAM 13 temporarily stores a control program read from the hard disk device 14, data necessary for code generation processing and circuit design support processing described later, and the like.

The hard disk device 14 stores a control program for realizing code generation processing, circuit design support processing, and the like. The hard disk device 14 also stores a circuit description representing an electronic circuit mounted on the integrated circuit. The circuit description is classified into C language level description, RTL description, block level description, hardware level description, and the like according to the description level.
For example, the C language level description represents an electronic circuit mounted on an integrated circuit in C language. For example, the RTL description represents an electronic circuit mounted on an integrated circuit using HDL (Hardware Description Language).
For example, the block level description represents an electronic circuit mounted on an integrated circuit by a net list.
For example, the hardware level description represents an electronic circuit mounted on an integrated circuit by a configuration code. Further, the hard disk device 14 stores a simulation code obtained by converting the circuit description at each description level.

  The display control unit 15 generates an image signal to be displayed on the display device 20 under the control of the CPU 11 and supplies the image signal to the display device 20. The display device 20 displays an image according to the image signal supplied from the display control unit 15. For example, the display device 20 displays a screen showing a circuit description at each description level, a screen showing a result of on-chip debugging, a screen showing a result of simulation, and the like. The display device 20 includes, for example, an LCD (Liquid Crystal Display), a CRT (Cathode Ray Tube), and the like.

  The interface 16 relays data exchange between each component included in the circuit design support device 100 and the external input device 30 or the target substrate 40. The input device 30 receives an operation input from a user under the control of the CPU 11. The input device 30 is composed of, for example, a keyboard and a mouse. The target substrate 40 is a substrate including a DRP that is a target for on-chip debugging. The target substrate 40 will be described in detail with reference to FIG.

  As shown in FIG. 2, the target substrate 40 includes an interface 41, a code writing unit 42, a circuit control unit 43, a data writing unit 44, a data reading unit 45, and a DRP 46.

  The interface 41 relays data exchange between each component included in the target board 40 and each component included in the circuit design support apparatus 100.

  The code writing unit 42 mounts the electronic circuit 47 on the DRP 46 by writing the configuration code supplied from the circuit design support apparatus 100 via the interface 41 to the DRP 46.

  The circuit control unit 43 controls the operation of the electronic circuit 47 mounted on the DRP 46. Specifically, the circuit control unit 43 operates the electronic circuit 47 for one cycle to advance the operation of the electronic circuit 47 by one cycle, or operates the electronic circuit 47 for a plurality of cycles continuously to operate the electronic circuit 47. The operation of the circuit 47 is advanced by a plurality of cycles. It is possible to appropriately adjust how many cycles are made, for example, how many clocks.

  The data writing unit 44 writes data supplied from the circuit design support apparatus 100 via the interface 41 to a register, a memory, a port, or the like in the electronic circuit 47. The data reading unit 45 reads data stored in a register, a memory, a port, and the like in the electronic circuit 47 and supplies the data to the circuit design support apparatus 100 via the interface 41. Data writing by the data writing unit 44 and data reading by the data reading unit 45 are executed, for example, while the electronic circuit 47 is not operating.

  Here, with reference to FIG. 3, data that can be acquired by the data reading unit 45 and data that cannot be acquired will be described. As shown in FIG. 3, the computing unit 60 includes an adder 61 and an adder 62. In FIG. 3, a register 51 is a register that stores data A, a register 52 is a register that stores data B, and a register 53 is a register that stores data C. The adder 61 calculates the sum of the data A supplied from the register 51 and the data B supplied from the register 52, and supplies data indicating the result to the adder 62. The adder 62 calculates the sum of the data supplied from the adder 61 and the data C supplied from the register 53, and supplies data X indicating the result to the register 54. That is, the arithmetic unit 60 calculates and outputs the sum of the three supplied values, that is, performs an operation of X = A + B + C.

  Here, the addition by the adder 61 and the addition by the adder 62 are executed in the same cycle, and data supplied from the adder 61 to the adder 62 is not stored in the register. At this time, the data reading unit 45 can acquire data A, data B, data C, and data X, but cannot acquire data supplied from the adder 61 to the adder 62. As described above, data cannot be acquired by on-chip debugging, and as a result, detailed debugging may not be possible. As will be described later, according to the circuit design support device 100, data that cannot be acquired by on-chip debugging can be analyzed by simulation.

  Next, functions of the circuit design support apparatus 100 according to the present embodiment will be described with reference to FIG.

  As shown in FIG. 4, the circuit design support apparatus 100 functionally includes an on-chip debug unit 110, a storage unit 120, and a simulation unit 130.

  The on-chip debug unit 110 operates the electronic circuit 47 mounted on the DRP 46 and extracts data in the electronic circuit 47. Here, the on-chip debug unit 110 operates the electronic circuit 47 until the electronic circuit 47 reaches a switching stage described later. Then, when the electronic circuit 47 reaches the switching stage, the on-chip debug unit 110 stops the operation of the electronic circuit 47, reads data in the electronic circuit 47, and supplies the data to the simulation unit 130. Further, the on-chip debug unit 110 generates an image signal for causing the display device 20 to display a screen (on-chip debug screen) for displaying the extracted data, and supplies the image signal to the display device 20, for example. Present the extracted data to the user. The on-chip debug unit 110 includes, for example, a CPU 11, a display control unit 15, an interface 16, and the like.

  The storage unit 120 stores a simulation code 121 for simulating the electronic circuit 47 on a computer. The simulation code 121 may be obtained by converting a circuit description of any description level. The storage unit 120 is configured by, for example, the hard disk device 14.

  The simulation unit 130 simulates the operation of the electronic circuit 47 on the computer using the simulation code 121 stored in the storage unit 120. Here, the simulation unit 130 uses the data supplied from the on-chip debug unit 110 to simulate the operation of the electronic circuit 47 after the switching stage. That is, the user performs debugging using the on-chip debugging unit 110 until the switching stage, and performs debugging using the simulation unit 130 after the switching stage. For example, the simulation unit 130 generates an image signal for displaying a simulation screen and supplies the image signal to the display device 20. The simulation unit 130 includes, for example, a CPU 11, a display control unit 15, an interface 16, and the like.

  Next, a code generation process executed by the circuit design support apparatus 100 will be described using the flowchart shown in FIG. In the code generation process, a configuration code is generated from the C language level description, and the generated configuration code is written in the DRP 46 to mount the electronic circuit 47 on the DRP 46. Further, any circuit description is converted and simulation is performed. This is a process for generating a code for use. The code generation process is executed prior to the circuit design support process described later.

  First, the CPU 11 receives an input of a C language level description from the user (step S101). The CPU 11 may accept a C language level description newly generated by the user through the input device 30. Alternatively, a C language level description preliminarily stored in the hard disk device 14 or an external storage device (not shown) of the circuit design support device 100 specified by the user may be received. The CPU 11 stores the accepted C language level description in the hard disk device 14.

  Next, the CPU 11 generates an RTL description by behaviorally synthesizing the C language level description received in step S101 (step S102). The CPU 11 stores the generated RTL description in the hard disk device 14.

  Then, the CPU 11 generates a block level description based on the RTL description generated in step S102 (step S103). Here, the block level description corresponds to, for example, a net list. The CPU 11 stores the generated block level description in the hard disk device 14.

  Further, the CPU 11 generates a hardware level description based on the block level description generated in step S103 (step S104). Specifically, the CPU 11 generates a hardware level description (that is, a configuration code) by performing arrangement and wiring design of each resource described on the net list. The CPU 11 stores the generated hardware level description in the hard disk device 14.

  Then, the CPU 11 writes the hardware level description generated in step S104 into the DRP 46 (step S105). That is, the CPU 11 mounts the electronic circuit 47 on the DRP 46 by writing the configuration code generated in step S104 into the DRP 46.

  Further, the CPU 11 converts any circuit description to generate a simulation code (step S106). Which description level of the circuit description is converted by the CPU 11 to generate the simulation code is arbitrary. For example, the CPU 11 converts the RTL description generated in step S102 to generate a simulation code. When the CPU 11 completes the process of converting the circuit description and generating the simulation code (step S106), the CPU 11 ends the code generation process.

  Next, a circuit design support process executed by the circuit design support apparatus 100 according to the present embodiment will be described using the flowchart shown in FIG. The circuit design support process is a process that supports the design of the user's electronic circuit by appropriately switching between the on-chip debug function and the simulation function and providing it to the user.

  First, the CPU 11 advances the operation of the electronic circuit 47 until an abnormality is detected (step S201). Specifically, the CPU 11 operates the electronic circuit 47 and extracts data in the electronic circuit 47 in order to allow the user to debug the electronic circuit 47 mounted on the DRP 46 on-chip. The CPU 11 presents the extracted data content to the user by causing the display device 20 to display the data content.

  Then, the CPU 11 determines whether or not an abnormality is detected by on-chip debugging (step S202). For example, the CPU 11 determines that an abnormality has been detected when the data extracted from the electronic circuit 47 does not match the predetermined data. Further, the CPU 11 may determine that an abnormality has been detected when an operation input indicating that the abnormality has been detected is made by the user. If the CPU 11 determines that no abnormality is detected by the on-chip debugging (step S202: NO), the circuit design support process is terminated.

  On the other hand, if the CPU 11 determines that an abnormality has been detected by on-chip debugging (step S202: YES), the CPU 11 identifies the time point at which the abnormality was detected (step S203). For example, when the CPU 11 operates the electronic circuit 47 for a predetermined number of cycles, when the data extracted from the electronic circuit 47 does not match the predetermined data, an abnormality is detected for the predetermined number of cycles. Specify as time. Further, the CPU 11 may specify the number of cycles received from the user when an abnormality is detected.

  When the CPU 11 finishes the specific process (step S203) when the abnormality is detected, the CPU 11 restarts the electronic circuit 47 and advances the operation of the electronic circuit 47 until one cycle before the abnormality is detected (step S204). ). Specifically, first, the CPU 11 supplies a reset signal to the DRP 46 on which the electronic circuit 47 is mounted to place the electronic circuit 47 in an initial state. Then, the CPU 11 supplies the clock signal to the DRP 46 and advances the operation of the electronic circuit 47 until one cycle before the time point specified in step S203. In the present embodiment, a time point one cycle before the time point when an abnormality is detected is set as a switching stage in which the debugging method is switched from on-chip debugging to simulation.

  Next, the CPU 11 acquires data in the electronic circuit 47 (step S205). Note that the data acquired by the CPU 11 is data stored in a register, memory, port, or the like in the electronic circuit 47.

  Next, the CPU 11 reproduces the state of the electronic circuit 47 using the data acquired in step S205 (step S206). Specifically, the CPU 11 uses the simulation code generated in step S106 of FIG. 5 and the data acquired in step S205 to determine the state of the electronic circuit 47 mounted on the DRP 46 at the switching stage described above. Reproduce above.

  Next, the CPU 11 simulates the operation of the electronic circuit 47 after the switching stage on the computer using the simulation code (step S207).

  Based on the result of this simulation, the user can examine in detail the location where there is an abnormality. Thereafter, if necessary, the user can re-operate the electronic circuit 47 from the current state (switching stage) and perform on-chip debugging up to the next abnormal location.

  According to the circuit design support apparatus 100 according to the present embodiment, it is possible to support the user to efficiently debug the electronic circuit 47. For example, the circuit design support apparatus 100 can shorten the debugging time by operating the electronic circuit 47 with the on-chip debugging function until an abnormality is detected. The operation of the electronic circuit 47 immediately before the point in time when the abnormality is detected is simulated by the simulation function, thereby enabling detailed debugging. According to the circuit design support apparatus 100 according to the present embodiment, data that is difficult to confirm by on-chip debugging, such as data supplied from the adder 61 to the adder 62, can be confirmed by simulation.

(Second Embodiment)
In the first embodiment, an example has been described in which debugging of an electronic circuit including an arithmetic unit that completes an operation in one cycle is supported. However, according to the present invention, it is possible to support debugging of an electronic circuit including a multi-cycle arithmetic unit that requires a plurality of cycles from when data is supplied until the data is output. Examples of the multi-cycle arithmetic unit include a multi-cycle arithmetic unit and a pipeline arithmetic unit. Here, the multi-cycle arithmetic unit will be described with reference to FIG.

  As shown in FIG. 7, the multicycle computing unit 70 includes a flip-flop 71 and a flip-flop 72. First, data is supplied from the external register 73 to the flip-flop 71 in the first cycle. Then, data is supplied from the flip-flop 71 to the flip-flop 72 in the second cycle. Further, data is supplied from the flip-flop 72 to the external register 74 in the third cycle. Thus, the multi-cycle calculator 70 requires three cycles to execute the calculation. Although not shown, the pipeline arithmetic unit requires a large number of cycles for the calculation, like the multi-cycle arithmetic unit.

  As described above, when an arithmetic unit that requires many cycles for calculation is included in the electronic circuit 47 mounted on the integrated circuit, the data included in the arithmetic unit cannot be referred to immediately by on-chip debugging. However, in order to simulate the operation of the electronic circuit 47 mounted on the integrated circuit, it is necessary to accurately grasp the data included in such an arithmetic unit. The circuit design support apparatus 100 according to the present embodiment makes it possible to accurately simulate the operation of the electronic circuit 47 by acquiring data in the electronic circuit 47 over several cycles. Hereinafter, the circuit design support processing executed by the circuit design support apparatus 100 according to the present embodiment will be described with reference to the flowchart shown in FIG. Note that the configuration of the circuit design support apparatus 100 according to the present embodiment is the same as that of the circuit design support apparatus 100 according to the first embodiment, and a description thereof will be omitted.

  First, the CPU 11 advances the operation of the electronic circuit 47 until an abnormality is detected (step S301). Then, the CPU 11 determines whether or not an abnormality is detected by on-chip debugging (step S302). If the CPU 11 determines that no abnormality has been detected by the on-chip debugging (step S302: NO), the circuit design support process ends.

  On the other hand, if the CPU 11 determines that an abnormality has been detected by on-chip debugging (step S302: YES), the CPU 11 identifies the time point at which the abnormality was detected (step S303). When the CPU 11 specifies the time point at which the abnormality is detected, the CPU 11 restarts the electronic circuit 47 and advances the operation of the electronic circuit 47 until a predetermined number of cycles before the time point at which the abnormality is detected (step S304). In the present embodiment, a time point a predetermined number of cycles before an abnormality is detected is set as a switching stage in which the debugging method is switched from on-chip debugging to simulation. The number of cycles here is the largest of the number of cycles required for execution of each multi-cycle arithmetic unit included in the electronic circuit 47. Next, the CPU 11 acquires data in the electronic circuit 47 (step S305).

  Next, the CPU 11 reproduces the state of the electronic circuit 47 using the data acquired in step S305 (step S306). Next, the CPU 11 determines whether or not the operation of the electronic circuit 47 has been advanced to the time point when the abnormality is detected (step S307).

  If the CPU 11 determines that the operation of the electronic circuit 47 has not been advanced to the time when the abnormality is detected (step S307: NO), the operation of the electronic circuit 47 is advanced by one cycle (step S308), and the data in the electronic circuit 47 is Is acquired (step S309). Further, the CPU 11 executes a simulation for one cycle on the computer using the data acquired in step S309 (step S310).

  On the other hand, when the CPU 11 determines that the operation of the electronic circuit 47 has been advanced to the point in time when the abnormality is detected (step S307: YES), the circuit design support process is terminated. The user can examine the abnormal part in detail based on the result of the above simulation.

  According to the circuit design support apparatus 100 according to the present embodiment, even when the electronic circuit 47 to be debugged includes a multi-cycle arithmetic unit or a pipeline arithmetic unit, the data acquired by on-chip debugging is used. It can be used for accurate simulation. Therefore, according to the circuit design support apparatus 100 according to the present embodiment, it is possible to support the user to efficiently debug the electronic circuit 47 as in the circuit design support apparatus 100 according to the first embodiment.

(Third embodiment)
In the second embodiment, after the state of the electronic circuit 47 is reproduced on the computer using the acquired data, a simulation for one cycle is executed every time the operation of the electronic circuit 47 is advanced by one cycle. It was. However, after reproducing the state of the electronic circuit 47 on the computer using the acquired data, the operation of the electronic circuit 47 is advanced by the number of cycles required for the operation of the multi-cycle arithmetic unit, and then the simulation for the number of cycles is summarized. May be executed. Hereinafter, the circuit design support process executed by the circuit design support apparatus 100 according to the present embodiment will be described with reference to the flowchart shown in FIG. Note that the configuration of the circuit design support apparatus 100 according to the present embodiment is the same as that of the circuit design support apparatus 100 according to the first and second embodiments, and thus description thereof is omitted.

  First, the CPU 11 advances the operation of the electronic circuit 47 until an abnormality is detected (step S401). Then, the CPU 11 determines whether or not an abnormality has been detected by on-chip debugging (step S402). If the CPU 11 determines that no abnormality has been detected by on-chip debugging (step S402: NO), the circuit design support process is terminated.

  On the other hand, if the CPU 11 determines that an abnormality has been detected by on-chip debugging (step S402: YES), the CPU 11 identifies the time point at which the abnormality has been detected (step S403). When the CPU 11 specifies the time point at which the abnormality is detected, the CPU 11 restarts the electronic circuit 47 and advances the operation of the electronic circuit 47 until a predetermined number of cycles before the time point at which the abnormality is detected (step S404). In this embodiment, as in the second embodiment, a time point that is a predetermined number of cycles before an abnormality is detected is set as a switching stage in which the debugging technique is switched from on-chip debugging to simulation. The number of cycles here is the largest of the number of cycles required for execution of each multi-cycle arithmetic unit included in the electronic circuit 47. Next, the CPU 11 acquires data in the electronic circuit 47 (step S405).

  Next, the CPU 11 reproduces the state of the electronic circuit 47 using the data acquired in step S405 (step S406). Next, the CPU 11 determines whether or not the operation of the electronic circuit 47 has been advanced to the time point when the abnormality is detected (step S407).

  If the CPU 11 determines that the operation of the electronic circuit 47 has not been advanced to the time point when the abnormality is detected (step S407: NO), the operation of the electronic circuit 47 is advanced by one cycle (step S408), and the data in the electronic circuit 47 is Is acquired (step S409). And CPU11 returns a process to the process (step S407: NO) which discriminate | determines whether operation | movement of the electronic circuit 47 was advanced to the time of detecting abnormality.

  On the other hand, if the CPU 11 determines that the operation of the electronic circuit 47 has been advanced to the point in time when the abnormality is detected (step S407: YES), the CPU 11 executes the simulation for the number of cycles of the operation using the data acquired in step S409. (Step S410). The user can examine the abnormal part in detail based on the result of the above simulation.

  According to the circuit design support apparatus 100 according to the present embodiment, the electronic circuit 47 to be debugged includes a multi-cycle arithmetic unit or a pipeline arithmetic unit, as in the circuit design support apparatus 100 according to the second embodiment. Even if it is, it can simulate correctly using the data acquired by on-chip debugging. Therefore, according to the circuit design support apparatus 100 according to the present embodiment, it is possible to support the user to efficiently debug the electronic circuit 47, similarly to the circuit design support apparatus 100 according to the first and second embodiments. .

(Fourth embodiment)
In the first to third embodiments, the example in which the electronic circuit 47 is simulated using the simulation code obtained by converting the circuit description of any one description level is shown. However, the electronic circuit 47 can also be simulated using each of the simulation codes obtained by converting each of the circuit descriptions at a plurality of description levels. According to this configuration, by comparing the simulation results, it is possible to determine whether the detected abnormality is due to a defect in the configuration code written in the DRP 46 or due to other defects. Hereinafter, the circuit design support process executed by the circuit design support apparatus 100 according to the present embodiment will be described with reference to the flowchart shown in FIG. Note that the configuration of the circuit design support apparatus 100 according to the present embodiment is the same as that of the circuit design support apparatus 100 according to the first to third embodiments, and thus description thereof is omitted.

  First, the CPU 11 advances the operation of the electronic circuit 47 until an abnormality is detected (step S501). Then, the CPU 11 determines whether or not an abnormality is detected by on-chip debugging (step S502). If the CPU 11 determines that no abnormality has been detected by the on-chip debugging (step S502: NO), the circuit design support process ends.

  On the other hand, when the CPU 11 determines that an abnormality has been detected by on-chip debugging (step S502: YES), the CPU 11 identifies the time point at which the abnormality has been detected (step S503). When the CPU 11 finishes the specific process when the abnormality is detected, the CPU 11 restarts the electronic circuit 47 and advances the operation of the electronic circuit 47 until one cycle before the abnormality is detected (step S504). Next, the CPU 11 acquires data in the electronic circuit 47 (step S505).

  Next, the CPU 11 executes a C level simulation (step S506). Specifically, the CPU 11 executes a simulation using the data acquired in step S505 and the simulation code obtained by converting the C language level description. In addition, the CPU 11 executes RTL simulation (step S507). Specifically, the CPU 11 executes a simulation using the data acquired in step S505 and the simulation code obtained by converting the RTL description.

  Then, the CPU 11 determines whether or not the simulation results at the respective description levels are the same (step S508).

  If the CPU 11 determines that the simulation results at the respective description levels are the same (step S508: YES), the CPU 11 determines that there is a defect in the configuration code written in the DRP 46 (step S509). Then, the CPU 11 displays a message to that effect on the display device 20 and presents it to the user, and ends the circuit design support process.

  On the other hand, if the CPU 11 determines that the simulation results at the respective description levels are not the same (step S508: NO), the CPU 11 determines that there is a defect other than the configuration code (step S510). Then, the CPU 11 displays a message to that effect on the display device 20 and presents it to the user, and ends the circuit design support process.

  According to the circuit design support device 100 according to the present embodiment, if an abnormality is detected by comparing simulation results of a plurality of description levels, is it due to a defect in the configuration code written in the DRP 46? Alternatively, it is possible to determine whether it is due to other problems. Therefore, according to the circuit design support apparatus 100 according to the present embodiment, it is possible to support the user to efficiently debug the electronic circuit 47.

  The circuit design support apparatus according to the present invention can be realized using a normal computer system, not a dedicated system. For example, a computer system such as a flexible disk, a CD-ROM (Compact Disk Read-Only Memory), a DVD (Digital Versatile Disk), or an MO (Magneto Optical Disk) can be read by a computer system. A circuit design support apparatus that executes the above-described processing may be configured by storing and distributing in a recording medium and installing it in a computer system.

  Furthermore, the circuit design support apparatus may be configured by storing a program in a disk device or the like of a server device on the Internet and, for example, superimposing it on a carrier wave and downloading it to a computer system.

  This application is based on Japanese Patent Application No. 2009-34867 filed on Feb. 18, 2009. This specification will be addressed with reference to the specification, claims, and drawings as a whole.

  The present invention can be used, for example, in a circuit design support apparatus that supports circuit design of an electronic circuit.

10 Bus 11 CPU
12 ROM
13 RAM
14 Hard disk device 15 Display control unit 16 Interface 20 Display device 30 Input device 40 Target substrate 41 Interface 42 Code writing unit 43 Circuit control unit 44 Data writing unit 45 Data reading unit 46 DRP
47 Electronic circuit 51, 52, 53, 54 Register 60 Operation unit 61, 62 Adder 70 Multicycle operation unit 71, 72 Flip-flop 73, 74 External register 100 Circuit design support device 110 On-chip debug unit 120 Storage unit 121 For simulation Code 130 Simulation unit 1000 Circuit design support system

The present invention is suitable circuit design support apparatus to perform debugging electronic circuits effectively, the circuit design support method, and relates to a program for realizing these on a computer.

In order to achieve the above object, a program according to another aspect of the present invention provides:
On the computer,
An on-chip debug step for operating an electronic circuit mounted on the integrated circuit on the integrated circuit and extracting data in the electronic circuit;
A simulation step of simulating the operation of the electronic circuit using a simulation code representing the electronic circuit;
An abnormality detection step for detecting an operation abnormality of the electronic circuit and specifying a time point when the operation abnormality is detected, and a program for executing
In the on-chip debugging step, when the operation abnormality is detected, the electronic circuit is re-operated until a switching stage that is a predetermined number of cycles before the specified time, and the data in the electronic circuit is further operated. Extract
In the simulation step, the state of the electronic circuit in the switching stage is reproduced using the simulation code and the data extracted by the on-chip debugging unit, and then the operation of the electronic circuit after the switching stage is performed. To simulate,
It shall be the features a.

Claims (10)

An on-chip debug unit for operating an electronic circuit mounted on the integrated circuit on the integrated circuit and extracting data in the electronic circuit;
A simulation unit for simulating the operation of the electronic circuit using a simulation code representing the electronic circuit;
An abnormality detection unit that detects an operation abnormality of the electronic circuit and identifies a time point when the operation abnormality is detected, and
When the operation abnormality is detected, the on-chip debug unit re-operates the electronic circuit until a switching stage that is a predetermined number of cycles before the specified time, and further, the data in the electronic circuit Extract
The simulation unit reproduces the state of the electronic circuit in the switching stage using the simulation code and the data extracted by the on-chip debugging unit, and then performs an operation of the electronic circuit after the switching stage. To simulate,
A circuit design support device characterized by that. A configuration code generator for generating a configuration code to be written to the integrated circuit based on a circuit description of a predetermined description level;
A configuration code writing unit that writes the generated configuration code to the integrated circuit, and
The electronic circuit is mounted on the integrated circuit by writing the configuration code to the integrated circuit.
The circuit design support apparatus according to claim 1. A simulation code generating means for generating the simulation code based on a circuit description of a predetermined description level;
The circuit design support apparatus according to claim 1, wherein the circuit design support apparatus is provided. The switching stage is a time point one cycle before the time point specified by the abnormality detection unit.
The circuit design support apparatus according to claim 1, wherein the circuit design support apparatus is a circuit design support apparatus. The electronic circuit includes a multi-cycle arithmetic unit that internally includes the data in the middle of an operation that requires a plurality of cycles to execute the operation and is not referred to from the outside,
The switching stage is a time before the plurality of cycles before the time specified by the abnormality detection unit,
When the state of the electronic circuit in the switching stage is reproduced by the simulation unit, the on-chip debug unit performs processing for operating the electronic circuit for one cycle and processing for extracting data in the electronic circuit. Repeat until reaching the time point specified by the abnormality detection unit,
The simulation unit simulates the operation of the electronic circuit using the simulation code and the data extracted by the on-chip debugging unit every time the electronic circuit operates for one cycle.
The circuit design support apparatus according to claim 1, wherein the circuit design support apparatus is a circuit design support apparatus. The electronic circuit includes a multi-cycle arithmetic unit that internally includes the data in the middle of an operation that requires a plurality of cycles to execute the operation and is not referred to from the outside,
The switching stage is a time before the plurality of cycles before the time specified by the abnormality detection unit,
When the state of the electronic circuit in the switching stage is reproduced by the simulation unit, the on-chip debug unit performs processing for operating the electronic circuit for one cycle and processing for extracting data in the electronic circuit. Repeat until reaching the time point specified by the abnormality detection unit,
The simulation unit uses the simulation code and the data extracted by the on-chip debug unit to simulate the operation of the electronic circuit from the switching stage to the specified time point.
The circuit design support apparatus according to claim 1, wherein the circuit design support apparatus is a circuit design support apparatus. The simulation unit simulates the operation of the electronic circuit using a first simulation code obtained by converting the first circuit description representing the electronic circuit, and based on the first circuit description. The second simulation code obtained by converting the generated second circuit description is used to simulate the operation of the electronic circuit, the simulation result using the first simulation code, and the second simulation code. It is determined whether or not there is an abnormality in the configuration code by comparing the result of simulation using the simulation code.
The circuit design support apparatus according to claim 2, wherein the circuit design support apparatus is provided. The simulation unit determines that the configuration code is abnormal when the result of the simulation using the first simulation code is the same as the result of the simulation using the second simulation code. To do.
The circuit design support apparatus according to claim 7. An on-chip debug step for operating an electronic circuit mounted on the integrated circuit on the integrated circuit and extracting data in the electronic circuit;
A simulation step for simulating the operation of the electronic circuit using a simulation code representing the electronic circuit;
An abnormality detection unit that detects an operation abnormality of the electronic circuit and identifies an abnormality detection step that detects the operation abnormality; and
In the on-chip debugging step, when the operation abnormality is detected, the on-chip debugging unit re-operates the electronic circuit until a switching stage that is a predetermined number of cycles before the identified time point, and Extracting the data in the electronic circuit,
In the simulation step, the simulation unit reproduces the state of the electronic circuit in the switching stage using the simulation code and the data extracted by the on-chip debugging unit, and then performs the switching after the switching stage. Simulate the operation of electronic circuits,
A circuit design support method characterized by the above. On the computer,
An on-chip debug step for operating an electronic circuit mounted on the integrated circuit on the integrated circuit and extracting data in the electronic circuit;
A simulation step of simulating the operation of the electronic circuit using a simulation code representing the electronic circuit;
An abnormality detection step for detecting an operation abnormality of the electronic circuit and specifying a time point when the operation abnormality is detected, and a program for executing
In the on-chip debugging step, when the operation abnormality is detected, the electronic circuit is re-operated until a switching stage that is a predetermined number of cycles before the specified time, and the data in the electronic circuit is further operated. Extract
In the simulation step, the state of the electronic circuit in the switching stage is reproduced using the simulation code and the data extracted by the on-chip debugging unit, and then the operation of the electronic circuit after the switching stage is performed. To simulate,
The computer-readable recording medium which recorded the program characterized by the above-mentioned.

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