JPWO2010082529A1 - SIMD type parallel data processing apparatus, data sorting method, and processing element - Google Patents

Abstract

Improve sort processing efficiency. When the exchange determination signal generated by the execution of the first subtraction exchange instruction has a predetermined value, the numeric data of the register 12i of the own PE 11i and the numeric data of the register 12i + 1 of the adjacent PE 11i + 1 are exchanged. When the exchange determination signal generated by the execution of the second subtraction exchange instruction has a predetermined value, the numeric data of the register 12i of the own PE 11i and the numeric data of the register 12i-1 of the adjacent PE 11i-1 are exchanged. .

Description

  The present invention relates to a SIMD type parallel data processing device, a data sorting method in a SIMD type parallel data processing device, and a processing element, and more particularly, to a data sorting in a SIMD type parallel data processing device and a SIMD type parallel data processing device with improved sort processing. The present invention relates to a method and a processing element.

  In image processing of video signals and the like, it has been conventionally known to use a SIMD (Single Instruction Multiple Data) type parallel computing device (SIMD type parallel processor). This SIMD type computing device is roughly composed of a plurality of processing elements PE and a control processor. The electrical configuration of the one-dimensional SIMD type parallel computing device is shown in a block diagram as shown in FIG. As a method of setting numerical data one by one for all PEs of a one-dimensional SIMD type parallel computing device and sorting a set of numerical data consisting of the numerical data in ascending or descending order, the so-called “even-even transformation sorting method” is effective. It is known that there is.

When this odd / even transform sort method is applied to a SIMD type parallel computing device to sort a set of numerical data, the number of PEs is n and the input numerical data string S = {x (0), x (1),. , X (n-1)} and x (i) is assigned to PE (i), first, in the first step, each even-numbered PE (i) is the right-hand side PE (i). +1) to x (i + 1), and if x (i)> x (i + 1), PE (i) and PE (i + 1) hold the numeric data x Exchange (i) and x (i + 1).
Next, in the second step, each even-numbered PE (i) excluding the number 0 PE at the leftmost end receives x (i-1) from the PE (i-1) adjacent to the left, and x If (i-1)> x (i), PE (i-1) and PE (i) exchange the held numerical data x (i) and x (i-1).

By repeatedly executing these two steps in succession, after the maximum (n + 1) / 2 iterations, no further exchange of numerical data occurs and the sorting of the input numerical data string S is completed.
FIG. 4 shows an example of sorting in the SIMD type parallel computing device to which the odd / even transform sorting method is applied. This sorting example is an example in which the number of PEs is 7, and the numerical data 7, 6, 5, 4, 3, 2, 1 in descending order are sorted into numerical data in ascending order. The sorting is performed by combining the above two steps. When the sorting operation is regarded as one iteration, numerical data 1, 2, 3, 4, 5, 6, 7 in ascending order is obtained by repeating the iteration.

Non-Patent Document 1 describes a related technique for realizing the above-described two steps (one iteration) in a one-dimensional SIMD type parallel computing device. In this related technology, when each PE can execute processing only with a general instruction set, in order to implement the above-mentioned odd-even transformation sort method in the apparatus, two adjacent PEs are paired in different forms. In addition to being handled as a (pair), a mechanism that allows different operations to be performed within the pair is adopted.
That is, for example, when sorting in ascending order, the first PE receives a small value in the first step, while the right adjacent PE (odd PE) paired with the even PE receives a large value, and the second step Then, while the even number PE receives a large value, the left adjacent PE (odd number PE) paired with the even number PE receives a large value and tries to obtain a predetermined sort. is there.

However, if different operations as described above (the above-mentioned operation A in the first step and operation B in the second step) are performed in the PE pair, the one-dimensional SIMD type parallel operation that operates according to the same instruction stream. In the case of a computing device, generally, using a mask register (mr) that designates a PE as inoperable (hereinafter, mr = 1 represents an operation, and mr = 0 represents an inoperative). While the instruction code specifying the operation A is broadcast from the control processor (CP), the instruction specifying the operation B while the mr of one PE is 1 and the mr of the other PE is 0 While the code is broadcast from the CP, the mr of one PE is set to 0 and the mr of the other PE is set to 1.
That is, the value of mr must be changed for each PE, and the instruction codes corresponding to the operations A and B must be broadcast from the CP.

More specifically, regarding the related technology described in Non-Patent Document 1, the following seven sequences will be followed to perform the processing of the first step and the second step described above. The seven sequences are as follows.
In the first sequence 1), all PEs transfer the numerical data of the right adjacent PE to the own PE, and in the second sequence 2), the numerical data obtained by the transfer in 1) and the numerical data on the own PE. The third sequence 3) sets mr to 1 so that only even PEs are operated. The fourth sequence 4) sets mr = 1 PE (even PE). If the carry flag value of the subtraction result is 1, the numerical data received from the right adjacent PE in 2) is substituted into the numerical data of the own PE. The fifth sequence 5) The sixth sequence 6) of transferring the numerical data and the “logical value of the carry flag value and mr” to the right adjacent PE, inverts mr in all the PEs to inactivate the even PEs, and the odd PEs. The seventh sequence 7) sets the operation and Odd PE was Tsu, in turn if the value of the logical product came transferred to the own PE the above 5) is 1, substitutes the numeric data came transferred at 5) to the self PE numeric data.

By following the above-described sequences 1) to 7), the first step processing in the odd-even conversion sorting method is finally realized.
Similarly, the second step process in the odd-even conversion sort method can also be realized. To do so, replace “right neighbor” in “1) to 7)” with “left neighbor” and “only even PE” in 3) with “even PE excluding the leftmost PE”. It is necessary to configure to follow the sequence of 1) to 7).

  Japanese Patent Application Laid-Open No. 2004-228561 describes related technology regarding a SIMD type microprocessor. In this related technique, in a SIMD type microprocessor having a plurality of processor elements, a first instruction performs a size comparison between data stored in a specific register of each processor element and data stored in an operand-designated source register. The large data of the two data is stored in the specific register, while the small data is stored in the source register or stored in the destination register indicated by the operand other than the source register. The second instruction compares the data stored in the specific register with the data stored in the operand-designated source register, and stores the smaller data of the two data in the specific register. Big de Data is stored in a source register or stored in a destination register indicated by an operand other than the source register, and the sort buffer register of the processor element is used as the source register and destination register for the storage, and the data This relates to a technique for performing the sorting process at a high speed.

JP 2007-102799 A

Akihiro Kyo, "Automotive Video Recognition LSI with 128 4-way VLIW RISC Cores Integrated" IEICE Technical Report, Integrated Circuits Research Group (ICD), May 2003, Vol.103, No. 89, pp.19-24

By the way, in Non-Patent Document 1 described above, if the odd-even transformation sort method is executed in the one-dimensional coupled SIMD type parallel computing device, n numerical data are sorted by maximum (n + 1) / 2 iterations. I can.
However, there is a technical problem that the sorting can be performed only by executing many instructions for each iteration, and the processing time is long and the efficiency is low.
Patent Document 1 adopts a mechanism for sorting a plurality of processor elements for each processor element in a SIMD type microprocessor. What is the relationship with other processor elements in the plurality of processor elements? There is no place to touch.
Therefore, there is still a problem to be solved in improving the efficiency of the sorting process.

  The present invention has been made in view of the above circumstances, and provides a SIMD type parallel data processing device capable of achieving efficient sorting of data to be sorted, a data sorting method in the SIMD type parallel data processing device, and a processing element. It is an object.

  In order to solve the above-mentioned problem, a first configuration of the present invention relates to a SIMD type parallel data processing apparatus for sorting sort target data, and has a storage means for storing sort target data, and is one-dimensionally coupled. Based on the plurality of processing elements, the control information output means for supplying sort control information, and the sort control information input from the control information output means, the processing element of a predetermined one of the plurality of processing elements And a data exchange unit for each processing element for exchanging the sort target data of the storage unit and the sort target data of the storage unit of a predetermined other processing element.

  A second configuration of the present invention relates to a data sorting method in a SIMD type parallel data processing apparatus, receives sort control information from control information output means, and sorts data to be sorted based on the supplied sort control information. It has a storage means for storing, and the sort target data of the storage means of both processing elements is exchanged between predetermined processing elements among a plurality of processing elements that are one-dimensionally coupled.

  A third configuration of the present invention relates to a processing element used in a SIMD type parallel data processing apparatus, and is based on control information input means for receiving sort control information, and the sort control information output from the control information input means. Data for exchanging sort target data set in the storage means of a predetermined processing element among a plurality of processing elements that are one-dimensionally coupled with sort target data set in the storage means of the processing element of its own And an exchange means.

  According to the present invention, since the subtraction exchange instruction is realized by a combination of simple operations with few operations, each step of the odd-even conversion sort method can be implemented in a single machine cycle. Therefore, it is possible to efficiently realize the data sorting process based on the odd / even conversion sorting method while suppressing the increase in hardware cost slightly.

FIG. 1 is a block diagram showing the main part of the electrical configuration of a SIMD type parallel processor according to Embodiment 1 of the present invention. It is a block diagram which shows the whole electric structure of the same SIMD type | mold parallel processor. It is a block diagram of a subtraction logic circuit used in the processing element of the SIMD type parallel processor. It is operation | movement explanatory drawing when the number of processing elements of the same SIMD type | mold parallel processor and the number of sort object data are the same. It is operation | movement explanatory drawing when the number of processing elements of the SIMD type | mold parallel processor which is Embodiment 2 of this invention is smaller than the number of sort object data.

  This application claims priority based on Japanese Patent Application No. 2009-004380 filed on Jan. 13, 2009, the entire disclosure of which is incorporated herein.

Embodiment 1

1 is a block diagram showing the main part of the electrical configuration of a SIMD type parallel processor according to Embodiment 1 of the present invention, FIG. 2 is a block diagram showing the entire electrical configuration of the SIMD type parallel processor, and FIG. FIG. 4 is a block diagram of a subtraction logic circuit used in the processing element of the SIMD type parallel processor, and FIG. 4 is an operation explanatory diagram when the number of processing elements and the number of data to be sorted in the SIMD type parallel processor are the same.
The SIMD type parallel processor 10 of this embodiment relates to an apparatus capable of executing each of the first step and the second step of the odd-even conversion sort method in a single machine cycle, and its main part is as shown in FIG. , And a plurality of processing elements (hereinafter abbreviated as PE) 11 _i (i = 0, 1, 2,..., N) And a control processor (CP) 40 (FIG. 2) that broadcasts instructions to the PE array of these PEs via the inter-PE coupling line 30 (FIG. 2). A subtraction exchange instruction described below is programmed in an instruction set executed by the processor 40, and the execution of the subtraction exchange instruction controls the PE array so as to achieve a predetermined sorting process. Whole is composed of.

The function of the subtraction exchange command is generally as follows. In order to execute the first step in the even-odd conversion sort method described above, if one subtraction exchange instruction is used and exchange decision information (exchange decision bit) xchg = 1 generated by execution of the instruction, the data to be sorted by the own PE is selected. At the same time as updating with the sort target data of the right adjacent PE, the sort target data of the right adjacent PE is updated with the sort target data of the self PE, and then the second step in the even-odd conversion sort method described above is executed. However, if the exchange decision bit xchg = 1 generated by executing another instruction using another subtraction exchange instruction, the data to be sorted by the own PE is updated with the data to be sorted by the PE adjacent to the left, and at the same time, This is to cause an operation of updating the sort target data of the PE with the sort target data of the own PE.
In the subtraction exchange command, operation designation information I and an operation mode flag flg described later are embedded in advance.

Next, each configuration of the PE 11 _i that performs the operation just described will be described.
Each of the PEs 11 _i includes a register (src) 12 _i , a selector 14 _i, and a selector 16 _i . In the following description, i represents an even number.
In addition, the even-numbered PE11 _i is further provided with a subtraction logic circuit 20 _i , an operation mode flag (flg) register 22 _i, and a mask register (mr) 24 _i, while the odd-numbered PE11 _i-1. And PE11 _{i + 1} are further provided with a selector 18 _i-1 and a selector 18 _{i + 1} .

Even-numbered PE11 _i selector 14 _i and subtractor logic circuit 20 _i selector 203 _i (described later), odd-numbered PE11 _i-1 and PE11 _{i + 1} selector 14 _i-1 , selector 14 _{i + 1} , selector 18 _i-1 An operation designation signal (also referred to as an operation designation bit) I is supplied from the control processor 40 via the PE connection line 30 to each selection control input of the selector 18 _{i + 1} .

The output of the selector 16 _i is connected to the register 12 _i of the even-numbered PE 11 _i . The selector 14 _i is connected to the output of the left adjacent PE11 _i-1 (the output of the register 12 _i-1 ) and the output of the right adjacent PE11 _{i + 1} (the output of the register 12 _{i + 1} ). It is configured to be selectively output according to the value of the input operation designation signal I. The selector 16 _i of the even-numbered PE11 _i, register 12 outputs _i and the selector 14 _i is connected, exchange determination signal (exchange decision bit output from the selection control input of the selector 16 _i of the subtraction logic 20 _i also referred) xchg is input as a selection control signal 21 _i, and is configured to measure the register 12 _i or selector 14 _i according to the value of the selection control signal 21 _i is selected and output.

The outputs of the selector 16 _i-1 and the register 16 _{i + 1} are connected to the registers 12 _i-1 and 12 _{i + 1} of the odd-numbered PE11 _i-1 and PE11 _{i + 1} , respectively. The selector 14 _i-1 is connected to the output of the left adjacent PE11 _i-2 (the output of the register 12 _i-2 ) and the output of the right adjacent PE11 _i (the output of the register 12 _i ). It is configured to be selectively output according to the value of the operation designation signal I input thereto. The selector 14 _{i + 1} is connected to the output of the left adjacent PE11 _i (output of the register 12 _i ) and the output of the right adjacent PE11 _{i + 2} (output of the register 12 _{i + 2} ), and one of them is input thereto. The operation designation signal I is selectively output according to the value of the operation designation signal I.

Further, the selection control input of the selectors 16 _i-1 and the selectors 16 _{i + 1} of the odd-numbered PE11 _i-1 and PE11 _{i + 1} is an exchange decision signal output from the selectors 18 _i-1 and 18 _{i + 1. i-1} and selection control signal 19 are supplied as _{i + 1} .
Here, the numerical data output from the register 12 _i-1 is represented by src-left 12L, and the numerical data output from the register 12 _{i + 1} is used to represent by src-right 12R. Also, src-left 12L and src-right 12R are used. In this notation, src-left12L is used for the numerical data of the left PE register and src-right12R is used for the numerical data of the right PE register with reference to the PE of interest.

The selection operation of the selector 14 _i and the selector 16 _i of the even-numbered PE 11 _i is as follows.
For example, if the value of the operation designation bit I is 1, the selector 14 _i selects and outputs the src-right 12R, and if the value of the operation designation bit I is 0, selects the src-left 12L.
The selector 16 _i, for example, if the value of the selection control signal 21 _i is 0, updates the register 12 _i selects and outputs the numerical data of the selector 14 _i to the register 12 _i, also, the selection control signal 21 the value of _i is 1, then selectively outputs the numerical data of the register 12 _i to the register 12 _i, i.e. the update is not performed.
The selection operation of the selector 14 _i and the selector 16 _i of the even-numbered PE 11 _i applies equally to the odd-numbered selector 14 _i−1 , selector 14 _{i + 1,} selector 16 _i−1 , and selector 16 _{i + 1.} .

The selection operation of the selector 18 _i-1 and the selector 18 _{i +} of the PE11 _i-1 and PE11 _{i + 1} is as follows.
The selector 18 _i-1 and the selector 18 _{i + 1} are connected to the output of the subtraction logic circuit of the adjacent PEs on both sides, that is, the subtraction logic circuit 20 _i-2 and the subtraction logic circuit 20 _{i + 2} , and according to the value of the operation designation bit I Thus, one of the exchange decision bits xchg-left 20L and xchg-right 20R output from the _two subtraction logic circuits 20 _i-2 and 20 _{i + 2} is selected as a selection control signal 19 _i-1 and a selection control signal 19 _{i + 1.} It is configured to output. For example, if the value of the operation designation bit I is 0, the selector 18 _i-1 and the selector 18 _{i + 1} select and output xchg-right 20R if the value of the operation designation bit I is 1, and select xchg-left 20L if the value of the operation designation bit I is 1, for example. To do.
The selector _{18 i-1} and signal output selected from the selector _{18 i + 1} are each different, the odd selector ₁₆ provided in the PE of _i-1 and the selector _{16 i + 1} of the selection control input to the selection control signal _{19 i- 1} and selection control signal 19 _{i + 1} .

The subtraction logic circuit 20 _i includes numerical data from the register 12 _i and the selector 14 _i , an operation designation bit I, an operation mode flag (flg) and a mask register (mr) 24 from the operation mode flag (flg) register 22 _i. 3 is a circuit that generates an exchange decision signal (bit) xchg based on the mask value from _i . As shown in FIG. 3, a subtraction circuit (SUB) 201 _i , an inverting circuit (NOT) 202 _i , a selector 203 _i , It consists of an exclusive OR circuit (XOR) 204 _i and an AND circuit (AND) 205 _i . The exchange determination signal xchg is used as a selection control signal 21 _i supplied to the selection control input of the selector 16 _i of the own PE 11 _i .

The subtraction circuit 201 _i, the output of the register 12 _i and the selector 14 _i is connected to the selector 203 _i, either one thereof is inputted thereto the output of the subtraction circuit 201 _i and the inversion circuit 202 _i is connected Are configured to be selectively output according to the value of the operation designation bit I. For example, when the operation designation bit I to the selector 203 _i is 1, the output signal (carry flag cf) from the subtraction circuit 201 _i is selected, and when the operation designation signal I is 0, the output from the inverting circuit 202 _i Select the output signal. To the exclusive OR circuit 204 _i, the output of the selector 203 _i and the operation mode flag (flg) register 22 _i is connected to the AND circuit 205 _i, the exclusive OR circuit 204 _i and the mask register (mr) 24 _i outputs are connected. The output signal from the AND circuit 205 _i becomes the exchange determination signal xchg generated by the PE 11 _i .

The operation mode flag (flg) register 22 _i is a register for storing the operation mode flag (flg), and the operation mode flag is a flag indicating a sort type. The operation mode flag (flg) is broadcast to an even number of PEs via the inter-PE coupling line 30 and set in the operation mode flag (flg) register 22 _i when the subtraction exchange command is executed by the control processor 40.
The mask register (mr) 24 _i is set according to the value of the operation designation bit I broadcasted to the even number of PEs via the inter-PE coupling line 30 when the subtraction exchange instruction is executed by the control processor 40. For example, if the value of the operation designation signal I is 1, 1 is automatically set in the mask register (mr) 24 _i of the even PE, whereas if the value of the operation designation signal I is 0, the leftmost mask register 24 ₀ 0 of PE11 ₀ is automatically set, also 1 is automatically set in the mask register 24 _i of other even-PE. The mask value is information for designating the operation / non-operation of the PE.

Next, the operation of this embodiment will be described with reference to FIGS.
The SIMD type parallel processor 10 is configured with 7 PEs, and in the data processing in the SIMD type parallel processor 10, the registers (one of these PEs 11 _i (one of i = 0, 1,..., 6)) ( src) 12 _i It is assumed that numerical data 7, 6, 5, 4, 3, 2, 1 in descending order as shown in FIG. To do. In the following, for convenience, it will be representative of the PE11 ₀ to PE11 ₆ as PE0 to PE6.
In the first subtraction / exchange instruction for performing the first step of the sorting process in the program for performing the data processing, 1 is set as the value of the operation designation signal I, and 0 is set as the value of the operation mode flag flg. It is set in advance. In the second subtraction / exchange instruction for performing the second step of the sorting process, 0 is set in advance as the value of the operation designation signal I, and 0 is set as the value of the operation mode flag flg.
In this first step, 1 is set in advance as the value of the operation designation signal I in the first subtraction / exchange instruction. However, even if 0 is preset as the value of the operation designation signal I, the same result is obtained. Is obtained.

When the first subtraction / exchange instruction is executed, the operation designation signal I of 1 is supplied to each PE, and the operation mode flag flg of 0 is set in the operation mode flag register 22 _i of the even PE _i .
Since the value of the operation designation signal I is 1, 1 is automatically set in the mask register (mr) 24 _i of the even PE.

In the process of Step 1 above, while the numerical data set in the register 12 ₀ PE0 is 7, the value of the operation designating signal is 1, the numerical data output from the selector 14 _0, src- right (= 6) Accordingly, the carry flag cf the subtraction logic 20 ₀ of the subtraction circuit 201 _0-1 are output.
In step 1, the operation mode flag register 22 _0, already have been set operation mode flag flgt of 0, the selector 203 ₀ selects one of the carry flag cf the first operation designation signal I output because it has to, first signal from the exclusive OR circuit 204 ₀ is output. Further, in the step 1, the mask register 24 _0, already from the first mask information mr is set, it outputs the exchange determination signal xchg of 1 from the AND circuit 205 _0.

Subtraction logic circuit 20 ₀ 1 exchange determination signal xchg output from is supplied as a selection control signal 21 ₀ of 1, PE0 to the selector 16 ₀ PE0. Numerical data that selector 16 ₀ which is outputted from the selector 14 _0, and selects and outputs the 6 In this step 1. The numerical data (= 6) is written to the register 12 _0.

On the other hand, the PE1 to the right of the PE0, although the first replacement determination signal xchg from PE0 is input to the selector 18 _1, the value of the operation designating signal I supplied thereto in step 1 is also 1, exchange determination signal xchg be selected by the selector 18 _1, rather than xchg-. right, because selecting xchg-left, a 1 also selection control signal 19 ₁ in PE1. This one selection control signal 19 ₁ is supplied to the selector 16 ₁ . Two numerical data input to the selector 16 _1, the selector 14 src-left output from ₁ (i.e., the numerical data 7 that is set in the register 12 ₀₎ as the numerical data of the register 12 _1. The selector 16 _1, the first selection control signal 19 _1, src-left12L, i.e., selects a numerical data 7. The numerical data 7 is written to the register 12 _1.

On the other hand, in the rightmost PE (PE6 in this example) adjacent to the left of PE0, the 1 exchange decision signal xchg generated in PE0 is xchg-right in the rightmost PE6, but the PE6 operation designation signal since the value of I is also a 1, the selector 18 ₆ in xchg-. right of PE6 is not selected, therefore the value written to the register 12 ₆ PE6 rightmost, depending on the value of the replacement determination signal xchg output from PE0 Is not affected.

The operation of PE2 in step 1 will be described as follows.
One measure is 5 which is set in the register 12 ₂ of PE2, the value of the operation designation signal I is 1, the numerical data output from the selector 14 _2, src-. Right output from PE3 ( = 4). Accordingly, the carry flag cf from the subtraction logic circuit 20 ₂ of the subtracting circuit 201 ₂ 1 is output.
In step 1, the operation mode flag register 22 _2, already, the operation mode flag flgt is set to 0, the selector 203 _2, by operation designation signal I is 1, 1 of the carry flag cf since selected and is output, the first signal from the exclusive OR circuit 204 ₂ is outputted. In step 1, the mask register 24 _2, already from the first mask information mr is set, it outputs the exchange determination signal xchg from the AND circuit 205 ₂ 1.

Subtraction exchange determination signal xchg of 1 output from the logic circuit 20 ₂ is supplied as a selection control signal 21 ₂ 1, PE2 PE2 to the selector 16 _2. That selector 16 _2, by the selection control signal 21 ₂ is 1, the numerical data output from the selector 14 _2, numerical data of the register 12 ₃ in step 1 PE3 (i.e., src-right12R) 4 Select and output. The numerical data (= 4) is written to the register 12 _2.

On the other hand, the PE3 the right of PE2, the value of the operation designating signal I supplied thereto in step 1 is also a 1, exchange determination signal xchg be selected by the selector 18 _3, rather than xchg-. Right, xchg to choose from the -left, it becomes also 1 and selection control signal 19 ₃ in PE3. The first selection control signal 19 ₃ is supplied to the selector 16 _3. At this time, the selector 14 ₃ by the operation designation signal I is 1, src-left input thereto, i.e., selects and outputs the numerical data 5 which is set in the register 12 _2. The selector 16 ₃ selects and outputs the numerical data 5 output from the selector 14 ₃ when the selection control signal 19 ₃ is 1. The numerical data 5 is written in the register 12 _3.

On the other hand, the PE1 to the left of the PE2, exchange determination signal xchg generated by the PE2, although the PE1 in xchg-. Right, because it is 1 the value of the operation designating signal I of PE1, the selector 18 ₁ of PE1 xchg-. right is not selected, therefore the value written to the register 12 ₁ of PE1 is not affected by the value of the exchange determination signal xchg output from PE2.

The operations described for PE0 and PE2 and the left and right adjacent PEs are similarly applied to PE4 and the left and right adjacent PEs in the first subtraction exchange instruction programmed for the processing of step 1. It is generated at the same time in the execution. Therefore, the explanation of each step is omitted.
In the PE6, exchange determination signal xchg will become 1 According to was described PE0 and PE2, therefore, since the selection control signal 21 ₆ to the selector 16 ₆ becomes 1, the register 12 ₆ by the selector 16 ₆ numerical data, where the numerical data 1 is selected is written to the register 12 _6. Numerical data of the register 12 ₆ is not changed.
FIG. 4 shows a state when the process of step 1 in the first iteration is completed. In FIG. 4, the sorting state is shown in the horizontal column indicating the first step (Step 1) in the first iteration (1st iteration). That is, the numerical data held in PE0, PE1, PE2, PE3, PE4, PE5, and PE6 are 6, 7, 4, 5, 2, 3, and 1, respectively.

  Subsequent to the process of step 1 described above, the process of step 2 in the first iteration is started. The second subtraction exchange instruction for this step 2 is placed following the first subtraction exchange instruction in the above-described program. The operation designation signal I set in the second subtraction exchange command is set to 0. The value of the operation mode flag flg is set to 0 like the first subtraction exchange instruction.

Enters step 2 of the process, when the second subtraction replacement instruction is executed by the control processor 40, while numerical data are 6 that has already been set in the register 12 ₀ PE0, the value of the operation specifying signal I since 0, the numerical data output from the selector 14 ₀ becomes src-left output from the rightmost PE (PE6) (= 1) . Accordingly, the carry flag cf the subtraction logic 20 ₀ of the subtraction circuit 201 _0-1 are output.

In the second subtraction replacement instruction, the operation mode flag register 22 _0, already have been set operation mode flag flg of 0, because the value of the operation designating signal I is 0, the selector 203 ₀ 1 carry since selects and outputs an output signal value 0 the inverter circuit 203 ₀ for inverting and outputting the flag cf, exclusive OR circuits 204 ₀ 0 signal (exclusive of 0) is output.

Then, if the value of the operation designating signal I is 0, among the even PE, only PE0 a leftmost PE, the mask register 24 _0, is already set to 0 in the mask information mr Therefore, even if the value of the exclusive OR of the carry flag cf and the operation mode flag flg is 1, the logical product of the exclusive OR and the mask information mr is always 0. Therefore, exchange determination signal xchg subtraction logic circuit 20 ₀ outputs will always be zero.

Exchange determination signal xchg of 0 is supplied to the selector 16 ₀ select control signal 21 ₀ as PE0. That selector 16 ₀ register (src) 12 ₀ numeric is output from the data, wherein selects and outputs 6. Since the numerical data (= 6) is written into the register 12 _0, the numerical data of the register 12 ₀ is not changed.

On the other hand, the PE1 to the right of the PE0, because in the second step is 0 the value of the operation designating signal I supplied thereto, exchange determination signal xchg be selected by the selector 18 _1, rather than xchg-left, since selecting xchg-. right, a 1 also select control signals 21 ₁ in PE1. Generation of the selection control signal 21 ₁ This 1 is also performed in accordance with the place described in step 1.
Since the selection control signal 21 ₁ of 1 is supplied to the selector 16 _1, the selector 16 ₁ selects and outputs the numerical data from the selector 14 _1. Numerical data selected by the selector 14 ₁ is set numeric data in the register 16 ₂ of PE2 in the process of step 1, wherein is 4. The numerical data 4 is written to the register 12 _1.

On the other hand, in the rightmost PE (PE6 in this example) adjacent to the left of PE0, the 0 exchange decision signal xchg generated in PE0 becomes xchg-right in the rightmost PE6, and the operation designation signal I of PE6 is since the value is also 0, xchg-. right of 0 from the selector 18 ₆ PE6 is selected, the selection control signal 21 ₆ of the 0 is supplied to the selector 16 _6. At this time, the selector 14 _6, src-left, i.e., selects and outputs the numerical data 3 in the register 12 _5. Therefore, the PE6 rightmost, numerical data of the register 12 ₅ by the selector 16 _6, where the written therein is supplied 3 is selected and the register 12 _6.

The operation at PE2 occurring in step 2 in the first iteration is described as follows.
While numerical data set in the register 12 ₂ of PE2 is 4, since the value of the operation designating signal I is 0, the numerical data output from the selector 14 _2, src-left output from PE1 ( = 7). Accordingly, the carry flag cf from the subtraction logic circuit 20 ₂ of the subtracting circuit 201 ₂ 0 is output.
In this step 2, the operation mode flag register 22 _2, already, the operation mode flag flg is set to 0, the first signal obtained by inverting the carry flag cf selector 203 ₂ 0 inversion circuit 202 ₂ since selected and is output, the first signal from the exclusive OR circuit 204 ₂ is outputted. In this step 2, the mask register 24 _2, already from the first mask information mr is set, it outputs the exchange determination signal xchg from the AND circuit 205 ₂ 1.

Subtraction exchange determination signal xchg of 1 output from the logic circuit 20 ₂ is supplied as a selection control signal 21 ₂ 1, PE2 PE2 to the selector 16 _2. Also, because there is 0 as an operation designation signal I as described above are supplied to the selector 14 _2, the selector 14 _2, numerical are set in the registers 12 ₁ of PE1 is numeric data src-left data, i.e. , 7 are selected and output.
Therefore, the selector 16 ₂ selects and outputs the numerical data (= 7) which is outputted from the selector 14 _2. The numerical data (= 7) is written to the register 12 _2.

On the other hand, the PE3 the right of PE2, the value of the operation designating signal I supplied thereto in step 2 is also zero, exchange determination signal xchg be selected by the selector 18 _3, rather than xchg-left, xchg Since -right is selected, the operation of PE3 is not affected by the exchange decision signal xchg output from PE2.
As the selection control signal used in PE3, the xchg-right selected as described above, that is, the 0 exchange decision signal processed and output in accordance with the above description is used. At this time, the selector 14 ₃ to choose is a src-. Right. Then, since 0 selection control signal is supplied to the selector 16 _3, numerical data selectively output from the selector 16 _3, src-. Right output from the selector 14 _3, i.e., the numerical values set in the register 12 ₄ Data 2. The numerical data 2 is written to the register 12 _3.

On the other hand, the PE1 to the left of the PE2, exchange determination signal xchg generated by the PE2, although the PE1 in xchg-. Right, because the value of the operation designating signal I of PE1 is 0, the selector 18 ₁ of PE1 with 1 of xchg-. right is selected, even the selector 14 ₁ src-. right, i.e., selects a numerical data set in the register 12 ₂ of PE2 (= 4).
Accordingly, the write value of the register 12 ₁ of the PE1, numerical data (= 4), and the numerical data of the register 12 ₁ is rewritten to 4.

The operations described for PE0, PE1, PE2, and PE3 are also performed simultaneously in the execution of the second subtraction exchange instruction programmed for the processing of step 2 in PE4, PE5, and PE6. Be born. Therefore, the explanation of each one is omitted.
FIG. 4 shows a state when the process of step 2 in the first iteration is completed. The sort state is as shown in the horizontal column in FIG. 4 indicating the second step (Step 2) in the first iteration. That is, the numerical data held in PE0, PE1, PE2, PE3, PE4, PE5, and PE6 are 6, 4, 7, 2, 5, 1, and 3, respectively.

By executing the first iteration described above, the numerical data initially set and held in each PE is exchanged between the PEs.
The same numerical data replacement is performed after the second iteration. As a result of these iterations, in the case of the numerical data example described above, ascending order sort processing is completed in four iterations as shown in FIG. 4, that is, no further numerical data replacement operation may occur. I understand.
The control processor 40 detects this sort state, that is, the numerical data in the registers (src) of all PEs is not changed, and exits from the subtraction exchange instruction issue loop to proceed to the next process of the program being executed. What should I do?

  In the above embodiment, the operation mode flag (flg) is 0, that is, the numerical data is sorted in ascending order. However, the operation mode flag (flg) is 1, that is, the numerical data is in descending order. Since it is obvious from the above description that the data can be sorted, the detailed description thereof will be omitted.

A program process for exiting from the above-described subtraction exchange instruction issue loop will be described below.
The instruction set that can be used in the above SIMD type parallel processor 10 includes an instruction MV for transferring a register value specified by the first operand on the PE to a register specified by the second operand, on the PE, in addition to the subtraction exchange instruction. Instruction SUB which subtracts the register value specified by the first operand and the register value specified by the second operand and stores the result in the register specified by the third operand, and sets the zero flag to 1 if the subtraction result is 0. And an instruction STS for designating an operation for storing 1-bit information obtained as a logical sum over all PEs of condition flag values on the type of PE designated by the first operand in a mask register on the control processor (CP), If the value of the mask register on the control processor is 1, a conditional branch instruction BRNM for specifying an operation for branching if it is 0 and not branching; To require the presence.

In addition to these conditions, the description “..” in the program description means that the instructions on both sides operate in the same cycle, and the part enclosed in / * / * /// Comment after the end of the line. A character string ending with: indicates the address of the occurrence position of the character string. When the same label is designated as an operand of a branch instruction, it means the same address.
Src, orig is an identifier of a register for storing data on the PE, and data equal to the number of PEs to be sorted is stored one by one in the register (src) of each PE, and the control processor Assume that the value of the mask register on the PC is set to 0 in advance. In addition, the value of the operation designation signal I is designated as the first operand for the subtraction exchange instruction (SUBXCHG instruction), and the identifier src of the data register storing the sort target data is designated as the second operand. In this example, since it is assumed that the data to be sorted is sorted in ascending order, it is assumed that 0 is set in the operation mode flag (flg) register.

Next, the example of the program according to the said conditions is described.
AGAIN:
/ * Address A + 0 * / SUBXCHG instruction 1, src. . / * Address A + 1 * / MV src, orig // step1 is executed and the original value of src is saved / * address A + 2 * / SUBXCHG instruction 0, src // step2 is executed / * address A + 3 * / SUBXCHG instruction 1, src. . / * Address A + 4 * / SUB src, orig // step1 is executed and the value of src is compared with the original value / * address A + 5 * / SUBXCHG instruction 0, src. . / * Address A + 6 * / STS% Z // Step 2 is executed and the zero flag of the comparison result is sent to the CP./* Address A + 7 * / SUBXCHG instruction 1, src // step 1 is executed / * Address A + 8 * / BRNM
AGAIN. . / * Address A + 9 * / Execute SUBXCHG instruction 0, src // step2 and send the comparison result zero flag to CP / * Address A + 10 * /

  In the case of this program code, the value of src is copied to the register (orig) by the MV instruction at / * address A + 1 * /. In the loop of / * address A + 3 * / to / * address A + 9 * /, a SUBXCHG instruction is issued 6 times for each iteration, and the number of sort processing iterations is 3 iterations. When the SUB instruction is issued in step 1, the src value and the orig value are the same, that is, whether or not the src value has changed even after one iteration is performed, and the STS instruction is used. When the logical sum over all PEs of the value of the condition flag Z representing the determination result is stored in the mask register on the CP, and the logical sum is 0, that is, when a change occurs in the value of src, / * address A + 8 * When / BRNM is executed, a branch is established, and in the next cycle, the operation jumps to / * address A + 0 * / instead of / * address A + 10 * /.

On the other hand, when the logical sum is 1, that is, when there is no change in the value of src, the process proceeds to / * address A + 10 * / without branching and exits from the loop.
In this way, even during the loop end determination, the subtraction exchange instruction can be issued every cycle. Therefore, the CP end determination process for exiting the loop that repeats the subtraction exchange instruction is minimized to the total number of processing cycles. It can be made to give only the influence of.

  Thus, according to this embodiment, since the subtraction exchange instruction is realized with a simple combination with few operations, the subtraction exchange instruction is not provided. For example, the SIMD described in the above-mentioned “non-patent document” In the above embodiment, each step of the odd / even transform sort method can be implemented in a single machine cycle, while it takes about 7 machine cycles to perform the processing equivalent to the subtraction exchange instruction in the type parallel computing device. Become. Therefore, in the SIMD type parallel computing device having the subtraction / exchange instruction, it is possible to efficiently realize the data sorting process based on the odd-even conversion sorting method while suppressing the increase in hardware cost slightly.

Embodiment 2

FIG. 5 is an operation explanatory diagram when the number of processing elements of the SIMD type parallel processor according to the second embodiment of the present invention is smaller than the number of data to be sorted.
The configuration of this embodiment is greatly different from that of the first embodiment in that the entire sorting process can be accelerated even if the number of data to be sorted is larger than the number of PEs.
The SIMD type parallel processor of this embodiment assigns two or more sort target data to each PE, and performs sort processing for the sort target data “within PE” and “between PEs”. The odd-even conversion sort process is divided into “even-odd conversion sort process”, and the odd-even conversion sort process described in the first embodiment is executed for the latter odd-even conversion sort process so as to achieve high speed of the entire sort process.

  For example, the operation explanatory diagram of FIG. 5 shows an example in which the number of PEs is 7, and 14 pieces of numerical data corresponding to twice the number of PEs are sorted. In the mark (1) in FIG. 5, the data exchange within the same PE (PEinternal) is realized by using the instruction set of the conventional PE array, while (2) and (3) in FIG. In the mark, data exchange between PEs is realized using the data exchange described in the first embodiment. The data exchange indicated by the marks (2) and (3) in FIG. 5 may be performed sequentially or simultaneously.

  According to the data exchange described above, the sort processing based on the odd-even conversion method can be performed at a higher speed than the conventional SIMD type parallel computing device that cannot efficiently exchange data between PEs.

Although the embodiments of the present invention have been described in detail with reference to the drawings, the specific configuration of the present invention is not limited to these embodiments, and the design does not depart from the gist of the present invention. These changes are included in the present invention.
For example, in the first and second embodiments, numerical data has been described as an example of sort target data. However, the present invention is not limited to this, and the present invention is also applied to sorting on other data having data order. Can do.
In the first embodiment and the second embodiment, the example in which the operation designation information I and the operation mode flag flg are embedded in the subtraction exchange instruction in advance has been described. However, a necessary instruction executed before the subtraction exchange instruction is described. The present invention is implemented by holding the setting at the time of execution and setting each information held at the time of execution of the subtraction / exchange instruction to a corresponding storage holding means, for example, a register and using it for the sort processing of the present invention. Is also possible.
In the first and second embodiments, the example in which the operation designation information I, the operation mode flag flg, and the mask value mr are set to 1 or 0 has been described. However, other predetermined values may be used.

  The SIMD type parallel data processing device and the data sorting method and processing element in the SIMD type parallel data processing device disclosed herein can be used for various data processing devices that require data sorting.

10 SIMD type parallel processor (SIMD type parallel data processing device)
11 _{0 to} 11 ₆ processing element 14 _{0 to} 14 ₆ selector (part of data exchange means, first data selection means)
16 _{0 to} 16 ₆ selector (remainder of data exchange means, second data selection means)
20 ₀ , 20 ₂ ,..., 20 ₆ subtraction logic circuit (part of control information output means, second control information supply means)
30 PE connection line (control information input means, first control information supply means)
40 Control processor (the remainder of the control information output means)

Claims (27)

A plurality of processing elements having a storage means for storing data to be sorted and one-dimensionally coupled;
Control information output means for supplying sort control information;
Based on the sort control information input from the control information output means, among the plurality of processing elements, the sort target data in the storage means of the predetermined one processing element and the predetermined other processing element A SIMD type parallel data processing apparatus comprising: a data exchanging unit for each processing element that exchanges the sort target data of the storage unit. A plurality of processing elements having a storage means for storing data to be sorted and one-dimensionally coupled;
Control information output means for supplying sort control information;
Based on the sort control information input from the control information output means, among the plurality of processing elements, the other data to be paired with the data to be sorted in the storage means of the one processing element to be paired. A SIMD type parallel data processing apparatus comprising: a data exchanging unit for each processing element that exchanges data to be sorted in the storage unit of the processing element.   The control information output means includes first control information output means for supplying first sort control information and second control information output means for supplying second sort control information, and the data exchange means includes: A first data selecting unit and a second data selecting unit, wherein the first data selecting unit is a storage unit of the processing element that is paired based on the first sort control information. A means for selecting and outputting any one of the data to be sorted, wherein the second data selection means is configured to select the first data selection means and the processing element of itself based on the second sort control information. A means for selecting the data to be sorted of one of the storage means and supplying the selected data to the storage means of the processing element of its own. SIMD type parallel data processing apparatus according to claim 2, wherein.   4. The first control information output means generates and outputs the first sort control information based on an instruction executed by a control device connected to the plurality of processing elements. The SIMD type parallel data processing device described.   The second control information output means of the even number processing element of the plurality of processing elements outputs the sort target data output from the storage means of its own processing element and the first data selection means. The second sort control information is generated based on the sort target data, the first sort control information, and the third sort control information generated together with the generation of the first sort control information. 4. The SIMD type parallel data processing apparatus according to claim 3, wherein the SIMD type parallel data processing apparatus outputs the data.   The second control information output means of the odd number processing element of the plurality of processing elements is configured to output a second sort based on the second sort control information generated by the processing elements adjacent to the odd number processing element. 4. The SIMD type parallel data processing apparatus according to claim 3, wherein the control information is generated and output.   The first sort control information is operation designation information embedded in advance in a subtraction exchange instruction executed by a control processor that controls the plurality of processing elements, and the third sort control information is the subtraction exchange 6. The SIMD type parallel data processing apparatus according to claim 5, wherein the SIMD type parallel data processing apparatus is an operation mode flag embedded in an instruction in advance and mask information set based on the operation designation information.   The second control information output means includes a subtraction logic circuit, an operation mode flag register, and a mask register. The subtraction logic circuit includes the sort target data output from the first data selection means, The second sort control information based on the data to be sorted in the storage means of the processing element of itself, the operation designation information, the operation mode flag of the operation mode flag register, and the mask information of the mask register 8. The SIMD type parallel data processing apparatus according to claim 7, wherein the SIMD type parallel data processing apparatus is a means for generating and outputting the data.   The mask information in the even number processing elements other than the first even number processing element among the even number processing elements is set as the first predetermined information regardless of the action designation information. The mask information in the first even-numbered processing element among the even-numbered processing elements when the information is predetermined information is set as information different from the first predetermined information. 8. The SIMD type parallel data processing device according to 8. Received the supply of sort control information from the control information output means,
Sorting of the storage means of both processing elements between predetermined processing elements among a plurality of one-dimensionally connected processing elements, having storage means for storing data to be sorted based on the supplied sort control information A data sorting method in a SIMD type parallel data processing device, wherein target data is exchanged. Received the supply of sort control information from the control information output means,
Based on the supplied sort control information, it has a storage means for storing data to be sorted, and one processing element that forms a pair among a plurality of processing elements that are one-dimensionally coupled and the other processing that forms the pair A data sorting method in a SIMD type parallel data processing apparatus, wherein the sort target data in the storage means of both processing elements is exchanged with an element.   The control information output means outputs first and second sort control information, and the one of the storage means of the processing elements that are paired based on the first sort control information. Sort target data is selected and output, and the one sort target data selected and output based on the second sort control information and the pair of the sort means of the storage means of the processing element of its own processing element 12. The data sorting method in the SIMD type parallel data processing apparatus according to claim 11, wherein any one of the data is selected and supplied to the storage means of the processing element of its own.   12. The data sort in the SIMD type parallel data processing device according to claim 11, wherein the first sort control information is generated based on an instruction executed by a control device connected to the plurality of processing elements. Method.   The second sort control information for an even-numbered processing element of the plurality of processing elements includes the sort target data output from the storage unit of the processing element of the self and the first sort control information. Generated based on the sort target data output based on the first sort control information, and the third sort control information generated together with the generation of the first sort control information. The data sorting method in the SIMD type parallel data processing device according to claim 12.   The second sort control information for an odd-numbered processing element among the plurality of processing elements is generated based on the second sort control information generated by the processing elements adjacent to the odd-numbered processing element. The data sorting method in the SIMD type parallel data processing device according to claim 12.   The first sort control information is operation designation information embedded in advance in a subtraction exchange instruction executed by a control processor that controls the plurality of processing elements, and the third sort control information is the subtraction exchange 15. The data sorting method in the SIMD type parallel data processing device according to claim 14, wherein the data is a mask information set based on an operation mode flag embedded in an instruction in advance and the operation designation information.   The second sort control information includes the sort target data output based on the first sort control information, the sort target data of the storage unit of the processing element of itself, the operation designation information, The data sort method in the SIMD type parallel data processing device according to claim 16, wherein the data sort method is generated based on an operation mode flag and mask information.   The mask information in the even number processing elements other than the first even number processing element among the even number processing elements is set as the first predetermined information regardless of the action designation information. 18. The mask information in the first even-numbered processing element among the even-numbered processing elements when the information is predetermined is set as information different from the first predetermined information. Sorting method in the SIMD type parallel data processing apparatus. Control information input means for receiving sort control information;
Based on the sort control information output from the control information input means, the sort target data set in the storage means of the predetermined processing element among the plurality of processing elements that are one-dimensionally coupled, and the processing of the processing apparatus itself. A processing element comprising data exchange means for exchanging data to be sorted set in the storage means of the element. Control information input means for receiving sort control information;
Based on the sort control information output from the control information input means, the sort target data set in the storage means of one of the processing elements that form a pair among the plurality of processing elements that are one-dimensionally combined, and A processing element comprising: data exchange means for exchanging data to be sorted set in the storage means of the other processing element of the pair.   The control information input means includes first control information supply means for supplying first sort control information and second control information supply means for supplying second sort control information, and the data exchange means includes: A first data selecting unit and a second data selecting unit, wherein the first data selecting unit is a storage unit of the processing element that is paired based on the first sort control information. , A means for selecting and outputting any one of the sort target data, wherein the second data selection means is configured to select the first data selection means and the processing of its own based on the second sort control information. A means for selecting the data to be sorted of any one of the storage means of an element and supplying the selected data to the storage means of the processing element of its own; Processing element of claim 20, wherein.   21. The first control information input unit receives the first sort control information generated based on a command executed by a control device connected to the plurality of processing elements. The processing element described.   When the processing element is an even-numbered processing element among the plurality of processing elements, the second control information supply means of the even-numbered processing element is configured to output the sort output from the storage means of its own processing element. Target data, the sort target data output from the first data selection means, the first sort control information, and the third sort control information generated together with the generation of the first sort control information; 23. The processing element according to claim 21, wherein the second sort control information is generated and output based on the information.   When the processing element is an odd processing element of the plurality of processing elements, the second control information supply means of the odd processing element is generated by the processing element on both sides of the odd processing element. The processing element according to claim 21, wherein the second sort control information is generated and output based on the second sort control information.   The first sort control information is operation designation information embedded in advance in a subtraction exchange instruction executed by a control processor that controls the plurality of processing elements, and the third sort control information is the subtraction exchange 24. The processing element according to claim 23, wherein the processing element is mask information set based on an operation mode flag embedded in an instruction in advance and the operation designation information.   The second control information supply unit includes a subtraction logic circuit, an operation mode flag register, and a mask register. The subtraction logic circuit includes the sort target data output from the first data selection unit, The second sort control information based on the data to be sorted in the storage means of the processing element of itself, the operation designation information, the operation mode flag of the operation mode flag register, and the mask information of the mask register 26. The processing element according to claim 25, wherein the processing element is a means for generating and outputting the data.   The mask information in the even number processing elements other than the first even number processing element among the even number processing elements is set as the first predetermined information regardless of the action designation information. 27. The mask information in the first even processing element among the even processing elements when the information is predetermined information is set as information different from the first predetermined information. The processing element described.

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