JPWO2009098831A1 - Manufacturing method of electronic component device - Google Patents

Manufacturing method of electronic component device Download PDF

Info

Publication number
JPWO2009098831A1
JPWO2009098831A1 JP2009552394A JP2009552394A JPWO2009098831A1 JP WO2009098831 A1 JPWO2009098831 A1 JP WO2009098831A1 JP 2009552394 A JP2009552394 A JP 2009552394A JP 2009552394 A JP2009552394 A JP 2009552394A JP WO2009098831 A1 JPWO2009098831 A1 JP WO2009098831A1
Authority
JP
Japan
Prior art keywords
electronic component
electrode
metal nanoparticle
nanoparticle paste
resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2009552394A
Other languages
Japanese (ja)
Other versions
JP5182296B2 (en
Inventor
達弥 舟木
達弥 舟木
宗一 久米
宗一 久米
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Murata Manufacturing Co Ltd
Original Assignee
Murata Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Murata Manufacturing Co Ltd filed Critical Murata Manufacturing Co Ltd
Priority to JP2009552394A priority Critical patent/JP5182296B2/en
Publication of JPWO2009098831A1 publication Critical patent/JPWO2009098831A1/en
Application granted granted Critical
Publication of JP5182296B2 publication Critical patent/JP5182296B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293Organic, e.g. plastic
    • H01L23/295Organic, e.g. plastic containing a filler
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/321Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05573Single external layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624Aluminium [Al] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644Gold [Au] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061Disposition
    • H01L2224/06102Disposition the bonding areas being at different heights
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/113Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1131Manufacturing methods by local deposition of the material of the bump connector in liquid form
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/13198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/13199Material of the matrix
    • H01L2224/13294Material of the matrix with a principal constituent of the material being a liquid not provided for in groups H01L2224/132 - H01L2224/13291
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/13198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/13298Fillers
    • H01L2224/13299Base material
    • H01L2224/133Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13338Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13339Silver [Ag] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/13198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/13298Fillers
    • H01L2224/13299Base material
    • H01L2224/133Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13338Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13344Gold [Au] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/13198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/13298Fillers
    • H01L2224/13299Base material
    • H01L2224/133Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13338Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13347Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/13198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/13298Fillers
    • H01L2224/13299Base material
    • H01L2224/133Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13338Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13355Nickel [Ni] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141Disposition
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81053Bonding environment
    • H01L2224/81054Composition of the atmosphere
    • H01L2224/81055Composition of the atmosphere being oxidating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119Arrangement of the bump connectors prior to mounting
    • H01L2224/81191Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119Arrangement of the bump connectors prior to mounting
    • H01L2224/81192Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119Arrangement of the bump connectors prior to mounting
    • H01L2224/81193Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119Arrangement of the bump connectors prior to mounting
    • H01L2224/81194Lateral distribution of the bump connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812Applying energy for connecting
    • H01L2224/81201Compression bonding
    • H01L2224/81203Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818Bonding techniques
    • H01L2224/8184Sintering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00013Fully indexed content
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01004Beryllium [Be]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01005Boron [B]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01047Silver [Ag]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/0105Tin [Sn]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01082Lead [Pb]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/02Fillers; Particles; Fibers; Reinforcement materials
    • H05K2201/0203Fillers and particles
    • H05K2201/0242Shape of an individual particle
    • H05K2201/0257Nanoparticles
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621Components characterised by their electrical contacts
    • H05K2201/10674Flip chip
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/11Treatments characterised by their effect, e.g. heating, cooling, roughening
    • H05K2203/1131Sintering, i.e. fusing of metal particles to achieve or improve electrical conductivity

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

生産性が高く、コストを低減することができ、安定した品質をもって、配線基板上にチップ部品が実装された電子部品装置を製造する方法を提供するために、金属ナノ粒子ペースト(1)を基板側電極(23)に付与し、配線基板(22)とチップ部品(26)とを位置合わせした状態で、荷重(30)を加え、それによって、金属ナノ粒子ペースト(1)を圧縮変形限界厚(31)まで圧縮変形させ、次いで、金属ナノ粒子ペースト(1)を加熱することより、金属ナノ粒子を焼結させた接合焼結体(6)を得、それによって、基板側電極(23)とチップ側電極(27)とを互いに接合させる。In order to provide a method for manufacturing an electronic component device in which a chip component is mounted on a wiring board with high quality, which can reduce cost and have a stable quality, a metal nanoparticle paste (1) is used as a substrate. A load (30) is applied to the side electrode (23) and the wiring substrate (22) and the chip component (26) are aligned, thereby applying the metal nanoparticle paste (1) to the compression deformation limit thickness. The bonded sintered body (6) in which the metal nanoparticles are sintered is obtained by compressing and deforming to (31) and then heating the metal nanoparticle paste (1), whereby the substrate-side electrode (23) And the chip side electrode (27) are joined to each other.

Description

この発明は、各々の電極が互いに接合された複数の電子部品からなる電子部品装置の製造方法に関するもので、特に、電極間の接合のために金属ナノ粒子を含む金属ナノ粒子ペーストが用いられる、電子部品装置の製造方法に関するものである。   The present invention relates to a method for manufacturing an electronic component device including a plurality of electronic components in which each electrode is bonded to each other, and in particular, a metal nanoparticle paste containing metal nanoparticles is used for bonding between electrodes. The present invention relates to a method for manufacturing an electronic component device.

近年、電子機器の小型化に伴って、半導体パッケージに対する高集積化の要求がますます強まってきている。半導体パッケージを配線基板に実装および固定して電気的な導通を得るようにした実装技術においても、さらに高集積度かつ高密度のものが要求されている。   In recent years, with the miniaturization of electronic devices, there has been an increasing demand for higher integration of semiconductor packages. Even in a mounting technique in which a semiconductor package is mounted and fixed on a wiring board to obtain electrical continuity, a higher integration and higher density are required.

このため、半導体パッケージの裏面全体に電極としてはんだボールを格子状に配列するようにした、いわゆるBGA(Ball Grid Array)による接合方式が注目され、実用に供されている。このBGA方式の半導体パッケージは、上記のように裏面全体に電極を配置するので、半導体パッケージにおける単位面積あたりの電極数を増やすことができ、その結果、高密度実装や実装面積の縮小に多大な効果を発揮させることができる。   For this reason, a so-called BGA (Ball Grid Array) bonding method in which solder balls are arranged in a grid pattern as electrodes on the entire back surface of the semiconductor package has attracted attention and is in practical use. In the BGA type semiconductor package, since the electrodes are arranged on the entire back surface as described above, the number of electrodes per unit area in the semiconductor package can be increased. The effect can be exhibited.

しかしながら、BGA方式を用いた場合、はんだボールの配列ピッチの狭小化に伴って、リフロー時にいわゆるはんだブリッジが生じ、電極間の短絡が発生しやすくなる。これは、はんだを加熱により一旦溶融させ、液状化した後、冷却して凝固させるという過程を経て接合を行なうマイクロソルダリングには不可避な現象と言える。   However, when the BGA method is used, a so-called solder bridge is generated at the time of reflow as the arrangement pitch of the solder balls is narrowed, and a short circuit between the electrodes is likely to occur. This can be said to be an inevitable phenomenon for micro soldering in which bonding is performed through a process in which solder is once melted by heating, liquefied, then cooled and solidified.

また、複数の必要な電子部品を接合して1つの電子部品装置を製造する際には電子部品の接合を繰り返す毎に、順次、融点のより低いはんだを用いる、いわゆるステップはんだ付けが行なわれるが、このステップはんだ付けを行なう場合、第1ステップのはんだ付けには高温はんだを用いる必要がある。このような高温はんだの実用材料としてはPb−5Sn系が挙げられるが、昨今の環境保全の要求に伴うPb使用に対する規制が厳しくなっており、代替材料の開発が強く望まれている。   In addition, when a plurality of necessary electronic components are joined to manufacture one electronic component device, so-called step soldering using solder having a lower melting point is sequentially performed every time the joining of electronic components is repeated. When performing this step soldering, it is necessary to use high temperature solder for the first step soldering. Pb-5Sn is a practical material for such high-temperature solder, but regulations on the use of Pb in accordance with recent demands for environmental protection have become strict, and the development of alternative materials is strongly desired.

以上のような課題を解決するため、接合材料として、上述したはんだに代えて、図10にその組成を模式的に示した金属ナノ粒子ペーストを用いることが、たとえば特開平9−326416号公報(特許文献1)および特開2004−128357号公報(特許文献2)において提案されている。   In order to solve the above problems, it is possible to use a metal nanoparticle paste whose composition is schematically shown in FIG. 10 instead of the above-described solder as a bonding material, for example, as disclosed in JP-A-9-326416 ( Patent Document 1) and Japanese Patent Application Laid-Open No. 2004-128357 (Patent Document 2).

図10を参照して、金属ナノ粒子ペースト1は、平均粒径が1〜100nmの金属ナノ粒子2と分散剤3と分散媒4とを含むものである。より具体的には、金属ナノ粒子2は、たとえばAu、Ag、Cuなどの導電性金属からなる。分散剤3は、金属ナノ粒子2を構成する金属元素と配位可能なものであり、金属ナノ粒子2を被覆する。分散剤3としては、たとえばアミン系、アルコール系、チオール系のものが用いられる。分散媒4は、分散剤3によって被覆された金属ナノ粒子2を安定に分散させるもので、たとえばトルエン、キシレン、テルピネオール、ミネラルスピリット、デカノール、テトラデカンなどの有機溶剤が用いられる。図示しないが、金属ナノ粒子ペースト1は、たとえば特開2002−299833号公報(特許文献3)に記載されるようなバインダ成分や還元剤などの添加物を含んでいてもよい。   Referring to FIG. 10, the metal nanoparticle paste 1 includes metal nanoparticles 2 having an average particle diameter of 1 to 100 nm, a dispersant 3, and a dispersion medium 4. More specifically, the metal nanoparticles 2 are made of a conductive metal such as Au, Ag, or Cu, for example. The dispersant 3 is capable of coordinating with the metal element constituting the metal nanoparticle 2 and coats the metal nanoparticle 2. As the dispersant 3, for example, an amine-based, alcohol-based, or thiol-based one is used. The dispersion medium 4 stably disperses the metal nanoparticles 2 coated with the dispersant 3, and for example, an organic solvent such as toluene, xylene, terpineol, mineral spirit, decanol, or tetradecane is used. Although not shown, the metal nanoparticle paste 1 may contain additives such as a binder component and a reducing agent as described in, for example, JP-A-2002-299833 (Patent Document 3).

上記のような金属ナノ粒子ペーストを用いれば、はんだを用いた場合のように、はんだを一旦溶融させた後、凝固させることにより接合するのではないため、前述したはんだボールの配列ピッチの狭小化に伴って、リフロー時にはんだブリッジが生じ、電極間の短絡が発生しやすくなる、といった問題を生じさせにくくすることができる。また、金属ナノ粒子ペーストによれば、環境保全の要求に伴って使用が厳しくされているPbをあえて用いる必要がない。また、金属ナノ粒子ペーストによれば、たとえば100〜300℃といった比較的低温で金属ナノ粒子を焼結させて接合部を形成することができ、一旦焼結した金属ナノ粒子の焼結体は、金属ナノ粒子を構成する金属の融点に達するまで、その形態が保持される。   If the metal nanoparticle paste as described above is used, the solder balls are not melted and then joined by solidification, as in the case of using solder. Accordingly, it is possible to make it difficult to cause a problem that a solder bridge is generated during reflow and a short circuit between the electrodes is likely to occur. Moreover, according to the metal nanoparticle paste, it is not necessary to dare to use Pb, which has been strictly used in accordance with environmental protection requirements. Further, according to the metal nanoparticle paste, the metal nanoparticle can be sintered at a relatively low temperature such as 100 to 300 ° C. to form a joint portion. The form is maintained until the melting point of the metal constituting the metal nanoparticle is reached.

これらのことから、金属ナノ粒子ペーストを用いれば、環境負荷を小さくすることができるとともに、いわゆるステップはんだ付けに相当する電子部品の接合の繰り返しを1種類の金属ナノ粒子ペーストだけで問題なく実施することができ、また、接合信頼性の高い電子部品装置を得ることができる。   For these reasons, if the metal nanoparticle paste is used, the environmental load can be reduced, and the repetitive joining of electronic components corresponding to so-called step soldering can be carried out without problems with only one type of metal nanoparticle paste. In addition, an electronic component device with high bonding reliability can be obtained.

次に、上述のような金属ナノ粒子ペーストを用いたフリップチップ接続を実施して得られる電子部品の製造方法の一例について説明する。   Next, an example of a method for manufacturing an electronic component obtained by performing flip chip connection using the metal nanoparticle paste as described above will be described.

まず、図11(1)に示すように、配線基板11が用意される。配線基板11上には、いくつかの基板側電極12およびレジスト膜13が形成されている。レジスト膜13の一部は、基板側電極12の周縁部上に乗り上げるように形成され、それによって、基板側電極12の周囲にはダム14が形成される。基板側電極12上には、金属ナノ粒子ペースト1が付与される。   First, as shown in FIG. 11A, a wiring board 11 is prepared. On the wiring substrate 11, several substrate-side electrodes 12 and a resist film 13 are formed. A part of the resist film 13 is formed so as to run on the peripheral edge of the substrate-side electrode 12, whereby a dam 14 is formed around the substrate-side electrode 12. The metal nanoparticle paste 1 is applied on the substrate side electrode 12.

他方、図11(2)に示すように、配線基板11上にフリップチップ実装されるべきチップ部品15が用意される。チップ部品15は、前述した基板側電極12にそれぞれ電気的に接続されるいくつかのチップ側電極16を有している。また、チップ部品15の、チップ側電極16が形成された面上には、パッシベーション膜17が形成される。パッシベーション膜17の一部は、チップ側電極16の周縁部上に乗り上げるように形成され、それによって、チップ側電極16の周囲にダム18が形成される。   On the other hand, as shown in FIG. 11B, a chip component 15 to be flip-chip mounted on the wiring board 11 is prepared. The chip component 15 has several chip-side electrodes 16 that are electrically connected to the substrate-side electrodes 12 described above. A passivation film 17 is formed on the surface of the chip component 15 on which the chip-side electrode 16 is formed. A part of the passivation film 17 is formed so as to run on the peripheral edge of the chip-side electrode 16, thereby forming a dam 18 around the chip-side electrode 16.

次に、同じく図11(2)に示すように、金属ナノ粒子ペースト1を互いの間に介在させた状態で、基板側電極12と関連のチップ側電極16とが互いに対向するように、配線基板11とチップ部品15とが互いに位置合わせされる。   Next, as also shown in FIG. 11 (2), in the state in which the metal nanoparticle paste 1 is interposed between the substrate side electrode 12 and the related chip side electrode 16 so as to face each other, The substrate 11 and the chip component 15 are aligned with each other.

次に、図11(3)に示すように、たとえばチップ部品15側から荷重19が与えられる。これによって、金属ナノ粒子ペースト1が圧縮変形する。   Next, as shown in FIG. 11 (3), a load 19 is applied from the chip component 15 side, for example. Thereby, the metal nanoparticle paste 1 is compressed and deformed.

次に、加熱工程が実施される。これによって、金属ナノ粒子ペースト1に含まれる分散剤3および分散媒4等が除去されるとともに、金属ナノ粒子2(図10参照)が焼結する。その結果、図11(4)に示すように、金属ナノ粒子ペースト1に由来する接合焼結体6が形成され、この接合焼結体6によって基板側電極12とチップ側電極16とが互いに接合される。   Next, a heating step is performed. Thereby, the dispersant 3 and the dispersion medium 4 contained in the metal nanoparticle paste 1 are removed, and the metal nanoparticles 2 (see FIG. 10) are sintered. As a result, as shown in FIG. 11 (4), a bonded sintered body 6 derived from the metal nanoparticle paste 1 is formed, and the substrate-side electrode 12 and the chip-side electrode 16 are bonded to each other by the bonded sintered body 6. Is done.

このようにして、目的とする電子部品装置20が得られる。   Thus, the target electronic component device 20 is obtained.

しかしながら、上述したような電子部品装置20の製造方法には、次のような解決されるべき課題がある。   However, the manufacturing method of the electronic component device 20 as described above has the following problems to be solved.

まず、はんだボールを適用する場合とは異なり、電子部品装置20における接合焼結体6の高さを調整するためには、図11(3)の工程において、金属ナノ粒子ペースト1の高さを調整しなければならない。このような接合焼結体6の高さの調整を精度良く行なうためには、荷重19を精度良く制御する必要がある。しかしながら、荷重19の精度を高めることとチップ部品15の搭載タクトを向上させることとはトレードオフの関係にあるため、荷重19の精度を高めると、生産性低下およびコストアップを招くことになる。   First, unlike the case where solder balls are applied, in order to adjust the height of the bonded sintered body 6 in the electronic component device 20, the height of the metal nanoparticle paste 1 is set in the step of FIG. Must be adjusted. In order to adjust the height of the bonded sintered body 6 with high accuracy, it is necessary to control the load 19 with high accuracy. However, since increasing the accuracy of the load 19 and improving the mounting tact of the chip component 15 are in a trade-off relationship, increasing the accuracy of the load 19 causes a reduction in productivity and an increase in cost.

また、配線基板11には、しばしば、反りやうねりが生じていて、複数の基板側電極12間で高さのばらつきが生じていることがある。このような場合、金属ナノ粒子ペースト1の付与厚みが十分でないと、図11(3)の工程において、最も高い位置にある基板側電極12においては良好な接合状態が得られても、最も低い位置にある基板側電極12では十分な接合状態が達成されないという問題が生じることがある。
特開平9−326416号公報 特開2004−128357号公報 特開2002−299833号公報
Further, the wiring substrate 11 is often warped or undulated, and there may be variations in height among the plurality of substrate-side electrodes 12. In such a case, if the applied thickness of the metal nanoparticle paste 1 is not sufficient, the substrate-side electrode 12 located at the highest position is the lowest in the step of FIG. There may be a problem that a sufficient bonding state is not achieved with the substrate-side electrode 12 in the position.
Japanese Patent Laid-Open No. 9-326416 JP 2004-128357 A JP 2002-299833 A

そこで、この発明の目的は、上述したような課題を解決し得る、電子部品の製造方法を提供しようとすることである。   Therefore, an object of the present invention is to provide an electronic component manufacturing method that can solve the above-described problems.

この発明は、第1の電極を有する第1の電子部品および第2の電極を有する第2の電子部品を用意する工程と、平均粒径が1〜100nmの金属ナノ粒子と分散剤と分散媒とを含む金属ナノ粒子ペーストを用意する工程と、第1の電極および第2の電極の少なくとも一方に、金属ナノ粒子ペーストを付与する、ペースト付与工程と、金属ナノ粒子ペーストを互いの間に介在させた状態で、第1の電極と第2の電極とが互いに対向するように、第1の電子部品と第2の電子部品とを互いに位置合わせする工程と、第1の電子部品と第2の電子部品とを互いに近接させる方向に荷重を加え、それによって、第1の電極と第2の電極との間にある金属ナノ粒子ペーストを圧縮変形させる工程と、次いで、金属ナノ粒子ペーストに含まれる分散剤および分散媒を除去できる温度以上、かつ金属ナノ粒子を構成する金属の融点未満の温度で加熱することにより、金属ナノ粒子を焼結させ、それによって、第1の電極と第2の電極とを互いに接合させる工程とを備える、電子部品装置の製造方法に向けられるものであって、上述した技術的課題を解決するため、次のような構成を備えることを特徴としている。   The present invention provides a step of preparing a first electronic component having a first electrode and a second electronic component having a second electrode, metal nanoparticles having an average particle diameter of 1 to 100 nm, a dispersant, and a dispersion medium A metal nanoparticle paste comprising: a metal nanoparticle paste applied to at least one of the first electrode and the second electrode; and a metal nanoparticle paste interposed between each other The first electronic component and the second electronic component are aligned with each other so that the first electrode and the second electrode are opposed to each other in the state where the first electronic component and the second electrode are in contact with each other; A step of compressing and deforming the metal nanoparticle paste between the first electrode and the second electrode by applying a load in a direction in which the electronic components of the metal component are brought close to each other, and then included in the metal nanoparticle paste Dispersants and The metal nanoparticles are sintered by heating at a temperature above the temperature at which the dispersion medium can be removed and less than the melting point of the metal constituting the metal nanoparticles, thereby causing the first electrode and the second electrode to adhere to each other. The present invention is directed to a method for manufacturing an electronic component device including a bonding step, and is characterized by having the following configuration in order to solve the technical problem described above.

すなわち、第1の電極と第2の電極との間にある金属ナノ粒子ペーストを圧縮変形させる工程において、金属ナノ粒子ペーストを圧縮変形限界厚まで圧縮変形させることを特徴としている。   That is, in the step of compressively deforming the metal nanoparticle paste between the first electrode and the second electrode, the metal nanoparticle paste is compressively deformed to the compression deformation limit thickness.

第1の電子部品が複数の第1の電極を有し、第2の電子部品が複数の第2の電極を有し、第1の電子部品と第2の電子部品とを互いに位置合わせしたとき、互いに対向する各第1の電極と各第2の電極とのそれぞれの間隔が互いに等しくないものを含む場合、ペースト付与工程において付与される金属ナノ粒子ペーストの厚みは、間隔の最大のものと最小のものとの間の差を圧縮変形限界厚に加えた厚み以上とされることが好ましい。   When the first electronic component has a plurality of first electrodes, the second electronic component has a plurality of second electrodes, and the first electronic component and the second electronic component are aligned with each other When the distance between each first electrode and each second electrode facing each other includes ones that are not equal to each other, the thickness of the metal nanoparticle paste applied in the paste application step is the maximum distance It is preferable that the difference from the minimum thickness is equal to or greater than the thickness obtained by adding the compression deformation limit thickness.

第1の電極の周囲および/または第2の電極の周囲には、金属ナノ粒子ペーストの広がりを防止するためのダムが形成されることが好ましい。   It is preferable that a dam for preventing the metal nanoparticle paste from spreading is formed around the first electrode and / or the second electrode.

この発明に係る電子部品装置の製造方法は、ラミネート封止用の未硬化状態のシート状樹脂を用意する工程と、第1の電極と第2の電極とを互いに接合させる工程の後、第1の電子部品および第2の電子部品のいずれか一方を、未硬化状態のシート状樹脂で覆う工程と、未硬化状態のシート状樹脂を第1の電子部品および第2の電子部品に向かって加圧する工程と、未硬化状態のシート状樹脂を硬化させる工程とをさらに備えていてもよい。   In the method for manufacturing an electronic component device according to the present invention, after the step of preparing an uncured sheet-shaped resin for laminate sealing and the step of bonding the first electrode and the second electrode together, Covering one of the electronic component and the second electronic component with an uncured sheet-like resin, and adding the uncured sheet-like resin toward the first electronic component and the second electronic component. A step of pressing and a step of curing the uncured sheet-like resin may be further provided.

上述の場合、シート状樹脂は、粒径が所定の寸法以下に揃えられたフィラーを含み、未硬化状態のシート状樹脂を加圧する工程において、第1の電子部品および第2の電子部品のいずれか一方を覆うシート状樹脂の最も薄い部分での厚みがフィラーの粒径によって支配されるように、シート状樹脂が加圧制御されることが好ましい。   In the case described above, the sheet-like resin includes a filler whose particle size is equal to or smaller than a predetermined dimension, and in the step of pressing the uncured sheet-like resin, any of the first electronic component and the second electronic component is used. It is preferable that the pressure of the sheet-shaped resin is controlled so that the thickness at the thinnest part of the sheet-shaped resin covering either of them is governed by the particle size of the filler.

また、この発明に係る電子部品装置の製造方法は、アンダーフィル封止用の未硬化状態の樹脂を用意する工程と、第1の電極と第2の電極とを互いに接合させる工程の後、第1の電子部品と第2の電子部品のうち、面積がより小さい方の電子部品の少なくとも周囲に未硬化状態の樹脂を付与する工程と、未硬化状態の樹脂を硬化させる工程とをさらに備えていてもよい。   The method of manufacturing an electronic component device according to the present invention includes a step of preparing an uncured resin for underfill sealing, a step of bonding the first electrode and the second electrode to each other, Of the first electronic component and the second electronic component, the method further includes the step of applying an uncured resin around at least the periphery of the smaller electronic component and the step of curing the uncured resin. May be.

この発明によれば、第1の電子部品と第2の電子部品とを互いに近接させる方向に荷重を加え、それによって、第1の電極と第2の電極との間にある金属ナノ粒子ペーストを圧縮変形させる工程において、金属ナノ粒子ペーストを圧縮変形限界厚まで圧縮変形させるため、荷重の制御を精度良く行なう必要がない。したがって、この圧縮変形させる工程の能率化を図れ、その結果、電子部品装置の生産性向上および低コスト化を実現することができる。   According to the present invention, a load is applied in a direction in which the first electronic component and the second electronic component are brought close to each other, whereby the metal nanoparticle paste between the first electrode and the second electrode is applied. In the step of compressing and deforming, the metal nanoparticle paste is compressively deformed to the compressive deformation limit thickness, so that it is not necessary to accurately control the load. Therefore, it is possible to improve the efficiency of the compressing and deforming step, and as a result, it is possible to improve the productivity and reduce the cost of the electronic component device.

また、上述の圧縮変形させる工程において、金属ナノ粒子ペーストを圧縮変形限界厚まで圧縮変形させるので、金属ナノ粒子を焼結させて得られる接合焼結体の高さを最大限低くすることができる。その結果、電子部品装置の低背化が可能となる。   Further, in the above-described compression deformation step, the metal nanoparticle paste is compressively deformed to the compression deformation limit thickness, so that the height of the bonded sintered body obtained by sintering the metal nanoparticles can be minimized. . As a result, the height of the electronic component device can be reduced.

また、圧縮変形させる工程において、金属ナノ粒子ペーストを圧縮変形限界厚まで圧縮変形させるため、この工程を終えたとき、金属ナノ粒子ペーストの密度が最高の状態になっていることになる。したがって、金属ナノ粒子ペーストを加熱して得られる接合焼結体を高強度かつ低抵抗なものとすることができる。その結果、第1の電極と第2の電極との間で高強度かつ低抵抗な接合部を形成した電子部品装置を得ることができる。   Further, in the step of compressing and deforming, the metal nanoparticle paste is compressively deformed to the compressive deformation limit thickness, and therefore, the density of the metal nanoparticle paste is in the highest state when this step is finished. Therefore, the bonded sintered body obtained by heating the metal nanoparticle paste can have high strength and low resistance. As a result, an electronic component device in which a high strength and low resistance joint is formed between the first electrode and the second electrode can be obtained.

この発明において、たとえば、チップ部品を搭載する配線基板側に反りやうねりがある場合などのように、第1の電子部品と第2の電子部品とを互いに位置合わせしたとき、互いに対向する複数の第1の電極の各々と複数の第2の電極の各々とのそれぞれの間隔が互いに等しくないものを含む場合であっても、ペースト付与工程において付与される金属ナノ粒子ペーストの厚みが、上記間隔の最大のものと最小のものとの間の差を圧縮変形限界厚に加えた厚みとされると、すべての第1の電極と第2の電極との間で良好な接合状態を確実に得ることができる。   In the present invention, for example, when the first electronic component and the second electronic component are aligned with each other, such as when there is a warp or undulation on the side of the wiring board on which the chip component is mounted, a plurality of facing each other Even when each of the first electrodes and each of the plurality of second electrodes includes a case where the intervals are not equal to each other, the thickness of the metal nanoparticle paste applied in the paste applying step is equal to the above interval. If the difference between the maximum and minimum values of the thickness is the thickness obtained by adding the compression deformation limit thickness, it is possible to reliably obtain a good bonding state between all the first electrodes and the second electrodes. be able to.

第1の電極の周囲および/または第2の電極の周囲に、金属ナノ粒子ペーストの広がりを防止するためのダムが形成されていると、圧縮変形させる工程において、金属ナノ粒子ペーストを容易かつ確実に圧縮変形限界厚まで圧縮変形させることができる。   If a dam is formed around the first electrode and / or around the second electrode to prevent the metal nanoparticle paste from spreading, the metal nanoparticle paste can be easily and reliably formed in the compression deformation process. Can be compressed and deformed up to the compression deformation limit thickness.

また、この発明によれば、金属ナノ粒子ペーストを圧縮変形限界厚まで圧縮変形させるので、この圧縮変形に際して及ぼされる荷重がばらついても、このばらつきが接合部を構成する接合焼結体の高さに影響を及ぼすことはなく、それゆえ、第1の電子部品と第2の電子部品との間隔をばらつかないようにすることができる。   In addition, according to the present invention, the metal nanoparticle paste is compressively deformed to the compressive deformation limit thickness. Therefore, even if the load exerted upon the compressive deformation varies, this variation causes the height of the bonded sintered body constituting the bonded portion. Therefore, the distance between the first electronic component and the second electronic component can be kept from varying.

上記の利点は、第1の電子部品と第2の電子部品との間での接合信頼性および耐湿性を向上させるために、アンダーフィル封止が施される場合において、次のような利点をもたらす。アンダーフィル封止が施される場合、アンダーフィル封止用の樹脂のはみ出しをより少なくすることが求められる。この樹脂のはみ出し量に影響する因子は、第1の電子部品と第2の電子部品との間隔と、樹脂の供給量とである。この発明によれば、第1の電子部品と第2の電子部品との間隔が上述のように安定しているので、樹脂のはみ出しを少なくするためには、樹脂の供給量の制御だけを行なえばよいことになり、結果的に、樹脂のはみ出しを少なくすることが容易である。   The above-described advantages are as follows when underfill sealing is applied in order to improve the bonding reliability and moisture resistance between the first electronic component and the second electronic component. Bring. When underfill sealing is performed, it is required to reduce the protrusion of the resin for underfill sealing. Factors affecting the amount of protrusion of the resin are the distance between the first electronic component and the second electronic component, and the amount of resin supplied. According to the present invention, since the distance between the first electronic component and the second electronic component is stable as described above, in order to reduce the protrusion of the resin, it is only possible to control the supply amount of the resin. As a result, it is easy to reduce the protrusion of the resin.

この発明において、電子部品装置がラミネート封止される場合、未硬化状態のシート状樹脂を加圧することが行なわれるが、第1の電子部品および第2の電子部品のいずれか一方を覆うシート状樹脂の最も薄い部分での厚みが、シート状樹脂に含まれるフィラーの粒径によって支配されるように、シート状樹脂が加圧制御されると、シート状樹脂を硬化させた段階で得られる電子部品の高さを高精度に制御することが容易である。   In the present invention, when the electronic component device is laminated and sealed, the uncured sheet-like resin is pressurized, and the sheet-like shape covers either the first electronic component or the second electronic component. When the pressure of the sheet resin is controlled so that the thickness at the thinnest part of the resin is governed by the particle size of the filler contained in the sheet resin, the electrons obtained at the stage of curing the sheet resin It is easy to control the height of the component with high accuracy.

この発明の第1の実施形態を説明するためのもので、電子部品装置21を製造するための工程を順次示す図である。BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a view for sequentially explaining steps for manufacturing an electronic component device 21 for explaining a first embodiment of the present invention; この発明の特徴となる金属ナノ粒子ペーストの圧縮変形限界厚を説明するためのもので、荷重と金属ナノ粒子ペーストの高さとの関係を示す図である。It is a figure for demonstrating the compression deformation limit thickness of the metal nanoparticle paste which becomes the characteristics of this invention, and is a figure which shows the relationship between a load and the height of a metal nanoparticle paste. 図2と同様、圧縮変形限界厚を説明するためのもので、金属ナノ粒子ペーストの高さと径との関係を示す図である。It is a figure for demonstrating compression deformation limit thickness similarly to FIG. 2, and is a figure which shows the relationship between the height and diameter of a metal nanoparticle paste. この発明の第2の実施形態による電子部品装置34を示す、図1(4)に相当する図である。It is a figure equivalent to FIG.1 (4) which shows the electronic component apparatus 34 by 2nd Embodiment of this invention. この発明の第3の実施形態による電子部品装置38を示す、図1(4)に相当する図である。It is a figure equivalent to FIG.1 (4) which shows the electronic component apparatus 38 by 3rd Embodiment of this invention. 図5に示した電子部品装置38に備えるラミネート樹脂39を形成するために実施される工程を示す図である。It is a figure which shows the process implemented in order to form the laminate resin 39 with which the electronic component apparatus shown in FIG. 5 is equipped. 図5の部分Aに相当する部分を拡大して示す図であり、ラミネート樹脂39となる未硬化状態のシート状樹脂40に含まれるフィラー43を図解的に示す図である。FIG. 6 is an enlarged view showing a portion corresponding to the portion A in FIG. 5, and is a view schematically showing a filler 43 included in an uncured sheet-like resin 40 that becomes a laminate resin 39. この発明の第4の実施形態による電子部品装置46を示す、図1(4)に相当する図である。It is a figure equivalent to FIG. 1 (4) which shows the electronic component apparatus 46 by 4th Embodiment of this invention. この発明の第5の実施形態を説明するための図1に相当する図である。It is a figure equivalent to FIG. 1 for demonstrating the 5th Embodiment of this invention. この発明において用いられる金属ナノ粒子ペースト1を模式的に示す拡大断面図である。It is an expanded sectional view showing typically metal nanoparticle paste 1 used in this invention. この発明にとって興味ある従来の電子部品装置の製造方法を示す図である。It is a figure which shows the manufacturing method of the conventional electronic component apparatus interesting for this invention.

符号の説明Explanation of symbols

1 金属ナノ粒子ペースト
2 金属ナノ粒子
3 分散剤
4 分散媒
6 接合焼結体
21,34,38,46,58 電子部品装置
22,51 配線基板(第1の電子部品)
23,53a,53b,53c 基板側電極(第1の電極)
25,29 ダム
26,52 チップ部品(第2の電子部品)
27,54a,54b,54c チップ側電極(第2の電極)
30 荷重
31,57 圧縮変形限界厚
39 ラミネート樹脂
40 シート状樹脂
41 ローラ
43 フィラー
47 アンダーフィル樹脂
55a,55b,55c 電極間の間隔
56 金属ナノ粒子ペーストの付与厚み
DESCRIPTION OF SYMBOLS 1 Metal nanoparticle paste 2 Metal nanoparticle 3 Dispersant 4 Dispersion medium 6 Junction sintered compact 21,34,38,46,58 Electronic component apparatus 22,51 Wiring board (1st electronic component)
23, 53a, 53b, 53c Substrate side electrode (first electrode)
25, 29 Dam 26, 52 Chip component (second electronic component)
27, 54a, 54b, 54c Chip side electrode (second electrode)
30 Load 31, 57 Compression deformation limit thickness 39 Laminate resin 40 Sheet-like resin 41 Roller 43 Filler 47 Underfill resin 55a, 55b, 55c Distance between electrodes 56 Application thickness of metal nanoparticle paste

図1は、この発明の第1の実施形態を説明するためのものである。図1には、電子部品装置の製造方法に含まれる代表的な工程が示され、図1(4)に、得られた電子部品装置22が示されている。   FIG. 1 is for explaining a first embodiment of the present invention. FIG. 1 shows a typical process included in the method of manufacturing an electronic component device, and FIG. 1 (4) shows the obtained electronic component device 22.

まず、図1(1)に示すように、第1の電子部品としての配線基板22が用意される。配線基板22は、たとえば、ガラスエポキシ基板などの樹脂基板、アルミナなどの焼成基板、Si基板などで構成されている。配線基板22の上面にはいくつかの基板側電極23が形成されている。また、配線基板22の上面の略全域にわたって、レジスト膜24が形成されている。レジスト膜24の一部は、基板側電極23の周縁部上に乗り上げており、それによって、基板側電極23の周囲には、ダム25が形成されている。このダム25は、後述する金属ナノ粒子ペースト1の広がりを防止するためのものである。   First, as shown in FIG. 1A, a wiring board 22 as a first electronic component is prepared. The wiring substrate 22 is configured by, for example, a resin substrate such as a glass epoxy substrate, a fired substrate such as alumina, or a Si substrate. Several substrate-side electrodes 23 are formed on the upper surface of the wiring substrate 22. A resist film 24 is formed over substantially the entire upper surface of the wiring board 22. A part of the resist film 24 rides on the peripheral edge of the substrate side electrode 23, whereby a dam 25 is formed around the substrate side electrode 23. The dam 25 is for preventing the metal nanoparticle paste 1 described later from spreading.

基板側電極23は、たとえばAu、Ag、Cuなどからなる単層構造とされても、あるいは、たとえばCu/Ni/Auなどからなる多層構造とされてもよい。基板側電極23の幅方向寸法は10〜150μm程度とされ、厚みは5〜50μm程度とされる。なお、基板側電極23は、配線基板22の厚み方向に延びるビア導体の端面を露出させた構造によって与えられてもよい。   The substrate-side electrode 23 may have a single layer structure made of, for example, Au, Ag, Cu, or a multilayer structure made of, for example, Cu / Ni / Au. The substrate-side electrode 23 has a width-direction dimension of about 10 to 150 μm and a thickness of about 5 to 50 μm. The substrate-side electrode 23 may be provided by a structure in which the end face of the via conductor extending in the thickness direction of the wiring substrate 22 is exposed.

他方、図1(2)に示すように、第2の電子部品としてチップ部品26が用意される。チップ部品26は、たとえば半導体素子や表面弾性波素子などの小型素子であり、その図による下面には、基板側電極23の各々に対応して、いくつかのチップ側電極27が形成されている。また、チップ部品26の、チップ側電極27が形成された面の略全域にわたって、パッシベーション膜28が形成されている。パッシベーション膜28の一部は、チップ側電極27の周縁部上に乗り上げるように形成され、それによって、チップ側電極27の周囲にはダム29が形成される。ダム29は、前述したダム25の場合と同様、金属ナノ粒子ペースト1の広がりを防止するためのものである。   On the other hand, as shown in FIG. 1B, a chip component 26 is prepared as a second electronic component. The chip component 26 is a small element such as a semiconductor element or a surface acoustic wave element, for example, and several chip side electrodes 27 corresponding to each of the substrate side electrodes 23 are formed on the lower surface of the figure. . Further, a passivation film 28 is formed over substantially the entire surface of the chip component 26 where the chip-side electrode 27 is formed. A part of the passivation film 28 is formed so as to run on the peripheral edge of the chip-side electrode 27, thereby forming a dam 29 around the chip-side electrode 27. The dam 29 is for preventing the spread of the metal nanoparticle paste 1 as in the case of the dam 25 described above.

チップ側電極27は、たとえば、Al、Al合金(90%以上のAlを含有し、CuやSiが添加されていてもよい。)、Au、Cuからなり、その厚みは0.5〜2μm程度とされる。   The chip-side electrode 27 is made of, for example, Al, an Al alloy (containing 90% or more of Al and Cu or Si may be added), Au, or Cu, and has a thickness of about 0.5 to 2 μm. It is said.

さらに、前述の図10に示すような金属ナノ粒子ペースト1が用意される。金属ナノ粒子ペースト1に含有される金属ナノ粒子2は、たとえばAu、Ag、Cu、Niなどの金属からなるものであっても、あるいは、たとえばCuコアAu、CuコアAgなどのように2種類以上の金属からなるものであってもよい。分散剤3としては、金属ナノ粒子2を構成する金属の融点よりも低い沸点を有し、かつ金属と結合できる有機物であればよく、たとえば、アミン、アルコール、フェノール、チオールなどを用いることができる。分散媒4としては、金属ナノ粒子2を構成する金属の融点よりも低い沸点を有する物質であればよく、たとえば、トルエン、キシレン、テルピネオール、ミネラルスピリット、デカノール、テトラデカンなどの有機溶剤を用いることができる。あるいは、分散媒4として、水などの水系のものを用いることもできる。金属ナノ粒子ペースト1は、さらに、少量の有機バインダ、分散剤3を取り込むため酸無水物のような捕捉物質を含有していてもよく、さらに、電極材料に対して、還元作用を有する物質を含有していてもよい。   Furthermore, the metal nanoparticle paste 1 as shown in FIG. 10 is prepared. The metal nanoparticles 2 contained in the metal nanoparticle paste 1 may be made of a metal such as Au, Ag, Cu, or Ni, or may be of two types, such as Cu core Au or Cu core Ag. You may consist of the above metals. The dispersant 3 may be any organic substance having a boiling point lower than the melting point of the metal constituting the metal nanoparticle 2 and capable of binding to the metal. For example, amine, alcohol, phenol, thiol, etc. can be used. . The dispersion medium 4 may be any substance having a boiling point lower than the melting point of the metal constituting the metal nanoparticle 2. For example, an organic solvent such as toluene, xylene, terpineol, mineral spirit, decanol, or tetradecane may be used. it can. Alternatively, an aqueous medium such as water can be used as the dispersion medium 4. The metal nanoparticle paste 1 may further contain a trapping substance such as an acid anhydride in order to incorporate a small amount of an organic binder and the dispersant 3, and further, a substance having a reducing action on the electrode material. You may contain.

図1(1)に示すように、基板側電極23に、金属ナノ粒子ペースト1が付与される。金属ナノ粒子ペーストの供給には、インクジェットやディスペンサによる吐出供給、スクリーン印刷、転写など、種々の供給方法を用いることができる。金属ナノ粒子ペースト1の供給量は、当然のことながら、互いに接合されるべき基板側電極23とチップ側電極27との隙間を埋めるのに必要な量以上、かつ基板側電極23の各々の隣り合うもの同士およびチップ側電極27の各々の隣り合うもの同士を接続してしまう量未満であればよい。   As shown in FIG. 1 (1), the metal nanoparticle paste 1 is applied to the substrate-side electrode 23. For supplying the metal nanoparticle paste, various supply methods such as discharge supply by ink jet or dispenser, screen printing, and transfer can be used. As a matter of course, the supply amount of the metal nanoparticle paste 1 is not less than an amount necessary for filling the gap between the substrate side electrode 23 and the chip side electrode 27 to be bonded to each other, and adjacent to each of the substrate side electrodes 23. What is necessary is just to be less than the amount of connecting the adjacent ones and the adjacent ones of the chip side electrodes 27.

なお、生産性を向上させるため、配線基板22が、後で分割されることが予定され、分割されることによって複数の配線基板22を取り出すことができる集合基板の状態で、上述の工程および以下の工程が実施されてもよい。また、金属ナノ粒子ペースト1は、上述のように、基板側電極23上ではなく、チップ側電極27上に付与されても、あるいは、基板側電極23上およびチップ側電極27上の双方に付与されてもよい。   In addition, in order to improve productivity, the wiring board 22 is scheduled to be divided later, and the above-described steps and the following are performed in a collective board state in which a plurality of wiring boards 22 can be taken out by the division. These steps may be performed. Further, as described above, the metal nanoparticle paste 1 may be applied not on the substrate side electrode 23 but on the chip side electrode 27 or on both the substrate side electrode 23 and the chip side electrode 27. May be.

次に、図1(2)に示すように、金属ナノ粒子ペースト1を互いの間に介在させた状態で、基板側電極23と対応のチップ側電極27とが互いに対向するように、配線基板22とチップ部品26とが互いに位置合わせされる。この位置合わせ工程は、従来のフリップチップ実装方法の場合と同様の方法を適用して実施することができる。   Next, as shown in FIG. 1 (2), the wiring substrate is arranged so that the substrate-side electrode 23 and the corresponding chip-side electrode 27 face each other with the metal nanoparticle paste 1 interposed therebetween. 22 and chip component 26 are aligned with each other. This alignment step can be performed by applying the same method as in the conventional flip chip mounting method.

次に、図1(3)に示すように、配線基板22とチップ部品26とを互いに近接させる方向に荷重30を加え、それによって、基板側電極23とチップ側電極27との間にある金属ナノ粒子ペースト1を圧縮変形させる工程が実施される。この圧縮変形させる工程において与えられる荷重30は、金属ナノ粒子ペースト1の圧縮変形が限界に達するような大きさとされ、それによって、金属ナノ粒子ペースト1は圧縮変形限界厚31まで圧縮変形される。この圧縮変形限界厚31について、以下に、より具体的に説明する。   Next, as shown in FIG. 1 (3), a load 30 is applied in a direction in which the wiring substrate 22 and the chip component 26 are brought close to each other, whereby the metal between the substrate-side electrode 23 and the chip-side electrode 27. A step of compressing and deforming the nanoparticle paste 1 is performed. The load 30 applied in this compressive deformation step is set to a size such that the compression deformation of the metal nanoparticle paste 1 reaches the limit, and thereby the metal nanoparticle paste 1 is compressively deformed to the compression deformation limit thickness 31. The compression deformation limit thickness 31 will be described more specifically below.

接合部1箇所について、金属ナノ粒子ペーストに与えられる荷重と、荷重によって圧縮変形する金属ナノ粒子ペーストの高さとの関係が、図2および表1に示されている。   FIG. 2 and Table 1 show the relationship between the load applied to the metal nanoparticle paste and the height of the metal nanoparticle paste that is compressively deformed by the load at one joint.

Figure 2009098831
Figure 2009098831

図2および表1において、例1、例2および例3は、金属ナノ粒子ペーストの供給量を異ならせた例であって、供給量については、例1<例2<例3という関係にある。   In FIG. 2 and Table 1, Example 1, Example 2 and Example 3 are examples in which the supply amount of the metal nanoparticle paste is varied, and the supply amount has a relationship of Example 1 <Example 2 <Example 3. .

図2および表1に示したデータからわかるように、例1〜3のいずれであっても、荷重を大きくすると、金属ナノ粒子ペーストの高さが低くなり、その値が飽和する。たとえば、例1の場合には、1箇所の金属ナノ粒子ペーストにつき、0.9N以上、例2および3の場合には、1箇所の金属ナノ粒子ペーストにつき、1.5N以上とすれば、金属ナノ粒子ペーストの高さは一定値となる。このことから、所定値以上の荷重を加えることにより、荷重の上限値を制御しなくても、金属ナノ粒子ペーストの高さを一定に制御できることがわかる。   As can be seen from the data shown in FIG. 2 and Table 1, in any of Examples 1 to 3, when the load is increased, the height of the metal nanoparticle paste decreases and the value is saturated. For example, in the case of Example 1, 0.9N or more per one metal nanoparticle paste, and in Examples 2 and 3, if 1.5N or more per one metal nanoparticle paste, The height of the nanoparticle paste is a constant value. From this, it is understood that the height of the metal nanoparticle paste can be controlled to be constant by applying a load of a predetermined value or more without controlling the upper limit value of the load.

ここで、所定値以上の荷重によって、金属ナノ粒子ペーストの高さが一定となる理由、すなわち圧縮変形が限界となる理由について説明する。図3は、付与された金属ナノ粒子ペーストの高さと径との関係を示す図である。図3から、金属ナノ粒子ペーストの高さを低くすると、金属ナノ粒子ペーストの径が急激に増大することがわかる。このことは、荷重を大きくする過程で、金属ナノ粒子ペーストの圧縮変形に伴って径が急激に増大し、圧縮変形が進まなくなることを示している。   Here, the reason why the height of the metal nanoparticle paste becomes constant by a load of a predetermined value or more, that is, the reason why compression deformation becomes a limit will be described. FIG. 3 is a diagram showing the relationship between the height and diameter of the applied metal nanoparticle paste. FIG. 3 shows that when the height of the metal nanoparticle paste is lowered, the diameter of the metal nanoparticle paste increases rapidly. This indicates that, in the process of increasing the load, the diameter rapidly increases with the compression deformation of the metal nanoparticle paste, and the compression deformation does not progress.

再び、図1(3)を参照して、荷重30は、たとえば、従来のフリップチップマウンタのような一般的なマウンタを用いて与えられる。また、荷重30は、通常、図示したように、チップ部品26側から与えられるが、金属ナノ粒子ペースト1を圧縮変形させ得るのであれば、配線基板22側から与えられても、あるいはチップ部品26および配線基板22の双方から与えられてもよい。   Referring again to FIG. 1 (3), the load 30 is applied using a general mounter such as a conventional flip chip mounter. The load 30 is normally applied from the chip component 26 side as shown in the figure. However, if the metal nanoparticle paste 1 can be compressed and deformed, the load 30 may be applied from the wiring substrate 22 side or the chip component 26. And may be provided from both of the wiring board 22.

次に、加熱工程が実施される。前述した金属ナノ粒子ペースト1を圧縮変形させた状態は、荷重30が除去されても維持されるので、この加熱工程では、荷重30を加える必要はない。加熱工程では、金属ナノ粒子ペースト1に含まれる分散剤3および分散媒4を除去できる温度以上、かつ金属ナノ粒子2を構成する金属の融点未満の温度で加熱される。たとえば、温度が100〜300℃、時間が1〜60分間というような加熱条件が選ばれる。この加熱によって、金属ナノ粒子2が焼結し、金属ナノ粒子ペースト1が、図1(4)に示すように、接合焼結体6を形成し、その結果、基板側電極23とチップ側電極27とが互いに接合される。なお、加熱工程で荷重30を加えてもよく、その場合は、より緻密な接合焼結体6を得ることができる。   Next, a heating step is performed. Since the state in which the metal nanoparticle paste 1 is compressed and deformed is maintained even when the load 30 is removed, it is not necessary to apply the load 30 in this heating step. In the heating step, heating is performed at a temperature not lower than the temperature at which the dispersant 3 and the dispersion medium 4 contained in the metal nanoparticle paste 1 can be removed and lower than the melting point of the metal constituting the metal nanoparticle 2. For example, heating conditions such as a temperature of 100 to 300 ° C. and a time of 1 to 60 minutes are selected. By this heating, the metal nanoparticles 2 are sintered, and the metal nanoparticle paste 1 forms a bonded sintered body 6 as shown in FIG. 1 (4). As a result, the substrate side electrode 23 and the chip side electrode are formed. 27 are joined together. Note that a load 30 may be applied in the heating step, and in that case, a denser bonded sintered body 6 can be obtained.

加熱工程は、たとえば、オーブン、リフロー炉、焼成炉などの加熱機能を有する設備を用いて実施される。また、従来の熱圧着や超音波接合方式のフリップチップ搭載設備に設けられている加熱装置を用いてもよい。なお、加熱工程を大気または大気以上の酸素を含む雰囲気中で実施すれば、分散剤3の除去を促進でき、その結果、接合信頼性が向上するため好ましい。   A heating process is implemented using the equipment which has heating functions, such as oven, a reflow furnace, a baking furnace, for example. Moreover, you may use the heating apparatus provided in the flip chip mounting equipment of the conventional thermocompression bonding or ultrasonic bonding system. Note that it is preferable to carry out the heating step in the atmosphere or in an atmosphere containing oxygen above the atmosphere because the removal of the dispersant 3 can be promoted, and as a result, the bonding reliability is improved.

以上のようにして、目的とする電子部品装置21が得られる。   The target electronic component device 21 is obtained as described above.

以上説明した実施形態では、基板側電極23およびチップ側電極27のそれぞれの周囲にダム25および29が形成されている。これらダム25および29は、前述したように、金属ナノ粒子ペースト1の広がりを防止するためのものである。したがって、たとえば、配線基板22における基板側電極23以外の部分には、金属ナノ粒子ペースト1が濡れ性の関係で濡れ広がらない場合には、ダム25は特に必要としない。同様に、チップ部品26におけるチップ側電極27以外の部分に、金属ナノ粒子ペースト1が濡れ広がらない場合には、ダム29は特に必要としない。しかしながら、それに関わらず、ダム25および29が設けられる場合には、図1(3)に示した圧縮変形工程において、金属ナノ粒子ペースト1がより確実にかつ容易に圧縮変形され得るという利点がもたらされる。なお、ダム25および29の双方が設けられる場合、上述の利点が、より顕著に奏されるが、いずれか一方だけが設けられる場合であっても、程度の差こそあれ、この利点は奏される。   In the embodiment described above, the dams 25 and 29 are formed around the substrate side electrode 23 and the chip side electrode 27, respectively. These dams 25 and 29 are for preventing the spread of the metal nanoparticle paste 1 as described above. Therefore, for example, if the metal nanoparticle paste 1 does not spread out due to the wettability in the portion other than the substrate-side electrode 23 in the wiring substrate 22, the dam 25 is not particularly required. Similarly, the dam 29 is not particularly required when the metal nanoparticle paste 1 is not wetted and spread on the part other than the chip side electrode 27 in the chip part 26. However, when the dams 25 and 29 are provided, the metal nanoparticle paste 1 can be more reliably and easily compressed and deformed in the compression deformation process shown in FIG. It is. In addition, when both the dams 25 and 29 are provided, the above-described advantages are more remarkably exhibited. However, even when only one of the dams is provided, this advantage is exhibited to some extent. The

また、上述した実施形態において形成されたレジスト膜14およびパッシベーション膜28は、それぞれ、配線基板22およびチップ部品26を保護するための絶縁膜であるが、これらについては、必要に応じて設けられるものであり、必須のものではない。   In addition, the resist film 14 and the passivation film 28 formed in the above-described embodiment are insulating films for protecting the wiring board 22 and the chip component 26, respectively, and these are provided as necessary. And not essential.

図4は、この発明の第2の実施形態による電子部品装置34を示す、図1(4)に相当する図である。図4において、図1(4)に示す要素に相当する要素に同様の参照符号を付し、重複する説明は省略する。   FIG. 4 is a view corresponding to FIG. 1 (4), showing an electronic component device 34 according to the second embodiment of the present invention. In FIG. 4, elements corresponding to those shown in FIG. 1 (4) are denoted by the same reference numerals, and redundant description is omitted.

図4に示した電子部品装置34は、チップ側電極27上にAuバンプ35が形成されていることを特徴としている。したがって、この電子部品装置34を製造する場合には、図1(2)に示した工程において、既にAuバンプ35が形成されていて、金属ナノ粒子ペースト1はAuバンプ35と基板側電極23との間に付与され、基板側電極23とチップ側電極27とは、Auバンプ35および接合焼結体6を介して互いに接合される。   The electronic component device 34 shown in FIG. 4 is characterized in that Au bumps 35 are formed on the chip-side electrode 27. Therefore, when manufacturing this electronic component device 34, the Au bump 35 has already been formed in the process shown in FIG. 1B, and the metal nanoparticle paste 1 is made of the Au bump 35, the substrate-side electrode 23, and the like. The substrate side electrode 23 and the chip side electrode 27 are bonded to each other via the Au bump 35 and the bonded sintered body 6.

図5ないし図7は、この発明の第3の実施形態を説明するためのものである。ここで、図5は、第3の実施形態による電子部品装置38を示す、図1(4)に相当する図である。図5において、図1(4)に示す要素に相当する要素には同様の参照符号を付し、重複する説明は省略する。   5 to 7 are for explaining a third embodiment of the present invention. Here, FIG. 5 is a view corresponding to FIG. 1 (4), showing an electronic component device 38 according to the third embodiment. In FIG. 5, elements corresponding to those shown in FIG. 1 (4) are denoted by the same reference numerals, and redundant description is omitted.

図5に示した電子部品装置38は、図1(4)に示した電子部品装置21が備える要素をすべて備えながら、さらにラミネート樹脂39によってチップ部品26が封止されていることを特徴としている。このような電子部品装置38を製造するため、図6に示す工程が実施される。   The electronic component device 38 shown in FIG. 5 is characterized in that the chip component 26 is sealed with a laminate resin 39 while including all the elements included in the electronic component device 21 shown in FIG. . In order to manufacture such an electronic component device 38, the process shown in FIG. 6 is performed.

図6を参照して、ラミネート封止用の未硬化状態のシート状樹脂40が用意される。他方、配線基板22およびチップ部品26にあっては、図1(4)に示すように、基板側電極23とチップ側電極27とが互いに接合された状態にある。上述の未硬化状態のシート状樹脂40は、チップ部品26を覆うようにローラ41によって案内される。ローラ41は、配線基板22との間で相対的に矢印42方向に移動するようにされ、それによって、複数のチップ部品26が、順次、シート状樹脂40によって覆われた状態とされる。   Referring to FIG. 6, an uncured sheet-like resin 40 for laminating and sealing is prepared. On the other hand, in the wiring board 22 and the chip component 26, as shown in FIG. 1 (4), the substrate side electrode 23 and the chip side electrode 27 are joined to each other. The uncured sheet-like resin 40 is guided by a roller 41 so as to cover the chip component 26. The roller 41 is moved relative to the wiring substrate 22 in the direction of the arrow 42, whereby the plurality of chip components 26 are sequentially covered with the sheet-like resin 40.

上述したローラ41は、未硬化状態のシート状樹脂40を配線基板22およびチップ部品26に向かって加圧するようにも作用する。このとき、シート状樹脂40の一部が、図5に示したように、チップ部品26と配線基板22との間に進入するようにされる。この進入を容易にするため、シート状樹脂40の粘度が最小となる軟化温度付近(通常、60〜100℃)にまで加熱し、シート状樹脂40の流動性を向上させることが好ましい。また、シート状樹脂40の上述の進入をより容易にするため、図6に示した工程を、たとえば数100〜数1000Pa程度の減圧雰囲気下で行なうことも有効である。   The roller 41 described above also acts to press the uncured sheet-like resin 40 toward the wiring board 22 and the chip component 26. At this time, a part of the sheet-like resin 40 enters between the chip component 26 and the wiring board 22 as shown in FIG. In order to facilitate this entry, it is preferable to improve the fluidity of the sheet-like resin 40 by heating it to near the softening temperature at which the viscosity of the sheet-like resin 40 is minimum (usually 60 to 100 ° C.). Further, in order to make the above-described entry of the sheet-like resin 40 easier, it is also effective to perform the process shown in FIG. 6 under a reduced pressure atmosphere of, for example, about several hundred to several thousand Pa.

次に、未硬化状態のシート状樹脂40が硬化され、それによって図5に示したラミネート樹脂39が形成される。   Next, the uncured sheet-like resin 40 is cured, thereby forming the laminate resin 39 shown in FIG.

前述したシート状樹脂40を加圧する工程では、たとえば0.1〜5MPa程度の圧力を加えることによって、未硬化状態のシート状樹脂40の余分なものをチップ部品26の周囲に流動させることが行なわれる。このとき、シート状樹脂40の最も薄い部分での厚み、すなわちチップ部品26の上面上での厚みがばらつかないようにすることが望ましい。そのため、従来、図6に示した工程を実施するとき、ローラ41の位置を厳格に制御することが行なわれているが、ローラ41は、均一な圧力をかけることを可能にするため、通常、柔らかい材質を有しているため、ローラ41の変形が生じやすい。そのため、シート状樹脂40の厚み、すなわちラミネート樹脂39の、チップ部品26の上面上での厚みがばらつかないようにすることは困難である。   In the step of pressurizing the sheet-like resin 40 described above, an excess of the uncured sheet-like resin 40 is caused to flow around the chip component 26 by applying a pressure of about 0.1 to 5 MPa, for example. It is. At this time, it is desirable that the thickness at the thinnest portion of the sheet-like resin 40, that is, the thickness on the upper surface of the chip component 26 does not vary. Therefore, conventionally, when carrying out the process shown in FIG. 6, the position of the roller 41 is strictly controlled. However, the roller 41 is usually capable of applying a uniform pressure. Since it has a soft material, the roller 41 is easily deformed. Therefore, it is difficult to prevent the thickness of the sheet-like resin 40, that is, the thickness of the laminate resin 39 on the upper surface of the chip component 26 from being varied.

この問題を解決するために、この実施形態では、次のような対策が講じられている。   In order to solve this problem, the following measures are taken in this embodiment.

図7は、図5の部分Aに相当する部分を示す拡大図である。図7は、図5に示したラミネート樹脂39が未硬化状態にある段階、すなわち未硬化状態のシート状樹脂40の段階で図示されている。シート状樹脂40は、たとえばエポキシ樹脂のような熱硬化性または熱可塑性樹脂であり、図7に示すように、粒径が所定の寸法以下に揃えられたフィラー43を含んでいる。フィラー43は、たとえばシリカからなり、50体積%以上の含有率を有している。   FIG. 7 is an enlarged view showing a portion corresponding to the portion A of FIG. FIG. 7 is shown in a stage where the laminate resin 39 shown in FIG. 5 is in an uncured state, that is, in a stage of the uncured sheet-like resin 40. The sheet-like resin 40 is a thermosetting or thermoplastic resin such as an epoxy resin, for example, and includes a filler 43 whose particle size is equal to or smaller than a predetermined dimension as shown in FIG. The filler 43 is made of silica, for example, and has a content of 50% by volume or more.

シート状樹脂40が、上述のように、フィラー43を含むことにより、図6に示したローラ41による加圧工程において、シート状樹脂40の最も薄い部分での厚みがフィラー43の粒径によって支配されるように、シート状樹脂40が加圧制御されることになる。より具体的には、シート状樹脂40の、チップ部品26の上面上での厚みが、フィラー43の最も大きい径を有するもの「43(A)」と略一致するようになる。その結果、シート状樹脂40の、チップ部品26の上面上での厚みを正確に制御することができる。   Since the sheet-like resin 40 includes the filler 43 as described above, the thickness of the thinnest portion of the sheet-like resin 40 is governed by the particle size of the filler 43 in the pressurizing step by the roller 41 shown in FIG. Thus, the pressure of the sheet-like resin 40 is controlled. More specifically, the thickness of the sheet-like resin 40 on the upper surface of the chip component 26 substantially coincides with “43 (A)” having the largest diameter of the filler 43. As a result, the thickness of the sheet-like resin 40 on the upper surface of the chip component 26 can be accurately controlled.

なお、図7では、シート状樹脂40の厚みがフィラー43の最も大きい径を有するもの「43(A)」と略一致するように図示されたが、このような厚みを支配するフィラー43の粒径は、1次粒子のものであっても、あるいは2次粒子のものであってもよい。   In FIG. 7, the thickness of the sheet-like resin 40 is illustrated so as to substantially coincide with “43 (A)” having the largest diameter of the filler 43, but the filler 43 particles that govern such thickness are illustrated. The diameter may be that of primary particles or secondary particles.

図8は、この発明の第4の実施形態による電子部品装置46を示す、図1(4)に相当する図である。図8において、図1(4)に示す要素に相当する要素には同様の参照符号を付し、重複する説明は省略する。   FIG. 8 is a view corresponding to FIG. 1 (4), showing an electronic component device 46 according to the fourth embodiment of the present invention. In FIG. 8, elements corresponding to the elements shown in FIG. 1 (4) are denoted by the same reference numerals, and redundant description is omitted.

図8に示した電子部品装置46は、図1(4)に示した電子部品装置21に備える要素をすべて備えるとともに、さらに、アンダーフィル樹脂47を備えることを特徴としている。このようにアンダーフィル樹脂47を形成するために、アンダーフィル封止用の未硬化状態の樹脂が用意される。他方、図1(4)に示すように、基板側電極23とチップ側電極27とを互いに接合させる工程が実施される。その後、配線基板22とチップ部品26のうち、面積がより小さい方のチップ部品26の少なくとも周囲に上述の未硬化状態の樹脂が付与される。これによって、未硬化状態の樹脂は、チップ部品26と配線基板22との間の隙間へと浸透する。次いで、未硬化状態の樹脂を硬化させれば、図8に示すような電子部品装置46が得られる。   The electronic component device 46 shown in FIG. 8 is characterized by including all the elements provided in the electronic component device 21 shown in FIG. 1 (4) and further including an underfill resin 47. In order to form the underfill resin 47 as described above, an uncured resin for underfill sealing is prepared. On the other hand, as shown in FIG. 1 (4), a step of bonding the substrate side electrode 23 and the chip side electrode 27 together is performed. Thereafter, the above-described uncured resin is applied to at least the periphery of the chip component 26 having the smaller area of the wiring board 22 and the chip component 26. As a result, the uncured resin penetrates into the gap between the chip component 26 and the wiring board 22. Next, if the uncured resin is cured, an electronic component device 46 as shown in FIG. 8 is obtained.

図9は、この発明の第5の実施形態を説明するための、図1に相当する図である。図9において、図1に示した要素に相当する要素には同様の参照符号を付し、重複する説明は省略する。   FIG. 9 is a view corresponding to FIG. 1 for explaining a fifth embodiment of the present invention. In FIG. 9, elements corresponding to those shown in FIG. 1 are denoted by the same reference numerals, and redundant description is omitted.

この実施形態は、図9(2)に示すように、配線基板51とチップ部品52とを互いに一合わせしたとき、互いに対向する基板側電極53a、53bおよび53cの各々とチップ側電極54a、54bおよび54cの各々とのそれぞれの間隔55a、55b、55cが互いに等しくないものを含む場合に有利に適用される。   In this embodiment, as shown in FIG. 9B, when the wiring substrate 51 and the chip component 52 are brought together, each of the substrate-side electrodes 53a, 53b and 53c facing each other and the chip-side electrodes 54a and 54b are arranged. And 54c are advantageously applied when their respective spacings 55a, 55b, 55c include those that are not equal to each other.

上述したような間隔55a〜55cの不揃いは、典型的には、配線基板51の製造過程において不可避的に生じる反りやうねりによってもたらされる。また、チップ部品52側においても、不所望な変形が生じることがある。さらには、間隔55a〜55cの不揃いは、上述したような不所望な事態によってもたらされる場合に限らず、既に設計の段階で予定されている場合もある。   The unevenness of the intervals 55a to 55c as described above is typically caused by warpage or undulation that is inevitably generated in the manufacturing process of the wiring board 51. Further, undesired deformation may occur on the chip component 52 side. Further, the unevenness of the intervals 55a to 55c is not limited to the case where it is caused by an undesired situation as described above, and may be already planned at the design stage.

この実施形態では、上述した間隔55a〜55cの不揃いに対処するため、図9(1)に示すように、金属ナノ粒子ペースト1を付与する工程において、金属ナノ粒子ペースト1の厚み56が、間隔55a〜55cのうち、最大のもの55cと最小のもの55aとの差を圧縮変形限界厚57(図9(3)参照)に加えた厚み以上とされる。   In this embodiment, in order to deal with the unevenness of the intervals 55a to 55c described above, as shown in FIG. 9 (1), in the step of applying the metal nanoparticle paste 1, the thickness 56 of the metal nanoparticle paste 1 is set to the interval. Among 55a to 55c, the difference between the maximum 55c and the minimum 55a is equal to or greater than the thickness obtained by adding the compression deformation limit thickness 57 (see FIG. 9 (3)).

具体的な数値をもって説明すると、図9(2)に示した位置合わせ状態において、
a.互いに対向する基板側電極53aとチップ側電極54aとの間隔が13μm、
b.互いに対向する基板側電極53bとチップ側電極54bとの間隔が16μm、
c.互いに対向する基板側電極53cとチップ側電極54cとの間隔が17μm
であるとき、間隔の最大のものは17μmであり、最小のものは13μmであり、最大のものと最小のものとの差は、17μm−13μm=4μmということになる。
To explain with specific numerical values, in the alignment state shown in FIG.
a. The distance between the substrate-side electrode 53a and the chip-side electrode 54a facing each other is 13 μm,
b. The distance between the substrate-side electrode 53b and the chip-side electrode 54b facing each other is 16 μm,
c. The distance between the substrate side electrode 53c and the chip side electrode 54c facing each other is 17 μm.
, The maximum interval is 17 μm, the minimum is 13 μm, and the difference between the maximum and minimum is 17 μm−13 μm = 4 μm.

また、図9(3)に示した工程において圧縮変形される金属ナノ粒子ペースト1の圧縮変形限界厚が5μmであるとする。   In addition, it is assumed that the compressive deformation limit thickness of the metal nanoparticle paste 1 that is compressed and deformed in the process shown in FIG.

このような場合、図9(1)に示した工程において付与される金属ナノ粒子ペースト1の厚み56は、上述した差4μmに圧縮変形限界厚5μmを加えた厚み以上、すなわち9μm以上とされる。   In such a case, the thickness 56 of the metal nanoparticle paste 1 applied in the step shown in FIG. 9 (1) is equal to or greater than the thickness obtained by adding the compression deformation limit thickness of 5 μm to the difference of 4 μm, that is, 9 μm or more. .

上述のような厚み56をもって金属ナノ粒子ペースト1が付与されると、図9(3)に示した工程において、荷重30が与えられ、基板側電極53aとチップ側電極54aとの間に位置する金属ナノ粒子ペースト1が圧縮変形限界厚57に達するまで圧縮変形されたとき、他の基板側電極53bおよび53cの各々とチップ側電極54bおよび54cの各々との間に位置する金属ナノ粒子ペースト1についても、圧縮変形限界厚57に達しないまでも、基板側電極53bおよび53cとチップ側電極54bおよび54cとの双方に確実に接触させることができる。したがって、図9(4)に示すように、加熱工程を経て、目的とする電子部品装置58が得られたとき、基板側電極53a〜53cとチップ側電極54a〜54cとの間のすべての接合焼結体6について、良好な接合状態を得ることができる。   When the metal nanoparticle paste 1 is applied with the thickness 56 as described above, a load 30 is applied in the step shown in FIG. 9 (3), and the metal nanoparticle paste 1 is positioned between the substrate side electrode 53a and the chip side electrode 54a. When the metal nanoparticle paste 1 is compressed and deformed until it reaches the compression deformation limit thickness 57, the metal nanoparticle paste 1 positioned between each of the other substrate-side electrodes 53b and 53c and each of the chip-side electrodes 54b and 54c. Even if the compression deformation limit thickness 57 is not reached, both the substrate-side electrodes 53b and 53c and the chip-side electrodes 54b and 54c can be reliably brought into contact with each other. Accordingly, as shown in FIG. 9 (4), when the target electronic component device 58 is obtained through the heating process, all the bondings between the substrate side electrodes 53a to 53c and the chip side electrodes 54a to 54c are performed. About the sintered compact 6, a favorable joining state can be obtained.

以上、この発明を図示した実施形態に関連して説明したが、この発明の範囲内において、その他種々の変形例が可能である。   While the present invention has been described with reference to the illustrated embodiment, various other modifications are possible within the scope of the present invention.

たとえば、図4に示した実施形態において開示したAuバンプ35は、図5、図8および図9にそれぞれ示した実施形態においても適用可能である。   For example, the Au bump 35 disclosed in the embodiment shown in FIG. 4 can be applied to the embodiments shown in FIGS. 5, 8, and 9, respectively.

また、図示の実施形態では、第1の電子部品が配線基板であり、第2の電子部品がチップ部品であったが、その他の電子部品の組み合わせであっても、この発明を等しく適用することができる。   In the illustrated embodiment, the first electronic component is a wiring board and the second electronic component is a chip component. However, the present invention is equally applied to a combination of other electronic components. Can do.

Claims (7)

第1の電極を有する第1の電子部品および第2の電極を有する第2の電子部品を用意する工程と、
平均粒径が1〜100nmの金属ナノ粒子と分散剤と分散媒とを含む金属ナノ粒子ペーストを用意する工程と、
前記第1の電極および前記第2の電極の少なくとも一方に、前記金属ナノ粒子ペーストを付与する、ペースト付与工程と、
前記金属ナノ粒子ペーストを互いの間に介在させた状態で、前記第1の電極と前記第2の電極とが互いに対向するように、前記第1の電子部品と前記第2の電子部品とを互いに位置合わせする工程と、
前記第1の電子部品と前記第2の電子部品とを互いに近接させる方向に荷重を加え、それによって、前記第1の電極と前記第2の電極との間にある前記金属ナノ粒子ペーストを圧縮変形限界厚まで圧縮変形させる工程と、
次いで、前記金属ナノ粒子ペーストに含まれる前記分散剤および前記分散媒を除去できる温度以上、かつ前記金属ナノ粒子を構成する金属の融点未満の温度で加熱することにより、前記金属ナノ粒子を焼結させ、それによって、前記第1の電極と前記第2の電極とを互いに接合させる工程と
を備える、電子部品装置の製造方法。
Providing a first electronic component having a first electrode and a second electronic component having a second electrode;
Preparing a metal nanoparticle paste comprising metal nanoparticles having an average particle diameter of 1 to 100 nm, a dispersant and a dispersion medium;
A paste applying step of applying the metal nanoparticle paste to at least one of the first electrode and the second electrode;
The first electronic component and the second electronic component are arranged so that the first electrode and the second electrode face each other with the metal nanoparticle paste interposed therebetween. Aligning each other;
A load is applied in a direction to bring the first electronic component and the second electronic component close to each other, thereby compressing the metal nanoparticle paste between the first electrode and the second electrode. A step of compressive deformation to the deformation limit thickness;
Next, the metal nanoparticles are sintered by heating at a temperature that is higher than the temperature at which the dispersant and the dispersion medium contained in the metal nanoparticle paste can be removed and less than the melting point of the metal constituting the metal nanoparticles. And, thereby, joining the first electrode and the second electrode to each other.
前記第1の電子部品は複数の前記第1の電極を有し、前記第2の電子部品は複数の前記第2の電極を有し、前記第1の電子部品と前記第2の電子部品とを互いに位置合わせしたとき、互いに対向する各前記第1の電極と各前記第2の電極とのそれぞれの間隔が互いに等しくないものを含み、前記ペースト付与工程において付与される前記金属ナノ粒子ペーストの厚みは、前記間隔の最大のものと最小のものとの間の差を前記圧縮変形限界厚に加えた厚み以上とされる、請求項1に記載の電子部品装置の製造方法。   The first electronic component has a plurality of the first electrodes, the second electronic component has a plurality of the second electrodes, and the first electronic component, the second electronic component, Of the metal nanoparticle paste applied in the paste applying step, wherein the first electrode and the second electrode facing each other are not equal to each other. 2. The method of manufacturing an electronic component device according to claim 1, wherein the thickness is equal to or greater than a thickness obtained by adding a difference between the maximum and minimum distances to the compression deformation limit thickness. 前記第1の電極の周囲には、前記金属ナノ粒子ペーストの広がりを防止するためのダムが形成される、請求項1に記載の電子部品装置の製造方法。   The method for manufacturing an electronic component device according to claim 1, wherein a dam for preventing the metal nanoparticle paste from spreading is formed around the first electrode. 前記第2の電極の周囲には、前記金属ナノ粒子ペーストの広がりを防止するためのダムが形成される、請求項1に記載の電子部品装置の製造方法。   The method for manufacturing an electronic component device according to claim 1, wherein a dam for preventing the metal nanoparticle paste from spreading is formed around the second electrode. ラミネート封止用の未硬化状態のシート状樹脂を用意する工程と、前記第1の電極と前記第2の電極とを互いに接合させる工程の後、前記第1の電子部品および前記第2の電子部品のいずれか一方を、前記未硬化状態のシート状樹脂で覆う工程と、前記未硬化状態のシート状樹脂を前記第1の電子部品および前記第2の電子部品に向かって加圧する工程と、前記未硬化状態のシート状樹脂を硬化させる工程とをさらに備える、請求項1ないし4のいずれかに記載の電子部品装置の製造方法。   After the step of preparing an uncured sheet-shaped resin for sealing the laminate and the step of bonding the first electrode and the second electrode together, the first electronic component and the second electronic Covering any one of the components with the uncured sheet-shaped resin, pressing the uncured sheet-shaped resin toward the first electronic component and the second electronic component, The method of manufacturing an electronic component device according to claim 1, further comprising a step of curing the uncured sheet-like resin. 前記シート状樹脂は、粒径が所定の寸法以下に揃えられたフィラーを含み、前記未硬化状態のシート状樹脂を加圧する工程において、前記第1の電子部品および前記第2の電子部品のいずれか一方を覆う前記シート状樹脂の最も薄い部分での厚みが前記フィラーの粒径によって支配されるように、前記シート状樹脂が加圧制御される、請求項5に記載の電子部品装置の製造方法。   The sheet-like resin includes a filler whose particle size is equal to or less than a predetermined dimension, and in the step of pressurizing the uncured sheet-like resin, any one of the first electronic component and the second electronic component 6. The manufacturing of the electronic component device according to claim 5, wherein the pressure of the sheet-shaped resin is controlled so that the thickness at the thinnest portion of the sheet-shaped resin covering either of them is governed by the particle size of the filler. Method. アンダーフィル封止用の未硬化状態の樹脂を用意する工程と、前記第1の電極と前記第2の電極とを互いに接合させる工程の後、前記第1の電子部品と前記第2の電子部品のうち、面積がより小さい方の電子部品の少なくとも周囲に前記未硬化状態の樹脂を付与する工程と、前記未硬化状態の樹脂を硬化させる工程とをさらに備える、請求項1ないし4のいずれかに記載の電子部品装置の製造方法。   After the step of preparing an uncured resin for underfill sealing and the step of bonding the first electrode and the second electrode together, the first electronic component and the second electronic component 5. The method according to claim 1, further comprising a step of applying the uncured resin to at least a periphery of an electronic component having a smaller area, and a step of curing the uncured resin. The manufacturing method of the electronic component apparatus as described in any one of.
JP2009552394A 2008-02-07 2008-12-25 Manufacturing method of electronic component device Active JP5182296B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2009552394A JP5182296B2 (en) 2008-02-07 2008-12-25 Manufacturing method of electronic component device

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2008027285 2008-02-07
JP2008027285 2008-02-07
PCT/JP2008/073522 WO2009098831A1 (en) 2008-02-07 2008-12-25 Method for manufacturing electronic component device
JP2009552394A JP5182296B2 (en) 2008-02-07 2008-12-25 Manufacturing method of electronic component device

Publications (2)

Publication Number Publication Date
JPWO2009098831A1 true JPWO2009098831A1 (en) 2011-05-26
JP5182296B2 JP5182296B2 (en) 2013-04-17

Family

ID=40951914

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009552394A Active JP5182296B2 (en) 2008-02-07 2008-12-25 Manufacturing method of electronic component device

Country Status (3)

Country Link
JP (1) JP5182296B2 (en)
CN (1) CN101933129B (en)
WO (1) WO2009098831A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113419385A (en) * 2021-05-31 2021-09-21 北海惠科光电技术有限公司 Display panel, preparation method thereof and display device

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5445167B2 (en) * 2010-01-25 2014-03-19 パナソニック株式会社 Semiconductor device and manufacturing method thereof
MY160373A (en) * 2010-07-21 2017-03-15 Semiconductor Components Ind Llc Bonding structure and method
JP2012216612A (en) * 2011-03-31 2012-11-08 Toyota Industries Corp Electronic component module and manufacturing method therefor
TWI707484B (en) 2013-11-14 2020-10-11 晶元光電股份有限公司 Light-emitting device
JP6255949B2 (en) * 2013-11-29 2018-01-10 富士通株式会社 Bonding method and semiconductor device manufacturing method
US9230832B2 (en) 2014-03-03 2016-01-05 International Business Machines Corporation Method for manufacturing a filled cavity between a first and a second surface

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09326416A (en) * 1996-06-05 1997-12-16 Kokusai Electric Co Ltd Packaging of semiconductor device and product thereof
JP3900248B2 (en) * 2001-03-30 2007-04-04 ハリマ化成株式会社 Multilayer wiring board and method for forming the same
JP3827569B2 (en) * 2001-12-06 2006-09-27 旭化成エレクトロニクス株式会社 Circuit component for fine pattern connection and method for forming the same
JP2004128357A (en) * 2002-10-04 2004-04-22 Ebara Corp Electrode arranged substrate and its electrode connection method
JP3702961B2 (en) * 2002-10-04 2005-10-05 東洋通信機株式会社 Manufacturing method of surface mount type SAW device
JP2005116612A (en) * 2003-10-03 2005-04-28 Murata Mfg Co Ltd Flip chip packaging method and electronic circuit device using the same
JP2006202938A (en) * 2005-01-20 2006-08-03 Kojiro Kobayashi Semiconductor device and its manufacturing method
WO2007034893A1 (en) * 2005-09-22 2007-03-29 Nihon Handa Co., Ltd. Pasty metal particle composition, method of hardening pasty metal particle composition, method of bonding metal member, process for producing printed wiring board
JP5305148B2 (en) * 2006-04-24 2013-10-02 株式会社村田製作所 Electronic component, electronic component device using the same, and manufacturing method thereof
JP4361572B2 (en) * 2007-02-28 2009-11-11 株式会社新川 Bonding apparatus and method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113419385A (en) * 2021-05-31 2021-09-21 北海惠科光电技术有限公司 Display panel, preparation method thereof and display device
CN113419385B (en) * 2021-05-31 2022-09-27 北海惠科光电技术有限公司 Display panel, preparation method thereof and display device

Also Published As

Publication number Publication date
CN101933129B (en) 2012-03-28
CN101933129A (en) 2010-12-29
JP5182296B2 (en) 2013-04-17
WO2009098831A1 (en) 2009-08-13

Similar Documents

Publication Publication Date Title
US10515918B2 (en) Methods of fluxless micro-piercing of solder balls, and resulting devices
JP5182296B2 (en) Manufacturing method of electronic component device
JP5305148B2 (en) Electronic component, electronic component device using the same, and manufacturing method thereof
US9224713B2 (en) Semiconductor device and manufacturing method thereof
EP1445995B1 (en) Method of mounting an electronic component on a circuit board and system for carrying out the method
US9263426B2 (en) PoP structure with electrically insulating material between packages
KR100958857B1 (en) Semiconductor device and manufacturing method of the semiconductor device
JPH10256425A (en) Package substrate and manufacturing method thereof
WO2010070806A1 (en) Semiconductor device, flip-chip mounting method and flip-chip mounting apparatus
JPWO2007043152A1 (en) Semiconductor device and manufacturing method thereof
JP2012204631A (en) Semiconductor device, semiconductor device manufacturing method and electronic apparatus
JP5003689B2 (en) Conductive bump
WO2010016170A1 (en) Compression bonding device, compression bonding method, package, and pressing plate
KR102006637B1 (en) Method Of Forming Bump And Semiconductor device including The Same
JP3847693B2 (en) Manufacturing method of semiconductor device
JPWO2008120564A1 (en) Electronic component mounting structure and electronic component mounting method
KR20100095031A (en) Method for manufacturing electronic component module
CN107230667B (en) Electronic component, anisotropic connection structure, and method for designing electronic component
JP3972209B2 (en) Semiconductor device and manufacturing method thereof, circuit board, and electronic apparatus
JP2005340448A (en) Semiconductor device, its manufacturing method, circuit board, and electronic apparatus
KR100834804B1 (en) Flip-chip interconnecting method using metal stud stack or column, and electric circuit board
JP2002299809A (en) Electronic component mounting method and equipment
JP3768870B2 (en) Mounting method of semiconductor element
JP2002016104A (en) Mounting method of semiconductor device and manufacturing method of semiconductor device mounted assembly
JP4561969B2 (en) Semiconductor device

Legal Events

Date Code Title Description
A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20121023

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20121119

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20121218

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20121231

R150 Certificate of patent or registration of utility model

Ref document number: 5182296

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20160125

Year of fee payment: 3