JPWO2009084396A1 - Delay monitor circuit and delay monitor method - Google Patents

Abstract

It is an object of the present invention to provide a delay monitor circuit that solves the problem that a different critical path delay circuit needs to be provided for each semiconductor integrated circuit. The basic delay ring unit 2 oscillates the input signal Data and generates an input signal Data having a frequency characteristic according to design information of the semiconductor integrated circuit. The counter unit 3 counts the output signal of the basic delay ring unit 2 and determines whether or not the count value is larger than a reference value. The counter unit 3 outputs an internal signal when the count value is larger than the reference value. The evaluation unit evaluates the delay time of the semiconductor integrated circuit based on the internal signal output from the counter unit 3.

Description

  The present invention relates to a delay monitor circuit for evaluating a delay time of a semiconductor integrated circuit, and more particularly to a delay monitor circuit and a delay monitor method for evaluating a delay time of a semiconductor integrated circuit in order to control a power supply voltage, a threshold voltage, and the like. About.

  In recent years, low power consumption system LSI technology has been developed. In the low power consumption system LSI technology, a power supply control method is adopted in which the power consumption voltage and the threshold voltage of transistors and the like are controlled in accordance with the clock frequency to achieve low power consumption.

  In such a power supply control system, the delay time of the semiconductor integrated circuit is evaluated, and the power supply voltage and the threshold voltage are controlled so that the delay time is within a predetermined range.

  FIG. 1 is a block diagram showing a configuration of a delay monitor circuit for evaluating a delay time of a semiconductor integrated circuit.

  This delay monitor circuit includes a critical path delay unit 102 and delay margin units 103 and 104 between register units 101 and 105.

  The critical path delay unit 102 delays the input signal Data fetched into the register unit 101 by the critical path delay time of the semiconductor integrated circuit and outputs it. The delay margin unit 103 delays the signal output from the critical path delay unit 102 by the first additional delay time and outputs the delayed signal. The delay margin unit 104 delays the signal output from the delay margin unit 103 by the second additional delay time and outputs the delayed signal.

  Based on the signals output from the critical path delay unit 102 and the delay margin units 103 and 104, the determination unit 106 determines that the delay time of the semiconductor integrated circuit is greater than the sum of the critical path delay time and the first delay time, and Then, it is determined whether or not it is included in a range smaller than the sum of the critical path delay time and the second delay time.

  Examples of application of such a delay monitor circuit are described in Non-Patent Document 1 and Non-Patent Document 2, for example.

  The delay monitor circuit described in Non-Patent Document 1 includes a plurality of critical path delay units. Since the critical path changes according to the operating environment of the semiconductor integrated circuit, it is difficult to accurately evaluate the critical path delay time with only one critical path delay circuit. Since the delay monitor circuit described in Non-Patent Document 1 includes a plurality of critical path delay units, the critical path delay time can be evaluated more accurately.

The delay monitor circuit described in Non-Patent Document 2 has a plurality of gate elements and wiring elements instead of providing a critical path delay circuit. This delay monitor circuit uses the gate element and the wiring element to generate a critical path delay unit.
J. Friedrich, et al., “Design of the Power6TM Microprocessor,” ISSCC2007, pp.96-97, 2007. M. Nakai, S. Akui, K. Seno, T. Meguro, T. Seki, T. Kondo, A. Hashiguchi, H. Kawahara, K. Kumano, and M. Shimura, "Dynamic voltage and frequency management for a low -power embedded microprocessor, "IEEE Journal of Solid-State Circuits, vol. 40, pp. 28-35, January 2005.

  In the delay monitor circuits described in Non-Patent Document 1 and Non-Patent Document 2, in order to evaluate the critical path delay time, a critical path is specified for each semiconductor integrated circuit, and a critical path having the same delay characteristics as the critical path A delay circuit must be provided. For this reason, there is a problem that it is necessary to provide a different critical path delay circuit for each semiconductor integrated circuit.

  For example, in the delay monitor circuit described in Non-Patent Document 1, it is necessary to specify a critical path for each semiconductor integrated circuit and incorporate a critical path delay circuit having the same delay characteristics as the critical path into the delay circuit.

  In the delay monitor circuit described in Non-Patent Document 2, it is necessary to specify a critical path for each semiconductor integrated circuit, determine a circuit configuration having the same delay characteristics as the critical path, and generate the circuit.

  Accordingly, an object of the present invention is to provide a delay monitor circuit and a delay monitor method that solve the above-mentioned problem that it is necessary to provide a different critical path delay circuit for each semiconductor integrated circuit.

  A delay monitor circuit according to the present invention is a delay monitor circuit for evaluating a delay time of a semiconductor integrated circuit, and repeatedly delays an input signal Data with a delay characteristic determined according to design information of the semiconductor integrated circuit. A basic delay means for outputting the received input signal every time the delay is repeated, the input signal output from the basic delay means is counted, and it is determined whether or not the count value is greater than a reference value. Counter means for outputting an internal signal when the value is larger than the reference value, and evaluation means for evaluating the delay time of the semiconductor integrated circuit based on the internal signal output from the counter means.

  A delay monitoring method according to the present invention is a delay monitoring method for evaluating a delay time of a semiconductor integrated circuit, and repeatedly delays an input signal Data with a delay characteristic determined according to design information of the semiconductor integrated circuit, and the delay The output signal is output every time the delay is repeated, the output input signal is counted, it is determined whether or not the count value is greater than a reference value, and if the count value is greater than the reference value The internal signal is output, and the delay time of the semiconductor integrated circuit is evaluated based on the output internal signal.

  According to the present invention, it is not necessary to provide a different critical path delay circuit for each semiconductor integrated circuit.

It is the block diagram which showed the structure of the delay monitor circuit of related technology. 1 is a block diagram showing a configuration of a delay monitor circuit according to a first embodiment of the present invention. It is the circuit diagram which showed the structural example of the basic delay ring part. It is the circuit diagram which showed the structural example of the counter part. 6 is a timing chart for explaining the operation of the delay monitor circuit. It is the block diagram which showed the structure of the delay monitor circuit of the 2nd Embodiment of this invention. It is the block diagram which showed the structure of the delay monitor circuit of the 3rd Embodiment of this invention. It is the circuit diagram which showed the other structural example of the basic delay ring part. It is a timing chart for demonstrating the operation example of a basic delay ring part. It is the block diagram which showed the structure of the delay monitor circuit of the 4th Embodiment of this invention. It is the block diagram which showed the structural example of the maximum delay detection part. It is the block diagram which showed the structure of the delay monitor circuit of the 5th Embodiment of this invention. It is the block diagram which showed the structure of the delay monitor circuit of the 6th Embodiment of this invention. It is the block diagram which showed the structure of the delay monitor circuit of the 7th Embodiment of this invention. It is the circuit diagram which showed the structural example of the selector part. It is the circuit diagram which showed the other structural example of the counter part.

  Embodiments of the present invention will be described below with reference to the drawings. In addition, in each drawing, the same code | symbol is attached | subjected to what has the same function, and the description may be abbreviate | omitted.

  FIG. 2 is a block diagram showing the configuration of the delay monitor circuit according to the first embodiment of the present invention. In FIG. 2, the delay monitor circuit includes a register unit 1, a basic delay ring unit 2, a counter unit 3, delay margin units 4a and 4b, a register unit 5, a determination unit 6, and a register unit 7. . Here, the delay margin units 4a and 4b, the register unit 5, the determination unit 6, and the register unit 7 constitute an evaluation unit. In addition, the register unit 5 and the determination unit 6 constitute a determination unit.

  The register unit 1 captures the input signal Data in synchronization with the clock signal CLK of the semiconductor integrated circuit, and inputs the captured input signal Data to the basic delay ring unit 2 and the register unit 5. The input signal Data is, for example, a high (high) pulse for the width of one cycle of the clock signal CLK. In the following description, it is assumed that each signal is 1 in the case of High and 0 in the case of Low.

  The basic delay ring unit 2 is an example of basic delay means. The basic delay ring unit 2 repeatedly delays the input signal Data with the delay characteristics determined according to the design information of the semiconductor integrated circuit, and the delayed input signal Data is repeated each time the delay is repeated. Output.

  The design information includes a library used for designing the semiconductor integrated circuit, a design standard indicating the semiconductor integrated circuit, the wiring length of each gate, the allowable range of the capacitive load, and the like. The delay characteristic of the basic delay ring unit 2 is determined so as to reflect the critical path delay time.

  Specifically, the basic delay ring unit 2 includes a ring oscillator in which a plurality of delay circuits corresponding to design information of a semiconductor integrated circuit are connected in a ring shape. The ring oscillator repeatedly delays the input signal Data by the ring-shaped delay circuit to obtain an oscillation signal.

  Here, by determining the delay circuit according to the design information so as to reflect the delay of the critical path, the delay characteristic of the basic delay ring unit 2 is determined to reflect the delay characteristic of the critical path. The

  Examples of the delay circuit that reflects the delay characteristic of the critical path include an inverter gate circuit having the minimum number of vertically stacked transistors in the inverter gate circuit in the library, and a vertically stacked number of nMOS transistors in the NAND gate circuit in the library. Among the largest NAND gate circuits and NOR gate circuits in the library, there are NOR gate circuits having the largest number of vertically stacked pMOS transistors. The delay circuit may be a composite gate circuit having the maximum number of vertically stacked nMOS transistors and the maximum number of vertically stacked pMOS transistors among the composite gate circuits in the library. In addition, as the delay circuit, the repeater circuit in the library has a load having a wiring having the maximum length allowed by the design standard, and the logic gate circuit in the library has the maximum allowable by the design standard. A circuit having a capacitive load may be used.

  In the present embodiment, the ring oscillator is an odd-numbered ring oscillator. The odd-numbered ring oscillator is a ring oscillator in which an odd number of delay circuits are connected in a ring shape.

  FIG. 3 is a circuit diagram showing a configuration example of the basic delay ring unit 2. In FIG. 3, the basic delay ring unit 2 includes an odd-numbered ring oscillator having an even number of delay gate circuits 11 and a NAND gate circuit 12, and an inverter gate circuit 13. The NAND gate circuit 12 is the first stage of the ring oscillator. In this embodiment, the delay gate circuit 11 is an inverter gate circuit. The delay gate circuit 11 and the NAND gate circuit 12 are examples of delay circuits.

  Returning to FIG. The counter unit 3 counts the input signal Data output from the basic delay ring unit 2. For example, the counter unit 3 counts the number of rising edges of the input signal Data.

  The counter unit 3 determines whether or not the count value is larger than a predetermined reference value. The counter unit 3 outputs the internal signal tD0 when the count value is larger than the reference value.

  FIG. 4 is a circuit diagram illustrating a configuration example of the counter unit 3. In FIG. 4, the counter unit 3 includes a counter 21, a count value setting unit 22, a comparator 23, and an SR latch 24.

  The counter 21 counts the input signal Data output from the basic delay ring unit 2 and outputs the count value.

  The count value setting unit 22 holds the reference value and outputs the reference value.

  The comparator 23 compares the count value output from the counter 21 with the reference value output from the count value setting unit 22. When the count value becomes larger than the reference value, the comparator 23 outputs the input signal Data as the internal signal tD0 via the SR latch 24.

  Here, the number of stages of the ring oscillator and the reference value determine the delay time of the internal signal tD0 with respect to the input signal Data. This delay time is set to a value that achieves a desired delay time under a predetermined condition within an allowable range permitted by the setting standard of the semiconductor integrated circuit in accordance with the design information of the semiconductor integrated circuit.

  The predetermined condition is, for example, that the thickness of the wiring is the thinnest within the allowable range, the temperature of the semiconductor integrated circuit is the highest within the allowable range, and the threshold voltage of the transistor in the library is the highest within the allowable range. For example, conditions that are large or medium.

  The desired delay time is the cycle of the clock signal CLK of the semiconductor integrated circuit. However, even if the delay time of the internal signal tD0 with respect to the input signal Data is set to the cycle of the clock signal CLK according to the design information of the semiconductor integrated circuit, there is a possibility that it will be shifted from the cycle of the clock signal CLK of the actual semiconductor integrated circuit. is there. Therefore, the delay time of the internal signal tD0 with respect to the input signal Data is set to a value that provides a desired delay time based on the test result of the operation test of the delay monitor circuit performed in a specific operating environment. Good.

  The specific operating environment is, for example, an operating environment in which the temperature and the power supply voltage have the following values.

  For example, the temperature is a temperature at which the critical path delay time is longest. The power supply voltage is a power supply voltage that is within the power supply voltage allowed by the design standard and when the semiconductor integrated circuit operates at the highest frequency.

  The temperature is room temperature. The power supply voltage is within the power supply voltage permitted by the design standard and operates at a frequency at room temperature corresponding to the highest frequency at which the semiconductor integrated circuit operates at a temperature at which the critical path delay time is longest. Voltage.

  Returning to FIG. An evaluation unit including delay margin units 4a and 4b, register unit 5, determination unit 6, and register unit 7 evaluates the delay time of the semiconductor integrated circuit based on internal signal tD0 output from counter unit 3. To do. Specifically, each part which comprises an evaluation part performs the following processes.

  The delay margin unit 4a delays the internal signal tD0 output from the counter unit 3 by a first delay time to generate an internal signal tD1. The delay margin unit 4b generates the internal signal tD2 by delaying the internal signal tD1 generated by the delay margin unit 4a by the second delay time.

  The critical path delay time changes according to device variations. The first delay time corresponds to a margin for compensating for device variations. The second delay time corresponds to a margin for compensating for an overshoot or a control delay in the circuit speed control.

  The determination unit including the register unit 5 and the determination unit 6 compares the delay time of the internal signals tD1 and tD2 delayed by the delay margin units 4a and 4b with respect to the input signal Data, and the cycle of the clock signal CLK. The delay time of the semiconductor integrated circuit is evaluated.

  Specifically, the register unit 5 first converts the input signal Data output from the register unit 1 and the internal signals tD1 and tD2 generated by the delay margin units 4a and 4b, respectively, to the clock signal CLK. Capture in sync with.

  The determination unit 6 evaluates the delay time of the semiconductor integrated circuit based on the signal taken into the register unit 5.

  Specifically, the determination unit 6 evaluates whether the delay time of the semiconductor integrated circuit is within a predetermined range, whether the delay time is larger than the predetermined range, or whether the delay time is smaller than the predetermined range. To do.

  More specifically, the determination unit 6 evaluates that the delay time of the semiconductor integrated circuit is larger than a predetermined range when both of the internal signals tD1 and tD2 taken into the register unit 5 are 0. In this case, the clock cycle is smaller than the delay time of the internal signal tD1 with respect to the input signal Data.

  Further, when the internal signal tD1 taken into the register unit 5 is 1 and the internal signal tD2 taken into the register unit 5 is 0, the determination unit 6 has a delay time of the semiconductor integrated circuit within a predetermined range. Evaluate to be the value of. In this case, the clock cycle is larger than the delay time of the internal signal tD1 with respect to the input signal Data and smaller than the delay time of the internal signal tD2 with respect to the input signal Data.

  Further, when both the internal signals tD1 and tD2 taken into the register unit 5 are 1, the determination unit 6 evaluates that the delay time of the semiconductor integrated circuit is smaller than a predetermined range. In this case, the clock cycle is longer than the delay time of the internal signal tD2 with respect to the input signal Data.

  The register unit 7 captures the evaluation result of the determination unit 6 in synchronization with the evaluation clock signal CLK0, and outputs the captured evaluation result as an evaluation output signal.

  Next, the operation will be described.

  FIG. 5 is a timing chart for explaining the operation of the delay monitor circuit of this embodiment. FIG. 5 shows waveform changes of the clock signal CLK, the input signal Data, the internal signals tD1 and tD2, the evaluation results Up0 and Down0, the evaluation clock signal CLK0, the evaluation output signals Up and Down.

  The register unit 1 captures the input signal Data in synchronization with the clock signal CLK, and outputs the captured input signal Data to the basic delay ring unit 2 and the register unit 5.

  The basic delay ring unit 2 receives the input signal Data output from the register unit 1. The basic delay ring unit 2 oscillates the input signal Data, and outputs the input signal Date to the counter 21 of the counter unit 3 for each basic delay time.

  The counter 21 counts the input signal Data output from the basic delay ring unit 2 and outputs the count value to the comparator 23.

  The comparator 23 receives a count value from the counter 21 and receives a reference value from the count value setting unit 22. The comparator 23 compares the count value with the reference value, and when the count value becomes larger than the reference value, outputs the input signal Data to the delay margin unit 4a via the SR latch 24 as the internal signal tD0.

  The delay margin unit 4a receives the internal signal tD0 output from the counter unit 3, and delays the internal signal tD0 by a first delay time to generate the internal signal tD1. Then, the delay margin unit 4a outputs the internal signal tD1 to the delay margin unit 4b and the register unit 5.

  The delay margin unit 4b receives the internal signal tD1 output from the delay margin unit 4a and delays the internal signal tD1 by a second delay time to generate the internal signal tD2. Then, the delay margin unit 4a outputs the internal signal tD2 to the register unit 5.

  The register unit 5 synchronizes the input signal Data output from the register unit 1, the internal signal tD1 output from the delay margin unit 4a, and the internal signal tD2 output from the delay margin unit 4b with the clock signal CLK. Capture. The register unit 5 outputs each of the captured signals to the determination unit 6.

  The determination unit 6 receives the input signal Data, the internal signal tD1, and the internal signal tD2 output from the register unit 5.

  The determination unit 6 compares the input signal Data and the internal signal tD1. The determination unit 6 outputs the evaluation result Up0 having a value of 1 to the register unit 7 when the input signal Data is 1 and the internal signal tD1 is 0, and otherwise outputs the evaluation result Up0 having a value of 0 to the register unit 7 Output to.

  The determination unit 6 compares the input signal Data and the internal signal tD2. The determination unit 6 outputs the evaluation result Down0 having a value of 1 to the register unit 7 when the input signal Data is 1 and the internal signal tD2 is 1, and otherwise outputs the evaluation result Down0 having a value of 0 to the register unit 7 Output to.

  The register unit 7 captures the evaluation results Up0 and Down0 output from the determination unit 6 in synchronization with the evaluation clock signal CLK0. The evaluation clock signal CLK0 is adjusted to arrive at the register unit 7 after the evaluation results Up0 and Down0 are determined.

  The register unit 7 outputs evaluation output signals Up and Down according to the fetched evaluation results Up0 and Down0.

  When the evaluation result Up0 is 1 and the evaluation result Down is 0, the register unit 7 sets the evaluation output signal Up to 1 and sets the evaluation output signal Down to 0. When the evaluation result Up0 is 0 and the evaluation result Down is 0, the register unit 7 sets the evaluation output signal Up to 0 and sets the evaluation output signal Down to 0. Further, when the evaluation result Up0 is 0 and the evaluation result Down is 1, the register unit 7 sets the evaluation output signal Up to 0 and sets the evaluation output signal Down to 1.

  When the evaluation output signal Up is 1, the power supply voltage and the threshold voltage are controlled so that the circuit speed is increased. When the evaluation output signal Down is 1, the power supply voltage is adjusted so that the circuit speed is decreased. Threshold voltage etc. are controlled.

  The evaluation clock signal CLK0 can also be used as a reset signal. By resetting the counter 21 and the SR latch 24 in the counter unit 3 with the evaluation clock signal CLK0, the counter unit 3 can be reset in preparation for the next evaluation.

  Next, the effect will be described.

  In the present embodiment, the basic delay ring unit 2 repeatedly delays the input signal Data with the delay characteristics determined according to the design information of the semiconductor integrated circuit, and the delayed input signal Data is repeated each time the delay is repeated. Output. The counter unit 3 counts the input signal Data output from the basic delay ring unit 2 and determines whether or not the count value is larger than a reference value. The counter unit 3 outputs the internal signal tD0 when the count value is larger than the reference value. The evaluation unit evaluates the delay time of the semiconductor integrated circuit based on the internal signal tD0 output from the counter unit 3.

  In this case, the input signal Data is repeatedly delayed with a delay characteristic corresponding to the design information of the semiconductor integrated circuit. The delayed input signal Data is output every time the delay is repeated. The outputted input signal Data is counted, and when the count value is larger than the reference value, the internal signal tD0 is outputted. Further, the delay time of the semiconductor integrated circuit is evaluated based on the internal signal tD0.

  In this case, if the reference value is set so that the delay time of the internal signal tD0 with respect to the input signal Data becomes the clock cycle of the semiconductor integrated circuit, the semiconductor integrated circuit can be provided without providing a critical path delay circuit for each semiconductor integrated circuit. It becomes possible to evaluate the delay time of the circuit.

  In this embodiment, the basic delay ring unit 2 includes a ring oscillator in which a plurality of delay circuits according to design information of the semiconductor integrated circuit are connected in a ring shape, and the ring oscillator oscillates the input signal Data. The input signal Data is repeatedly delayed.

  In this case, if a delay circuit is appropriately selected, the delay time of the semiconductor integrated circuit can be evaluated without providing a critical path delay circuit for each semiconductor integrated circuit.

  In this embodiment, the delay circuit in the ring oscillator includes an inverter gate circuit having the smallest number of vertically stacked transistors in the inverter gate circuit in the library, and a vertically stacked number of nMOS transistors in the NAND gate circuit in the library. The largest NAND gate circuit, the NOR gate circuit having the largest number of vertically stacked pMOS transistors in the NOR gate circuit in the library, and the compound gate circuit in the library having the largest number of vertically stacked nMOS transistors and the pMOS transistor For complex gate circuits with the maximum number of vertical stacks, circuits that have the maximum wiring length allowed by the design criteria in the load, and circuits that have the maximum capacity load allowed by the design criteria in the logic gate circuits in the library is there.

  In this case, it becomes possible to accurately reflect the delay characteristic of the critical path.

  Further, in the present embodiment, the number of stages of the ring oscillator is set to a predetermined value within an allowable range in which the delay time of the internal signal tD0 with respect to the input signal Data is allowed by the design standard of the semiconductor integrated circuit, according to the design information of the semiconductor integrated circuit. The value is set so as to obtain a desired delay time under conditions.

  In this case, the power supply voltage and the threshold voltage can be controlled so that the critical path delay time becomes the desired delay time, and the performance of the semiconductor integrated circuit can be brought close to the target performance.

  In the present embodiment, the reference value is a predetermined condition within the allowable range allowed by the design standard of the semiconductor integrated circuit, in which the delay time of the internal signal tD0 with respect to the input signal Data is determined according to the design information of the semiconductor integrated circuit. Are set to values that provide a desired delay time.

  In this case, the power supply voltage and the threshold voltage can be controlled so that the critical path delay time becomes the desired delay time, and the performance of the semiconductor integrated circuit can be brought close to the target performance.

  In the present embodiment, the reference value is set to a value such that the delay time of the internal signal tD0 with respect to the input signal Data becomes a desired delay time according to the test result of the operation test performed in a specific operation environment. Is set.

  In this case, the delay time of the semiconductor integrated circuit can be evaluated more accurately. As a result, for example, the margin by the delay margin unit 4a can be reduced.

  In the present embodiment, an odd-numbered ring oscillator can be used as the basic delay ring unit 2.

  In this case, the configuration of the basic delay ring unit 2 can be simplified.

  Next, a second embodiment will be described.

  FIG. 6 is a block diagram showing the configuration of the delay monitor circuit of the second embodiment. In FIG. 6, the delay monitor circuit has a configuration in which the delay margin portion 4a is removed from the configuration shown in FIG.

  Further, the reference value held by the counter unit 3 is increased as compared with the first embodiment. That is, a value is added to the reference value so that the delay time of the internal signal tD1 with respect to the input signal Data is increased by the first delay time of the delay margin portion 4a. The first delay time is an example of an additional delay time.

  Next, the effect will be described.

  In the present embodiment, a value that increases the delay time of the internal signal tD1 with respect to the input signal Data by the first delay time is added to the reference value.

  In this case, if the first delay time is appropriately set, for example, it is not necessary to provide a circuit for delaying the internal signal by a delay time corresponding to a margin for compensating for device variations.

  Next, a third embodiment will be described.

  The critical path varies depending on the operating environment such as device performance, temperature, power supply voltage, and substrate bias voltage. This is because the delay characteristics of transistors, wirings, and the like vary depending on the operating environment, and the number of vertically stacked transistors varies depending on the type of gate.

  For this reason, if there is only one basic delay ring unit 2, the delay characteristic of the basic delay ring unit 2 may reflect a critical path when the operating environment changes. In the present embodiment, a plurality of basic delay ring units 2 are provided to compensate for a change in the critical path due to a change in the operating environment.

  FIG. 7 is a block diagram showing the configuration of the delay monitor circuit of the third embodiment. In FIG. 7, the delay monitor circuit further includes a maximum delay detector 8 in addition to the configuration shown in FIG. 6. There are a plurality of basic delay ring units 2 and a plurality of counter units 3. The number of basic delay ring units 2 and counter units 3 is 4 in FIG. 7, but is not limited to 4 in practice.

  Each of the basic delay ring units 2 has different delay characteristics. This is because, for example, the ring oscillator in the first basic delay ring unit 2 uses an inverter gate circuit in which the number of vertically stacked transistors in the library is the minimum as a delay circuit, and the second basic delay ring unit 2 This can be realized by using a NAND gate circuit having the maximum number of vertically stacked nMOS transistors as a delay circuit.

  Each of the basic delay ring units 2 is adjusted so that the delay times are equal to each other in a predetermined operating environment. The predetermined operating environment is preferably an operating environment in which the delay time of the semiconductor integrated circuit can be compensated by controlling the power supply voltage and the performance of the semiconductor integrated circuit is the highest. For example, the device performance is medium, the power supply voltage is medium, and the temperature is high. The predetermined operating environment may have low device performance, a medium power supply voltage, and a high temperature.

  Each of the counter units 3 has a one-to-one correspondence with each of the basic delay ring units 2. Each of the counter units 3 counts the input signal Data output from the basic delay ring unit 2 associated with itself. The counter unit 3 determines whether or not the count value is larger than the reference value. When the count value is larger than the reference value, the counter unit 3 outputs the input signal Data as the internal signal tD0.

  The maximum delay detection unit 8 outputs the internal signal tD0 output last from the internal signal tD0 output from each of the counter units 3 as the internal signal tD1.

  The maximum delay detection unit 8 is, for example, an AND gate circuit. In this case, when all the internal signals tD0 output from the counter unit 3 become 1, the maximum delay detection unit 8 outputs the internal signal tD1 having a value of 1.

  Further, when a buffer is used as the delay circuit, the delay time of the delay circuit changes. For example, the delay time of the delay circuit is maximized in the case of a rising edge or a falling edge of a signal propagating through the delay circuit.

  In this case, the basic delay ring unit 2 can accurately evaluate the delay time by oscillating the input signal Data with an even number of ring oscillators. The even-numbered ring oscillator is a ring oscillator in which an even number of delay gates are connected in a ring shape.

  FIG. 8 is a circuit diagram showing an even-numbered ring oscillator. FIG. 9 is a timing chart showing an operation example of the even-numbered ring oscillator.

  The even-stage ring oscillator includes an even-stage delay gate circuit 31, a NAND gate circuit 32, a NOR gate circuit 33, an inverter gate circuit 34, a register 35 with a reset function, and an SR latch 36. Here, the even-numbered delay gate circuit 31 is a circuit in which even-numbered delay gate circuits are connected in series. There are two NOR gate circuits 33, two inverter gate circuits 34, and two registers 35 with a reset function.

  In the even-numbered ring oscillator, as shown in the timing chart of FIG. 9, when the input signal EN becomes High, the High signal is taken into the register 35 with the reset function via the SR latch 36 and the two NOR gate circuits 33. It is. The register 35 with a reset function inputs the taken High signal to the even-numbered delay gate circuit 31, so that the High signal propagates to the even-numbered delay gate 31.

  A signal propagating through the even-numbered delay gate 31 is extracted as an intermediate signal A from the even-numbered delay gate 31. The register with reset function 35 uses the midway signal A to cause the captured High signal to fall to Low. After that, when the Low signal is output from the even-numbered delay gate circuit 31, the High signal propagates again through the even-numbered delay gate 31 circuit.

  By repeating the above operation, the input signal Data can be oscillated by the even-numbered ring oscillator.

  Next, the effect will be described.

  According to this embodiment, there are a plurality of basic delay ring units 2. In addition, each of the basic delay ring units 2 has different delay characteristics.

  Each delay characteristic of the basic delay ring unit 2 can be reflected in each delay characteristic of the critical path that changes according to the operating environment. Therefore, even if the critical path changes due to the change in the operating environment, it becomes possible to accurately evaluate the delay time of the semiconductor integrated circuit.

  In the present embodiment, the counter units 3 are associated with the basic delay ring units 2 on a one-to-one basis. Each of the counter units 3 counts the input signal Data output from the basic delay ring unit corresponding to itself. The maximum delay detection unit 8 outputs the internal signal tD0 output last from the internal signal tD0 output from each of the counter units 3 as the internal signal tD1. The evaluation unit evaluates the delay time of the semiconductor integrated circuit based on the internal signal tD1 output from the maximum delay detection unit 8.

  In this case, the delay time of the semiconductor integrated circuit is evaluated based on the internal signal tD0 output last among the internal signals tD0. The delay time of the last output internal signal with respect to the input signal Data reflects the critical path delay time.

  Therefore, it is possible to evaluate the delay time of the semiconductor integrated circuit based on the internal signal reflecting the critical path delay time without measuring the operating environment. Therefore, the delay time of the semiconductor integrated circuit can be easily evaluated.

  In the present embodiment, each of the basic delay ring units 2 may set the reference value of the counter unit in accordance with each of the basic delay ring units 2, and each delay of the internal signal tD0 in a predetermined operating environment. Time is equal.

  In this case, if a predetermined operating environment is appropriately set, a deviation from the target performance of the semiconductor integrated circuit can be directly observed.

  In the present embodiment, an even-numbered ring oscillator can also be used as the basic delay ring unit 2.

  In this case, even if a buffer or the like is used as the delay circuit of the ring oscillator, it becomes possible to accurately evaluate the delay time of the semiconductor integrated circuit.

  Next, a fourth embodiment will be described.

  FIG. 10 is a block diagram showing a configuration example of a delay monitor circuit according to the fourth embodiment of the present invention.

  In the third embodiment, the delay monitor circuit has the maximum delay detection unit 8 at the subsequent stage of the plurality of basic delay ring units 2 and the counter unit 3. In the present embodiment, the delay monitor circuit includes a maximum delay detection unit 8 at the subsequent stage of the plurality of basic delay ring units 2 and a counter unit 3 at the subsequent stage of the maximum delay detection unit 8.

  The maximum delay detection unit 8 outputs the input signal Data output last among the input signals Data output from each of the basic delay ring units 2. The counter unit 3 counts the input signal Data output from the maximum delay detection unit 8.

  FIG. 11 is a block diagram showing a configuration of the maximum delay detection unit 8 of the present embodiment.

  In FIG. 11, the maximum delay detection unit 8 includes a phase comparison unit 61, a selector 62, a head pulse removal unit 63, and an enable signal generation unit 64.

  The phase comparison unit 61 compares the phases of the input signals Data output from each of the plurality of basic delay ring units 2.

  The selector 62 is an example of a selection unit. The selector 62 outputs the input signal Data output last based on the comparison result of the phase comparator 61.

  The leading pulse removal unit 63 prevents the leading pulse from being crushed due to the detection delay of the input signal Data output last.

  The enable signal generation unit 64 is an example of a gating unit. The enable signal generation unit 64 stops the operation of the basic delay ring unit 2 different from the basic delay ring unit 2 that output the input signal Data last.

  Next, the operation will be described. In FIG. 11, each of S <b> 1 to S <b> 4 indicates the input signal Data output from each of the basic delay ring units 2. Further, each of AT, BT, CT, AB, BB, and CB indicates a comparison result of the phase comparison unit 61.

  When the reset signal R is input, the phase comparison unit 61 becomes AT = BT = CT = 0 and AB = BB = CB = 1, and the output of the NOR gate circuit in the leading pulse removal unit 63 becomes 1. Become.

  After reset release, when the output of the input signal DataS2 is slower than the output of the input signal DataS1, AT = 1 and AB = 0, and vice versa, AT = 0 and AB = 1. Further, when the output of the input signal DataS4 is slower than the output of the input signal DataS3, CT = 1 and CB = 0, and vice versa, CT = 0 and CB = 1.

  In addition, when the slower output of the input signal DataS3 and the input signal DataS4 is slower than the slower output of the input signal DataS1 and the input signal DataS2, BT = 1 and BB = 0, and vice versa. = 0 and BB = 1. The output of the OR gate circuit is output from 1 to 0 when all the input signals Data are output.

  The selector 62 outputs the last output input signal Data based on each of the comparison results AT, BT, CT, AB, BB and CB. For example, when AT = CT = BT = 1 and AB = BB = CB = 0, the selector 62 outputs the input signal DataS4.

  When the reset signal R is input, the head pulse removing unit 63 masks propagation of the input signal Data and stops outputting the input signal Data. When the input signal Data output last is input and the output of the OR gate circuit of the phase comparison unit 61 changes from 1 to 0, and the input signal Data changes from 1 to 0, the input of the NOR gate circuit becomes 00. And the mask is released. Thereafter, the input signal Data is output.

  When the reset signal R is input, the enable signal generation unit 64 continues to output the enable signal to all the basic delay ring units 2. Further, the enable signal generation unit 64 continues to output only the enable signal to the basic delay ring unit 2 that output the last output input signal Data, and stops outputting the enable signal to the other basic delay ring units 2. .

  Next, the effect will be described.

  According to the present embodiment, the maximum delay detection unit 8 outputs the input signal Data output last among the input signals Data output from each of the basic delay ring units 2. The counter unit 3 counts the input signal Data output from the maximum delay detection unit 8.

  In this case, it is not necessary to provide the counter unit 3 for each basic delay ring unit 2, so that the number of counter units 3 can be reduced. Therefore, the area overhead can be reduced.

  In the present embodiment, the maximum delay detection unit 8 includes a phase comparison unit 61 and a selector 62. The phase comparison unit 61 compares the phase of the input signal Data generated by each of the basic delay ring units 2. The selector 62 outputs the input signal Data output last based on the comparison result of the phase comparator 61.

  In this case, it is possible to easily output the input signal Data output last.

  In the present embodiment, the enable signal generation unit 64 stops the operation of the basic delay ring unit 2 different from the basic delay ring unit 2 that output the input signal Data last.

  In this case, the operation of the basic delay ring unit 2 that does not reflect the delay characteristics of the critical path can be stopped, so that power saving can be achieved.

  Next, a fifth embodiment will be described.

  FIG. 12 is a block diagram showing the configuration of the delay monitor circuit according to the fifth embodiment of the present invention. In FIG. 12, the delay monitor circuit further includes a frequency divider 9 in addition to the configuration shown in FIG.

  The frequency divider 9 divides the clock signal CLK to generate a divided clock signal CLKDIV.

  The frequency dividing unit 9 outputs the divided clock signal CLKDIV to the register units 1 and 5. The reference value is increased according to the frequency division ratio of the frequency divider 9. For example, the reference value is increased n times when the frequency division ratio is n.

  The evaluation unit compares the delay time of the input signal Data of the internal signal tD1 with the cycle of the divided clock signal CLKDIV to evaluate the delay time of the semiconductor integrated circuit.

  Differences in processing performed by each unit constituting the evaluation unit are as follows.

  The register unit 1 captures the input signal Data in synchronization with the divided clock signal CLKDIV. The register unit 5 takes in each of the input signal Data, the internal signal tD1, and the internal signal tD2 in synchronization with the divided clock signal CLKDIV.

  Next, the effect will be described.

  When the cycle of the clock signal CLK of the semiconductor integrated circuit is compared with the delay time of the internal signal tD0 with respect to the input signal Data, the ratio of the delay time of the reference delay ring unit 2 to the cycle of the clock signal CLK may increase. . In this case, since the reference value becomes small, the setting error of the reference value becomes large.

  According to the present embodiment, the frequency divider 9 divides the clock signal CLK of the semiconductor integrated circuit to generate the divided clock signal CLKDIV. The evaluation unit evaluates the delay time of the semiconductor integrated circuit by comparing the delay time with respect to the input signal of the internal signal tD1 and the cycle of the divided clock signal CLKDIV. The delay time of the internal signal tD1 with respect to the input signal Data is a value obtained by multiplying the delay time of the reference delay ring unit 2 by the reference value, and represents the critical path delay time.

  In this case, the delay time of the internal signal tD0 with respect to the input signal Data is compared with the period of the divided clock signal CLKDIV obtained by dividing the clock signal CLK. For this reason, the ratio of the delay time of the reference delay ring unit 2 to the period of the divided clock signal CLKDIV is reduced. Therefore, even if the ratio of the delay time of the reference delay ring unit 2 to the cycle of the clock signal CLK increases, the reference value can be increased. Therefore, it becomes possible to reduce the setting error of the reference value.

  Next, a sixth embodiment will be described.

  FIG. 13 is a block diagram showing the configuration of the delay monitor circuit of the sixth embodiment. In FIG. 13, the delay monitor circuit further includes a register delay unit 10 in addition to the configuration shown in FIG.

  The register delay unit 10 delays the internal signal tD0 output from the counter unit 3 by a third delay time to generate the internal signal tD1. Here, the third delay time corresponds to a delay time corresponding to the frequency division ratio of the frequency divider 9.

  The determination unit including the register 5 and the determination unit 6 compares the delay time of the internal signal tD1 generated by the register delay unit 10 with respect to the input signal Data, and the period of the divided clock signal CLKDIV, thereby comparing the semiconductor integrated circuit Evaluate the delay time.

  Next, the effect will be described.

  In the present embodiment, the register delay unit 10 delays the internal signal tD0 output from the counter unit 3 by a third delay time. The third delay time corresponds to a delay time corresponding to the frequency division ratio of the frequency divider 9. The determination unit compares the delay time of the internal signal tD0 delayed by the register delay unit 10 with respect to the input signal Data and the period of the divided clock signal CLKDIV to evaluate the delay time of the semiconductor integrated circuit.

  In this case, an error in the delay time of the internal signal tD0 caused by dividing the clock signal can be reduced.

  Next, a seventh embodiment will be described.

  FIG. 14 is a block diagram showing the configuration of the delay monitor circuit of the seventh embodiment. 14, the delay monitor circuit includes a selector unit 15, register units 16a to 16d, an OR gate circuit 17, and an AND gate circuit 18 in addition to the configuration shown in FIG. Here, the register units 16a to 16d, the OR gate circuit 17, and the AND gate circuit 18 are included in an evaluation unit (more specifically, a determination unit). There are a plurality of basic delay ring units 2. The number of basic delay ring units 2 is only 4 in FIG. 14, but is not limited to 4 in practice.

  The counter unit 3 sequentially counts the input signal Data output from each of the basic delay ring units 2 by a predetermined time. The counter unit 3 outputs an internal signal tD0 every time the count value becomes larger than the reference value. The predetermined time is the cycle of the evaluation clock signal CLK0. Further, the reference value may be different every predetermined time.

  Specifically, first, the selector unit 15 selects one of the input signals Data output from each of the basic delay ring units 4. The selector unit 15 changes the input signal Data to be selected in order every predetermined time.

  Subsequently, the counter unit 3 counts the input signal output from the selector unit 15, and outputs an internal signal tD1 when the count value becomes larger than the reference value. The counter unit 3 resets the count value every predetermined time.

  Hereinafter, the configuration of the counter unit 3 and the selector unit 15 will be described in detail with reference to FIGS. 15 and 16.

  FIG. 15 is a block diagram illustrating a configuration example of the selector unit 15. In FIG. 15, the selector unit 15 includes a select value setting unit 151 and a selector unit 152. In FIG. 15, as in FIG. 11, each of S <b> 1 to S <b> 4 indicates the input signal Data output from each of the basic delay ring units 2.

  The count value setting unit 151 includes four select value setting register units 151a. Each of the select value setting register units 151a is associated with one of the basic delay ring units 1 on a one-to-one basis.

  Each of the select value setting register units 151a is either a selection signal indicating selection of the input signal Data output from the corresponding basic delay ring unit 1 or a non-selection signal indicating non-selection of the input signal Data. Hold. Each of the select value setting register units 151 a outputs the selection signal or the non-selection signal held therein to the selector unit 152.

  Here, any one of the select value setting register units 151a holds a selection signal, and the other select value setting register units 151a hold non-selection signals.

  Each of the select value setting register units 151a takes in a selection signal or a non-selection signal output from another predetermined select value setting register unit 151 in synchronization with the evaluation clock signal CLK0.

  The selector unit 152 includes four selectors 152a. Each of the selectors 152a is in one-to-one correspondence with one of the select value setting register units 151a and the basic delay ring unit 2 corresponding to the select value setting register unit 151a.

  Each of the selectors 152a receives an input signal Data output from the basic delay ring unit 2 corresponding to itself and a selection signal or a non-selection signal output from the select value setting register unit 151a corresponding to itself.

  Each of the selectors 152a outputs the input signal Data every time the input signal Data is received from when the selection signal is received until the non-selection signal is received. Further, when each of the selectors 152a receives a non-selection signal, the selector 152a thereafter stops outputting the input signal Data.

  FIG. 16 is a block diagram illustrating a configuration example of the counter unit 3. In FIG. 16, in the counter unit 3, the count value setting unit 22 includes four count value setting register units 22a.

  The count value setting register unit 22a constitutes a shift register. Each of the count value setting register units 22a holds a reference value and outputs the reference value. The reference values held by the count value setting register unit 22a may be different from each other.

  The count value setting register unit 22a takes in a reference value output from another predetermined count value setting register unit 22a in synchronization with the evaluation clock signal CLK0. Further, any one of the count value setting register units 22 a outputs the held reference value to the comparator 23.

  Further, the counter 21 receives the evaluation clock signal CLK0 as a reset signal.

  Returning to FIG. The evaluation unit evaluates the delay time of the semiconductor integrated circuit for each internal signal output from the counter unit 3 based on the internal signal. The evaluation unit evaluates the true delay time of the semiconductor integrated circuit based on each evaluation result.

  Specifically, when all the evaluation results indicate that the delay time of the semiconductor integrated circuit is smaller than a predetermined range, the evaluation unit evaluates that the true delay time of the semiconductor integrated circuit is smaller than the predetermined range.

  Further, when at least one of the evaluation results indicates that the delay time of the semiconductor integrated circuit is larger than the predetermined range, the evaluation unit evaluates that the true delay time of the semiconductor integrated circuit is larger than the predetermined range.

  More specifically, the evaluation unit evaluates the true delay time of the semiconductor integrated circuit as follows.

  Each of the register units 16a to 16d is connected to each other in series. The register unit 16a is the first stage. The register unit 16a captures the evaluation results Up and Down output from the determination unit 5 in synchronization with the evaluation clock signal CLK0. The register unit 16a outputs the fetched evaluation results Up and Down.

  Each of the register units 16b to 16d captures the evaluation results Up and Down output from the previous register unit in synchronization with the evaluation clock signal CLK0. Each of the register units 16b to 16d outputs the fetched evaluation results Up and Down.

  The OR gate circuit 17 outputs an evaluation result Up having a value of 1 when at least one of the evaluation results UP0 output from each of the register units 16a to 16d is 1, and all of the evaluation results Up are 0. The evaluation result Up having a value of 0 is output.

  The AND gate circuit 18 outputs an evaluation result Down having a value of 1 when all of the evaluation results Down output from the register units 16a to 16d are 1, and if at least one of the evaluation results Down is 0. The evaluation result Down having a value of 0 is output.

  The register unit 7 captures the evaluation result Up output from the OR gate circuit 17 and the evaluation result Down output from the AND gate circuit 18 in synchronization with the divided evaluation clock signal. The divided evaluation clock signal CLK0 / 4 is a signal obtained by dividing the evaluation clock signal CLK0. This division ratio is the same as the number of basic delay ring units 2. That is, in the present embodiment, the frequency division ratio is 4.

  Next, the effect will be described.

  According to this embodiment, the counter unit 3 counts each of the input signals Data output from each of the basic delay ring units 2 in order for a predetermined time, and every time the count value becomes larger than the reference value. Output internal signals. The evaluation unit evaluates the delay time of the semiconductor integrated circuit for each internal signal output from the counter unit 3 based on the internal signal. The evaluation unit evaluates the true delay time of the semiconductor integrated circuit based on each evaluation result.

  In this case, it is not necessary to provide the counter unit 3 for each basic delay ring unit 2, so that the number of counter units 3 can be reduced. Therefore, the area overhead can be reduced.

  The present invention can be used for a delay monitor circuit of a system LSI compatible with DVFS (Dynamic Voltage and Frequency Scaling).

  Although the present invention has been described with reference to the embodiments, the present invention is not limited to the above embodiments. Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the scope of the present invention.

  This application claims the priority on the basis of Japanese application Japanese Patent Application No. 2007-340385 for which it applied on December 28, 2007, and takes in those the indications of all here.

Claims (25)

A delay monitor circuit for evaluating a delay time of a semiconductor integrated circuit,
Basic delay means for repeatedly delaying an input signal with delay characteristics determined according to design information of the semiconductor integrated circuit, and outputting the delayed input signal every time the delay is repeated;
A counter that counts the input signal output from the basic delay means, determines whether or not the count value is greater than a predetermined reference value, and outputs an internal signal when the count value is greater than the reference value Means,
A delay monitor circuit comprising: an evaluation unit that evaluates a delay time of the semiconductor integrated circuit based on an internal signal output from the counter unit; In the delay monitor circuit according to claim 1,
There is a plurality of basic delay means, and the delay characteristics are different from each other in each of the plurality of basic delay means. In the delay monitor circuit according to claim 2,
The counter means includes a plurality of counter means, and each of the plurality of counter means is associated with one of the plurality of basic delay means on a one-to-one basis, and counts an input signal output from the associated basic delay means. ,
Among the internal signals output by each of the plurality of counter means, including a maximum delay detection means for outputting the last output internal signal,
The evaluation unit is a delay monitor circuit that evaluates a delay time of the semiconductor integrated circuit based on an internal signal output from the maximum delay detection unit. In the delay monitor circuit according to claim 3,
The maximum delay detecting means is a delay monitor circuit which is an AND gate circuit. In the delay monitor circuit according to claim 2,
Among the input signals output from each of the plurality of basic delay means, including a maximum delay detection means for outputting the input signal output last,
The counter means is a delay monitor circuit for counting the input signal output from the maximum delay detecting means. In the delay monitor circuit according to claim 5,
The maximum delay detecting means is
Phase comparison means for comparing phases of input signals output from each of the plurality of basic delay means;
A delay monitor circuit including a selection unit that outputs the last output input signal based on a comparison result of the phase comparison unit; In the delay monitor circuit according to claim 5 or claim 6,
The maximum delay detecting means is
A delay monitor circuit comprising gating means for stopping the operation of a basic delay means different from the basic delay means that last outputted the input signal. In the delay monitor circuit according to claim 2,
The counter means counts each of the input signals output from each of the plurality of basic delay means in order for a predetermined time, and outputs an internal signal each time the count value becomes larger than the reference value,
The evaluation unit evaluates the delay time of the semiconductor integrated circuit based on the internal signal for each internal signal output from the counter means, and determines the true delay of the semiconductor integrated circuit based on each evaluation result. A delay monitor circuit that evaluates time. In the delay monitor circuit according to any one of claims 2 to 8,
Each of the plurality of basic delay means is a delay monitor circuit in which a delay time is equal to each other in a predetermined operating environment. The delay monitor circuit according to any one of claims 1 to 9, wherein
Frequency dividing means for dividing the clock signal of the semiconductor integrated circuit to generate a divided clock signal;
A delay monitor circuit configured to evaluate a delay time of the semiconductor integrated circuit by comparing a delay time of the internal signal with respect to the input signal and a cycle of the divided clock signal; In the delay monitor circuit according to claim 10,
The evaluation means includes a register delay means for delaying the internal signal by a delay time according to a frequency dividing ratio of the frequency dividing means,
A judgment means for evaluating a delay time of the semiconductor integrated circuit by comparing a delay time of the internal signal delayed by the register delay means with respect to the input signal and a cycle of the divided clock signal; Delay monitor circuit. The delay monitor circuit according to any one of claims 1 to 11, wherein:
The basic delay means includes a ring oscillator in which a plurality of delay circuits corresponding to the design information are connected in a ring shape,
The ring oscillator is a delay monitor circuit that repeatedly delays with the ring-shaped delay circuit. In the delay monitor circuit according to claim 12,
The ring oscillator includes a delay monitor circuit including, as the delay circuit, an inverter gate circuit having a minimum number of vertically stacked transistors among the inverter gate circuits in the library used in the design of the semiconductor integrated circuit. In the delay monitor circuit according to claim 12,
The ring oscillator is a delay monitor circuit including, as the delay circuit, a NAND gate circuit having a maximum number of vertically stacked nMOS transistors among NAND gate circuits in a library used for designing the semiconductor integrated circuit. In the delay monitor circuit according to claim 12,
The ring oscillator is a delay monitor circuit including, as the delay circuit, a NOR gate circuit having a maximum number of vertically stacked pMOS transistors among NOR gate circuits in a library used for designing the semiconductor integrated circuit. In the delay monitor circuit according to claim 12,
The ring oscillator delays a composite gate circuit having a maximum number of vertically stacked nMOS transistors and a maximum number of vertically stacked pMOS transistors among the composite gate circuits in the library used for designing the semiconductor integrated circuit. A delay monitor circuit included as a circuit. In the delay monitor circuit according to claim 12,
The ring oscillator includes a repeater circuit in a library used in the design of the semiconductor integrated circuit as the delay circuit, and the repeater circuit loads a wiring having a maximum length allowed by the design standard of the semiconductor integrated circuit. A delay monitor circuit; In the delay monitor circuit according to claim 12,
The ring oscillator includes a logic gate circuit in a library used in the design of the semiconductor integrated circuit as a delay circuit, and the logic gate circuit has a maximum capacitive load allowed by a design standard of the semiconductor integrated circuit. , Delay monitor circuit. The delay monitor circuit according to any one of claims 12 to 18, wherein:
The number of stages of the basic delay means is set so that the delay time of the internal signal with respect to the input signal is a predetermined condition within an allowable range permitted by a design standard of the semiconductor integrated circuit according to design information of the semiconductor integrated circuit. A delay monitor circuit that is set to a value that results in a delay time of. In the delay monitor circuit according to claim 19,
The reference value is set to a value such that a delay time of the internal signal with respect to the input signal becomes the desired delay time under the predetermined condition according to design information of the semiconductor integrated circuit . In the delay monitor circuit according to claim 19,
The reference value is set to a value such that a delay time of the internal signal with respect to the input signal becomes the desired delay time according to a test result of an operation test performed in a specific operation environment. Monitor circuit. The delay monitor circuit according to any one of claims 19 to 21, wherein
A delay monitor circuit, wherein a value that increases a delay time of the internal signal with respect to the input signal by a predetermined additional delay time is added to the reference value. The delay monitor circuit according to any one of claims 11 to 22, wherein
The ring oscillator is a delay monitor circuit which is an odd-numbered ring oscillator. The delay monitor circuit according to any one of claims 11 to 22, wherein
The ring oscillator is a delay monitor circuit which is an even-numbered ring oscillator. A delay monitoring method for evaluating a delay time of a semiconductor integrated circuit,
The input signal is repeatedly delayed with delay characteristics determined according to the design information of the semiconductor integrated circuit, and the delayed input signal is output every time the delay is repeated,
Counting the output input signal, determining whether the count value is greater than a predetermined reference value, if the count value is greater than the reference value, an internal signal is output,
A delay monitoring method for evaluating a delay time of the semiconductor integrated circuit based on the output internal signal.

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