JPWO2008142968A1 - Image pickup device and image pickup apparatus including the same - Google Patents

Abstract

The image pickup apparatus according to the present invention includes readout amplifiers 22 connected to the respective vertical transfer CCDs in the same number as the number of vertical transfer CCDs. The power supply unit 9a and the timing generator 9b sequentially drive the respective readout amplifiers 22. Thus, the read amplifier 22 reads only a fraction of the vertical transfer CCD without reducing the transfer cycle of the accumulation CCD and the vertical transfer CCD and the signal output frequency during signal readout. The frequency can be lowered, thereby reducing the readout noise of the amplifier while keeping the dark signal noise generated in the storage CCD and the vertical transfer CCD low.

Description

  The present invention relates to an image sensor that performs imaging by converting incident light into electric charge to generate a signal charge corresponding to the intensity of the light, and an image pickup apparatus including the same.

  As this type of imaging device, for example, there is a CCD (Charge Coupled Device) type solid-state imaging device. In recent years, in such a CCD solid-state imaging device (hereinafter abbreviated as “CCD”), in order to enable high-speed imaging, signal charges corresponding to the intensity of the light are generated by converting incident light into charges. There is an element provided with a plurality of charge storage units (for example, storage CCD cells) that store and store signal charges generated from the photoelectric conversion units beside a photoelectric conversion unit (for example, a photodiode) (see, for example, Patent Document 1). ). In this image sensor, a photoelectric conversion unit and a charge storage unit are arranged on a chip.

  In Patent Document 1, a CCD called a “pixel peripheral recording type image pickup device” is employed. This CCD will be described with reference to FIG. As shown in FIG. 7, the CCD 50 includes a plurality of the photodiodes 51 and storage CCDs 52 described above, and a vertical transfer CCD 53 that transfers the signal charges in the storage CCDs 52 in the vertical direction shown in FIG. I have. A read gate 54 for reading signal charges from the photodiode 51 to the storage CCD 52 adjacent to the photodiode 51 is provided beside each photodiode 51. In addition, a horizontal transfer CCD 55 is provided for transferring the signal charges transferred from the vertical transfer CCD 53 in the horizontal direction shown in FIG.

  In this “pixel peripheral recording type image pickup device”, the linear storage CCD 52 extends in an oblique direction. In this way, the CCD cells can be packed so as not to cause a wasteful space on the chip.

As described above, the “pixel peripheral recording type image pickup device” includes a plurality of storage CCDs, thereby enabling high-speed imaging with a shooting speed of 1.0 × 10 ⁶ frames / second (1,000,000 frames / second). Thus, even when the imaging cycle is as short as 1 μs, it is possible to perform imaging by transferring the signal charge from the accumulation CCD to the adjacent accumulation CCD in a short imaging cycle while sequentially accumulating the signal charges.

  Returning to the description of FIG. 7, a readout unit 57 including a readout amplifier 56 is connected downstream of the horizontal transfer CCD 55. Here, exposure / charge generation by a photoelectric conversion unit represented by a photodiode or photogate and transfer / storage to a charge accumulation unit represented by a CCD for storage are called “photographing”. If the charge transfer by the charge transfer unit represented by a CCD for external use and the external output via the read amplifier are called “read”, the operations of “shoot” and “read” are completely independent in time. This is a feature of the “pixel peripheral recording type imaging device”. That is, the readout frequency (amplifier drive frequency) is not limited to the imaging frequency (that is, the imaging speed) and can be set completely independently.

In order to make the operations of “photographing” and “reading” completely independent, a photodiode, a readout gate, a storage CCD, and a vertical transfer CCD are adopted as a CCD structure, and a readout unit including a readout amplifier is a CMOS. It is adopted as a (Complementary Metal Oxide Semiconductor) structure and formed separately using a semiconductor manufacturing process (for example, see Non-Patent Document 1). Specifically, a photodiode, a readout gate, a storage CCD, and a vertical transfer CCD are arranged on a CCD substrate, and a readout unit including a readout amplifier is arranged on a ROIC (CMOS Read Out Integrated Circuit) substrate. . Then, the CCD substrate and the ROIC substrate are electrically connected by indium bumps.
JP-A-9-55889 Xinqiao (Chiao) Liu, Boyd A. Fowler, Steve K. Onishi, Paul Vu, David D. Wen, Hung Do, and Stuart Horn, “CCD / CMOS Hybrid FPA for Low Light Level Imaging”, Fairchild Imaging, Inc. 1801 McCarthy Boulevard, Milpitas, CA 95035 U. S. Army Night Vision and Electronic Sensors Directorate, 10221 Burbeck Rd. , Fort Belvoir, VA 22060-5806

However, the CCD having such a configuration has the following problems.
That is, since the dark signal noise is added to the signal charge stored in the storage CCD in proportion to the storage time, the signal charge must be read promptly after the “shooting” is completed. For this reason, if the amplifier is driven at a high speed by increasing the read frequency (ie, reducing the sampling period) at the time of “read”, the read noise of the amplifier will increase and the equivalent noise electron number will be added to the signal charge. . FIG. 8 shows the relationship between the readout noise of such an amplifier and the sampling period. In other words, if reading is performed at a high speed so as to reduce the dark signal noise generated in the storage CCD, this causes a dilemma that the read noise of the amplifier increases.

  The present invention has been made in view of such circumstances, and it is possible to reduce both dark signal noise added to a signal during signal accumulation and dwelling and readout noise of an amplifier added to a signal during reading. An object of the present invention is to provide an image pickup device that can be used and an image pickup apparatus including the image pickup device.

In order to achieve such an object, the present invention has the following configuration.
That is, the imaging device of the present invention accumulates signal charges generated from a plurality of photoelectric conversion means for generating signal charges corresponding to the intensity of the light by converting incident light into charges. By providing a plurality of charge storage means for storing and a charge transfer means for reading and transferring the signal charges of the plurality of charge storage means, the photoelectric conversion means generates a signal charge, and the signal charge is converted into the charge An image pickup device configured to perform imaging while sequentially storing from a storage unit to a charge storage unit adjacent to the storage unit, and a read amplifier connected to each of the charge transfer units is connected to the charge transfer unit. The number of the read amplifiers is sequentially driven in preparation for the same number.

As described above, dark signal noise is added to the signal charge accumulated in the charge accumulation means (accumulation CCD) in proportion to the accumulation time. As shown in FIG. For example, if the interface state of the Si—SiO ₂ interface is shorter than the time for filling with electrons, dark signal noise does not occur until a predetermined signal accumulation / stay time is reached. FIG. 9 shows the relationship between such dark signal noise and signal accumulation / stay time. Therefore, it is desirable to shorten the time during which the signal charge stays in the charge storage means (storage CCD) during “reading” to some extent. For this purpose, in the structure having only one conventional read amplifier as shown in FIG. 7, sampling is performed by moving the read amplifier at high speed in order to read all signal charges to the outside in as short a time as possible. However, if the sampling period is reduced (that is, the read frequency is increased) in this way, as described above, the read noise added in the read amplifier increases. Therefore, according to the image pickup device of the present invention, the number of read amplifiers connected to each charge transfer means is the same as the number of charge transfer means, and each read amplifier is sequentially driven. Then, the transfer frequency of the charge storage / charge transfer means and the frequency of the signal output from the signal final output terminal to the outside of the sensor remain the same as before, but the same number as the charge transfer means, and in each connected read amplifier, Since the sampling period can be made longer than the conventional one (by a fraction of the charge transfer means, the readout frequency can be made lower than the conventional one), the readout noise of the amplifier added to the output signal Only reduces. In other words, each read amplifier operates at a very low speed even though all signal charges are read out quickly at a time interval that does not generate a dark signal in the charge storage / charge transfer means. Therefore, an ideal situation occurs in which almost no readout noise is added to the output signal. As a result, it is possible to reduce both the dark signal noise added to the signal during signal accumulation / dwell and the readout noise of the amplifier added to the signal during readout.

  In an example of the above-described invention, the imaging device is configured to be disposed on the first base and the second base other than the first base, and the photoelectric conversion unit, the charge storage unit, and the charge transfer unit are disposed on the first base. At the same time, the read amplifier is disposed on the second board, and the first board and the second board are electrically connected.

  In another example of the invention described above, the image sensor is configured to be disposed on a first base, a second base other than the first base, and a third base further different from the base, and the charge storage means. The charge transfer means is disposed on the first substrate, the read amplifier is disposed on the second substrate, the photoelectric conversion means is disposed on the third substrate, and the third substrate and the first substrate are electrically connected. And connecting the first base and the second base electrically.

  At least the charge storage means, the charge transfer means, and the read amplifier have different structures from each other (for example, the charge storage means and the charge transfer means have a CCD structure and the read amplifier has a CMOS structure). Therefore, as in the former example and the latter example, the imaging element is disposed on the first substrate and a second substrate different from the first substrate, and at least the charge storage unit and the charge transfer unit are disposed on the first substrate. At the same time, the read amplifier is disposed on the second substrate, and the first substrate and the second substrate are electrically connected, so that each substrate can be formed using a separate semiconductor manufacturing process. By electrically coupling (connecting) the substrates manufactured by separate processes in this way using inter-substrate connection technology (for example, indium bumps), for example, charge storage means and charge transfer means hold analog signals in an area-efficient manner. Each process can be manufactured using a CCD process with an embedded channel that can be used, and signal readout circuits such as shift registers and readout amplifiers can be integrated using a CMOS process to achieve complex readout control and reduce readout noise. The optimum design can be made by taking advantage of the above. In the latter example, the photoelectric conversion means is disposed on the third substrate, so that the area of the photoelectric conversion means can be increased without being occupied by the charge storage means and the charge transfer means. Thus, the aperture ratio can be improved.

  In the former example, specifically, the first substrate is a substrate manufactured by the CCD process, and the second substrate is a substrate manufactured by the CMOS process. Then, the first substrate manufactured by the CCD process and the second substrate manufactured by the CMOS process are electrically connected using indium bumps. More specifically, a charge injection diffusion layer is formed adjacent to the transfer gate at the lowest end of the charge transfer means, and the first base charge injection diffusion layer manufactured by the CCD process and the CMOS process are used. The second substrate is stacked on the first substrate so that the second substrate read amplifier is electrically connected, and the substrates are electrically connected to each other by indium bumps.

  In the latter example, specifically, the photoelectric conversion means is a photodiode, the first substrate is a substrate manufactured by the CCD process, the second substrate is a substrate manufactured by the CMOS process, and the third substrate is further formed. A substrate on which a photodiode is disposed.

  The imaging apparatus according to the present invention stores a plurality of photoelectric conversion units that generate signal charges corresponding to the intensity of light by converting incident light into electric charges, and accumulates and stores signal charges generated from the photoelectric conversion units. By providing a plurality of charge storage means and a charge transfer means for reading and transferring the signal charges of the plurality of charge storage means, the photoelectric conversion means generates a signal charge, and the signal charge is transferred to the charge storage means. An image pickup device comprising: an image pickup device configured to perform image pickup by transferring while sequentially storing in a charge storage unit adjacent thereto; and an image pickup device control unit that controls driving of the image pickup device, The image pickup device includes read amplifiers connected to the charge transfer units, respectively, in the number and number of charge transfer units, and the image pickup device control unit sequentially sets the read amplifiers. It is characterized in that controlled to movement.

  According to the imaging apparatus of the present invention, the readout amplifiers connected to the respective charge transfer units are provided in the same number as the number of the charge transfer units, and the imaging element control unit controls the readout amplifiers to be sequentially driven. Thus, in the read amplifier, the sampling period can be made longer than that of the conventional method by several times that of the charge transfer means (the read frequency can be made lower than that of the conventional method by a fraction of the charge transfer means). Can be reduced. On the other hand, the output frequency of the signal from the final signal output terminal is the same as in the prior art, and therefore the time that the signal charge stays in the charge storage / charge transfer means is small, so that no dark signal noise is added.

  According to the image pickup device and the image pickup apparatus including the same according to the present invention, the number of read amplifiers connected to each charge transfer means is the same as the number of charge transfer means, and the read amplifiers are sequentially driven. In the read amplifier, the sampling cycle can be made longer than the conventional method by several times the charge transfer means (the read frequency can be lowered by a fraction of the charge transfer means), thereby reducing the read noise of the amplifier. Can be made. On the other hand, the output frequency of the signal from the final signal output terminal is the same as in the prior art, and therefore the time that the signal charge stays in the charge accumulation / charge transfer means is small, so that no dark signal noise is added.

It is a block diagram which shows the outline of the imaging device using the CCD type solid-state image sensor (CCD) based on an Example. It is a block diagram which shows the structure of CCD which concerns on an Example. FIG. 4 is a circuit diagram of a reading unit according to an embodiment and a schematic diagram of the periphery thereof. (A), (b) is the schematic which showed the arrangement | positioning relationship of the CCD base | substrate and ROIC base | substrate which concern on an Example. (A)-(d) is a timing chart of each signal regarding the reading which concerns on an Example, (e) is a timing chart of each signal regarding the conventional reading. It is the schematic which showed the arrangement | positioning relationship of the CCD board | substrate and ROIC board | substrate which concern on a modification. It is a block diagram which shows the structure of the conventional CCD. It is the graph which showed the relationship between the read noise of an amplifier, and a sampling period. It is the graph which showed the relationship between dark signal noise and signal accumulation | storage time.

Explanation of symbols

1 ... CCD type solid-state imaging device (CCD)
9a: Power supply section 9b: Timing generator 11: Photodiode 12: Storage CCD
13 ... CCD for vertical transfer
22 ... Readout amplifier 30 ... CCD base 40 ... ROIC base

Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 is a block diagram illustrating an outline of an image pickup apparatus using a CCD solid-state image pickup device (CCD) according to an embodiment, and FIG. 2 is a block diagram illustrating a configuration of the CCD.

The imaging apparatus according to the embodiment is configured to capture an optical image of a subject, convert the captured optical image into a signal charge, and convert it into an electrical signal to capture the subject. That is, as shown in FIG. 1, the imaging apparatus includes a solid-state imaging device (CCD) 1, a lens 2, a correlated double sampling unit 3, an AD converter 4, an image processing calculation unit 5, a monitor 6, and an operation unit 7. And a control unit 8. Furthermore, the imaging apparatus includes a power supply unit 9a and a timing generator 9b. This imaging apparatus is used for high-speed imaging with a shooting speed of 1.0 × 10 ⁶ frames / second (1,000,000 frames / second). The solid-state image sensor (CCD) 1 corresponds to the image sensor in the present invention, and the power supply unit 9a and the timing generator 9b correspond to the image sensor control means in the present invention.

  The lens 2 captures an optical image of the subject. The correlated double sampling unit 3 performs a process of removing a reset noise component from the electric signal converted into a voltage amplitude proportional to the number of signal charges by the read amplifier 22 described in the CCD 1 and passes it to the subsequent stage. The AD converter 4 converts the electric signal into a digital signal. The image processing arithmetic unit 5 performs various arithmetic processes to create a two-dimensional image of the subject based on the electrical signal digitized by the AD converter 4. The monitor 6 outputs the two-dimensional image on the screen. The operation unit 7 performs various operations necessary for execution of imaging. The control unit 8 performs overall control of the entire apparatus in accordance with operations such as shooting conditions set by the operation unit 7.

  The power supply unit 9a applies a voltage to a read gate 14 (see FIG. 2) described later, a transfer electrode that transfers signal charges in the CCD 1, and the like. The timing generator 9b generates a voltage application timing, an imaging timing, a clock, and the like. As described above, the timing generator 9b generates timing, clock, and the like, and the power supply unit 9a applies a voltage to the transfer electrode and the like, so that the power supply unit 9a and the timing generator 9b drive the CCD 1. In particular, in the present embodiment, as shown in timing charts of FIGS. 5A to 5D described later, a reading unit 20 (see FIG. 2) for each vertical transfer CCD 13 described later (see FIG. 2). Are controlled in order to drive sequentially.

  Next, a specific configuration of the CCD 1 will be described with reference to FIG. 2 in comparison with FIG. 7 which is a block diagram showing a configuration of a conventional CCD.

  As shown in FIG. 2, the CCD 1 converts a incident light (optical image of a subject) into a charge to generate a signal charge corresponding to the intensity of the light, and a signal generated from the photodiode 11. There are provided a plurality of accumulation CCDs 12 for accumulating and storing charges, and a vertical transfer CCD 13 for transferring signal charges in these accumulation CCDs 12 in the vertical direction shown in FIG. The photodiode 11 corresponds to the photoelectric conversion means in the present invention, the storage CCD 12 corresponds to the charge storage means in the present invention, and the vertical transfer CCD 13 corresponds to the charge transfer means in the present invention.

  A readout gate 14 is disposed beside each photodiode 11, and each readout gate 14 reads signal charges from the photodiode 11 to the storage CCD 12 adjacent thereto.

  Each accumulating CCD 12 is connected in a line, and a plurality of accumulating CCDs 12 are arranged. The signal charges generated from the photodiodes 11 are accumulated in each accumulation CCD 12 while being sequentially transferred to the adjacent accumulation CCDs 12. Then, the signal charges sequentially transferred from the storage CCD 12 are joined to the vertical transfer CCD 13. The signal charges transferred from the vertical transfer CCD 13 are read out to a reading unit 20 described later.

  The photodiodes 11 are two-dimensionally arranged, and the linear storage CCD 12 extends in an oblique direction because the photodiodes 11 are arranged in parallel in the horizontal and vertical directions. The CCD 1 according to the present embodiment is a so-called “pixel peripheral recording type image pickup device”.

By providing a plurality of storage CCDs 12 in this manner, image pickup is performed by sequentially transferring signal charges from the storage CCDs 12 to the storage CCDs 12 adjacent thereto. Therefore, even when the shooting cycle is as short as 1 μs as in the case of high-speed imaging with a shooting speed of 1.0 × 10 ⁶ frames / second (1,000,000 frames / second), imaging is performed with a short shooting cycle. Can do.

  In the present embodiment, the difference from the conventional CCD (see FIG. 7) is that, in the prior art, a readout unit 57 having a readout amplifier 56 is used as a readout unit 20 downstream of the vertical transfer CCD 13 as shown in FIG. The horizontal transfer CCD 55 (see FIG. 7) is eliminated. More specifically, the readout amplifiers 22 (see FIG. 3) of the readout unit 20 connected to the respective vertical transfer CCDs 13 are provided in the same number as the vertical transfer CCDs 13. Then, the read amplifiers 22 described later are sequentially driven by the power supply unit 9a and the timing generator 9b via the row selector 23 described later (see FIG. 3).

  Next, a more specific configuration of the reading unit 20 will be described with reference to FIG. FIG. 3 is a circuit diagram of the reading unit and a schematic diagram of the periphery thereof. In FIG. 3, a description will be given by taking four-phase pulse driving as an example on the CCD substrate 30 side. In addition, it is not limited to 4 phase pulse drive, For example, 2 phase, 3 phase, and 5 phase pulse drive may be sufficient.

  In this embodiment, a photodiode 11, a readout gate 14, a storage CCD 12, and a vertical transfer CCD 13 (all of which are shown in FIG. 2) are arranged on a CCD substrate 30, and a readout unit 20 including a readout amplifier 22. Are arranged on a ROIC (CMOS Read Out Integrated Circuit) base 40. In this embodiment, the CCD substrate 30 employs an N-sub / P-well type.

That is, as shown in FIG. 3, the CCD substrate 30 includes an N-type silicon substrate (indicated as “N-sub” in FIG. 3) 31, and a P-well region 32 in which P-type ions are diffused (in FIG. And a buried channel 33 in which N-type ions (indicated by “n” in FIG. 3) are further diffused. As a four-phase pulse drive, a transfer gate 34 for applying _four transfer electrodes Φ ₁ , Φ ₂ , Φ ₃ , and Φ ₄ is stacked on the buried channel 33.

At the lowest end of the vertical transfer CCD 13 (see FIG. 2), a transfer gate 35 for applying a signal TX (TX1, TX2, TX3, TX4,...) Is stacked on the P-well region 32, and P A charge injection diffusion layer (also referred to as “floating diffusion” or “sense node”) 36 in which high-concentration N-type ions (indicated by “n ⁺ ” in FIG. 3) are diffused in the well region 32 is adjacent to the transfer gate 35. Let it form.

  On the other hand, the ROIC substrate 40 (that is, the reading unit 20) employs a CMOS (Complementary Metal Oxide Semiconductor) structure. The read unit 20 is connected to the power supply voltage VDD, and a reset gate 21 that applies a signal RX (RX1, RX2, RX3, RX4,...) To the gate, and a read amplifier 22 (“Buf” in FIG. 3) connected thereto. , AMP1, AMP2, AMP3, AMP4,..., And a row selector 23 connected to the gate and applying a signal RS (RS1, RS2, RS3, RS4,...) To the gate, and a signal RX ( RX1, RX2, RX3, RX4,..., And a signal RS (RS1, RS2, RS3, RS4,...) Applied to the gate of the row selector 23, represented by “Shift Register” in FIG. ). Since each vertical transfer CCD 13 (see FIG. 2) includes a read amplifier 22, the number of reset gates 21 and row selectors 23 in the read unit 20 is the same as the number of vertical transfer CCDs 13, and each signal TX, RX and RS are the same as the number of CCDs 13 for vertical transfer. The read amplifier 22 corresponds to the read amplifier in this invention.

  The charge injection diffusion layer 36 of the CCD substrate 30 and the reset gate 21 and the read amplifier 22 of the ROIC substrate 40 (readout unit 20) are electrically connected by indium bumps 50 by extending lead wires (not shown) and the like. ing. On the other hand, downstream of the row selector 23 of the reading unit 20, the outputs of the row selector 23 for each of the vertical transfer CCDs 13 (see FIG. 2) arranged in a row (Row) are combined into one metal wiring 25 (FIG. 2). , See FIG.

As is apparent from this configuration, the reading unit 20 is configured by combining a detector called a conventional floating diffusion amplifier (FDA), a row selector 23 and a shift register 24. Transfer electrodes Φ ₁ , Φ ₂ , Φ ₃ , Φ ₄ , signal TX (TX1, TX2, TX3, TX4,...), Signal RX (RX1, RX2, RX3, RX4,...) And signal RS (RS1, RS1). RS2, RS3, RS4,... Are generated by the power supply unit 9a together with the applied voltage applied to the above-described read gate 14 (see FIG. 2), and are applied at a predetermined timing by the timing generator 9b.

  In particular, in the present embodiment, the power supply unit 9a and the timing generator 9b are supplied with signals TX (TX1, TX2, TX3, TX4,...) At the timings shown in the timing charts of FIGS. The read amplifiers 22 are sequentially driven by controlling the signal RX (RX1, RX2, RX3, RX4,...) And the signal RS (RS1, RS2, RS3, RS4,...). The signal RX (RX1, RX2, RX3, RX4,...) And the signal RS (RS1, RS2, RS3, RS4,...) Are sent from the power supply unit 9a and the timing generator 9b to the reset gate 21 via the shift register 24. The voltage is applied to the gate and the gate of the row selector 23, respectively.

  In this way, by controlling the signal TX (TX1, TX2, TX3, TX4,...), The signal RX (RX1, RX2, RX3, RX4,...) And the signal RS (RS1, RS2, RS3, RS4,...). Each row selector 23 selects the vertical transfer CCDs 13 (see FIG. 2) arranged in a row (Row) one by one, and sequentially turns on the gate switching for each selected vertical transfer CCD 13. Drive.

  Next, a specific arrangement relationship between the substrates 30 and 40 will be described with reference to FIG. FIG. 4 is a schematic diagram showing the arrangement relationship between the CCD base and the ROIC base.

  The photodiode 11, the readout gate 14, the accumulation CCD 12 and the vertical transfer CCD 13 (see FIG. 2) and the readout section 20 (see FIG. 3) including the readout amplifier 22 have different structures from each other. ing. The photodiode 11, the readout gate 14, the accumulation CCD 12, and the vertical transfer CCD 13 have a CCD structure as described above, and the readout section 20 has a CMOS structure. Therefore, as shown in FIGS. 3 and 4, the photodiode 11, the readout gate 14, the accumulation CCD 12 and the vertical transfer CCD 13 are arranged on the CCD substrate 30, and the readout unit 20 including the readout amplifier 22 is provided in the ROIC. It is disposed on the base 40. Then, by electrically connecting the CCD substrate 30 and the ROIC substrate 40 by the indium bumps 50, the substrates 30 and 40 can be formed using different semiconductor manufacturing processes.

  By electrically connecting (connecting) the substrates 30 and 40 manufactured by separate processes in this manner by using an inter-substrate connection technology (for example, indium bump 50), for example, the storage CCD 12 and the vertical transfer CCD 13 can generate analog signals. Embedded in a CCD process of a buried channel capable of holding the area efficiently, and signal readout circuits (reading unit 20 in this embodiment) such as the shift register 24 and the readout amplifier 22 are integrated using a CMOS process, and complicated readout control is performed. The optimum design can be made by taking advantage of each process, such as realizing the above and reducing read noise. The CCD substrate 30 corresponds to the first substrate in the present invention, and the ROIC substrate 40 corresponds to the second substrate in the present invention.

  As shown in FIG. 4A, the ROIC substrate 40 is stacked on the CCD substrate 30. At this time, each substrate 30, 40 is connected so that the charge injection diffusion layer 36 of the CCD substrate 30 and the reset gate 21 and readout amplifier 22 (see FIG. 3) of the ROIC substrate 40 are electrically connected by the indium bump 50. Adjust the position of. Then, as shown in FIG. 4B, the ROIC substrate 40 is stacked on the CCD substrate 30, and the substrates 30 and 40 are electrically connected to each other by the indium bumps 50.

  Next, specific drive control of the reading unit 20 will be described with reference to FIGS. 5 (a) to 5 (d). FIG. 5A to FIG. 5D are timing charts of signals related to reading according to the present embodiment. Further, in order to compare with a timing chart of each signal related to conventional reading, a description will be given with reference to FIG. FIG. 5E is a timing chart of signals related to conventional reading. In this embodiment, the readout frequency of the readout amplifier 22 of the readout unit 20 is 1 MHz (sampling period 1 μs, expressed as “1000 ns” in FIGS. 5A to 5D), and the number of CCDs 13 for vertical transfer. Is described as 4.

  FIG. 5A shows signals RX1, RX2, and so on for each vertical transfer CCD 13 applied to the gate of the reset gate 21 (see FIG. 3, represented by “Reset Gate” in FIG. 5A). 4 is a timing chart of RX3 and RX4. FIG. 5B shows the signals TX1, TX2, TX3, TX4 for each vertical transfer CCD 13 applied to the transfer gate 35 (see FIG. 3, expressed as “Transfer Gate” in FIG. 5B). It is a timing chart. FIG. 5C shows signals RS1, RS2, RS3 for the respective vertical transfer CCDs 13 applied to the gate of the row selector 23 (see FIG. 3, expressed as “Row Select” in FIG. 5C). It is a timing chart of RS4. FIG. 5D is a timing chart of the signals RX1, TX1, RS1 when attention is paid to one read amplifier 22 (see FIG. 3, “AMP1” in FIG. 5D).

  5A to 5D used for comparison with FIGS. 5A to 5D show one readout amplifier in the readout unit 57 downstream of the horizontal transfer CCD 55 in the conventional CCD 50. FIG. 56 (refer to FIG. 7 for each) 56 is a timing chart of each signal RX, TX, RS. In FIG. 5E, the readout frequency of the readout amplifier 56 is 4 MHz (sampling period 0.25 μs, in FIG. 5E, expressed as “250 ns”).

  When attention is paid to one read amplifier 22 (see FIG. 3, “AMP1” in FIG. 5D), the signals RX1, TX1, RS1 are applied as shown in FIG. 5D. Specifically, the signal RX1 is applied to the gate of the reset gate 21 (see FIG. 3; expressed as “Reset Gate” in FIG. 5A). By applying the signal RX1, the potential of the charge injection diffusion layer 36 (see FIG. 3) is reset. When the application of the signal RX1 is stopped, the potential of the charge injection diffusion layer 36 is in a floating state (that is, in a floating state).

  After the application of the signal RX1 is stopped, the signal charge is transferred to the lowermost end of the vertical transfer CCD 13 (see FIG. 2), and this time, the transfer gate 35 (see FIG. 3 and FIG. The signal TX1 is applied to the “Transfer Gate”. By applying the signal TX1, the signal charge transferred to the lowermost end is sent to the charge injection diffusion layer 36 (see FIG. 3) via the transfer gate 35. By feeding signal charges into the charge injection diffusion layer 36, the potential of the floating charge injection diffusion layer 36 changes. The change in the potential of the charge injection diffusion layer 36 due to the signal charge is proportional to the sent signal charge. This potential change is subsequently taken out by applying the signal RS1 to the gate of the row selector 23 (see FIG. 3, represented by “Row Select” in FIG. 5C).

  Focusing only on the read amplifier, except for the read frequency, the timing chart of FIG. 5 (d) is the same as the conventional timing chart of FIG. 5 (e). The difference from the conventional timing chart of FIG. 5 (e) is that, as shown in FIGS. 5 (a) to 5 (c), signals RX1, RX2, RX3, RX4, signals TX1, TX2, TX3, TX4, By applying the signals RS1, RS2, RS3, and RS4 and sequentially turning on each vertical transfer CCD 13 (see FIG. 2), the gate switching is sequentially turned on for each selected vertical transfer CCD 13. It is in the point to drive.

  That is, paying attention to the reset gate 21 (refer to FIG. 3 and represented by “Reset Gate” in FIG. 5A), when applying the signals RX1, RX2, RX3, RX4 to the gate of the reset gate 21, respectively, As shown in FIG. 5A, signals RX1, RX2, RX3, RX4 are sequentially applied to each vertical transfer CCD 13. Specifically, while the signal RX1 is applied to the gates of the reset gates 21, the signals RX2, RX3, RX4 are not applied to the remaining gates of the reset gates 21. That is, only the reset gate 21 related to the signal RX1 connected to the read amplifier 22 is selected, the potential of the charge injection diffusion layer 36 (see FIG. 3) is reset, and the remaining reset gates related to the signals RX2, RX3, RX4. 21 is not selected. When the application of the signal RX1 is stopped, the next signal (the signal RX2 in FIG. 5A) is applied to the gate of the reset gate 21. Similarly, while the signal RX2 is applied to the gates of the reset gates 21, the signals RX1, RX3, RX4 are not applied to the remaining gates of the reset gates 21.

  When the application of the signal RX2 is stopped in the same manner, the next signal (the signal RX3 in FIG. 5A) is applied to the gate of the reset gate 21. Similarly, while the signal RX3 is applied to the gate of the reset gate 21, the signals RX1, RX2, and RX4 are not applied to the remaining gates of the reset gate 21. When the application of the signal RX3 is stopped in the same manner, the next signal (the signal RX4 in FIG. 5A) is applied to the gate of the reset gate 21. Similarly, while the signal RX4 is applied to the gate of the reset gate 21, the signals RX1, RX2, and RX3 are not applied to the remaining gates of the reset gate 21. In this embodiment, since the number of the vertical transfer CCDs 13 is 4, when the application of the signal RX4 is stopped, the next signal returns to the signal RX1 and the signal RX1 is applied to the gate of the reset gate 21 in the same procedure. .

  Focusing on the transfer gate 35 (refer to FIG. 3, represented by “Transfer Gate” in FIG. 5B), when applying the signals TX1, TX2, TX3, TX4 to the transfer gate 35, respectively, FIG. As shown in FIG. 8, signals TX1, TX2, TX3, and TX4 are sequentially applied to each vertical transfer CCD 13. Specifically, when the signal TX1 is applied to the transfer gate 35, the time is delayed by the mutual time delay of the application of the signals RX1, RX2, RX3, and RX4 in FIG. In (b), the signal TX2) is applied to the transfer gate 35. That is, when the signal TX1 is applied, the signal charge is sent to the charge injection diffusion layer 36 (see FIG. 3), and after being delayed by the time delay described above, the signal TX2 is applied and the signal TX1 is applied to the charge injection diffusion layer 36. Send in charge.

  In the same manner, when the signal TX2 is applied to the transfer gate 35, the time is delayed by the mutual time delay of the application of the signals RX1, RX2, RX3, RX4 in FIG. In b), the signal TX3) is applied to the transfer gate 35. When the signal TX3 is applied to the transfer gate 35 in the same manner, the time is delayed by the mutual time delay of the application of the signals RX1, RX2, RX3, RX4 in FIG. 5A, and the next signal (FIG. 5 ( In b), the signal TX4) is applied to the transfer gate 35. Since the number of the vertical transfer CCDs 13 is 4, when the signal TX4 is applied to the transfer gate 35, the next signal returns to the signal TX1, and the signal TX is applied to the transfer gate 35 in the same procedure. Note that when the signal TX4 is applied to the transfer gate 35, the application of the signal TX1 to the transfer gate 35 is already stopped.

  Focusing on the row selector 23 (refer to FIG. 3, represented by “Row Select” in FIG. 5C), when the signals RS1, RS2, RS3, and RS4 are respectively applied to the gates of the row selector 23, FIG. As shown in c), the signals RS1, RS2, RS3, and RS4 are sequentially applied to each vertical transfer CCD 13. Specifically, while the signal RS1 is being applied to the gate of the row selector 23, the signals RS2, RS3, and RS4 are not applied to the remaining gates of the row selector 23. That is, only the row selector 23 related to the signal RS1 connected to the read amplifier 22 is selected, the potential change is taken out from the charge injection diffusion layer 36 (see FIG. 3), the read amplifier 22 is driven, and the signals RS2, RS3 The read amplifiers 22 connected to the remaining row selectors 23 for RS4 are not driven. When the application of the signal RS1 is stopped, the next signal (the signal RS2 in FIG. 5C) is applied to the gate of the row selector 23. Similarly, while the signal RS2 is being applied to the gate of the row selector 23, the signals RS1, RS3, and RS4 are not applied to the remaining gates of the row selector 23.

  When the application of the signal RS2 is stopped in the same manner, the next signal (the signal RS3 in FIG. 5C) is applied to the gate of the row selector 23. Similarly, while the signal RS3 is applied to the gate of the row selector 23, the signals RS1, RS2, and RS4 are not applied to the remaining gates of the row selector 23. When the application of the signal RS3 is stopped in the same manner, the next signal (the signal RS4 in FIG. 5C) is applied to the gate of the row selector 23. Similarly, while the signal RS4 is applied to the gate of the row selector 23, the signals RS1, RS2, and RS3 are not applied to the remaining gates of the row selector 23. In this embodiment, since the number of CCDs 13 for vertical transfer is set to 4, when the application of the signal RS4 is stopped, the next signal returns to the signal RS1 and the signal RS1 is applied to the gate of the row selector 23 in the same procedure. . Note that the mutual time delay of the application of the signals RX1, RX2, RX3, RX4 in FIG. 5A is the same as the mutual time delay of the application of the signals RS1, RS2, RS3, RS4 in FIG. Please note that.

  To summarize the above, a reset gate related to the signal RX1 connected to the read amplifier 22 by applying the signal RX1 to the gate of the reset gate 21 (see FIG. 3, represented by “Reset Gate” in FIG. 5A). Only 22 is selected, and the potential of the charge injection diffusion layer 36 (see FIG. 3) is reset. After stopping the application of the signal RX, the signal TX1 is applied to the transfer gate 35 (see FIG. 3; expressed as “Transfer Gate” in FIG. 5B), thereby sending the signal charge into the charge injection diffusion layer 36. . In a state where the signal TX1 is applied, the signal RS1 connected to the read amplifier 22 is applied by applying the signal RS1 to the gate of the row selector 23 (see FIG. 3, referred to as “Row Select” in FIG. 5C). Only the row selector 23 is selected, the potential change is taken out from the charge injection diffusion layer 36, and the read amplifier 22 is driven.

  Apart from the readout amplifier 22 for the signals RX1, TX1, RS1, FIG. 5 (a) after application of the signal RX1 to the gate of the reset gate 21 (see FIG. 3, denoted as “Reset Gate” in FIG. 5 (a)). ) By delaying the time by the mutual time delay of the application of the signals RX1, RX2, RX3, RX4, and applying the signal RX2 to the gate of the reset gate 21, thereby selecting only the reset gate 21 related to the signal RX2. Then, the potential of the charge injection diffusion layer 36 (see FIG. 3) is reset. Since the signals TX2 and RS2 are the same as the signals TX1 and RS1, their description is omitted.

  Separately from the read amplifier 22 relating to the signals RX2, TX2, and RS2, after applying the signal RX2 to the gate of the reset gate 21 (see FIG. 3, referred to as “Reset Gate” in FIG. 5A), FIG. ), The signal RX3 is applied to the gate of the reset gate 21 by delaying the time by the mutual time delay of the application of the signals RX1, RX2, RX3, RX4, and only the reset gate 21 related to the signal RX3 is selected. Then, the potential of the charge injection diffusion layer 36 (see FIG. 3) is reset. Since the signals TX3 and RS3 are the same as the signals TX1 and RS1, the description thereof is omitted. Further, the subsequent read amplifiers 22 related to the signals RX4, TX4, and RS4 are the same as the read amplifiers 22 related to the signals RX1, TX1, and RS1, and thus the description thereof is omitted.

As described above, dark signal noise is added to the signal charge stored in the storage CCD 12 in proportion to the storage time, but as shown in FIG. If the interface state of the SiO ₂ interface is shorter than the time for filling with electrons, dark signal noise does not occur until a predetermined signal accumulation / stay time is reached. Therefore, it is desirable to shorten the time during which the signal charge stays in the storage CCD 12 during “reading” to some extent. For this purpose, in the conventional structure as shown in FIG. 7 (structure having only one read amplifier 56), there is only one read amplifier for quickly reading out all the signal charges stored in the storage CCD to the outside of the sensor. 22 is driven at a high frequency at high speed. However, if the sampling period is reduced in this way (that is, the read frequency is increased), as described above, the read noise added in the read amplifier 22 is increased.

  Therefore, according to the above-described CCD 1 and the image pickup apparatus including the same, the readout amplifiers 22 respectively connected to the vertical transfer CCDs 13 are provided in the same number as the number of the vertical transfer CCDs 13 (four in this embodiment). The power supply unit 9a and the timing generator 9b drive each read amplifier 22 sequentially. Then, the transfer frequency of the storage CCD 12 and the vertical transfer CCD 13 and the frequency of the signal output from the signal final output terminal to the outside of the sensor remain the same as before, but the same number as the vertical transfer CCD 13 and the connected readouts. In the amplifier 22, the sampling cycle is made longer than the conventional one by several times (four times in this embodiment) of the vertical transfer CCD 13 (one quarter of the vertical transfer CCD 13 (one quarter in this embodiment)). (In FIG. 5 (a) to FIG. 5 (b), 1 MHz, sampling period 1000 ns), only the amplifier read noise added to the output signal is reduced. That is, although all the signal charges are read out to the outside quickly at a time interval that does not generate a dark signal in the storage CCD 12 and the vertical transfer CCD 13, the read amplifiers 22 are extremely slow. Since it is operating, an ideal situation arises in which almost no readout noise is added to the output signal. Therefore, only the readout noise of the amplifier can be reduced by slowing only the sampling frequency of each read amplifier 22 without slowing the charge transfer rate or the output frequency of the signal from the final output terminal. As a result, it is possible to reduce both the dark signal noise added to the signal during signal accumulation / dwell and the readout noise of the amplifier added to the signal during readout.

  The present invention is not limited to the above-described embodiment, and can be modified as follows.

  (1) The above-described embodiment is suitable for high-speed imaging with a shooting speed of 100,000 frames / second or more, but may be applied to normal imaging with a shooting speed of less than 100,000 frames / second.

  (2) In the above-described embodiments, a photodiode is taken as an example of the photoelectric conversion means, but a photogate may be used instead.

  (3) In the above-described embodiments, the “pixel peripheral recording type image pickup device” using the oblique CCD is described as an example. However, the image pickup device is configured so that the linear storage CCD extends in the vertical direction. Alternatively, the present invention can also be applied to a storage element constituted by a matrix-shaped storage CCD.

  (4) In the above-described embodiment, as shown in FIG. 4, the photodiode 11, the readout gate 14, the accumulation CCD 12, and the vertical transfer CCD 13 (all refer to FIG. 2) are disposed on the CCD substrate 30. The readout unit 20 (see FIG. 3) including the readout amplifier 22 is disposed on the ROIC board 40 and the CCD board 30 and the ROIC board 40 are electrically connected. However, the structure is not limited to that shown in FIG. . For example, as shown in FIG. 6, a CCD substrate 30, a ROIC substrate 40 different from the CCD substrate 30, and another PD (Photo Diode) substrate 60 other than the substrates 30 and 40, a storage CCD 12 and a vertical transfer CCD 13 ( 2 (see FIG. 2) is disposed on the CCD substrate 30, the readout unit 20 (see FIG. 3) including the readout amplifier 22 is disposed on the ROIC substrate 40, and the photodiode 11 is connected to the PD substrate 60. The PD substrate 60 and the CCD substrate 30 may be electrically connected, and the CCD substrate 30 and the ROIC substrate 40 may be electrically connected. In the case of this modification (4), since the photodiode 11 is disposed on the PD substrate 60, the area of the photodiode 11 is increased without being occupied by the storage CCD 12 and the vertical transfer CCD 13. And the aperture ratio can be improved. The PD base 60 corresponds to the third base in the present invention.

Claims (8)

  A plurality of photoelectric conversion means for generating signal charges according to the intensity of the light by converting incident light into charges; a plurality of charge storage means for storing and storing signal charges generated from the photoelectric conversion means; Charge transfer means for reading out and transferring signal charges of the plurality of charge storage means, and generating signal charges by the photoelectric conversion means, and the signal charge is transferred from the charge storage means to the charge storage means adjacent thereto. The image pickup device is configured to perform image pickup by transferring while sequentially storing the read amplifiers, and has the same number of read amplifiers connected to each of the charge transfer means as the number of charge transfer means, and each read amplifier The image sensor is configured to sequentially drive the sensors.   2. The imaging device according to claim 1, wherein the imaging device is arranged on a first base and a second base different from the first base, and the photoelectric conversion means, the charge storage means, and the charge transfer means are provided. An image pickup device, wherein the image pickup device is provided on the first base, and the read amplifier is provided on the second base to electrically connect the first base and the second base.   3. The image pickup device according to claim 2, wherein the first base is a base manufactured by a CCD process, and the second base is a base manufactured by a CMOS process.   4. The image pickup device according to claim 3, wherein the first base manufactured by a CCD process and the second base manufactured by a CMOS process are electrically connected using indium bumps. .   5. The image pickup device according to claim 4, wherein a charge injection diffusion layer is formed adjacent to a transfer gate at a lowermost end of the charge transfer means, and the charge injection diffusion layer on the first substrate manufactured by a CCD process is provided. The second substrate is stacked on the first substrate so that the second substrate read amplifier manufactured by the CMOS process is electrically connected, and the substrates are electrically connected to each other by the indium bumps. Connecting.   The image pickup device according to claim 1, wherein the image pickup device is arranged on a first base, a second base other than the first base, and a third base further different from the base, and the charge accumulation. And the charge transfer means are disposed on the first base, the read amplifier is disposed on the second base, the photoelectric conversion means is disposed on the third base, and a third base is provided. An image pickup device characterized by electrically connecting the first base and the first base, and electrically connecting the first base and the second base.   7. The imaging device according to claim 6, wherein the photoelectric conversion means is a photodiode, and the first base is a base manufactured by a CCD process, the second base is a base manufactured by a CMOS process, and The image pickup device, wherein the third base is a base on which the photodiode is disposed.   A plurality of photoelectric conversion means for generating signal charges according to the intensity of the light by converting incident light into charges; a plurality of charge storage means for storing and storing signal charges generated from the photoelectric conversion means; Charge transfer means for reading out and transferring signal charges of the plurality of charge storage means, and generating signal charges by the photoelectric conversion means, and the signal charge is transferred from the charge storage means to the charge storage means adjacent thereto. An image pickup apparatus comprising: an image pickup device configured to transfer images while sequentially storing images; and an image pickup device control unit that controls driving of the image pickup device; The number of readout amplifiers connected to the charge transfer means is the same as the number of charge transfer means, and the image sensor control means is controlled to drive each readout amplifier sequentially. Imaging device according to claim Rukoto.

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