JPWO2007138646A1 - NONVOLATILE MEMORY ELEMENT, MANUFACTURING METHOD THEREOF, AND SEMICONDUCTOR DEVICE USING NONVOLATILE MEMORY ELEMENT - Google Patents

Abstract

The nonvolatile memory element includes a variable resistance portion and a memory cell selection MISFET connected in series to the variable resistance portion. The variable resistance portion includes a thin film (tantalum pentoxide film 20) made of a strongly correlated electron material whose outermost electron trajectory is composed of d electrons or f electrons, and a first electrode in ohmic contact with one surface of the thin film. (Electrode 21) and the second electrode (plug 19) in non-ohmic contact with the other surface of the thin film, and the magnitude of the electric resistance value at the interface between the thin film made of strongly correlated electron material and the second electrode To store information. As the strongly correlated electron material or electrode material, a material already used in an existing silicon process or a material that can be easily introduced is used.

Description

  The present invention relates to a nonvolatile memory element and a manufacturing technique thereof, and more particularly to a technique effective when applied to a variable resistance nonvolatile memory using a strongly correlated electron material.

  Large scale integration technology using silicon (Si) has become an indispensable technology for modern society. For example, personal computers and mobile phones are equipped with a plurality of LSIs. These LSIs include what is called a processor that processes information, such as a CPU (Central Processing Unit), and what is called a memory that stores information, such as DRAM (Dynamic Random-Access Memory). and so on. As the semiconductor microfabrication technology advances, more processors and memories can be integrated into a single semiconductor chip (hereinafter simply referred to as a chip), and more information can be processed. It can be done. High integration by miniaturization of elements is called scaling and is a guiding principle that supports the semiconductor industry.

  However, as the minimum processing dimension at the product level falls below 100 nm, great difficulty has arisen in further miniaturization of elements. For example, each of the transistors that support the CPU is mainly a field effect transistor (Metal Insulator Semiconductor Field Effect Transistor; MISFET). The thickness of the gate insulating film of the MISFET is less than 2.0 nm. This is actually as thin as about 10 atomic layers. Therefore, when the gate insulating film is further thinned, a tunnel current directly flows in the film, resulting in an increase in power consumption.

Therefore, in order to solve this problem, as a gate insulating film material, a high dielectric constant gate insulating film having a dielectric constant larger than that of conventional silicon oxide (SiO ₂ ) (the relative dielectric constant is often expressed by k). Research and development (called high-k membranes) are being actively carried out all over the world. Although the application of the high-k film to the gate insulating film has not yet been put into practical use, it is considered to be an indispensable technology for the next-generation CPU.

  In this way, as you can see from the transistor example, it is not enough to simply scale down the structure for further scaling, and we are considering introducing new materials that are not used in the silicon process. There is a need to. By introducing new materials, if the performance that is currently considered to be the limit can be overcome, the performance of the LSI chip can be further enhanced, and more advanced information processing can be performed. You will be able to meet your needs.

Performance improvements due to the introduction of new materials are not limited to CPUs. A DRAM, which is a kind of memory, stores information by the amount of electric charge stored in a capacitor. However, in order to store more electric charge, a high-voltage such as tantalum oxide (Ta ₂ O ₅ ) is used as a capacitor insulating film. k membranes have been applied and are already in mass production.

  However, even in DRAMs, further thinning of the high-k insulating film causes an increase in leakage current, which is not allowed from the viewpoint of device performance deterioration and reliability reduction. In addition, in the DRAM, there is a problem that when the area of the capacitor is reduced by miniaturization, the capacity is reduced. Until now, the area has been prevented from decreasing by making the capacitor structure deep trench type. However, when further miniaturization is promoted, the aspect ratio of the trench reaches the limit of processing, and even with the most advanced processing technology, it becomes impossible to make a device with high yield. Limitations are being considered.

  In view of such a situation, various new memory devices have been proposed recently. For example, a phase change memory using a chalcogenide material, an MRAM (Magnetic RAM) using spin, a molecular memory using oxidation / reduction of organic molecules, an RRAM (Resistance Random Access Memory), and the like can be given. Whether these memories can be a replacement technology for DRAMs is currently a hundred-year-old controversy, but in order to replace the currently popular DRAMs, it is not possible to simply extend the technology. That is, in addition to the high-speed read memory characteristics of current DRAMs, new added value is required. Specifically, the non-volatility of maintaining the memory characteristics even when the power is shut off is required. If a non-volatile RAM is realized, for example, an OS (Operating System) can be started immediately after the personal computer is turned on, so that the convenience for consumers is greatly improved.

Of the many nonvolatile RAM candidates described above, the RRAM is a memory element that is attracting attention because it uses a substance called a strongly correlated electron system and can read and write at high speed. For example, in Patent Document 1 (US Pat. No. 6,673,691B2), a non-volatile memory characteristic occurs in a quaternary perovskite structure in which Pt layers are in contact with the upper and lower sides of a Pr _0.7 Ca _0.3 MnO ₃ layer. In addition, it is disclosed that the memory can be rewritten by inverting the sign of the voltage pulse. Further, Patent Document 1 discloses that when an RRAM is used, the time required for writing / erasing is shorter than that of a DRAM, and sufficient retention characteristics as a nonvolatile memory can be obtained.

Non-Patent Document 1 (Applied Physics Letters, (2004) pp.4073-4075) epitaxially grows a Pr _0.7 Ca _0.3 MnO ₃ layer on a SrRuO ₃ lower electrode epitaxially grown on a SrTiO ₃ substrate. Furthermore, it has been reported that in a structure in which the upper electrode is made of Ti, non-linear rectification characteristics can be obtained and hysteresis appears. On the other hand, Non-Patent Document 2 (Technical Digest of International Electron Device Meeting, (2004) pp.587-590) is non-volatile in a structure in which a noble metal layer is laminated on and under a NiO layer which is a binary transition metal oxide. It is reported that a symmetric current-voltage (IV) characteristic can be obtained even if the positive / negative sign is inverted. In addition, when a voltage having a single sign of only a positive voltage or only a negative voltage is applied, depending on whether a low voltage or a high voltage is applied, the resistance of the element is changed to a high resistance state or a low resistance It is reported that it can be in a state.
US Pat. No. 6,673,691B2 Applied Physics Letters, (2004) pp.4073-4075 Technical Digest of International Electron Device Meeting, (2004) pp.587-590

  As described above, there have been several attempts to apply strongly correlated electron materials to memory devices, but so far, there is a prospect that they will be integrated and commercialized on a large scale like DRAM. It's hard to say standing. The problems to be solved which the present inventors have studied are described below.

First of all, the RRAM reported so far does not reveal the mechanism of memory operation. The inventors of the present application previously examined RRAM. The material of Pr _0.7 Ca _0.3 MnO ₃ reported in Patent Document 1 and Non-Patent Document 1 is also called CMR material because it exhibits giant magnetoresistance (CMR). Giant magnetoresistance refers to a phenomenon in which the resistance drops significantly when a magnetic field is applied. It is understood that this negative magnetoresistance is caused by the suppression of magnetic scattering by applying a magnetic field. However, such a phenomenon appears only at a temperature of −50 ° C. or lower, typically about −200 ° C. or lower, and the relationship with the memory effect observed at room temperature is not clear.

As disclosed in Non-Patent Document 1, the resistance value observed in the RRAM is overwhelmingly larger than the bulk resistance value inherent in the material itself of Pr _0.7 Ca _0.3 MnO ₃ . This suggests that a large resistance is generated at the interface between Pr _0.7 Ca _0.3 MnO ₃ and the electrode, which determines the characteristics of RRAM. However, in the structure disclosed in Patent Document 1, that is, when the same electrode material (Pt) is formed above and below Pr _0.7 Ca _0.3 MnO ₃ , the properties of the upper and lower interfaces are symmetrical. It is believed that there is.

However, it cannot be understood that a memory property appears when a symmetrical structure is used. This is because if a voltage is applied to one interface and the interface becomes a low resistance (or high resistance) state, the other interface becomes a high resistance (or low resistance) state. Even if the sign of the voltage is changed, the fact that one interface has a high resistance and the other has a low resistance should not change, so that the memory performance cannot be explained. Non-Patent Document 1 discovered that memory properties appear when the upper and lower electrode materials of Pr _0.7 Ca _0.3 MnO ₃ are changed, and the Schottky barrier generated at the interface is not changed. We argue that there is not. However, the reason why the Schottky barrier changes and the memory operation is observed has not been sufficiently elucidated academically.

  Regarding the mechanism of the memory operation, Non-Patent Document 2 argues that the formation of a filamentous percolation path caused by applying a voltage is related to the memory operation. However, if the formation of such a conduction path is the origin of memory, the device is about to undergo dielectric breakdown, and it is difficult to mass-produce devices with long-term reliability with high yield. It is done.

  Thus, if the memory operating mechanism is unknown, there is a problem that guidelines for optimizing the memory structure and process development cannot be established. In addition, it cannot be determined whether the observed memory is scalable. Moreover, the problem that reliability evaluation is difficult also arises.

The second problem of the RRAM is that the affinity for the silicon process is low because the memory material and the electrode material are special. For example, Pr _0.7 Ca _0.3 MnO ₃ disclosed in Patent Document 1 and Non-Patent Document 1 is a quaternary system in which four elements are used, so that a uniform film can be formed with good control. It is very difficult. That is, it is known that the composition group is a substance group in which the resistance value of the material changes greatly if the composition is slightly different, and it is difficult to make many devices with a high yield. In addition, CMR materials represented by Pr _0.7 Ca _0.3 MnO ₃ have a complicated crystal structure called a perovskite structure. Such a complex crystal structure is not suitable for mass production. Actually, in order to use the epitaxial growth technique used in Non-Patent Document 1, a single crystal substrate as a base such as a SrTiO ₃ substrate is required, and silicon having a large lattice constant cannot be used as the substrate.

  In addition to the memory material, the electrode material is also special, which makes it difficult to introduce it into the silicon process. In the RRAM disclosed in Patent Document 1 and Non-Patent Document 1, a Pt electrode is used. However, Pt is likely to become a contamination source because of its high thermal diffusion rate, and it is not easy to introduce it into a silicon process. In order to obtain the memory characteristics of the RRAM, it is desirable that it is a noble metal. However, for the same reason, it is difficult to introduce any noble metal such as Pt into a silicon process. Non-Patent Document 2 also describes that a noble metal electrode is desirable when NiO is used as a memory material.

  An object of the present invention is to provide a nonvolatile memory element using a strongly correlated electronic material.

  Another object of the present invention is to provide a technique for manufacturing a nonvolatile memory element using a strongly correlated electronic material.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  First, in order to achieve the first object of the present invention, the principle that the memory property appears will be described. Since the nonvolatile RAM of the present invention utilizes a phenomenon called metal-insulator transition or “Mott transition”, this will be briefly described first.

  1A to 1F schematically show the crystal structure of a series of substance groups called strongly correlated electron systems. A state in which the atomic sites 1 are arranged in order is forming a crystal lattice. Here, for the sake of simplicity, only the atomic sites 1 that contribute to conduction are shown. In addition, although explanation of the band degeneration effect and the like is omitted, the expansion to the case where there is band degeneration is easy.

It is the outermost electrons, not the inner electrons that are strongly bound in the atoms, that determine the physical properties such as the magnitude of electrical resistance. FIG. 1 shows an electron 2 having an upward spin and an electron 3 having a downward electron among the outermost electrons. FIG. 1A shows the number of electrons per unit volume (a combination of electrons 2 having upward spins and electrons 3 having downward electrons with respect to the number of atomic sites 1 per unit volume (N _site )). The case where N _el ) is overwhelmingly small (N _site >> N _el ) is shown. In this case, since the number of electrons serving as carriers contributing to conduction is small, the electric resistance is high, and the system behaves as a band insulator.

Here, consider increasing the number of electrons to the state shown in FIG. Changing the number of conduction electrons is called doping. As a doping method, a method of substituting a part of the atomic site 1 with an atom having a different valence, putting excess oxygen into a gap between crystals, Methods such as putting in are known. In the state of FIG. 1B, since many electrons exist (N _site > N _el ), the electric resistance is low, and the system behaves as a metal.

Here, it is assumed that the number of electrons is further increased and the state shown in FIG. In the state of FIG. 1C, the number of atomic sites 1 and the number of electrons are approximately the same (N _{site to} N _el ). The characteristic of the strongly correlated electron system appears best in the state shown in FIG.

  A state in which an electron 2 having an upward spin and an electron 3 having a downward electron simultaneously enter the same atomic site 1 is called a double occupation state. In a strongly correlated electron system, a very strong electron-electron interaction works between electrons in a double occupation state. This is because most of the strongly correlated electron systems are transition metal oxides and the like, and the outermost orbit is composed of d electrons or f electrons, so that the electron orbits are strongly bound to the atomic site 1. is there.

  As a result of such strong Coulomb repulsion, the electrons move away from each other so as not to occupy the atomic sites 1 as much as possible. In the state of FIG. 1C in which the number of atomic sites 1 is the same as the number of electrons, it is difficult to move because the atomic site 1 adjacent to many electrons is already occupied by another electron. It is. Here, there is a restriction that electrons having the same spin cannot absolutely enter the same atomic site 1 due to the Pauli exclusion rate. In order to move without violating Pauli's exclusion rate, it must be in a double occupancy state, but in this case, it becomes a double occupancy state because a very strong Coulomb interaction works and becomes energetically disadvantageous. The probability is small. As a result, although the number of electrons is very large, the electrons cannot move around, so the electrical resistance is high, and the system behaves as an insulator. This state is called a Mott-insulator after the physicist motto that has been analyzed for a long time. Thus, the phenomenon of becoming a metal or becoming an insulator with the change in the number of electrons is called a metal-insulator transition or a Mott transition.

  Next, consider the state of FIG. 1D in which the number of electrons is further increased from the state of FIG. In this case, either the electron 2 having an upward spin or the electron 3 having a downward electron occupies almost all the atomic sites 1, and an excessive electron occupies the atomic sites 1 doubly. ing. The state of being occupied twice is said to have high energy. However, since there are excessive electrons, it is necessary to occupy double even if the energy is high. In the state of FIG. 1 (d) where the double occupation state is small, the system is still a Mott insulator.

However, in the state of FIG. 1 (e) where the number of electrons is further large, many atomic sites 1 are in a double occupied state and coexist with some of the single occupied states. In the state of FIG. 1E, even if the single occupancy state moves to the adjacent atomic site 1, the Coulomb interaction energy does not change. In other words, the single occupation state corresponds to doping a hole having a spin opposite to the double occupation state, and the hole can move around. As a result, the state of FIG. 1E becomes a metal state with low resistance because the number of holes (N _hole ) is large. Here, considering the state of FIG. 1 (f) where the number of electrons is further increased, this time, since all atomic sites 1 are occupied twice, the number of holes is small (N _site >> N _hole ). The system becomes a band insulator with high resistance.

  As described above, the metal-insulator transition that occurs in the states of FIGS. 1D, 1E, and 1F is the metal-insulator that occurs in the states of FIGS. 1A, 1B, and 1C. Symmetric with transition. This reflects the symmetry of electrons / holes inherently possessed by strongly correlated electron systems, and is generally established. Strictly speaking, the symmetry of electrons and holes does not hold, such as the effective masses of electrons and holes differ, reflecting the complexity of the band structure. The qualitative symmetry that it becomes or becomes an insulator is established.

  The nonvolatile RAM of the present invention uses the principle of metal-insulator transition described above. To that end, it is needless to say that a material that becomes a strongly correlated electron system is necessary. As described above, the strongly correlated electron system is a system having a strong Coulomb interaction between electrons, and a substance whose outermost orbital of electrons is composed of d electrons and f electrons, such as transition metal oxides. It is.

Here, attention is paid to the definition of strongly correlated electron systems. The strong interaction between electrons greatly affects the properties of the entire system, as shown in FIG. 1C, with the number of electrons (N _el ) being the same as the number of atomic sites 1 (N _site ). This is the case of (N _{site to} N _el ). When the number of electrons is small, the probability that the electrons collide with each other is small. Therefore, in the states of FIGS. 1A and 1B, the influence of the Coulomb interaction is not so large. Therefore, the classification that only the Mott insulator and the metal in the vicinity of the state of FIG.

However, the fact that the Coulomb interaction is strong when the atomic site 1 is doubly occupied is irrelevant to the number of electrons. Therefore, in the present invention, the number of electrons is small in FIGS. 1 (a) and 1 (b). This state is also called a strongly correlated electron system. For example, SrTiO ₃ , HfO ₂ , ZrO ₂ , Ta ₂ O ₅ , TiO _2, etc. belong to band insulators from the normal classification, but the outermost orbital that is important for conductivity is d-electron or f Even though the number of electrons is small, the Coulomb interaction acting between the electrons is strong, so that it is a strongly correlated electron system. It goes without saying that Mott insulators such as NiO and V ₂ O ₃ and metals doped with carriers belong to the strongly correlated electron system.

On the other hand, the material that is not a strongly correlated electron system is often a substance whose outer shell orbit is composed of s electrons and p electrons, and examples thereof include SiO ₂ and Al ₂ O ₃ . Even if the outermost electron orbit is composed of s-electrons and p-electrons, there are exceptionally strongly correlated electron materials. For example, organic materials such as BEDT-TTF (bis (ethylenedithio) tetrathiafulvalene) Mention may be made of molecular crystals.

  However, organic molecular crystals such as BEDT-TTF are not very suitable materials considering the consistency with the silicon process, which is the second problem of the present invention. In general, some material groups that are strongly correlated electron systems may be Mott insulators, some may be metals, and some may be band insulators depending on the number of electrons. One model that handles strongly correlated electron systems is called the Hubbard model, which has two important energy scales: kinetic energy (t) and interaction energy (U). Exists. The above-described strongly correlated electron system is a system having a larger interaction energy (U) than kinetic energy (t) regardless of the number of electrons. That is, a strongly correlated electron system is defined as a system with strong interaction between electrons, but this is a natural definition.

  The nonvolatile RAM of the present invention uses a thin film of a strongly correlated electron material as described above, and an electrode material having good electrical contact with the strongly correlated electron material is provided on one surface of the thin film. Join. Here, “electrically good contact” means that the contact resistance value that accompanies the contact is smaller than that of an unfavorable contact. Desirably, an ohmic contact that provides a linear IV characteristic between the strongly correlated electron system material and the electrode material is used, but it may not be strictly linear. In order to achieve good contact, the value from the vacuum level to the conduction band or valence band of the strongly correlated electron material may be combined with a material close to the work function value of the electrode material. It is also possible to adjust the Fermi level by doping a strongly correlated electron system material to facilitate ohmic connection with the electrode.

  Next, an electrode material having poor electrical contact with the strongly correlated electron material is bonded to the other surface of the thin film of the strongly correlated electron material. Here, the electrically unsatisfactory contact means that the contact resistance value is larger than that of a good contact on the other surface, or that the IV characteristic at the interface with the unsatisfactory electrode material is non-ohmic. It means to be in contact. In order to form such an interface, the materials must be combined so that the value from the vacuum level to the conduction band or valence band of the strongly correlated electron system material does not match the work function value of the electrode material. Just choose. In the nonvolatile RAM of the present invention, due to the poor contact formed in this way, the interface between the electrode material and the strongly correlated electron material plays an important role in the appearance of memory properties.

  Thus, the nonvolatile RAM of the present invention has an electrode having good electrical contact connected to one surface of a thin film made of a strongly correlated electron material, and an electrode having poor electrical contact to the other surface. An MIM (Metal-Insulator-Metal) structure is used to connect the two. Although described as MIM here, the thin film of the strongly correlated electron material may be a doped material as described above, and thus is not necessarily an insulator. Needless to say, when a band insulator or a Mott insulator is used as the strongly correlated electron material, it is an insulator.

  Next, the principle that memory performance appears in such a structure will be described. FIG. 2 shows a state before connecting a strongly correlated electron material and an electrode that makes poor contact with the material. FIG. 2A shows the relationship between energy and electron density at the interface between the prepared strongly correlated electron material and the electrode. FIG. 2A shows a state in which electrons are doped as carriers in the band insulator so that the electron density is around 0.5 as a strongly correlated electron material. For the sake of clarity, the description will be given in the case of doping with electrons, but it goes without saying that the same argument holds even when holes are doped. In this case, there is a stable state 4 in which the energy is at a minimum value near the electron density = 0.5.

FIG. 2B shows a band diagram before the strongly correlated electron material 5 is brought into contact with the electrode 6 that makes poor contact with the material 5. It is important that the Fermi level (E _F ) of the electrode 6 that makes an unfavorable contact is not adjacent to the valence band (E _V ) or the conduction band (E _C ) of the strongly correlated electron material 5.

  FIG. 3 shows the density of states in the vicinity of the interface before the strongly correlated electron material 5 and the electrode 6 that makes poor contact with the strongly correlated electron material 5 are brought into contact with each other. In order to realize poor contact, it is important that the Fermi levels of the two before contact do not match. If it is expressed more accurately, it is required that the work function values before contact do not match.

  Next, the state in which the electrode 6 that makes an unsatisfactory contact with the strongly correlated electron material 5 is in contact will be described with reference to FIG. FIG. 4A shows the relationship between energy and electron density when contacted. Since charging energy is generated with the contact as described later, there is a stable state 4 which is stable at a density slightly lower than the electron density = 0.5.

FIG. 4B shows that a Schottky barrier 7 is generated near the bonded interface. This reflects the fact that the work functions of the strongly correlated electron material 5 before contact and the electrode 6 that makes poor contact do not match. More generally, it is known that the height of the Schottky barrier 7 may simply deviate from the value expected from the work function because chemical reactions often occur at the contacted interface. Yes. For example, a chemical reaction occurs at the interface, and a phenomenon called Fermi Level Pinning in which the Fermi level (E _F ) near the interface changes effectively may occur.

However, there is no problem if the device is designed in consideration of the value of the Schottky barrier 7 finally observed in the experiment in consideration of the interface reaction. As a result of the contact as shown in FIG. 4 (b), some of the electrons present in the strongly correlated electron system material 5 are applied to the electrode 6 having a lower energy level and having a poor contact. Inflow. As a result, the interface on the strongly correlated electron-based material 5 side is positively charged, and the interface of the electrode 6 that makes an unfavorable contact is negatively charged. FIG. 5 shows the density of states near the interface in this state. Based on the principle of statistical mechanics, it is coincident with the Fermi level of the correlated electron material 5 (E _F) and the Fermi level of the electrode 6 (E _F). This is because electrons can be exchanged when they are in contact with each other, so that the chemical potentials of both in contact are equal.

  In the present invention, the Fermi level and the chemical potential are treated as the same meaning. Because the device of the present invention operates at room temperature, it is more scientifically accurate to use the term chemical potential than to use the term Fermi level, but the term Fermi level is often used following convention. I will decide. In addition, when a voltage is applied, the term “electrochemical potential” is sometimes used without using the term “Fermi level” or “chemical potential”, but these are not distinguished in the present invention.

In the state of FIG. 5 in which no voltage is applied, the Fermi levels (E _F ) of both coincide with each other, and the Schottky barrier 7 is formed at the interface. As a result, in the strongly correlated electron material 5 The band will be deformed gently. When a current is allowed to flow perpendicularly to this interface, electrons must pass through the Schottky barrier 7 by the quantum mechanical tunnel effect. In the state shown in FIG. 5, since the width of the Schottky barrier 7 is large, the tunnel effect hardly occurs. This reflects that the tunnel effect is less likely to occur depending on the exponential function of the tunneling distance. Therefore, in the state of FIG. 5, a high resistance state in which the contact resistance value at the interface is large is realized.

Here, the energy change near the interface accompanying the contact will be described with reference to FIG. In addition to the energy of the strongly correlated electron system, there is charging energy due to the charging effect near the interface. This is because, at the interface, the Fermi level of the electrode 6 that makes an unsatisfactory contact does not coincide with the conduction band of the strongly correlated electron system material 5, so that a voltage is effectively applied even if no potential difference is given from the outside. It is because it corresponds to that. According to classical electromagnetism, the capacitance C per unit volume is C = when the relative permittivity of the strongly correlated electron material is k, the relative permittivity of vacuum is e ₀ , and the thickness of the Schottky barrier is d. k * e0 / d. In addition, when the charge stored in the Schottky barrier is Q, the charging energy (E _charge ) is given by E _charge = Q ^ 2 / (2 * C). Therefore, in order to store more charge Q through the Schottky barrier, it is desirable that the relative permittivity (k) of the strongly correlated electron material is large and the thickness (d) of the Schottky barrier is thin.

  Considering the charging energy calculated in this way, the total energy in the vicinity of the interface is a double well type as shown in FIG. Among these, the state with the lowest energy is the stable state 4, and the state having the local minimum value is the metastable state 8. As described above, the stable state 4 is a high resistance state. On the other hand, as shown below, the metastable state 8 becomes a low resistance state. Here, in the example shown in FIG. 6, the state realized near the electron density = 1.2 is described as the metastable state 8, but this state is extremely stable when the nonvolatile RAM according to the present invention is used. It functions as a state. Certainly, in terms of energy, the energy is higher than in the stable state 4 which is the most stable state. However, once the electronic state in the vicinity of the interface is in this state, the system is protected by an enormous energy barrier of 0.5 to several eV per atomic site, and thus extremely stable memory retention characteristics can be obtained.

  Thus, since the metastable state 8 is a state having a local minimum value, the metastable state 8 is automatically maintained even when a perturbation as a disturbance factor is applied from the outside. Become. For example, even when some of the electrons held at the interface are lost, the system again binds nearby electrons to return to the metastable state 8 in order to maintain a thermodynamically stable state. Repair automatically. Thus, it can be seen that a system in which the stable state 4 and the metastable state 8 are realized can be used extremely stably when used as a nonvolatile memory.

  Next, the principle for operating a strongly correlated electron material as a memory element will be described. In order to operate as a memory element, it is necessary to switch from the stable state 4 to the metastable state 8 or vice versa. This switching method will be described.

  FIG. 7 shows a voltage of + 4V applied to the electrode 6 having an unfavorable contact in contact with the other interface with reference to an electrode (not shown) having an excellent contact in contact with one interface of the strongly correlated electron material 5. The state (a) and the band diagram (b) of the energy in the interface at the time of applying are shown. In this case, the strongly correlated electron system material 5 side is charged to have a negative charge through the Schottky barrier 7, and the electrode 6 side having an unfavorable contact is charged to have a positive charge. As a result, as shown in FIG. 7A, there is a point where the energy becomes the minimum value 4 in the vicinity of electron density = 1.7> 1.0. This corresponds to the state (e) among the states (a) to (f) in FIG. Once in this state, when the voltage is not applied, the system is stabilized in the metastable state 8 in the energy state of FIG.

  Next, a method of changing from the metastable state 8 to the stable state 4 in the energy state shown in FIG. 6 will be described. As shown in FIG. 8, this time, an unfavorable contact with the other interface is taken with reference to an electrode (not shown) that makes a good contact with one interface of the strongly correlated electron material 5. A voltage of −2 V having the opposite sign is applied to the electrode 6. FIG. 8A shows the state of energy at the interface, and FIG. 8B shows the band diagram.

  In this case, the strongly correlated electron system material 5 side is charged to have a negative charge through the Schottky barrier 7, and the electrode 6 side having an unfavorable contact is charged to have a positive charge. As a result, as shown in FIG. 8A, the energy becomes the minimum value 4 near the electron density = 0.4 <1.0. Once this state is reached, when the voltage is applied to 0 V, where no voltage is applied, the system is stabilized in the stable state 4 among the energy states shown in FIG. This corresponds to the state (b) among the states (a) to (f) in FIG. Reflecting that the stable state 4 has lower energy than the metastable state 8, to return from the metastable state 8 to the stable state 4, the absolute value of the voltage to be applied is set smaller. It becomes possible. In this way, it can be seen that the state of FIG. 1B and the state of FIG. 1E can be switched to each other by applying positive and negative voltages to the electrodes.

  Next, how to read out the state thus switched will be described. Therefore, a little more explanation about the metastable state 8 will be added. FIG. 9 shows (a) the energy of the interface and (b) the band diagram when the interface state is metastable state 8, and FIG. 10 shows the density of states near the interface at this time.

  In FIG. 9B, it can be seen that the band of the valence band in the strongly correlated electron material 5 is bent greatly through the Schottky barrier 7. This reflects the splitting of the valence band into a state called the lower Hubbard band and a state called the upper Hubbard band due to the strong Coulomb interaction unique to the strongly correlated electron system, as shown in FIG. . As a result, in the state shown in FIG. 9B, the width of the Schottky barrier 7 is narrow, and the tunnel current flowing through the Schottky barrier 7 is much easier to flow. Therefore, in the metastable state 8, the value of the interface resistance generated at the interface is small. In order to realize such a state, a large amount of charges must be electrostatically stored through the Schottky barrier 7. Therefore, it is desirable that the relative permittivity of the strongly correlated electron material 5 is large (preferably 20 or more).

  However, the difference from a normal high-k material is that charges are taken in and out in the strongly correlated electron material 5, so that one interface of the strongly correlated electron material 5 has good electrical contact with the electrode. There is a need to. Therefore, it is necessary to reduce the band offset with respect to at least one of the electrodes. This is exactly the opposite of the usual high-k material search guidelines. In a normal high-k film application, it is necessary to reduce the leakage current. Therefore, the materials are combined so that the band offset is as large as possible. Thus, it can be seen that in the present invention, it is necessary to fabricate a device using a guideline that is completely opposite to the way the conventional MIM structure is used.

  As can be seen from the above description, in order to read out whether the stable state 4 is realized or whether the metastable state 8 is realized, it is only necessary to read the difference in the interface resistance value. That is, when the stable state 4 is realized, the interface resistance value is large because the width of the Schottky barrier 7 is wide. Therefore, the current that flows when a voltage is applied to the interface is small. On the other hand, when the metastable state 8 is realized, since the width of the Schottky barrier 7 is narrow, the interface resistance value is small. Therefore, the current that flows when a voltage is applied to the interface is small.

  Here, it has been described that the interface resistance value can be distinguished by the magnitude of the interface resistance value. However, as noted above, when the flowing current is non-linear, it is difficult to simply define the resistance value. However, even in that case, the magnitude of the current value when the voltage is applied can be distinguished. Therefore, hereinafter, the fact that the current that flows when the same voltage is applied, including the case where the current-voltage characteristics are nonlinear, will simply be described as having a large (or small) interface resistance value. . Needless to say, the voltage applied at the time of reading the memory state is smaller than the voltage applied at the time of rewriting. When a small voltage is applied, neither the stable state 4 nor the metastable state 8 changes, so that it is possible to read without disturbing the memory state. Thus, the strongly correlated electronic memory of the present invention has a clear device operation principle.

  Next, a variable resistance memory that can be easily formed using an existing silicon process and a manufacturing method thereof, which are the second object of the present invention, will be described.

Based on the operation principle of the device described above, it is possible to manufacture a variable resistance memory using a material already used in an existing silicon process or a material that can be easily introduced. As the strongly correlated electron material, a material containing d electrons or f electrons and easy to use in the silicon process may be used. For example, transition metal oxides or oxynitrides such as Ta ₂ O ₅ , Nb ₂ O ₅ , TiO ₂ , Ti ₂ O ₃ , HfO ₂ , ZrO ₂ , V ₂ O ₃ , VO ₂ , WO ₃ , oxygen and Materials such as TaO _x , NbO _x , TiO _x , NiO _x , CoO _x , MnO _x , CrO _x , and CuO _x whose mixing ratio with the transition metal is not an integer (x can take a non-integer value with a formal valence), Alternatively, a material obtained by doping them may be used.

Doping is equivalent to adjusting the Fermi level of the strongly correlated electron system material and has a role of adjusting electrical contact with the electrode. For example, the fact that Cr or Ti having a valence different from V can be added to V ₂ O ₃ is well known in the bulk state, but in the strongly correlated electronic memory of the present invention, it is also applied in the thin film state. be able to. In addition, it is known as a capacitor application technique that the value of the lattice constant is changed and the relative dielectric constant is increased by adding Nb to Ta ₂ O ₅ . It can also be applied to correlated electronic memories.

Also, carrier doping is possible by replacing W and Ta having different valences with respect to Ta ₂ O ₅ . TiO ₂ can be changed from TiO ₂ which is a band insulator to Ti ₂ O ₃ which is a Mott insulator by changing the valence of oxygen. This corresponds to changing the formal valence of oxygen from 1.5 to 2.0 if Ti ₂ O ₃ is formally expressed as TiO _1.5 . The Fermi level can be adjusted by adjusting to an intermediate value from 1.5 to 2.0. Such adjustment can be easily adjusted by annealing in an oxygen atmosphere after film formation using a silicon process. In addition, doping can be further controlled by adding V or the like to TiO _x .

  In the strongly correlated electronic memory according to the present invention, only the interface with the electrode has a memory property, and therefore does not depend on the crystal state of the strongly correlated electron material 5. Therefore, since it is not necessary to grow a single crystal using an epitaxial growth technique, it is not necessary to select an underlying substrate. Therefore, it can also be manufactured by a wiring process in a silicon process. In fact, it is confirmed that when a thin film of strongly correlated electron system material 5 is formed by CVD (Chemical Vapor Deposition) method or sputtering method, it is often in an amorphous state or a polycrystalline state in which a part of the material is crystallized. Has been. in this way. When the strongly correlated electron material 5 is used in the thin film state, even if the composition or structure is unstable in the bulk single crystal state, it may be realized in the thin film state, and the device characteristics of the strongly correlated electron memory can be improved.

  Using these electrode materials that can be produced by an existing silicon process, an electrode material that makes good electrical contact and an electrode material that makes poor electrical contact are brought into contact with these strongly correlated electron materials. . For that purpose, a material having a large work function and a material having a small work function may be combined. Examples of the electrode material that makes good contact include Ti, polycrystalline silicon doped with n-type impurities at a high concentration, TiN, and Al. Examples of the electrode material that makes poor contact include W, NiSi, CoSi, and polycrystalline silicon doped with a high concentration of p-type impurities.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  If the strongly correlated electronic memory based on one invention of this application is used, since the operation principle of the device is clear, a variable resistance nonvolatile RAM capable of easily designing an optimum material can be provided.

  In addition, the strongly correlated electronic memory according to one invention of the present application utilizes the bistability of energy because of its fundamental configuration, and thus extremely stable and highly reliable device characteristics can be obtained. As a result, even if silicon devices are scaled in the future, reliability that satisfies the demands of the industry can be expected.

  In addition, the strongly correlated electronic memory according to the invention of the present application can be manufactured using an apparatus used in an existing silicon process, and a new problem such as metal contamination does not occur. That is, mass production is possible using existing equipment, and no new capital investment is required.

(A)-(f) is the figure which showed typically the crystal structure of a strongly correlated electron type substance. (A) is a figure which shows the relationship between the energy of a strongly correlated electron system material, and an electron density, (b) is the band before making a strongly correlated electron system material and the electrode which has an unfavorable contact with this contact. -It is a figure which shows a diagram. It is a figure which shows the density of states in the interface vicinity before contacting a strongly correlated electron type material and the electrode which takes an unfavorable contact with this. (A) is a figure which shows the relationship between the energy and electron density in the interface of a strongly correlated electron system material and the electrode which takes an unfavorable contact with this, (b) is a strongly correlated electron system material and this It is a figure which shows the band diagram in the state which contacted the electrode which takes an unfavorable contact. It is a figure which shows the density of states in the interface vicinity in the state which made the strongly correlated electron type material and the electrode which takes an unfavorable contact with this contact. It is a figure explaining the energy change in the interface vicinity in the state which made the strongly correlated electron type material and the electrode which takes a poor contact with this contact. It is a figure explaining the method of switching a strongly correlated electron system from a stable state to a metastable state, Comprising: (a) is already on the basis of the electrode which contacts the one interface of a strongly correlated electron system material, and has a favorable contact. The figure which shows the relationship between the energy and the electron density in the interface at the time of applying a voltage to the electrode which contacts the one interface which takes an unfavorable contact, (b) is contacting one interface of the strongly correlated electron system material It is a figure which shows a band diagram at the time of applying a voltage to the electrode which contacts the other interface and makes the poor contact on the basis of the electrode which makes a favorable contact. It is a figure explaining the method of switching a strongly correlated electron system from a metastable state to a stable state, Comprising: (a) is already on the basis of the electrode which contacts the one interface of a strongly correlated electron system material, and has a favorable contact. The figure which shows the relationship between the energy and the electron density in the interface at the time of applying a voltage to the electrode which contacts the one interface which takes an unfavorable contact, (b) is contacting one interface of the strongly correlated electron system material It is a figure which shows a band diagram at the time of applying a voltage to the electrode which contacts the other interface and makes the poor contact on the basis of the electrode which makes a favorable contact. (A) is a figure which shows the relationship between the energy and electron density in an interface when the state of the interface of a strongly correlated electron system material and the electrode which takes an unfavorable contact with this becomes a metastable state, b) is a diagram showing a band diagram when the interface state between the strongly correlated electron-based material and the electrode that makes poor contact with the material is metastable. It is a figure which shows the density of states in the interface vicinity when the state of the interface of a strongly correlated electron type material and the electrode which takes an unfavorable contact with this becomes a metastable state. It is sectional drawing which shows the manufacturing method of the strongly correlated electronic memory which is Embodiment 1 of this invention. It is sectional drawing which shows the manufacturing method of the strongly correlated electronic memory following FIG. It is sectional drawing which shows the manufacturing method of the strongly correlated electronic memory following FIG. It is sectional drawing which shows the manufacturing method of the strongly correlated electronic memory following FIG. It is sectional drawing which shows the manufacturing method of the strongly correlated electronic memory following FIG. FIG. 16 is a cross-sectional view showing a method for manufacturing the strongly correlated electronic memory following FIG. 15. FIG. 17 is a cross-sectional view showing a method for manufacturing the strongly correlated electronic memory following FIG. 16. It is sectional drawing which shows the manufacturing method of the strongly correlated electronic memory which is Embodiment 2 of this invention. FIG. 19 is a cross-sectional view showing a method for manufacturing the strongly correlated electronic memory following FIG. 18. FIG. 20 is a cross-sectional view showing a method for manufacturing the strongly correlated electronic memory following FIG. 19. It is sectional drawing which shows the manufacturing method of the strongly correlated electronic memory which is Embodiment 3 of this invention. FIG. 22 is a cross-sectional view showing a method for manufacturing the strongly correlated electronic memory following FIG. 21. FIG. 23 is a cross-sectional view showing a method for manufacturing the strongly correlated electronic memory following FIG. 22. It is sectional drawing which shows the manufacturing method of the strongly correlated electronic memory which is Embodiment 4 of this invention. FIG. 25 is a cross-sectional view showing a method for manufacturing the strongly correlated electronic memory following FIG. 24. FIG. 26 is a cross-sectional view showing a method for manufacturing the strongly correlated electronic memory following FIG. 25. It is a circuit diagram of the memory array which integrated the strongly correlated electronic memory of this invention. It is a wave form diagram which shows the rewriting method of the strongly correlated electronic memory of this invention. It is a wave form diagram which shows the reading method of the strongly correlated electronic memory of this invention.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

(Embodiment 1)
The manufacturing method of the strongly correlated electronic memory according to the present embodiment will be described in the order of steps with reference to FIGS. First, as shown in FIG. 11, a p-type semiconductor substrate (hereinafter referred to as a substrate) 9 made of single crystal silicon having a plane orientation (100) is prepared. As the substrate 9, a semiconductor substrate other than the single crystal silicon substrate, for example, an SOI substrate (Silicon On Insulator), a single crystal Ge substrate, a GOI substrate (Ge On Insulator), a strained silicon substrate in which strain stress is applied to the crystal, or the like is used. There is no problem.

  Next, after opening the substrate 9 by dry etching using the silicon nitride film as a mask, a silicon oxide film is embedded in the opening. Subsequently, the surface of the substrate 9 is planarized by a chemical mechanical polishing (CMP) method, and an STI (Shallow Trench Isolation) portion 24 is formed, thereby defining an active region in which a transistor is formed.

  Next, ion implantation for substrate concentration adjustment and stretching heat treatment, and ion implantation for threshold voltage adjustment and activation heat treatment are performed. Subsequently, after cleaning the surface of the substrate 9 with a dilute hydrofluoric acid aqueous solution, a thermal oxidation process is performed to form a gate insulating film 10 made of a silicon oxide film having a thickness of about 3 nm. As the gate insulating film 10, an insulating film other than a silicon oxide film, for example, a silicon oxynitride film (SiON film) obtained by nitriding the surface, a high-k film obtained by oxidizing or nitriding various metals, or a laminated film thereof You can use it.

  Next, a polycrystalline silicon film 11a is deposited on the gate insulating film 10 by the CVD method. The polycrystalline silicon film 11a serves as a gate electrode material and has a thickness of about 70 nm. As the gate electrode material, a silicide film or a metal film may be used in addition to the polycrystalline silicon film 11a.

Next, after depositing a silicon oxide film (not shown) having a thickness of about 10 nm on the polycrystalline silicon film 11a by the CVD method, phosphorus or arsenic is used to change the conductivity type of the polycrystalline silicon film 11a to n-type. Ion implantation. Subsequently, the impurity concentration of the polycrystalline silicon film 11a is set to about 2 × 10 ²⁰ cm ⁻³ by performing heat treatment for extending and activating impurity ions in a nitrogen atmosphere at 950 ° C. for about 30 seconds. Next, the silicon oxide film is removed using a hydrofluoric acid aqueous solution.

Next, as shown in FIG. 12, the polycrystalline silicon film 11a is patterned by dry etching using a photoresist film as a mask to form the gate electrode 11. Next, phosphorus or arsenic is ion-implanted into the substrate 9 to form a shallow n ⁻ -type diffusion layer 12, and then boron is ion-implanted into the substrate 1 so as to surround the shallow n ⁻ -type diffusion layer 12. A p-type diffusion layer 13 for preventing through is formed.

Next, as shown in FIG. 13, sidewall spacers 14 are formed on the sidewalls of the gate electrode 11 by anisotropically etching the silicon oxide film deposited on the substrate 9. The silicon oxide film is deposited by a plasma-assisted deposition method (film formation temperature = 400 ° C.), and the film thickness is 50 nm. Next, after ion-implanting arsenic into the substrate 9, an activation heat treatment at 1000 ° C. is performed to form a high concentration n ⁺ diffusion layer 15 for the source and drain.

Next, as shown in FIG. 14, a Ni film is deposited on the substrate 9 by a sputtering method, and subsequently silicon (gate electrode 11 and substrate 9) and the Ni film are reacted by heat treatment, and then unreacted Ni The Ni silicide layer 16 is formed on the surface of the gate electrode 11 and the surface of the n ⁺ diffusion layer 15 by removing the film by wet etching. Co or the like can also be used as the metal material of the silicide layer. The n-channel type memory cell selection MISFET is completed through the steps so far.

  In the present embodiment, the memory cell selection MISFET is an n-channel MISFET. However, in the above-described process, the p-channel MISFET may be formed by changing the impurity conductivity type to the p-type. it can. As described above, a CMOS (Complementary Metal-Oxide-Semiconductor) circuit can be formed by forming an n-channel type MISFET and a p-channel type MISFET on the same substrate, so that a complicated circuit operation is performed with lower power consumption. be able to.

  In this embodiment, the gate electrode 11 of the memory cell selecting MISFET is formed of a laminated film of the polycrystalline silicon film 11a and the Ni silicide layer 16, but WN (as a barrier metal film on the polycrystalline silicon film 11a). It is also possible to form a gate electrode having a polymetal structure in which a tungsten nitride) film is laminated and a W (tungsten) film is further laminated thereon. Further, the gate electrode can be formed by a dummy gate process using a low melting point metal material. In the dummy gate process, the dummy gate electrode is first formed by processing the dummy gate electrode material (polycrystalline silicon film, etc.) deposited on the gate insulating film, and then the source diffusion layer and the drain diffusion layer are formed. Then, the gate insulating film and the dummy gate electrode are removed. Next, a gate insulating film is formed again. Subsequently, a low melting point metal film for a gate is deposited thereon, and then the low melting point metal film is processed to form a gate electrode. When this dummy gate process is used, the gate insulating film can be formed using a high-k material having a low crystallization temperature. As described above, there are a wide variety of methods for forming the memory cell selection MISFET. However, in order to drive the strongly correlated electronic memory of the present invention, any transistor manufactured using any method can be used. The description of the details of the dummy gate process is omitted.

Next, as shown in FIG. 15, a thick silicon oxide film 17 is deposited on the substrate 9 by the CVD method, and then the surface is planarized by the chemical mechanical polishing method, and then the gate electrode 11 and the n ⁺ diffusion layer are formed. A contact hole 18 is formed in the silicon oxide film 17 on each of 15 (source and drain), and a plug 19 is formed inside the contact hole 18. The plug 19 is composed of, for example, a laminated film of a TiN film and a W film. In the present embodiment, the W film constituting the main part of the plug 19 functions as the electrode 6 that makes an unfavorable contact with the strongly correlated electron material 5 described above.

Next, as shown in FIG. 16, a tantalum pentoxide (Ta ₂ O ₅ ) film 20 having a film thickness of about 2 nm is deposited on the silicon oxide film 17 as a strongly correlated electron material. The tantalum pentoxide film 20 is deposited by a thermal CVD method using, for example, a gas containing pentaethoxytantalum (Ta (C ₂ H ₅ O) ₅ ) as a source gas and forming a film in a reduced pressure state (eg, 400 mTorr) at 550 ° C. or lower. To do. Alternatively, it can be deposited by an atomic layer CVD method in which pentaethoxytantalum and an oxidizing agent (for example, H ₂ O) are alternately supplied. The tantalum pentoxide film 20 may be doped with a transition metal material having a different valence such as W. When W is doped, electrons are doped as carriers and the Fermi level of tantalum pentoxide is increased, so that it is possible to reduce the contact resistance value with an electrode that is in good electrical contact. The film thickness of the tantalum pentoxide film 20 is relatively thin, about 2 nm, because the characteristics of the strongly correlated electron memory are determined by the interface between the strongly correlated electron material and the electrode as described above. is there.

  Next, a polycrystalline silicon film 21a having a thickness of about 50 nm is deposited on the tantalum pentoxide film 20 by a CVD method. The polycrystalline silicon film 21a is doped with phosphorus during film formation to make its conductivity type n-type. The polycrystalline silicon film 21 a is an electrode material that makes good electrical contact with the tantalum pentoxide film 20. As this type of electrode material, a material having a small work function such as Ti can be used. However, it is desirable to use polycrystalline silicon from the viewpoint of consistency with the silicon process. In particular, since the valence band of tantalum pentoxide is near the valence band of silicon, relatively good electrical contact can be obtained when tantalum pentoxide is brought into contact with n-type polycrystalline silicon. Such a combination of materials is insane because a leakage current increases in producing a MIM capacitor, but is a desirable combination in order to realize the strongly correlated electronic memory of the present invention.

Next, as shown in FIG. 17, the polycrystalline silicon film 21a and the tantalum pentoxide film 20 are patterned by dry etching using a photoresist film as a mask to be connected to the n ⁺ diffusion layer 15 (drain). On the top of the plug 19, an electrode 21 is formed which makes good electrical contact with the tantalum pentoxide film 20.

  Since the characteristics of the strongly correlated electron memory are determined by the interface between the strongly correlated electron material and the electrode, the tantalum pentoxide film 20 is not necessarily patterned, but the tantalum pentoxide film 20 has a thin film thickness of about 2 nm. When the polycrystalline silicon film 21a is patterned, the tantalum pentoxide film 20 is usually patterned at the same time. Further, when the electrode 21 is formed by patterning the polycrystalline silicon film 21a, the width of the electrode 21 is made larger than the diameter of the plug 19 in order to avoid misalignment with the plug 19 due to microfabrication.

  Although illustration is omitted, after that, an interlayer insulating film made of a silicon oxide film is deposited on the upper portion of the electrode 21 by a CVD method, and then the interlayer insulating film on the upper portion of the electrode 21 is etched to form a through hole. By forming a metal wiring on the insulating film and electrically connecting the metal wiring and the electrode 21 through the through hole, the strongly correlated electronic memory of the present embodiment is completed.

  An external feature of the strongly correlated electronic memory of the present embodiment is that the diameter of the plug 19 is smaller than the width of the electrode 21. Therefore, although the area of the portion responsible for the characteristics of the strongly correlated electronic memory is reduced, the contact resistance value is different by one digit or more between the low resistance state and the high resistance state, so there is no problem at all. As described above, the strongly correlated electronic memory according to the present embodiment maintains non-volatility even if the area responsible for the characteristic is small, so that it is not necessary to form a deep trench unlike a DRAM capacitor. Therefore, even if device scaling is advanced, processing defects due to an increase in aspect ratio do not occur. Another feature of the strongly correlated electronic memory of the present embodiment is that no precious metal material having a high thermal diffusion is used.

Next, the operation of the strongly correlated electronic memory based on this embodiment will be described. In order to simplify the description, it is assumed that the potential of the n ⁺ diffusion layer 15 (source) is 0V. First, in order to bring the interface between the tantalum pentoxide film 20 and the W film (plug 19) into a low resistance state, a potential of −4 V is applied to the electrode 21 having good contact, and then a memory cell selecting MISFET. The potential of the gate electrode 11 is set to +1 V, and the transistor is turned on. Then, as shown in FIG. 7B, the band is deformed, and more electrons are stored in the interface. The voltage application time may be as short as about 10 ns. When all the potentials are returned to 0 V, the system state becomes the metastable state 8 shown in FIG. 9A, and the contact resistance generated at the interface decreases. The state of the system is metastable state 8, which is higher in energy than stable state 4. However, once this state was reached, it was confirmed that this metastable state 8 was maintained at least for a sufficiently long period of time. Therefore, the strongly correlated electronic memory according to the present embodiment is non-volatile.

  Next, in order to bring the interface between the tantalum pentoxide film 20 and the W film (plug 19) into a high resistance state, a potential of +2 V is applied to the electrode 21 having good contact, and then the memory cell selection The potential of the gate electrode 11 of the MISFET is set to +1 V, and the transistor is turned on. Then, as shown in FIG. 8B, the band is deformed, and electrons stored at the interface flow. The voltage application time may be as short as about 10 ns. When all the potentials are returned to 0 V, the system state becomes the stable state 4 shown in FIG. 4A, and the contact resistance generated at the interface increases.

At the time of reading, it is only necessary to apply a smaller voltage than to rewrite the memory and observe the magnitude of the flowing current. Accordingly, when the potential of the n ⁺ diffusion layer 15 (source) is set to 0 V, as in the case of rewriting, a potential of +1 V is applied to the electrode 20 having good contact, and then the memory cell selection MISFET. The potential of the gate electrode 11 may be +1 V and the magnitude of the flowing current may be observed. In the strongly correlated electronic memory based on the present embodiment, the current ratio due to the magnitude of the interface resistance is about 1000. This indicates that the high resistance state and the low resistance state can be sufficiently distinguished.

(Embodiment 2)
The manufacturing method of the strongly correlated electronic memory according to the present embodiment will be described in the order of steps with reference to FIGS. In the present embodiment, first, as shown in FIG. 18, a memory cell selection MISFET is formed on the main surface of the substrate 9, and then the thick silicon oxide film 17 deposited on the substrate 9 is formed by a chemical mechanical polishing method. After planarization, a contact hole 18 is formed in the silicon oxide film 17 on each of the gate electrode 11 and the n ⁺ diffusion layer 15 (source, drain), and a plug 19 is formed inside the contact hole 18. The steps so far are the same as the steps shown in FIGS. 11 to 15 of the first embodiment. The plug 19 is composed of a laminated film of a TiN film and a W film. As in the first embodiment, the W film constituting the main part of the plug 19 functions as the electrode 6 that makes an unfavorable contact with the strongly correlated electron material 5.

Next, as shown in FIG. 19, the surface portion of the plug 19 (TiN film and W film) is heat-treated in an oxygen atmosphere. Thereby, on the surface portion of the plug 19, the central portion (region where the W film is formed) is made of the WO _x layer, and the side wall portion (region where the TiN film is formed) is made of the TiO _y N _z layer. A strongly correlated electron material film 22 is formed. Here, the WO _x layer is adjusted so that its formal valence x is 2.9. The film thickness of the WO _x layer is about 3.0 nm. Since the TiO _y N _z layer formed on the side wall portion has a volume that is about an order of magnitude smaller than the WO _x layer, the memory characteristics are not greatly affected.

Next, as shown in FIG. 20, after a Ti film is deposited on top of the silicon oxide film 17 by sputtering, the Ti film is patterned by dry etching using a photoresist film as a mask to achieve good contact. An electrode 23 is formed. The strongly correlated electron material film 22 formed in a region where the electrode 23 is not formed, that is, a region other than the upper portion of the n ⁺ diffusion layer 15 (drain) is patterned with a Ti film in order to reduce the resistance of the plug 26. Remove when doing. In this way, a step is formed between the surface of the plug 26 from which the strongly correlated electron material film 22 has been removed and the surface of the silicon oxide film 17, but this step is extremely small, about 3.0 nm. There is no problem.

  Although illustration is omitted, after that, an interlayer insulating film made of a silicon oxide film is deposited on the electrode 21 by a CVD method, and then the interlayer insulating film on the upper portion of the electrode 23 is etched to form a through hole. A metal wiring is formed on the insulating film, and the metal wiring and the electrode 23 are electrically connected through the through hole, whereby the strongly correlated electronic memory of the present embodiment is completed.

  As described above, in the manufacturing method of the strongly correlated electronic memory according to the present embodiment, the strongly correlated electron material is formed by thermally oxidizing W used as the wiring material of the existing silicon process. Therefore, a high-performance nonvolatile RAM can be manufactured without investing in new equipment.

(Embodiment 3)
The manufacturing method of the strongly correlated electronic memory according to the present embodiment will be described in the order of steps with reference to FIGS. First, in accordance with the steps shown in FIGS. 11 to 15 of the first embodiment, a contact hole 18 is formed in the silicon oxide film 17 deposited on the memory cell selection MISFET, and then a plug is formed inside the contact hole 18. 19 is formed. Next, as shown in FIG. 21, a Ti film having a thickness of about 50 nm is deposited on the silicon oxide film 17 by sputtering to form an electrode 23 that makes good contact with the strongly correlated electron material. To do.

Next, as shown in FIG. 22, the substrate 1 is heat-treated in an oxygen atmosphere, and the surface portion of the Ti film constituting the electrode 23 is oxidized, whereby a strongly correlated electron material made of TiO _x is formed on the surface of the electrode 23. A film 22 is formed. Here, the formal valence _x of the TiO _x layer is adjusted to be 1.57. Thus, by precisely controlling the oxygen concentration of the strongly correlated electron material film 22, the number of electrons existing at the Ti atom site is slightly less than x = 1.50 realized by the Mott insulator. Realize. The above-described method for forming the strongly correlated electron system material film 22 on the surface of the transition metal film by oxidation treatment includes, for example, Ta, Nb, Hf, Zr, V, W, Ni, Co, Mn, Cr in addition to Ti. It can also be realized by using Cu or the like.

  Next, as shown in FIG. 23, after depositing a W film having a film thickness of about 50 nm on the substrate 9 by sputtering, the W film is patterned by dry etching using a photoresist film as a mask. An electrode 25 is formed for contact. At this time, in order to prevent the elements 23 from being short-circuited by the electrode 23 made of the Ti film, it is necessary to pattern the electrode 23 having good contact together with the strongly correlated electron material film 22.

  Although not shown, after that, an interlayer insulating film made of a silicon oxide film is deposited on the upper portion of the electrode 25 by a CVD method, and then the interlayer insulating film on the upper portion of the electrode 25 is etched to form a through hole. A metal wiring is formed on the insulating film, and the metal wiring and the electrode 25 are electrically connected through the through hole, whereby the strongly correlated electronic memory of the present embodiment is completed.

  Next, in the same manner as in the first embodiment, an interlayer insulating film is deposited on the upper part of the electrode, a through hole is subsequently formed in the interlayer insulating film, and then a metal wiring is formed on the upper part of the interlayer insulating film. A strongly correlated electronic memory is completed by electrically connecting the metal wiring and the electrode through the hole.

  In the strongly correlated memory according to the present embodiment, since the carrier concentration is precisely controlled by the oxygen density, the erase voltage can be increased and decreased both at ± 2.0V. In addition, in the manufacturing method according to the present embodiment, when compared with the first and second embodiments, the electrode 25 that makes poor contact and the electrode 23 that makes good contact are upside down. It is necessary to pay attention to the sign of the power voltage. In this way, the device characteristics can be optimized by adjusting the Fermi level of the strongly correlated electron material film 22.

(Embodiment 4)
The manufacturing method of the strongly correlated electronic memory according to the present embodiment will be described in the order of steps with reference to FIGS. First, according to the steps shown in FIGS. 11 to 15 of the first embodiment, a contact hole 18 is formed in the silicon oxide film 17 deposited on the memory cell selecting MISFET, and then, as shown in FIG. A plug 26 is formed inside the hole 18.

  In the first embodiment, the plug 19 is composed of the laminated film of the TiN film and the W film. However, in the present embodiment, the plug 26 is composed of the TiN film. In this case, contrary to the first embodiment, the TiN film constituting the plug 26 functions as the electrode 6 that makes good contact with the strongly correlated electron material 5 described above.

Next, as shown in FIG. 25, the surface portion of the plug 26 (TiN film) is heat-treated in an oxygen atmosphere. Thereby, a strongly correlated electron material film 22 composed of a TiO _y N _z layer having a thickness of about 3.0 nm is formed on the surface portion of the plug 26. Next, as shown in FIG. 26, after depositing a W film having a thickness of about 50 nm on the substrate 9 by sputtering, the W film is patterned by dry etching using a photoresist film as a mask. An electrode 25 is formed for contact. The strongly correlated electron material film 22 formed in a region where the electrode 25 is not formed, that is, a region other than the upper portion of the n ⁺ diffusion layer 15 (drain) is patterned to reduce the resistance of the plug 26. Remove when doing. As a result, a step is generated between the surface of the plug 26 from which the strongly correlated electron material film 22 has been removed and the surface of the silicon oxide film 17, and this step is 3.0 nm as in the second embodiment. Since it is extremely small, there is no electrical problem.

  Subsequent steps are the same as those in the first to third embodiments. According to the manufacturing method of the present embodiment, the manufacturing process of the strongly correlated electronic memory can be simplified as compared with the first to third embodiments.

(Embodiment 5)
FIG. 27 is a circuit diagram of a memory array in which a number of strongly correlated electronic memories manufactured by the method of the third embodiment are integrated on a substrate 1, for example. The strongly correlated electronic memory is disposed at the intersection of a plurality of word lines WL extending in the X direction and a plurality of bit lines BL extending in the Y direction. Each word electrode WL is connected to each gate electrode 11 of a plurality of strongly correlated electronic memories arranged in the X direction.

The n ⁺ diffusion layer 15 (drain) of the strongly correlated electron memory and the substrate 1 are grounded. As shown in FIG. 23, the n ⁺ diffusion layer 15 (drain) is connected to the electrode 23 having good contact via the plug 19, and the strongly correlated electron material film formed on the electrode 23 and the upper portion thereof. The interface with 22 functions as a variable resistor. Further, the electrode 25 formed on the strongly correlated electron material film 22 and having an unfavorable contact is connected to the bit line BL.

  Next, the operation of the memory cell will be described using the circuit shown in FIG. First, at the time of writing, in order to bring the interface between the strongly correlated electron material film 22 and the electrode 25 into a low resistance state, a potential of +2 V is applied to the bit line BL connected to the memory cell to be brought into the low resistance state. After that, the potential of the word line WL connected to the memory cell is set to +1 V, and the memory cell selecting MISFET is turned on. Then, as shown in FIG. 7, the band is deformed, and more electrons are stored at the interface between the strongly correlated electron material film 22 and the electrode 25. The voltage application time may be as short as about 10 ns. When the potentials of the word line WL and the bit line BL are returned to 0 V, the system state becomes the metastable state 8 shown in FIG. 9 and the interface resistance is lowered.

  On the other hand, in order to set the interface between the strongly correlated electron material film 22 and the electrode 25 in a high resistance state, a potential of −2 V is applied to the bit line BL of the memory cell to be set in the high resistance state, and then the low resistance state is set. The potential of the word line WL of the desired memory cell is set to +1 V, and the memory cell selecting MISFET is turned on. Then, as shown in FIG. 8, the band is deformed, and electrons stored at the interface flow. Similarly, the voltage application time may be as short as about 10 ns. When the potentials of the word line WL and the bit line BL are returned to 0 V, the system state becomes the stable state 4 shown in FIG. 4, and the contact resistance generated at the interface increases. Thus, the memory array can selectively rewrite memory cells.

  Next, a memory cell read operation will be described. At the time of reading, it is only necessary to observe the magnitude of the flowing current by applying a smaller voltage than rewriting the memory cell. That is, after a potential of +1 V is applied to the bit line BL of the memory cell to be read, the potential of the word line WL of the memory cell to be brought into the low resistance state is set to +1 V, and the memory cell selection MISFET is turned on. At this time, when the interface is in a low resistance state, a large current flows through the bit line BL, but when the interface is in a high resistance state, only a small current flows through the bit line BL. When the voltage applied to the bit line BL is as small as about 1V, the stored memory information is not rewritten. In this way, information stored in the memory array can be selectively extracted.

  Waveforms when the above rewrite and read operations are performed will be described with reference to FIGS. A non-selected word line WL and bit line BL are both applied with a potential of 0 V so that no current flows from memory cells other than the selected memory cell. As shown in FIG. 28, in order to bring the memory cell into a low resistance state, a voltage of 2V is applied to the bit line BL, and a voltage of 1V is applied to the word line WL. As a result, the resistance changes to a low resistance state. Next, when rewriting the memory cell to a high resistance state, a voltage of −2 V is applied to the bit line BL connected to the selected memory cell, and a potential of 1 V is applied to the word line WL. As a result, the resistance changes to a high resistance state.

  In the case of reading, as shown in FIG. 29, a potential of 1 V is simultaneously applied to the word line WL and the bit line BL connected to the selected memory cell. Thus, the resistance state is distinguished by the magnitude of the flowing current. In addition to the selected memory cell, there is a memory cell to which the voltage of the word line WL or the bit line BL is applied. In such a memory cell, either the word line WL or the bit line BL is set to a voltage of 0V. Therefore, the memory cell selecting MISFET does not operate in the ON state and is not disturbed by memory cells other than the selected memory cell.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention can be applied to a variable resistance nonvolatile RAM using a strongly correlated electronic memory.

Claims (15)

A non-volatile memory element composed of a variable resistance portion and a memory cell selection MISFET connected in series to the variable resistance portion,
The variable resistance portion includes a thin film made of a strongly correlated electron material whose outermost electron trajectory is composed of d electrons or f electrons, a first electrode in ohmic contact with one surface of the thin film, A second electrode in non-ohmic contact with the other surface,
A non-volatile memory device, wherein information is stored according to a magnitude of an electric resistance value at an interface between the thin electrode made of the strongly correlated electron material and the second electrode.   The strongly correlated electron material includes any one or two or more elements selected from the group consisting of Ta, Nb, Ti, Hf, Zr, V, W, Ni, Co, Mn, Cr and Cu. The nonvolatile memory element according to claim 1, wherein the nonvolatile memory element is a transition metal oxide or a transition metal oxynitride.   3. The nonvolatile memory device according to claim 2, wherein the transition metal oxide has a non-integer mixing ratio of oxygen and transition metal.   The nonvolatile memory element according to claim 1, wherein a relative dielectric constant of the strongly correlated electron material is 20 or more.   2. The non-volatile memory device according to claim 1, wherein the first electrode in ohmic contact with one surface of the thin film is made of polycrystalline silicon doped with Ti, TiN, Al, or n-type impurities.   2. The non-volatile memory device according to claim 1, wherein the second electrode in non-ohmic contact with the other surface of the thin film is made of polycrystalline silicon doped with W, NiSi, CoSi, or p-type impurities. .   The nonvolatile memory element according to claim 1, wherein an electrical resistance value of the interface changes depending on a charge amount stored in an interface between the thin film made of the strongly correlated electron material and the second electrode.   The memory cell selecting MISFET formed on the main surface of the semiconductor substrate and the variable resistance portion formed at least partially on the insulating film covering the memory cell selecting MISFET are formed on the insulating film. 2. The nonvolatile memory element according to claim 1, wherein a drain of the memory cell selection MISFET and the first or second electrode of the variable resistance portion are electrically connected via a plug in the contact hole.   The nonvolatile memory element according to claim 8, wherein the second electrode is constituted by the plug. A nonvolatile memory element is formed at intersections of a plurality of word lines extending in a first direction on a main surface of a semiconductor substrate and a plurality of bit lines extending in a second direction orthogonal to the first direction. A semiconductor device,
The nonvolatile memory element includes a variable resistance portion and a memory cell selection MISFET connected in series to the variable resistance portion.
The variable resistance portion includes a thin film made of a strongly correlated electron material whose outermost electron trajectory is composed of d electrons or f electrons, a first electrode in ohmic contact with one surface of the thin film, A second electrode in non-ohmic contact with the other surface,
A semiconductor device characterized in that information is stored according to a magnitude of an electric resistance value at an interface between the thin film made of the strongly correlated electron material and the second electrode. A variable resistance section, and a memory cell selection MISFET connected in series to the variable resistance section;
The variable resistance portion includes a thin film made of a strongly correlated electron material whose outermost electron trajectory is composed of d electrons or f electrons, a first electrode in ohmic contact with one surface of the thin film, A second electrode in non-ohmic contact with the other surface,
A method for manufacturing a nonvolatile memory element that stores information according to a magnitude of an electrical resistance value at an interface between a thin film made of the strongly correlated electron material and the second electrode,
(A) forming the memory cell selection MISFET on the main surface of the semiconductor substrate;
(B) a step of forming a contact hole in the insulating film above the memory cell selecting MISFET after forming an insulating film on the memory cell selecting MISFET;
(C) after filling a plug in the contact hole, forming the variable resistance portion on the plug;
A method for manufacturing a non-volatile memory device, comprising:   The step (c) includes a step of embedding the plug constituting the second electrode in the contact hole, a step of forming a thin film made of the strongly correlated electron material on the plug, and the strong correlation The method of manufacturing a nonvolatile memory element according to claim 11, further comprising: forming the first electrode on a thin film made of an electronic material.   The step (c) includes the step of burying the plug constituting the second electrode in the contact hole, and oxidizing the surface portion of the plug to thereby form the strongly correlated electron material on the surface portion of the plug. 12. The method of manufacturing a nonvolatile memory element according to claim 11, comprising a step of forming a thin film comprising: and a step of forming the first electrode on the thin film comprising the strongly correlated electron material.   The step (c) includes a step of embedding a plug in the contact hole, a step of forming a first electrode on the plug, and oxidizing the surface portion of the first electrode. 12. The method includes: forming a thin film made of the strongly correlated electron-based material on a surface portion of the substrate; and forming the second electrode on the thin film made of the strongly correlated electron-based material. The manufacturing method of the non-volatile memory element of description.   The step (c) includes a step of embedding the plug constituting the first electrode in the contact hole, and oxidizing the surface portion of the plug to thereby form the strongly correlated electron material on the surface portion of the plug. 12. The method of manufacturing a nonvolatile memory element according to claim 11, further comprising: a step of forming a thin film made of: and a step of forming the second electrode on the thin film made of the strongly correlated electron material.

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