JPWO2006132158A1 - Nonvolatile semiconductor memory device and manufacturing method thereof - Google Patents

Abstract

An object of the present invention is to provide a semiconductor memory device and a method for manufacturing the same, in which the ratio of capacitance between the floating gate and the control gate is further increased without increasing the occupied area of the semiconductor memory device having the floating gate and the control gate. A semiconductor memory device having a memory cell composed of a floating gate and a control gate formed all around the side wall of the semiconductor layer, and by separating the floating gate from the bottom of the semiconductor layer, the control gate is placed below the floating gate. Form. Further, a means for forming a concave control gate is provided by forming a control gate on the floating gate.

Description

  The present invention relates to a nonvolatile semiconductor memory device and a manufacturing method thereof, and more particularly to a nonvolatile semiconductor memory device using a memory transistor having a floating gate and a control gate and a manufacturing method thereof.

  Conventionally, as a memory cell of an EEPROM, a device having a MOS transistor structure having a floating gate and a control gate in a gate portion, and injecting charges into the floating gate and discharging charges from the floating gate using a tunnel current. It has been known. In this memory cell, the difference in threshold voltage due to the difference in charge accumulation state of the floating gate is stored as data “0” and “1”.

  For example, in the case of an n-channel memory cell using a floating gate, in order to inject electrons into the floating gate, the source diffusion layer is grounded and a positive high voltage is applied to the drain diffusion layer and the control gate. At this time, near the drain diffusion layer, electrons having high energy capable of exceeding the energy barrier from the silicon surface to the oxide film, that is, hot electrons are generated, and these electrons cross the barrier of the silicon oxide film and are generated in the control gate. It is pulled by a high voltage and injected into the floating gate. By this electron injection, the threshold voltage of the memory cell moves in the positive direction.

  On the other hand, to emit electrons from the floating gate, the control gate is grounded and a positive high voltage is applied to either the source / drain diffusion layer or the substrate. At this time, electrons are emitted from the floating gate to the substrate side by a tunnel current. Due to this electron emission, the threshold voltage of the memory cell moves in the negative direction.

  In the above operation, in order to efficiently perform electron injection and emission, that is, writing and erasing, the relationship of capacitive coupling between the floating gate and the control gate and between the floating gate and the substrate is important. That is, as the capacitance between the floating gate and the control gate is larger, the potential of the control gate can be effectively transmitted to the floating gate, and writing and erasing are facilitated.

However, due to advances in semiconductor technology in recent years, particularly advances in microfabrication technology, the size and capacity of EEPROM memory cells are rapidly increasing.
Therefore, it is an important problem to reduce the memory cell area and to secure a large capacity between the floating gate and the control gate.

In order to increase the capacitance between the floating gate and the control gate, the gate insulating film between them is thinned, the dielectric constant is increased, or the facing area between the floating gate and the control gate is increased. It is necessary.
However, reducing the gate insulating film has a limit in reliability. In order to increase the dielectric constant of the gate insulating film, for example, it is conceivable to use a silicon nitrogen film or the like in place of the silicon oxide film. However, this also has a problem mainly in reliability and is not practical.

  Therefore, in order to secure a sufficient capacity, it is necessary to secure a counter area between the floating gate and the control gate at a certain value or more. This reduces the area of the memory cell and increases the capacity of the EEPROM. This is contrary to the plan.

  Therefore, an EEPROM is proposed in which a semiconductor substrate is separated by a lattice-like groove, a plurality of columnar semiconductor layers are arranged in a matrix form, and a memory transistor is configured using the sidewalls of the columnar semiconductor layers. (For example, Non-Patent Document 1). With such a configuration, a sufficiently large capacitance between the floating gate and the control gate can be secured with a small occupied area.

  In this configuration, the drain diffusion layer connected to the bit line of each memory cell is formed on the upper surface of the columnar semiconductor layer, and is completely electrically insulated by the groove. Furthermore, the element isolation region can be reduced, and the memory cell size can also be reduced. Therefore, it is possible to obtain a large capacity EEPROM in which memory cells having excellent writing and erasing efficiency are integrated.

  Another problem with nonvolatile semiconductor memory devices is that by increasing the capacitance between the floating gate and the control gate, the voltage between the semiconductor layer and the floating gate is increased even at a low control gate voltage, and electrons are injected into the floating gate. Writing can be performed.

Fumihiko Hayashi and James D. Plummer, “A Self-Aligned Split-Gate Flash EEPROM Cell with 3-D Pillar Structure”, 1999 Symposium on VSLI Technology, Session 7A, T7A-4, Kyoto, Japan

  Incidentally, in FIG. 17 showing the structure described in Non-Patent Document 1, in order to increase the coupling ratio between the thickness of the floating gate and the thickness of the control gate, the capacitance between the floating gate and the control gate is increased. Just make it bigger. For this purpose, the floating gate thickness should be increased. However, increasing the floating gate thickness also increases the capacitance between the semiconductor layer under the floating gate and the floating gate, resulting in a coupling ratio of It will decline.

  Thus, an object of the present invention is to increase the coupling ratio without increasing the capacitance between the semiconductor layer and the floating gate.

The present invention relates to a floating gate that includes a columnar semiconductor layer on a substrate and is arranged in parallel to the side surface of the columnar semiconductor layer.
(1) Whether the control gate is formed so as to cover the opposite surface and the upper side of the floating gate facing the columnar semiconductor layer, thereby increasing the coupling ratio;
(2) The control gate is formed so as to cover the opposite surface opposite to the side facing the columnar semiconductor layer of the floating gate and the lower portion, so that the semiconductor layer under the floating gate depending on the thickness of the floating gate Eliminate the capacitance between the floating gate, do not increase the capacitance between the semiconductor layer and the floating gate, and cause a decrease in the coupling ratio; or

(3) The capacitance between the floating gate and the control gate is increased by forming the control gate so as to cover the upper surface and the opposite surface of the floating gate opposite to the side facing the columnar semiconductor layer. Enable and consequently increase the coupling ratio;
Accordingly, a nonvolatile semiconductor memory device that solves the above-described problems is provided.

Thus, according to the present invention, a columnar semiconductor layer is provided on a substrate,
The floating gate is arranged in parallel to the side surface of the columnar semiconductor layer,
The control gate is formed through an insulating film so as to cover an opposite surface opposite to the side facing the columnar semiconductor layer of the floating gate and at least another surface adjacent to the control gate. A non-volatile semiconductor memory device is provided.

  According to the present invention, since the control gate is formed so as to cover the above-mentioned facing surface and the upper and / or lower part of the floating gate, the control gate and the floating gate are not increased without increasing the capacitance between the semiconductor layer and the floating gate. Only the capacity between the gates can be increased, and the coupling ratio can be made larger than that of the conventional SGT type flash memory. Therefore, the write characteristics are improved, and an ideal subthreshold swing S can be realized.

FIG. 6 is a schematic process cross-sectional view of the nonvolatile semiconductor memory device according to the first embodiment of the invention. FIG. 6 is a schematic process cross-sectional view of the nonvolatile semiconductor memory device according to the first embodiment of the invention. FIG. 6 is a schematic process cross-sectional view of the nonvolatile semiconductor memory device according to the first embodiment of the invention. It is a schematic process sectional view of a nonvolatile semiconductor memory device according to Example 1 of the invention. FIG. 6 is a schematic process cross-sectional view of the nonvolatile semiconductor memory device according to the first embodiment of the invention. FIG. 6 is a schematic process cross-sectional view of the nonvolatile semiconductor memory device according to the first embodiment of the invention. It is a schematic process sectional view of a nonvolatile semiconductor memory device according to Example 1 of the invention. FIG. 6 is a schematic process cross-sectional view of the nonvolatile semiconductor memory device according to the first embodiment of the invention.

FIG. 6 is a schematic process cross-sectional view of the nonvolatile semiconductor memory device according to the first embodiment of the invention. FIG. 6 is a schematic process cross-sectional view of the nonvolatile semiconductor memory device according to the first embodiment of the invention. FIG. 6 is a schematic process cross-sectional view of the nonvolatile semiconductor memory device according to the first embodiment of the invention. FIG. 6 is a schematic process cross-sectional view of the nonvolatile semiconductor memory device according to the first embodiment of the invention. FIG. 6 is a schematic process cross-sectional view of the nonvolatile semiconductor memory device according to the first embodiment of the invention. FIG. 6 is a schematic process cross-sectional view of the nonvolatile semiconductor memory device according to the first embodiment of the invention. FIG. 6 is a schematic process cross-sectional view of the nonvolatile semiconductor memory device according to the first embodiment of the invention. FIG. 6 is a schematic process cross-sectional view of the nonvolatile semiconductor memory device according to the first embodiment of the invention. FIG. 6 is a schematic process cross-sectional view of the nonvolatile semiconductor memory device according to the first embodiment of the invention.

It is sectional drawing of the non-volatile semiconductor memory device by Example 1 of this invention. It is sectional drawing of the non-volatile semiconductor memory device by Example 2 of this invention. It is sectional drawing of the non-volatile semiconductor memory device by Example 3 of this invention. It is sectional drawing of the non-volatile semiconductor memory device by Example 4 of this invention. FIG. 7 is a cross-sectional view of a nonvolatile semiconductor memory device according to Example 5 of the present invention. It is sectional drawing of the non-volatile semiconductor memory device by Example 6 of this invention. It is sectional drawing of the non-volatile semiconductor memory device by Example 7 of this invention.

It is sectional drawing of the non-volatile semiconductor memory device of a prior art. It is a figure for demonstrating the coupling ratio of a prior art. It is a figure for demonstrating the coupling ratio of a prior art. It is a figure for demonstrating the coupling ratio of a prior art. It is a figure for demonstrating the coupling ratio of the technique of this invention.

It is a figure for demonstrating the coupling ratio of the technique of this invention. It is a figure for demonstrating the coupling ratio of the technique of this invention. It is a figure for demonstrating the coupling ratio of the technique of this invention. It is a figure for demonstrating the coupling ratio of the technique of this invention.

It is a figure which compares the coupling ratio of the semiconductor device by a prior art, and the semiconductor memory device by this invention. It is a figure which compares the coupling ratio of the semiconductor device by a prior art, and the semiconductor memory device by this invention. It is a figure which compares the coupling ratio of the semiconductor device by a prior art, and the semiconductor memory device by this invention. It is a figure which compares the coupling ratio of the semiconductor device by a prior art, and the semiconductor memory device by this invention.

Explanation of symbols

1 Semiconductor substrate (p-type)
2, 5, 13 Silicon oxide film 3 Silicon oxide film (tunnel oxide film)
4 Polysilicon layer (floating gate)
6 First semiconductor layer (channel, p-type)
7/8 second semiconductor layer (source diffusion layer, n-type) / second semiconductor layer (drain diffusion layer, n-type)
9 Silicon oxide film (interpoly insulating film)
10 Silicon nitride film (interpoly insulating film)
11 Polysilicon layer (control gate)
12 Photoresist film 14 Bit line

  Specifically, according to the present invention, the substrate includes a columnar semiconductor layer, the floating gate is disposed in parallel to the side surface of the columnar semiconductor layer, and the control gate is disposed on the side of the floating gate facing the columnar semiconductor layer. There is provided a nonvolatile semiconductor memory device formed so as to cover the opposite facing surface and the upper, lower, or upper and lower portions of the floating gate adjacent thereto.

  The semiconductor substrate that can be used in the present invention is not particularly limited, and any known substrate can be used. Examples thereof include bulk substrates made of elemental semiconductors such as silicon and germanium, and compound semiconductors such as silicon germanium, GaAs, InGaAs, ZnSe, and GaN.

  In addition, the semiconductor layer on the surface includes various substrates such as an SOI (Silicon on Insulator) substrate, an SOS (Silicone on Sapphire) substrate or a multilayer SOI substrate, and those having a semiconductor layer on a glass or plastic substrate. Can be mentioned. Among these, a silicon substrate or an SOI substrate having a silicon layer formed on the surface is preferable. The semiconductor substrate has a p-type or n-type first conductivity type.

  Next, the columnar semiconductor layer formed on the substrate may be made of the same or different material as that constituting the substrate. In particular, it is preferably made of the same material, more preferably made of silicon.

The shape of the columnar semiconductor layer is not particularly limited, and various shapes such as a cylinder, a prism (a triangular column, a quadrangular column, a polygonal column), a cone, and a pyramid can be employed. Further, the columnar semiconductor layer may have the same conductivity type as the substrate or a different conductivity type.
The method for forming the columnar semiconductor layer is not particularly limited, and any known method can be used. For example, a method of forming a columnar semiconductor layer by depositing a semiconductor layer on a substrate using an epitaxial method and etching the semiconductor layer, or a method of forming a columnar semiconductor layer by digging down the substrate by etching is given. .

A floating gate is disposed on the side surface of the columnar semiconductor layer in parallel with the side surface.
The upper part or the lower part of the floating gate in the width direction is not necessarily in the vertical direction with respect to the columnar semiconductor layer, and may be arbitrarily inclined.
Moreover, although the formation method of a floating gate is not specifically limited, For example, the deposition method is mentioned.

The floating gate may be made of the same or different material as the material constituting the substrate and / or the columnar semiconductor layer, and is not particularly limited. For example, when formed by a deposition method as described above, chemical vapor deposition Polysilicon which is easy to deposit by the method is preferred.
An insulating film such as a silicon oxide film is usually formed between the columnar semiconductor layer and the floating gate.

Further, the control gate is formed via an insulating film so as to cover the opposite surface opposite to the side facing the columnar semiconductor layer of the floating gate and at least the other surface adjacent thereto.
The ratio of the control gate covering the floating gate is not particularly limited, but the control gate is formed so as to partially cover the entire opposite surface of the floating gate and at least one other surface adjacent thereto, preferably more than half. It is preferable from the viewpoint of increasing the coupling ratio.
Although the formation method of a control gate is not specifically limited, For example, the deposition method is mentioned.

The material constituting the control gate is not particularly limited, and examples thereof include semiconductors such as polysilicon and amorphous silicon, silicides, metals, refractory metals, and the like. Polysilicon that is easy to deposit by phase growth is preferred.
The insulating film (interpoly insulating film) formed between the control gate and the floating gate is, for example, an interpoly insulating film made of a silicon oxide film, or a silicon oxide film, a silicon nitride film, and a silicon oxide film. And an interpoly insulating film (ONO film) composed of three layers.

  Furthermore, an impurity diffusion layer can be formed above and below the columnar semiconductor layer or on the semiconductor substrate. The upper diffusion layer of this impurity diffusion layer functions as a drain / source region, and the diffusion layer formed below the columnar semiconductor layer or on the semiconductor substrate functions as a source / drain region. The lower diffusion layer of the columnar semiconductor layer may extend from the columnar semiconductor layer onto the semiconductor substrate.

  Further, when the impurity diffusion layer is formed on the semiconductor substrate, the entire upper surface of the semiconductor substrate excluding the base portion of the columnar semiconductor layer, or on the semiconductor substrate excluding the lower portion of the semiconductor substrate-like floating gate and control gate It may be formed in the peripheral part of the.

The impurity diffusion layer has a p-type second conductivity type when the semiconductor substrate and the columnar semiconductor layer are n-type in the first conductivity type, and p-type when the columnar semiconductor layer is the p-type in the second conductivity type. The first conductivity type preferably has an n-type.
A bit line can be formed by exposing the surface of the diffusion layer formed on the columnar semiconductor layer by a method known to those skilled in the art.

  Therefore, according to the present invention, the columnar semiconductor layer is provided on the substrate, the floating gate is arranged in parallel to the side surface of the columnar semiconductor layer, and the control gate is opposite to the side of the floating gate facing the columnar semiconductor layer. There is provided a nonvolatile semiconductor memory device formed so as to cover the opposing surface and the upper and lower portions.

  According to another aspect, a nonvolatile semiconductor memory device in which the control gate is formed so as to cover the opposing surface and the upper portion of the floating gate is also included in the scope of the present invention.

  Furthermore, according to another aspect, the control gate is included in the scope of the present invention in which the control gate is formed so as to cover the opposing surface and the lower portion of the floating gate.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following examples.
Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof is omitted in the description of the embodiments and the drawings.

FIG. 1 to FIG. 10 b are schematic views showing in steps the manufacturing method of one nonvolatile semiconductor memory device existing on a semiconductor substrate according to the present invention.
10b to 16 are schematic views showing the structure of a nonvolatile semiconductor memory device manufactured according to the present invention.

Further, FIGS. 17 to 20 and FIGS. 21 to 25 are schematic views showing the structures of the semiconductor device according to the prior art and the semiconductor memory device according to the present invention, respectively.
In these drawings, as an example, a columnar semiconductor layer formed on a semiconductor substrate has a cylindrical shape.

Example 1
Step 1:
For example, a thick silicon oxide film (2) is formed on a p-type semiconductor substrate (1) made of silicon by a thermal oxidation method (FIG. 1).

  Next, the silicon oxide film is formed as a mask for etching the p-type semiconductor substrate by lithography and reactive ion etching (RIE) technology (FIG. 2).

  Thereafter, a silicon pillar is formed by scraping the p-type semiconductor substrate by, for example, a depth of about 500 nm by the RIE technique (FIG. 3).

  Next, the etching mask and silicon oxide on the silicon pillar are removed by a wet etching technique (FIG. 4a). Then, the silicon pillar is thinned by sacrificial oxidation using a thermal oxidation technique and a wet etching technique (FIG. 4b).

Step 2:
Further, gate oxidation is performed to form a gate oxide film (3) on the entire surface including the periphery of the silicon pillar (FIG. 4c).

Step 3:
Thereafter, a polysilicon layer (4) is deposited by chemical vapor deposition (CVD) technique (FIG. 5a). Then, the polysilicon surface deposited by thermal oxidation is oxidized to form an oxide film (5) (FIG. 5b).

Step 4:
Next, the other portion of the oxide film formed on the polysilicon surface is removed by RIE so that only the side wall portion of the polysilicon remains (FIG. 6a).

Step 5:
Further, the polysilicon is removed by a wet etching technique (FIG. 6b) to form a floating gate.
In this step, when there are a plurality of memory cells on the semiconductor substrate, floating gates are formed separately from the adjacent memory cells.
Thereafter, all of the silicon oxide other than the inside of the polysilicon is removed by a wet etching technique (FIG. 6c).

Step 6:
Next, phosphorus (P) ions are implanted into the silicon pillar by oblique ion implantation to form a diffusion layer (7/8) that becomes the source / drain of the memory, thereby forming the first and Second semiconductor layers (6 to 8) are formed (FIG. 7).
During the above ion implantation, the silicon oxide film and the polysilicon film function as a mask, and the channel portion (6) of the memory is formed in a self-aligned manner.

The length of the channel of the formed memory in the y-axis direction is the channel length.
Note that the length of the channel can be easily adjusted by RIE of the polysilicon oxide film and wet etching of polysilicon shown in the respective steps of FIGS. 6a to 6c.

Step 7:
Thereafter, silicon oxide (9), silicon nitride (10), and silicon oxide (9) are deposited in this order on the above-described semiconductor layer by the CVD technique, thereby forming 3 between the floating gate and the control gate. A layer insulating film (interpoly insulating film, ONO film) is formed (FIG. 8).
Here, instead of the above-described three-layer ONO film, an interpoly insulating film made of one layer of silicon oxide can be formed.

Step 8:
Next, a polysilicon layer (11) is deposited on the surface of the silicon oxide formed as described above by a CVD technique, and the surface of this polysilicon is planarized by a chemical mechanical polishing (CMP) technique (FIG. 9a). .

Step 9:
Next, the side surface of the control gate is formed by lithography and RIE technology (FIG. 9b). Thereafter, the upper part of the control gate is formed by further forming polysilicon by RIE technique to obtain the structure shown in FIG. 9c.

Step 10:
Further, silicon oxide (13) is deposited on the surface of the obtained structure by a CVD technique. By this step, when a plurality of memory cells are present on the semiconductor substrate, they can be insulated from adjacent memory cells.

Step 11:
Next, the drain portion is exposed by scraping silicon, silicon oxide and silicon nitride on the top of the structure by CMP technology (FIG. 10a).

Step 12:
Thereafter, a bit line (14) is formed by CVD technology and lithography, thereby providing a nonvolatile semiconductor memory device in which a control gate is formed so as to cover the opposing surface and upper and lower portions of the floating gate ( FIG. 10b).

  In the semiconductor device thus obtained, the channel portion is not floating, and is arranged in parallel with the channel portion without sandwiching the control gate below the floating gate. It has a transistor portion.

  FIGS. 11 to 16 respectively show the nonvolatile semiconductor memory device according to the different embodiments of the present invention obtained by slightly changing the manufacturing conditions in the method for manufacturing the nonvolatile semiconductor memory device shown in FIG. 10b (Example 1). A production example is shown.

Example 2
In Example 1, the semiconductor memory shown in FIG. 11 in which the p-type channel is formed between the n-type drain diffusion layer and the n-type source diffusion layer to have substantially the same length as the floating gate by changing the conditions in the step 5. A device is obtained.

  The semiconductor memory device thus obtained does not have a transistor portion because the channel portion is floating and the diffusion layer is next to the control gate below the floating gate.

Example 3
Next, in Example 1, the semiconductor memory shown in FIG. 12 in which the p-type channel is formed longer than the floating gate length between the n-type drain diffusion layer and the n-type source diffusion layer by changing the conditions in the step 5. A device is obtained.

  In the semiconductor memory device thus obtained, the channel portion is in a floating state, and the control gate below the floating gate is arranged in parallel with the channel portion without sandwiching the floating gate. Also have a transistor portion.

Example 4
The semiconductor memory device shown in FIG. 13 in which the interpoly insulating film is composed of only one silicon oxide film is obtained in the same manner as in Example 1 except that only the silicon oxide film is deposited in Step 7 of Example 1. .

  The semiconductor memory device thus obtained is obtained by changing the ONO film of the semiconductor memory device obtained in the first embodiment only to the silicon oxide film, and the coupling ratio thereof is compared with that of the semiconductor memory device of the first embodiment. Although it decreases, the number of manufacturing steps can be reduced.

Example 5
In step 4 of the first embodiment, the silicon oxide film and the polysilicon are subjected to RIE technology to form a floating gate disposed on the semiconductor substrate via the gate oxide film. The thickness of the floating gate is substantially the same as the thickness of the polysilicon.
Next, in step 7, a control gate is formed. Next, the source / drain diffusion layer forming portion is exposed using the control gate as a mask. Thereafter, in step 6, a drain / source diffusion layer of the memory is formed in the peripheral portion of the semiconductor substrate excluding the upper portion of the columnar semiconductor layer and the lower portion of the floating gate and the control gate. Thereafter, the control gate is formed so as to cover the opposite surface and the upper portion of the floating gate by performing the processes of steps 11 and 12, and the floating gate and the control gate are made of a p-type channel. The semiconductor memory device shown in FIG. 14 in which the n-type source diffusion layer is formed outside the control gate of the channel is obtained.

  The semiconductor memory device thus obtained has control gates on the side surface and upper part of the floating gate, and the coupling ratio is lower than that of the semiconductor memory device of Embodiment 1, but the number of manufacturing steps is reduced. Can do.

Example 6
In step 9 of Example 1, etching is performed until the interpoly insulating film formed on the floating gate is exposed. Next, in the order of steps 10, 11 and 12, a control gate is formed so as to cover the opposing surface and the lower part of the floating gate, and the control gate is made of a p-type channel. Thus, the semiconductor memory device shown in FIG. 15 in which the n-type source diffusion layer is formed outside the control gate is obtained.

  The semiconductor memory device obtained in this way has control gates on the side and bottom of the floating gate, and the coupling ratio is lower than that of the semiconductor memory device of the first embodiment, but the number of manufacturing steps is reduced. Can do.

Example 7
After step 1 of Example 1, phosphorus (P) ions are implanted into the silicon pillar and the substrate surface by vertical ion implantation into the substrate to form a source / drain diffusion layer (7/8) of the memory, and Except for the step 6, the semiconductor memory device shown in FIG. 16 is obtained by performing the processes after the step 2 in the same manner as in the first embodiment.

  The semiconductor memory device thus obtained also has a transistor portion above the floating gate, and has the same area as that of the semiconductor memory device of Example 1 in which the transistor portions other than the memory cells are only below the floating gate. It is possible to increase the reliability without increasing the value.

  Next, the difference between the conventional technique and the technique of the present invention for realizing an increase in the coupling ratio will be described with reference to FIG. FIG. 12 shows a semiconductor memory device having the highest coupling ratio among the nonvolatile semiconductor memory devices according to the present invention. In this device, the floating gate is arranged in parallel to the side surface of the columnar semiconductor layer, the control gate is opposite to the side of the floating gate facing the columnar semiconductor layer, the upper surface of the floating gate adjacent to the floating gate, and The lower part is covered with an insulating film (interpoly insulating film).

In addition, for explanation:
1) There is no overlap between the floating gate and the second semiconductor layer:
2) The capacitance of the corner portion in the capacitance between the floating gate and the control gate is negligible: 3) The length of the portion of the floating gate where the control gate and the facing surface overlap is the same as the channel length:
Assume that

First, a conventional technique will be described with reference to FIGS.
The total tunnel oxide film capacity (hereinafter _{referred to} as C _ox1 ) in the prior art is obtained by connecting a cylindrical capacity C _ox1-side (FIG. 19) and a parallel plate capacity C _ox1-under (FIG. 20) in parallel. Can be considered.

Here, as shown in FIG. 18, the pillar radius (hereinafter referred to as R) of the silicon pillar, the tunnel oxide thickness (hereinafter referred to as _Tox ), the floating gate thickness (hereinafter referred to as T _fg ), Interpoly insulating film thickness (hereinafter referred to as _Tip ), gate length (hereinafter referred to as L), circumference ratio (hereinafter referred to as π), and dielectric constant of silicon oxide (hereinafter referred to as _εox ). When used, the cylindrical capacity (C _oxl-side ) and the parallel plate capacity (C _oxl-under ) are respectively expressed by the following formulas:

,
The total tunnel oxide film capacity (C _ox1 ) is expressed by the formula:

It is represented by
Further, since the interpoly insulating film capacitance (hereinafter referred to as C _ip1 ) is only the capacitance having the cylindrical shape shown in FIG. 19, π, ε _ox , L, R, _Tox , T _fg , T defined above. By using _ip , the formula:

It is represented by

Next, the technique of the present invention will be described with reference to FIGS. Since the tunnel oxide film capacity (hereinafter referred to as C _ox2 ) in the present invention is only the capacity of the cylindrical shape shown in FIG. 23, L, R, _Tox and π and ε _ox shown in FIG. 21 are used. And the formula:

It is represented by

The total interpoly insulating film capacity (hereinafter referred to as _Cip2 ) is equal to the capacity of the cylindrical interpoly insulating film (hereinafter referred to as _Cip2-side ) (FIG. 23) and the parallel plate shape. It can be considered that interpoly insulating film capacitors (hereinafter referred to as _Cip2-under ) (FIG. 21) are connected in parallel.
That is, the total interpoly insulating film capacitance is C _ip2 = C _ip2-side + C _ip2-under .

However, on _Cip2-side , the ONO film has three layers. Therefore, L shown in FIGS. 21 and _{25, R, T ox, T} fg, π, ε using _ox, and then the silicon oxide film thickness inside of interpoly insulating film and the capacity and T _ip1 and C1, respectively, intermediate C1 and C2 where _Tip2 and C2 are the silicon nitride film thickness and its capacitance, respectively, and the dielectric constant of the silicon nitride film is ε _SiN and the outer silicon oxide film thickness and its capacitance are _Tip3 and C3, respectively. And C3 are represented by the formula:

It is represented by

On the other hand, the capacitance C _ip2-side of the interpoly insulating film in which the cylindrical shape can be regarded as a series combined capacitance of the capacitor of the ONO film, C _ip2-side has the formula:
It is represented by

On the other hand, the capacitance C _ip2-under the ONO film parallel plate-shaped, in the same manner as the C _oxl-under, wherein:
It is represented by
In the equation, T _ip ′ means a film thickness obtained by converting an ONO film having three layers into a silicon oxide film.

Therefore, the total interpoly insulation film capacity is the formula:
It is represented by

Next, as shown in the following test example, the column diameter and the gate length were changed, and the semiconductor memory device manufactured by the conventional technique (FIG. 17) and the semiconductor memory device according to Example 3 of the present invention (FIG. 12) were used. The coupling ratio was compared between the two.
The coupling ratio was calculated by dividing the tunnel oxide film capacitance and the interpoly insulating film capacitance, that is, the interpoly insulating film capacitance divided by the tunnel oxide film capacitance.
The results of calculation and comparison as described above for each semiconductor memory device manufactured in the following test examples are shown in FIGS.

Test example 1
Regarding a semiconductor memory device having a column diameter R = 300 nm and a gate length L = 520 nm actually prototyped in Non-Patent Document 1, and a semiconductor memory device according to Example 3 of the present invention under the same conditions (FIG. 12), FIG. 26 shows a graph that compares changes in the coupling ratio due to changes in the thickness of the floating gate.

In this graph, the vertical axis represents the coupling ratio, and the horizontal axis represents the floating gate film thickness T _fg .
From this graph, it was found that the semiconductor memory device according to the present invention had a larger coupling ratio than that according to the prior art, and the difference became larger as the floating gate film thickness was increased.

Test example 2
As in Test Example 1, FIG. 27 shows the results of comparison between a semiconductor memory device having a column diameter R = 300 nm and a gate length L = 50 nm prepared according to the prior art and the present invention.

Test example 3
As in Test Example 1, FIG. 28 shows the result of comparison between a semiconductor memory device having a column diameter R = 50 nm and a gate length L = 520 nm prepared according to the prior art and the present invention.

Test example 4
As in Test Example 1, FIG. 29 shows the result of comparison between a semiconductor memory device having a column diameter R = 50 nm and a gate length L = 50 nm created according to the prior art and the present invention.

From the results of the above test examples, in the nonvolatile semiconductor memory device according to the present invention, the difference in the coupling ratio with the semiconductor memory device according to the prior art increases as the thickness of the floating gate, that is, T _fg increases. I understand that.

This is a semiconductor memory device according to the prior art, the tunnel oxide capacitance C _ox1 is increased by increasing the T _fg, the semiconductor memory device according to the invention, the interpoly insulating film by increasing the T _fg capacitance C _This is thought to be based on the effect of increasing _ip2 .

  According to the present invention, since the control gate is above and below the floating gate, only the capacitance between the control gate and the floating gate can be increased without increasing the capacitance between the semiconductor layer and the floating gate, and the coupling ratio can be increased. It can be made larger than the conventional SGT type flash memory. Therefore, the write characteristics are improved, and an ideal subthreshold swing S can be realized.

Claims (7)

A columnar semiconductor layer is provided on the substrate,
The floating gate is arranged in parallel to the side surface of the columnar semiconductor layer,
A non-volatile semiconductor memory device in which a control gate is formed via an insulating film so as to cover a facing surface opposite to the side facing the columnar semiconductor layer of the floating gate and at least another surface adjacent to the control gate .   2. The nonvolatile semiconductor memory according to claim 1, wherein the control gate is formed so as to cover an opposing surface of the floating gate and an upper portion, a lower portion, or an upper and lower portion in the lateral width direction of the floating gate adjacent to the opposing surface. apparatus.   The nonvolatile semiconductor memory device according to claim 1, wherein the control gate is formed so as to cover an opposing surface and an upper and lower portion of the floating gate.   The nonvolatile semiconductor memory device according to claim 1, wherein the control gate is formed so as to cover an opposing surface and an upper portion of the floating gate.   The nonvolatile semiconductor memory device according to claim 1, wherein the control gate is formed so as to cover a facing surface and a lower portion of the floating gate.   2. The nonvolatile semiconductor memory device according to claim 1, wherein the insulating film is composed of one layer of silicon oxide film or three layers of a silicon oxide film, a silicon nitride film, and a silicon oxide film. Forming a columnar semiconductor layer on a first conductivity type semiconductor substrate;
Arranging a floating gate parallel to the side surface of the columnar semiconductor layer;
A non-volatile semiconductor comprising: a step of forming a control gate through an insulating film so as to cover an opposing surface opposite to the side facing the columnar semiconductor layer of the floating gate and at least one other surface adjacent thereto A method for manufacturing a storage device.