JP2005311251A - Semiconductor memory device, method for manufacturing the same, and portable electronic device equipped with the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an EEPROM which is high in writing speed and has small occupied area for a memory cell, and to provide a method for manufacturing the EEPROM. <P>SOLUTION: An island-like semiconductor layer 110, having a tilted part or at least one step part, is formed on a semiconductor substrate 100. The island-like semiconductor layer comprises a drain diffusion layer 600 formed thereon, a source diffusion layer 500 formed on at least a part of the bottom thereof, a charge accumulation layer 300, formed on the channel region of a sidewall sandwiched between the drain diffusion layer and the source diffusion layer via a gate insulating film, and a control gate 400 formed on the charge accumulation layer. The stage of the step part or the tilt angle of the tilted part is set so as to facilitate injection into the charge accumulation layer. Alternatively, the island-like semiconductor layer comprises a charge storing layer formed on a channel region as a region sandwiched between a drain diffusion layer and a source diffusion layer via a gate insulating film, a control gate formed on the charge storing layer, and a diffusion layer of conduction type which is opposite to that of the drain diffusion layer and located in a channel region adjacent to the drain diffusion layer. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a nonvolatile semiconductor memory device and a method for manufacturing the same, and a portable electronic device including the same, and more particularly to a semiconductor memory device having a three-dimensional structure memory cell having an island-shaped semiconductor on a substrate and a method for manufacturing the same.

  The gate has a charge storage layer and a control gate, injects charges into the charge storage layer using channel hot electrons, etc., and stores charge using a Fowler-Nordheim current (hereinafter abbreviated as FN current). 2. Description of the Related Art A semiconductor memory device (or EEPROM) having a memory cell having a MOS transistor structure for discharging charges from a layer is known. This memory cell stores unit data of “0” or “1” by utilizing the fact that the threshold voltage differs depending on the charge storage state of the charge storage layer. For example, in the case of an n-channel memory cell using a floating gate as a charge storage layer, the threshold voltage of the memory cell is moved in the positive direction by injecting hot electrons into the floating gate. In order to inject hot electrons, channel hot electrons are generated by applying an electric field between the source diffusion layer and the drain diffusion layer, and hot electrons generated by applying a positive voltage to the gate are injected into the floating gate. Conversely, in order to release the electrons injected into the floating gate, the control gate is grounded and a positive high voltage is applied to any of the source, drain diffusion layer, and substrate. At this time, electrons on the substrate side are emitted from the floating gate by a tunnel current. Due to this electron emission, the threshold voltage of the memory cell moves in the negative direction.

  In order to efficiently perform electron injection and emission, in other words, writing and erasing, a capacitive coupling relationship between the floating gate and the control gate is important. The larger the capacitance between the floating gate and the control gate, the more effectively the potential of the control gate can be transmitted to the floating gate, which facilitates writing and erasing. Due to advances in semiconductor technology in recent years, particularly advances in microfabrication technology, the size and capacity of EEPROM memory cells are rapidly increasing. Even if the memory cell area is small due to downsizing, a means that can ensure a large capacitance between the floating gate and the control gate is desired. In order to increase the capacitance between the floating gate and the control gate, the gate insulating film between them can be thinned, the dielectric constant can be increased, or the opposing area of the floating gate and the control gate can be increased. However, thinning the gate insulating film has a limit in reliability. As a means for increasing the dielectric constant of the gate insulating film, for example, a silicon nitrogen film or the like may be used instead of the silicon oxide film. However, this is also impractical, mainly due to reliability issues. The remaining means for securing a sufficient capacity is to secure an overlap area between the floating gate and the control gate above a certain value. However, this is an obstacle to reducing the memory cell area and increasing the capacity of the EEPROM.

  As one of the different means for overcoming the above-mentioned problems, an island-like semiconductor layer is formed on the surface of a semiconductor substrate, and a charge storage layer and a control gate are formed on the side wall so as to surround the island-like semiconductor layer. There has been proposed an EEPROM composed of memory cells having (see, for example, Patent Document 1 and Non-Patent Document 1). FIG. 45 is a cross-sectional structure diagram showing a schematic structure of a memory cell included in the EEPROM having this structure. The EEPROM shown in FIG. 45 can secure a sufficiently large capacitance between the charge storage layer and the control gate with a small substrate occupation area. The drain diffusion layer 19 connected to the bit line of each memory cell is formed on the upper surface of the island-like semiconductor layer, and is electrically completely insulated by the groove. Further, the element isolation region can be reduced, and the memory cell size is reduced. Therefore, it is possible to obtain a large capacity EEPROM in which memory cells having excellent writing and erasing efficiency are integrated.

  Writing and erasing into the memory cell having the above-described structure can be realized by applying the following voltage to each part, for example. First, in writing, the drain potential Vd is 6V, the control gate potential Vcg is 12V, and the source potential Vs is 0V. With these voltages, channel hot electrons generated in the channel region near the drain diffusion layer 19 are injected into the floating gate 15 via the tunnel oxide film 14. In erasing, Vd is set to Floating, Vcg is set to −12V, and Vs is set to 6V. By these voltages, electrons are extracted from the floating gate 15 to the source diffusion layer 18 by the FN current.

Furthermore, an EEPROM composed of memory cells using the side walls of the island-like semiconductor layer has the following advantages compared to an EEPROM composed of planar memory cells. First, it is possible to increase the gate length by increasing the island-shaped semiconductor layer 11. For this reason, the so-called short channel effect can be suppressed without increasing the area occupied by the memory cell. Second, since the region surrounding the periphery of the island-shaped semiconductor layer 11 is a channel region, a large gate width can be secured within a small occupied area.
Japanese Unexamined Patent Publication No. Hei 8-148585 Howard Pein et al. IEEE Electron Device Letters, Vol. 14, no. 8, pp415-pp. 417 1993

  As described above, an EEPROM composed of memory cells using the side walls of the island-shaped semiconductor layer has superior write / erase efficiency and forms a smaller area memory cell than an EEPROM composed of planar memory cells. can do.

  However, in an EEPROM using channel hot electrons for writing, if the injection efficiency of channel hot electrons into the floating gate is poor, the writing speed becomes very slow even if the capacitance between the charge storage layer and the control gate is large. . The channel hot electron traveling direction vector is a direction of an electric field due to a voltage applied between the source diffusion layer and the drain diffusion layer, that is, a linear direction from the source diffusion layer to the drain diffusion layer. In a memory cell having a conventional structure, the floating gate into which channel hot electrons are to be injected is in a direction parallel to the floating gate, and does not exist in the channel hot electron traveling direction. For this reason, the injection efficiency of channel hot electrons into the floating gate is poor, and the writing speed is slow.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide an EEPROM in which writing is fast and the area occupied by the memory cell is small, and a manufacturing method thereof.

  In the present invention, an island-shaped semiconductor layer having an inclined portion or at least one step portion is formed on a semiconductor substrate, and the island-shaped semiconductor layer is formed on at least a part of a drain diffusion layer formed on the top and a bottom portion thereof. A source diffusion layer formed; a charge storage layer formed on a channel region of a sidewall sandwiched between the drain diffusion layer and the source diffusion layer through a gate insulating film; a control gate formed on the charge storage layer; When electrons are injected into the charge storage layer, the electrons can easily be injected into the charge storage layer by colliding with the wall of the electrons moving in the channel region by the electric field from the source diffusion layer to the drain diffusion layer. Accordingly, there is provided a semiconductor memory device characterized in that the stepped portion or the inclined portion is inclined.

  The present invention also provides an island-shaped semiconductor layer formed on a semiconductor substrate, a drain diffusion layer formed on the top of the island-shaped semiconductor layer, and a source formed on at least a part of the bottom of the island-shaped semiconductor layer. Charge accumulation formed via a gate insulating film on a diffusion layer and a channel region which is at least a part of the sidewall surrounding the island-shaped semiconductor layer and sandwiched between the drain diffusion layer and the source diffusion layer There is provided a semiconductor memory device including a layer, a control gate formed on the charge storage layer, and a diffusion layer disposed in a channel region having a conductivity type opposite to that of the drain diffusion layer and in contact with the drain diffusion layer.

  In the semiconductor memory device of the present invention, when electrons are injected into the charge storage layer, the electrons are injected into the charge storage layer by collision of the electrons moving in the channel region with the electric field from the source diffusion layer to the drain diffusion layer on the wall surface. Therefore, channel hot electrons generated near the drain of the channel region at the time of writing are efficiently injected into the floating gate. Therefore, it is possible to increase the writing speed and voltage.

  In addition, since the semiconductor memory device of the present invention includes the diffusion layer that is opposite in conductivity type to the drain diffusion layer and is disposed in the channel region in contact with the drain diffusion layer, the diffusion layer having a higher impurity concentration than the other channel regions The generation efficiency of channel hot electrons in the substrate increases, and the efficiency of channel hot electron injection into the floating gate improves. Therefore, it is possible to increase the writing speed and voltage.

  In the semiconductor memory device of the present invention, an island-like semiconductor layer having an inclined portion or at least one step portion is formed on a semiconductor substrate, and the island-like semiconductor layer includes a drain diffusion layer formed on the upper portion thereof and a bottom portion thereof. A source diffusion layer formed at least in part, a charge storage layer formed via a gate insulating film on a channel region on a sidewall sandwiched between the drain diffusion layer and the source diffusion layer, and formed on the charge storage layer A control gate, and when the electrons are injected into the charge storage layer, the electrons are injected into the charge storage layer by collision with the wall of the electrons moving in the channel region by the electric field from the source diffusion layer to the drain diffusion layer. The step of the stepped portion or the inclination of the inclined portion is configured to facilitate the above.

  Here, the source diffusion layer formed on at least a part of the bottom of the island-shaped semiconductor layer is formed over the entire bottom of the island-shaped semiconductor layer so as to electrically separate the substrate and the island-shaped semiconductor layer. However, for example, a structure in which the sidewall of the island-shaped semiconductor layer is formed only in the vicinity of the semiconductor substrate and not formed on the bottom surface inside the island-shaped semiconductor layer may be employed. The stepped portion is a portion where the island-shaped semiconductor layer is formed such that the peripheral length of the cross-section parallel to the substrate of the island-shaped semiconductor layer is abruptly different from the surface separated from the substrate surface by a predetermined distance. . The inclined portion refers to a portion where the island-shaped semiconductor layer is formed so that the peripheral length of the cross section of the island-shaped semiconductor layer gradually changes within a certain distance from the substrate surface.

The stepped portion or the inclined portion may be configured so that the diameter of the stepped portion or the inclined portion decreases from the bottom portion to the upper direction.
Alternatively, the semiconductor memory device of the present invention includes an island-shaped semiconductor layer formed on a semiconductor substrate, a drain diffusion layer formed on the top of the island-shaped semiconductor layer, and at least a part of the bottom of the island-shaped semiconductor layer. Formed via the gate insulating film on the formed source diffusion layer and the channel region which is at least part of the region surrounding the island-shaped semiconductor layer and sandwiched between the drain diffusion layer and the source diffusion layer A charge storage layer, a control gate formed on the charge storage layer, and a diffusion layer disposed in a channel region having a conductivity type opposite to that of the drain diffusion layer and in contact with the drain diffusion layer.

  The source diffusion layer may be formed over the entire bottom portion of the island-shaped semiconductor layer, whereby the semiconductor substrate and the island-shaped semiconductor layer may be electrically separated. In this way, since the island-shaped semiconductor is electrically separated from the substrate, a potential effect is generated by the current flowing through the substrate, and the back bias effect in which the threshold value of the memory cell fluctuates due to this effect is suppressed.

The charge storage layer may be made of a floating gate using polycrystalline silicon, or may be made of a nitride film-oxide film-nitride film or nanocrystal silicon.
Further, the control gate may be made of metal. If metal is used for the control gate, the resistance of the word line when the memory cell array is formed can be reduced, and thereby wiring delay can be suppressed. Further, the threshold voltage can be controlled by using metals having various work functions.

Further, the stepped portion or inclined portion formed in the channel region is located at a position where the distance from the stepped portion or inclined portion to the drain diffusion layer side is smaller than the distance from the stepped portion or inclined portion to the source diffusion layer side. May be arranged. In this way, more of the channel hot electrons generated by acceleration by the electric field in the channel region are generated on the drain diffusion layer side of the stepped portion or the inclined portion and are guided to the stepped portion or the inclined portion. The injection efficiency can be further improved.
The diffusion layer having a conductivity type opposite to that of the drain diffusion layer and disposed in the channel region in contact with the drain diffusion layer may be shorter than half the height of the island-shaped semiconductor layer. Most of the channel hot electrons generated by acceleration to the drain diffusion layer side by the electric field of the channel region are generated on the drain diffusion layer side in the channel region. Therefore, with the above structure, the channel region has the source diffusion layer side. Can be formed in a low-concentration diffusion layer where a channel is likely to be formed, and the drain diffusion layer can be formed in a high-concentration diffusion layer with a high generation rate of hot electrons. Can be realized.
The portable electronic device of the present invention includes the semiconductor memory device.

  From another point of view, the present invention is a method of manufacturing a semiconductor memory device including an island-shaped semiconductor layer formed on a substrate and having a stepped portion on a side wall thereof, wherein the side wall is formed on the side wall of the island-shaped semiconductor layer. Manufacturing method including at least a sidewall forming step, and a further dug down step in which the substrate surface is further dug using the side wall as a mask, and a new side wall having a step portion with the already formed side wall is formed on the island-like semiconductor layer. I will provide a.

  Since the method of manufacturing the semiconductor memory device according to the present invention includes a dug-down process in which the substrate surface is further dug using the side wall as a mask, and a new side wall having a step portion with the already formed side wall is formed in the island-like semiconductor layer. A semiconductor memory device having at least one step on the side wall in the direction from the source diffusion layer to the drain diffusion layer can be manufactured, and channel hot electrons generated near the drain of the channel region at the time of writing are efficiently generated in the floating gate. A semiconductor memory device to be injected into the semiconductor device is obtained. Therefore, the semiconductor memory device manufactured by the manufacturing method of the present invention has a high writing speed, and the driving voltage at the time of writing can be lowered.

  Furthermore, in the manufacturing method of the present invention, the substrate surface is selectively dug down to a predetermined depth to form the uppermost side wall of the island-shaped semiconductor layer, and after the step, the side wall of the island-shaped semiconductor layer is 1 A step of forming the gate insulating film on the side wall of the island-like semiconductor layer; A step of forming a charge storage layer thereon, a step of forming an interlayer insulating film on the charge storage layer, a step of forming a control gate on the interlayer insulating film, and an uppermost portion of the island-like semiconductor layer and the substrate dug down And a step of diffusing impurities on the surface to form a drain diffusion layer and a source diffusion layer, respectively. As a result, it is possible to manufacture a semiconductor memory device that has a high speed as described above and can reduce the drive voltage at the time of writing.

  Alternatively, the present invention relates to a method of manufacturing a semiconductor memory device including a diffusion layer adjacent to a drain diffusion layer disposed on the uppermost part of an island-shaped semiconductor layer formed on a substrate and having a diffusion layer having a conductivity type opposite to that of the drain diffusion layer. Depositing a film around the sidewall of the island-shaped semiconductor layer, and depositing so that the drain diffusion layer formed on the top of the island-shaped semiconductor layer and the sidewall adjacent to the drain diffusion layer are exposed. And a step of injecting impurities into the side wall adjacent to the drain diffusion layer and the drain diffusion layer to form a diffusion layer having a conductivity type opposite to that of the drain diffusion layer adjacent to the drain diffusion layer. Provided is a manufacturing method including at least a reverse conductivity type diffusion layer forming step.

Since the semiconductor memory device manufacturing method according to the present invention includes the reverse conductivity type diffusion layer forming step, the semiconductor memory device including the source diffusion layer adjacent to the drain diffusion layer and having the opposite conductivity type to the drain diffusion layer is provided. A semiconductor memory device that can be manufactured, has high channel hot electron generation efficiency in the diffusion layer having a higher impurity concentration than other channel regions, and has high injection efficiency of the channel hot electrons into the floating gate. Therefore, the semiconductor memory device manufactured by the manufacturing method of the present invention has a high writing speed, and the driving voltage at the time of writing can be lowered.
Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a schematic sectional view showing one embodiment of a memory cell according to the semiconductor memory device of the present invention. In this embodiment, an n-type memory cell using a p-type substrate is shown.
In this embodiment, an island-shaped semiconductor layer 110 is formed on a p-type silicon substrate 100, and at least a part of the side surface of the island-shaped semiconductor layer 110 is an active region surface, and at least a part of the active region surface is formed. For example, a tunnel oxide film 200 formed by thermal oxidation is formed. Further, a floating gate 300 made of, for example, polycrystalline silicon is disposed so as to cover at least a part of the gate oxide film 200. Further, a control gate 400 made of, for example, polycrystalline silicon is disposed through an interlayer insulating film 450 formed so as to cover at least a part of the floating gate 300.

  The active region surface on the side surface of the island-shaped semiconductor layer 110 has a step portion at least at a part thereof, the source diffusion layer 500 made of an n-type diffusion layer on the upper surface of the island-shaped semiconductor layer 110, and n on the lower surface. A drain diffusion layer 600 made of a type diffusion layer is provided to constitute a memory cell having a three-dimensional structure.

In the above structure, there is a floating gate in the traveling direction due to the electric field of channel hot electrons generated near the drain of the channel region at the time of writing. Therefore, the efficiency with which channel hot electrons are injected into the floating gate is higher than that in the conventional structure in which the stepped portion is not formed in the island-shaped semiconductor layer 110. High writing efficiency contributes to high-speed writing and low voltage.
For example, a voltage is applied to each part of the memory cell so that the drain potential Vd is 6 V, the control gate potential Vcg is 12 V, and the source potential Vs is 0 V. Thereby, channel hot electrons generated near the drain of the channel region of the island-shaped semiconductor layer 110 have a traveling direction vector from the source diffusion layer 500 to the drain diffusion layer 600. Then, channel hot electrons are injected toward the floating gate formed in the traveling direction.

  Note that the stepped portion formed in the island-shaped semiconductor layer 110 is not necessarily horizontal to the surface of the semiconductor substrate 100 as shown in FIG. 1. For example, as shown in FIGS. 2 and 3, the stepped portion is formed on the surface of the semiconductor substrate 100. You may have a certain angle from a horizontal surface. Even with such a structure, an improvement in the efficiency of channel hot electron injection into the floating gate, which is an object of the present invention, is expected. Further, it is not always necessary to form the stepped portion in the island-shaped semiconductor layer 110, and a structure having an inclination so that the top portion of the island-shaped semiconductor layer becomes small as shown in FIG. Even with such a structure, improvement in the efficiency of channel hot electron injection into the floating gate is expected.

  The present invention is not limited to a flash memory using a floating gate made of polycrystalline silicon as in this embodiment. For example, as shown in FIG. 5, the charge storage layer may be a so-called MONOS type memory composed of an oxide film-nitride film-oxide film. Alternatively, as shown in FIG. 6, the present invention can also be applied to a memory cell using an insulating film containing at least one nanocrystal silicon as a charge storage layer. In the case of a structure using an insulating film containing nanocrystals as a charge storage layer, the distribution of the nanocrystalline silicon in the insulating film is not limited as long as a desired memory cell function can be obtained. It is desirable that the is distributed almost uniformly in the insulating film.

  FIG. 7 is a cross-sectional view illustrating an example of a memory cell in the case where the control gate is formed of the metal 420. Here, as a material of the control gate 400, for example, a metal containing an element such as aluminum, tungsten, or copper can be used. By using a metal for the control gate, the resistance of the word line when the memory cell array is formed is reduced, which makes it possible to suppress wiring delay. In addition, the threshold voltage can be controlled by using metals having various work functions.

  In this embodiment, the island-shaped semiconductor layer 110 is formed on the semiconductor substrate. However, the island-shaped semiconductor layer 110 is formed by a p-type impurity diffusion layer or a p-type silicon substrate formed in the n-type semiconductor substrate. It may be on a p-type impurity diffusion layer further formed in an n-type impurity diffusion layer formed therein. Also, the conductivity type of each impurity diffusion layer may be the opposite conductivity type as described above.

In the memory cell shown in this embodiment, the data stored in the memory cell may be multivalued by setting, for example, three or more threshold distributions.
As shown in FIGS. 1 to 7, the stepped portion formed in the island-shaped semiconductor layer is preferably formed in the upper portion of the island-shaped semiconductor layer. This is because most of the hot electrons injected into the floating gate are generated near the drain diffusion layer in the channel region.

  In the semiconductor memory device shown in this embodiment, the charge storage layer may not cover the entire channel region of the island-shaped semiconductor layer. For example, as shown in FIG. 8, it may be formed only in a part of the periphery of the stepped portion formed in the island-shaped semiconductor layer. Note that the semiconductor substrate 100 and the island-shaped semiconductor layer 110 are more preferably electrically separated. By being electrically separated, the semiconductor layer becomes electrically floating, and the substrate bias effect can be suppressed.

FIG. 9 is a schematic sectional view showing different embodiments of the memory cell according to the semiconductor memory device of the present invention. In this embodiment, an n-type memory cell using a p-type substrate is shown.
In this embodiment, an island-shaped semiconductor layer 110 is formed on a p-type silicon substrate 100, and at least a part of the side surface of the island-shaped semiconductor layer 110 is an active region surface, and is formed on at least a part of the active region surface. For example, a tunnel oxide film 200 formed by thermal oxidation is formed. Further, a floating gate 300 made of, for example, polycrystalline silicon is disposed so as to cover at least a part of the gate oxide film 200. Further, a control gate 400 made of, for example, polycrystalline silicon is disposed through an interlayer insulating film 450 formed so as to cover at least a part of the floating gate 300.

Further, a source diffusion layer 500 made of an n-type diffusion layer is provided on the upper surface of the island-like semiconductor layer 110, and a drain diffusion layer 600 made of an n-type diffusion layer is provided on the lower surface. Further, a diffusion layer 610 having a conductivity type opposite to that of the drain diffusion layer, that is, a p-type diffusion layer 610 is formed in the vicinity of the drain diffusion layer 600 in the channel region, thereby forming a three-dimensional memory cell.
With the structure in which the diffusion layer 610 is disposed as described above, the electric field in the vicinity of the drain of the channel region is increased, and the generation efficiency of channel hot electrons generated near the drain of the channel region is increased.

  For example, a voltage is applied to each part of the memory cell so that the drain potential Vd is 6 V, the control gate potential Vcg is 12 V, and the source potential Vs is 0 V. At this time, a p-type diffusion layer is disposed in the vicinity of the drain of the channel region of the island-shaped semiconductor layer 110, and since the impurity concentration is higher than that of the other channel regions, the generation efficiency of channel hot electrons increases, Channel hot electron injection efficiency is improved.

In FIG. 9, the diffusion layer 610 is formed only on the outer peripheral portion of the island-shaped semiconductor layer 110, but is not necessarily formed only on the outer peripheral portion of the island-shaped semiconductor layer 110. For example, the structure shown in FIG. 10 is also possible.
Although the present embodiment describes a flash memory using a floating gate made of polycrystalline silicon, the present invention is not limited to this. For example, as shown in FIG. 11, the charge storage layer is an oxide film. The present invention can also be applied to a so-called MONOS type memory composed of a nitride film-oxide film and a memory cell composed of an insulating film containing at least one nanocrystal silicon as shown in FIG. In the case of a structure using an insulating film containing nanocrystals in the charge storage layer, the distribution of the nanocrystalline silicon in the insulating film is not limited as long as a desired memory cell function can be obtained. It is desirable that the is distributed almost uniformly in the insulating film.

  FIG. 13 shows an example of a memory cell in which the control gate is formed of the metal 420. Here, as a material of the control gate 400, for example, a metal containing an element such as aluminum, tungsten, or copper can be used. By using a metal for the control gate, the resistance of the word line when the memory cell array is formed is reduced, which makes it possible to suppress wiring delay. In addition, the threshold voltage can be controlled by using metals having various work functions.

In this embodiment, the island-shaped semiconductor layer 110 is formed on the semiconductor substrate. However, the island-shaped semiconductor layer 110 is formed by a p-type impurity diffusion layer or a p-type silicon substrate formed in the n-type semiconductor substrate. It may be on a p-type impurity diffusion layer further formed in an n-type impurity diffusion layer formed therein. Also, the conductivity type of each impurity diffusion layer may be the opposite conductivity type as described above.
In the memory cell shown in this embodiment, the data stored in the memory cell may be multivalued by setting, for example, three or more threshold distributions.

As shown in FIGS. 9 to 13, the diffusion layer having a conductivity type opposite to the drain diffusion layer, which is disposed near the drain of the island-shaped semiconductor layer 110, is formed on the island-shaped semiconductor layer. preferable. This is because most of the hot electrons injected into the floating gate are generated near the drain diffusion layer in the channel region.
In the semiconductor memory device shown in this embodiment, the charge storage layer does not have to cover the entire channel region of the island-shaped semiconductor layer, and is formed on the island-shaped semiconductor layer, for example, as shown in FIG. The drain diffusion layer in the vicinity of the drain may be formed only in a part of the periphery of the diffusion layer of the reverse conductivity type.

  In this embodiment, as in the first embodiment, it is more preferable that the semiconductor substrate and the semiconductor layer are electrically separated. By being electrically separated, the semiconductor layer becomes floating and the substrate bias effect can be suppressed.

  In this embodiment, a method for manufacturing the memory cell having the three-dimensional structure described in Embodiment 1 will be described. In the memory cell of this embodiment, an island-shaped semiconductor layer is formed on a semiconductor substrate, and at least a part of the side surface of the island-shaped semiconductor layer is an active region surface, and a step portion is formed on at least a part of the active region surface. Furthermore, a tunnel oxide film formed by, for example, thermal oxidation is formed on at least a part of the active region surface. Further, a floating gate made of, for example, polycrystalline silicon is disposed so as to cover at least a part of the gate oxide film. Further, a control gate made of, for example, polycrystalline silicon is disposed through an interlayer insulating film formed so as to cover at least a part of the floating gate. Source and drain regions made of an n-type diffusion layer are provided on the upper and lower surfaces of the island-like semiconductor layer. 15 to 30 are schematic process cross-sectional views showing a method for manufacturing a memory cell having a three-dimensional structure in this embodiment.

  First, a first insulating film 701 made of, for example, a silicon oxide film and serving as a mask layer is deposited to a thickness of 200 to 2000 nm on the surface of the semiconductor substrate 100 made of, for example, a p-type silicon substrate. Then, using the resist R1 patterned by a known photolithography technique as a mask, the first insulating film 701 is etched by reactive ion etching (FIG. 15).

Here, the material of the first insulating film 701 may be any material that is not etched during the reactive etching of the p-type silicon substrate 100 or has a slower etching rate than silicon, and is not limited to the silicon oxide film. The first insulating film 701 may be, for example, a silicon nitride film, a conductive film, or a laminated film made of two or more materials.
Then, using the first insulating film 701 as a mask, the semiconductor substrate 100 is etched by a depth of 1 to 5000 nm by reactive ion etching to dig up the surface. Thereafter, the exposed portion of the semiconductor substrate 100 is thermally oxidized to form a second insulating film 702 made of, for example, a silicon oxide film with a thickness of 5 nm to 100 nm (FIG. 16). Note that the method for forming the second insulating film 702 is not limited to the above-described method, and the second insulating film 702 may be formed by deposition by CVD, for example. By this step, the second insulating film 702 is formed on the horizontal surface of the semiconductor substrate 100 and the side wall of the portion processed into an island shape.

  Next, a third insulating film 801 made of, for example, a silicon nitride film is deposited on the first insulating film 701 and the second insulating film 702 to a thickness of 1 to 1000 nm. Thereafter, the third insulating film 801 is etched by anisotropic etching. Accordingly, the third insulating film 801 is arranged in a sidewall shape on the second insulating film 702 formed on the sidewall portion of the semiconductor substrate 100 processed into an island shape and the sidewall of the first insulating film 701 ( FIG. 17).

Subsequently, using the third insulating film 801 as a mask, the second insulating film 702 is removed by etching by reactive ion etching. Then, the silicon substrate 100 exposed in the portion where the third insulating film 801 is not disposed is etched by a depth of 50 to 5000 nm and further dug down to process the p-type silicon substrate 100 into an island shape having a stepped portion. (FIG. 18).
Thereafter, for example, the exposed portion of the silicon substrate 100 is thermally oxidized to form a fourth insulating film 703 made of, for example, a silicon oxide film with a thickness of 3 nm to 100 nm (FIG. 19). Note that the formation method of the fourth insulating film 703 is not limited to the above method, and may be formed by deposition, for example. Further, the material of the film is not limited to the silicon oxide film, and may be a silicon nitride film, for example. Further, the fourth insulating film 703 is not necessarily formed.

  Subsequently, the first insulating film 701, the second insulating film 702, the third insulating film 801, and the fourth insulating film 703 formed on the semiconductor substrate are removed by isotropic etching, for example (FIG. 20). Then, the island-shaped semiconductor layer 110 is formed. Then, the surface of the island-shaped semiconductor layer 110 is oxidized, and a fifth insulating film 710 made of, for example, a silicon oxide film is formed to a thickness of 10 nm to 100 nm (FIG. 21). At this time, in the case where the diameter of the island-shaped semiconductor layer 110 is formed with the minimum processing size, the diameter of the island-shaped semiconductor layer 110 is reduced by etching after forming the fifth insulating film 710. Can do. That is, it is formed below the minimum processing dimension. Note that the fifth insulating film 710 is not necessarily formed.

Next, after removing the fifth insulating film 710 by, for example, isotropic etching, a sixth insulating film 711 made of, for example, a silicon oxide film is formed to a thickness of 3 to 100 nm by, for example, thermal oxidation. Note that the method of forming the sixth insulating film 711 is not limited to the above-described thermal oxidation, and may be, for example, deposition of a silicon oxide film by CVD.
Subsequently, a seventh insulating film 810 made of, for example, a silicon vagina film is deposited to a thickness of, for example, 5 to 1000 nm (FIG. 22), and then the seventh insulating film 810 and the first insulating film are formed by, for example, reactive ion etching. 6 insulating film 711 is anisotropically etched. Thus, the seventh insulating film 810 and the sixth insulating film 711 are processed into a sidewall shape on the sidewall of the island-shaped semiconductor layer 110 (FIG. 23).

Thereafter, impurities are introduced into the top and bottom of the island-like semiconductor layer 110 having a stepped portion to form an n-type impurity diffusion layer, and the source diffusion layer 500 and the drain diffusion layer 600 are disposed. The n-type impurity diffusion layer is formed by, for example, arsenic or phosphorus at 1 × 10 ¹³ to 1 × 10 ¹⁷ / cm ^{2 with} an implantation energy of 5 to 100 keV from a direction inclined by about 0 to 7 ° by an ion implantation method. It can be formed by introducing only a certain amount of dose.

Subsequently, after the element isolation film 250 is formed by, for example, thermal oxidation, the sixth insulating film 711 and the seventh insulating film 810 are selectively removed by, for example, isotropic etching (FIG. 24). Then, channel ion implantation is performed on the sidewall of the island-shaped semiconductor layer 110 using oblique ion implantation as necessary. For example, boron is implanted at a dose of about 1 × 10 ¹¹ to 1 × 10 ¹³ / cm ² with an implantation energy of 5 to 100 keV from a direction inclined by about 5 to 45 °. In channel ion implantation, it is preferable to implant the island-shaped semiconductor layer 110 from multiple directions. This is because the surface impurity concentration of the sidewalls of the island-like semiconductor layer 110 is made more uniform. Alternatively, instead of the channel ion implantation method described above, an oxide film containing boron may be deposited by a CVD method, and boron diffusion from the deposited oxide film may be used. Note that the order of steps for introducing impurities from the surface of the island-shaped semiconductor layer 110 is not limited to the above-described order, and the introduction may be completed before the island-shaped semiconductor layer 110 is formed. Further, the method of introducing impurities from the surface of the island-shaped semiconductor layer 110 is not limited to the above method, and the means is not limited as long as the impurity concentration distribution is equivalent.

  Subsequently, an eighth insulating film 200 made of, for example, a silicon oxide film is formed around the island-shaped semiconductor layer 110 by using, for example, a thermal oxidation method (FIG. 25). The eighth insulating film 200 is a tunnel oxide film having a thickness of about 10 nm, for example. The eighth insulating film 200 is not limited to a thermal oxide film, and may be a CVD oxide film or an oxynitride film, for example.

Subsequently, after depositing a first conductive film 300 made of, for example, a polycrystalline silicon film to a thickness of about 20 nm to 200 nm (FIG. 26), impurities are introduced into the first conductive film 300 by, eg, ion implantation. Do. For example, arsenic or phosphorus is implanted at an implantation energy of 5 to 100 keV and a dose of 1 × 10 ¹² to 1 × 10 ¹⁷ / cm ² . Next, the first conductive film 300 is etched by, for example, reactive ion etching so that the first conductive film 300 is disposed only on the side wall portion of the island-shaped semiconductor layer 110 (FIG. 27). The first conductive film 300 thus formed becomes a charge storage layer. Note that the thickness of the first conductive film 300 is preferably larger than the thickness of the third insulating film 801. Further, the order of the steps for introducing the impurities into the first conductive film 300 is not limited to immediately after the polycrystalline silicon film is deposited as described above. For example, the first conductive film 300 is made different by reactive ion etching. It does not matter even after anisotropic etching. In addition, the method for introducing impurities into the first conductive film 300 is not limited to the above-described ion implantation method, and is not particularly limited as long as a desired impurity concentration distribution can be obtained. For example, an oxide film containing arsenic or phosphorus may be deposited by a CVD method, and diffusion of arsenic or phosphorus from the oxide film may be used. Alternatively, in-situ arsenic or phosphorus doping may be performed when the first conductive film is deposited. The method is not particularly limited as long as a desired impurity concentration distribution is obtained.

Next, an interlayer insulating film 450 is formed on the surface of the first conductive film 300. The interlayer insulating film 450 is preferably a so-called ONO film, for example. Specifically, a silicon oxide film having a thickness of 5 to 10 nm is formed on the surface of the first conductive film 300 by a thermal oxidation method, and a silicon nitride film having a thickness of 5 to 10 nm is further deposited by a CVD method. Further, a silicon oxide film having a thickness of 5 to 10 nm is deposited thereon. Subsequently, a second conductive film 400 made of, for example, a polycrystalline silicon film is deposited to a thickness of 15 nm to 150 nm (FIG. 28). The second conductive film 400 thus formed serves as a control gate. Subsequently, impurities are introduced into the second conductive film capacitor 400 by, for example, an ion implantation method. For example, arsenic or phosphorus is implanted at a dose of 1 × 10 ¹² to 1 × 10 ¹⁷ / cm ² with an implantation energy of 5 to 100 keV.

  Next, a ninth insulating film 712 made of, for example, a silicon oxide film is deposited. Then, using the resist R2 patterned only as a word line by a known photolithography technique as a mask, the ninth insulating film 712 made of, for example, a silicon oxide film is etched by, eg, reactive ion etching (FIG. 29). . Note that the etching of the ninth insulating film 712 is not limited to reactive ion etching, and may be isotropic etching, for example. As long as a desired shape is obtained, the etching method is not particularly limited. The material of the ninth insulating film 712 is not limited to a silicon oxide film, and may be a silicon nitride film, a conductive film, or a laminated film made of two or more materials, for example. Any material may be used as long as it is not etched at the time of etching the second conductive film 400 or has a slower etching rate than that of polycrystalline silicon.

  Subsequently, the second conductive film 400 is etched by, for example, reactive ion etching using the ninth insulating film 712 as a hard mask. Note that an etching method for etching the second conductive film 400 is not limited to the above-described reactive ion etching, and for example, CDE (Chemical Dry Etching) may be used. The method is not particularly limited as long as a desired shape is obtained. In this embodiment, the second conductive film 400 is etched using the ninth insulating film 712 as a hard mask. However, the ninth conductive film 712 is not deposited and the second conductive film is used using the resist R2 as a mask. The film 400 may be etched.

  Subsequently, the ninth insulating film 712 used as a hard mask when the second conductive film 400 is etched is removed by, for example, isotropic etching (FIG. 30). Note that the order of introducing impurities into the second conductive film 400 is not limited to immediately after the second conductive film 400 is deposited as described above. For example, the first conductive film 400 is etched after the second conductive film 400 is etched. It may be after etching the insulating film 712 of No. 9. The order of the steps is not particularly limited as long as a desired impurity concentration distribution is obtained. The method for introducing impurities into the second conductive film 400 is not limited to the above-described ion implantation method. For example, an oxide film containing arsenic or phosphorus is deposited by CVD, and arsenic or phosphorus is diffused from the oxide film. May be used. Alternatively, in-situ arsenic or phosphorus doping may be performed when the second conductive film 400 is deposited. If a desired impurity concentration distribution can be obtained, the method for introducing impurities is not particularly limited.

  After that, an interlayer insulating film 910 (for example, shown in FIG. 1) is deposited, and after etching back by, for example, isotropic etching, contacts and metal wiring are formed using a known technique. Thus, a semiconductor memory device having a memory function is realized by the charge state accumulated in the first conductive film (functioning as a floating gate or a charge accumulation layer).

  In this embodiment, in order to form the island-shaped semiconductor layer 110 in a step shape, the third insulating film 801 is formed in a sidewall shape, and the sidewall is used as a mask in the reactive ion etching of the semiconductor substrate 100. However, the step portion can be formed by a method other than the above-described method. For example, an insulating film or a conductive film is embedded so that only the tip of the island-shaped semiconductor layer 100 is exposed, and the tip of the island-shaped semiconductor layer 110 is formed by performing, for example, thermal oxidation or isotropic etching on the exposed portion. The step portion of the island-shaped semiconductor layer 110 may be formed by narrowing the portion.

  In this embodiment, an island-shaped semiconductor layer having a stepped portion at least in part is formed on the surface of the semiconductor substrate, and a floating gate and a control gate are disposed on the side surface of the island-shaped semiconductor layer. A method of manufacturing a memory cell having a three-dimensional structure in which source and drain regions are provided on the upper and lower surfaces, respectively, has been described.

  In this embodiment, a method for manufacturing the memory cell having the three-dimensional structure described in the second embodiment will be described. In the memory cell of this embodiment, an island-shaped semiconductor layer is formed on a semiconductor substrate, and at least a part of the side surface of the island-shaped semiconductor layer is an active region surface, and at least a part of the active region surface is, for example, A tunnel oxide film formed by thermal oxidation is formed, and a floating gate is formed, for example, of polycrystalline silicon so as to cover at least a part of the gate oxide film. Further, a control gate made of, for example, polycrystalline silicon is disposed through an interlayer insulating film formed so as to cover at least a part of the floating gate, and n is formed on the upper and lower surfaces of the island-shaped semiconductor layer. A memory cell having a three-dimensional structure in which a source / drain region composed of a type diffusion layer is provided and a diffusion layer having a conductivity type opposite to the drain diffusion layer is formed in the vicinity of the drain diffusion layer in the channel region.

31 to 43 shown below are schematic process cross-sectional views showing a method of manufacturing a memory cell having a three-dimensional structure different from the above in this embodiment.
First, a first insulating film 751 made of, for example, a silicon oxide film and serving as a mask layer is deposited to a thickness of 200 to 2000 nm on the surface of the semiconductor substrate 100 made of, for example, a p-type silicon substrate. Then, using the resist R1 patterned by a known photolithography technique as a mask, the first insulating film 751 is etched by reactive ion etching (FIG. 31).

Here, the material of the first insulating film 751 may be any material that is not etched during the reactive etching of the p-type silicon substrate 100 or has a slower etching rate than silicon, and is not limited to the silicon oxide film. For example, a silicon nitride film, a conductive film, or a laminated film made of two or more materials may be used.
Then, using the first insulating film 751 as a mask, the semiconductor substrate 100 is etched by a depth of 5 to 5000 nm by reactive ion etching to dig up the surface.

  Subsequently, the first insulating film 751 is removed by, for example, isotropic etching. Then, the surface of the island-shaped semiconductor layer 110 is oxidized, and a second insulating film 752 made of, for example, a silicon oxide film is formed to a thickness of 10 nm to 100 nm (FIG. 32). At this time, in the case where the diameter of the island-shaped semiconductor layer 110 is formed with the minimum processing size, the diameter of the island-shaped semiconductor layer 110 can be reduced by forming the second insulating film 752. That is, it is formed below the minimum processing dimension. Note that the second insulating film 752 is not necessarily formed.

  Next, after removing the second insulating film 752 by, for example, isotropic etching, a third insulating film 753 made of, for example, a silicon oxide film is formed to a thickness of 3 to 100 nm by, for example, thermal oxidation. Note that the method of forming the third insulating film 753 is not limited to the above-described thermal oxidation, and may be, for example, deposition of a silicon oxide film by CVD.

  Subsequently, a fourth insulating film 851 made of, for example, a silicon nitride film is deposited to a thickness of, for example, 5 to 1000 nm (FIG. 33), and then the third insulating film 753 and the fourth insulating film are formed by, for example, reactive ion etching. The insulating film 851 is anisotropically etched. Thus, the third insulating film 753 and the fourth insulating film 851 are processed into a sidewall shape on the sidewall of the island-shaped semiconductor layer 110 (FIG. 34).

Thereafter, impurities are introduced into the top and bottom of the island-like semiconductor layer 110 to form an n-type impurity diffusion layer, and the source diffusion layer 500 and the drain diffusion layer 600 are disposed. The n-type impurity diffusion layer is formed by, for example, using arsenic or phosphorus at 1 × 10 ¹³ to 1 × 10 ¹⁷ / cm ^{2 with} an implantation energy of 5 to 100 keV from a direction inclined by about 0 to 7 ° by an ion implantation method. It can be formed by introducing only a certain amount of dose.

Subsequently, after the element isolation film 250 is formed by, for example, thermal oxidation, the third insulating film 753 and the fourth insulating film 851 are selectively removed by, for example, isotropic etching (FIG. 35). Then, channel ion implantation is performed on the sidewall of the island-shaped semiconductor layer 110 using oblique ion implantation as necessary. For example, boron is implanted at a dose of about 1 × 10 ¹¹ to 1 × 10 ¹³ / cm ² with an implantation energy of 5 to 100 keV from a direction inclined by about 5 to 45 °. In channel ion implantation, it is preferable to implant the island-shaped semiconductor layer 110 from multiple directions. This is because the surface impurity concentration of the sidewalls of the island-like semiconductor layer 110 is made more uniform. Alternatively, instead of the channel ion implantation method described above, an oxide film containing boron may be deposited by a CVD method, and boron diffusion from the deposited oxide film may be used. Note that the order of steps for introducing impurities from the surface of the island-shaped semiconductor layer 110 is not limited to the above-described order, and the introduction may be completed before the island-shaped semiconductor layer 110 is formed. Further, the method of introducing impurities from the surface of the island-shaped semiconductor layer 110 is not limited to the above method, and the means is not limited as long as the impurity concentration distribution is equivalent.

  Next, for example, a fifth insulating film 754 made of, for example, a silicon oxide film is deposited to a thickness of, for example, 10 to 2000 nm, and thereafter, for example, isotropic etching is performed to expose the tip of the island-shaped semiconductor layer 110 ( FIG. 36). The means for exposing the tip of the island-shaped semiconductor layer is not limited to the above-described means, and for example, a resist etch back method may be used. The fifth insulating film 754 is not limited to a silicon oxide film, and may be a material that can be selectively removed as a mask for ion implantation for forming a diffusion layer of a reverse conductivity type near the drain. Good. For example, a silicon nitride film, a conductive film, or a laminated film made of two or more materials may be used.

Next, using the fifth insulating film 754 as a hard mask, a p-type diffusion layer is formed in the vicinity of the drain of the island-shaped semiconductor layer 110 using, for example, an oblique ion implantation method (FIG. 37). In the oblique ion implantation, for example, implantation is performed from a direction inclined by about 3 to 60 °. The conditions at this time are, for example, an implantation energy of 5 keV to 1 MeV and a dose amount of about 1 × 10 ¹¹ to 1 × 10 ¹⁵ / cm ^{2 of} boron.
Note that the ion implantation is preferably performed from multiple directions of the island-shaped semiconductor layer 110. This is because the impurity concentration on the sidewall of the island-shaped semiconductor layer 110 can be made uniform. Alternatively, instead of ion implantation, an oxide film containing boron may be deposited by a CVD method, and boron diffusion from the oxide film may be used. Note that the order of steps for introducing impurities from the surface of the island-shaped semiconductor layer 110 is not limited to the above-described steps, and the introduction may be completed before the island-shaped semiconductor layer 110 is formed. Further, the means for introducing impurities is not limited to the above, and it is sufficient that the impurity concentration distribution of the island-like semiconductor layer 110 is equal.

  Subsequently, a sixth insulating film 200 made of, for example, a silicon oxide film and having a thickness of about 10 nm is formed around the island-shaped semiconductor layer 110 by using, for example, a thermal oxidation method (FIG. 38). This sixth insulating film becomes a tunnel oxide film. Here, the method of forming the seventh insulating film is not limited to the thermal oxide film, but may be a CVD oxide film or an oxynitride film.

Subsequently, after depositing a first conductive film 300 made of, for example, a polycrystalline silicon film to a thickness of about 20 nm to 200 nm (FIG. 39), impurities are introduced into the first conductive film 300 by, eg, ion implantation. Do. For example, arsenic or phosphorus is implanted at an implantation energy of 5 to 100 keV and a dose of 1 × 10 ¹² to 1 × 10 ¹⁷ / cm ² . Next, the first conductive film 300 is etched by, for example, reactive ion etching so that the first conductive film 300 is disposed only on the sidewall portion of the island-shaped semiconductor layer 110 (FIG. 40). The first conductive film 300 thus formed becomes a charge storage layer. Note that the order of the steps for introducing impurities into the first conductive film 300 is not limited to immediately after the polycrystalline silicon film is deposited, but, for example, after the polycrystalline silicon 300 is anisotropically etched by reactive ion etching. It doesn't matter. Further, the method for introducing impurities into the first conductive film 300 is not limited to the above-described ion implantation method, and is not particularly limited as long as a desired impurity concentration distribution is obtained. For example, an oxide film containing arsenic or phosphorus may be deposited by a CVD method, and diffusion of arsenic or phosphorus from the oxide film may be used. Alternatively, in-situ arsenic or phosphorus doping may be performed when the first conductive film is deposited. The method is not particularly limited as long as a desired impurity concentration distribution is obtained.

Next, an interlayer insulating film 450 is formed on the surface of the first conductive film 300. The interlayer insulating film 450 is preferably a so-called ONO film, for example. Specifically, a silicon oxide film having a thickness of 5 to 10 nm is formed on the surface of the first conductive film 300 by a thermal oxidation method, and a silicon nitride film having a thickness of 5 to 10 nm is further deposited by a CVD method. A silicon oxide film having a thickness of 5 to 10 nm is deposited. Subsequently, a second conductive film 400 made of, for example, a polycrystalline silicon film is deposited to a thickness of 15 nm to 150 nm (FIG. 41). Subsequently, impurities are introduced into the polycrystalline silicon 400 by, for example, an ion implantation method. For example, arsenic or phosphorus is implanted at a dose of 1 × 10 ¹² to 1 × 10 ¹⁷ / cm ² with an implantation energy of 5 to 100 keV. The second conductive film 400 thus formed serves as a control gate. Here, the introduction of impurities into the polycrystalline silicon 400 is not limited to the ion implantation method. For example, an oxide film containing arsenic or phosphorus is deposited by the CVD method, and diffusion of arsenic or phosphorus from the oxide film is utilized. Alternatively, in-situ arsenic or phosphorus doping may be performed when the polycrystalline silicon film is deposited. If a desired impurity concentration distribution is obtained, the method for introducing impurities is not particularly limited.

  Next, a seventh insulating film 755 made of, for example, a silicon oxide film is deposited. Then, using the resist R2 patterned only as a word line by a known photolithography technique as a mask, the seventh insulating film 755 made of, for example, a silicon oxide film is etched by, eg, reactive ion etching (FIG. 42). . Note that the etching method for etching the silicon oxide film 755 serving as the seventh insulating film is not limited to reactive ion etching, and for example, isotropic etching may be used. The method is not particularly limited as long as a desired shape is obtained. The seventh insulating film 755 is not particularly limited as long as the seventh insulating film 755 is not etched when the second conductive film 400 is etched or the etching rate is lower than that of the second conductive film 400. For example, a silicon nitride film, a conductive film, or a laminated film made of two or more materials may be used.

  Subsequently, the seventh insulating film 755 used as a hard mask for etching the second conductive film 400 is removed by, for example, isotropic etching (FIG. 43). Note that the introduction of impurities into the second conductive film 400 is not limited to immediately after the second conductive film 400 is deposited as described above, and may be performed after the seventh insulating film 755 is etched, for example. The order of the steps is not particularly limited as long as a desired impurity concentration distribution is obtained.

  Thereafter, an interlayer insulating film 910 (for example, described in FIG. 9) is deposited, and after etching back by, for example, isotropic etching, contacts and metal wiring are formed using a known technique. Thus, a semiconductor memory device having a memory function is realized by the charge state stored in the first conductive film (functioning as a charge storage layer serving as a floating gate).

  In this embodiment, as described above, the island-shaped semiconductor layer is formed on the semiconductor substrate, the floating gate and the control gate are disposed on the side surface of the island-shaped semiconductor layer, and the source and drain are respectively formed on the upper surface and the lower surface of the island-shaped semiconductor layer. A method of manufacturing a memory cell having a three-dimensional structure in which a region is provided and a diffusion layer having a conductivity type opposite to that of the drain is provided near the drain of the channel region has been described.

An embodiment of the portable electronic device of the present invention will be described with reference to FIG. The semiconductor memory device or the semiconductor device described in the above embodiment can be used for a battery-driven portable electronic device, particularly a portable information terminal. Examples of portable electronic devices include portable information terminals, mobile phones, and game devices.
FIG. 44 shows an example of a mobile phone. The mobile phone incorporates the semiconductor device of the present invention.

By using the semiconductor device of the present invention for a portable electronic device, a circuit can be reduced in size and a device having a high writing speed can be obtained.
As shown in FIG. 44, a mobile phone 1000 includes a control circuit unit 1001, a man-machine interface unit 1008, an RF (radio frequency) circuit unit 1010, and an antenna unit 1011. In the control circuit unit 1001, there are a data memory unit 1004, a calculation unit 1002, a control unit 1003, a ROM 1005 and a RAM 1006. Each of the above parts is connected by a wiring 1007 (including a data bus, a power supply line, and the like).

  In the semiconductor device of the present invention, for example, various circuits other than the memory, for example, the arithmetic unit 1002 and the control unit 1003 described above can be mounted in the same semiconductor device. In addition, since the use efficiency of the chip area is better than that in which elements are arranged in a plane on the semiconductor surface, the capacity of the memory can be increased. Alternatively, if the memory capacity is the same, the chip area is small, and the semiconductor device can be downsized. Moreover, writing to the memory is performed at high speed. If this semiconductor device is used in the data memory unit 1004 or the like of the mobile phone 1000, the mobile phone 1000 can be downsized.

  In this embodiment, a data memory unit 1004, a calculation unit 1002, a control unit 1003, a ROM 1005, and a RAM 1006 in the control circuit unit 1001 are configured on a single chip using the semiconductor device of the present invention. Therefore, it can be expected to obtain a cost reduction effect by forming the control circuit portion 1001 including the data memory portion 1004, the ROM 1005, and the RAM 1006 on one chip.

It is typical sectional drawing which shows one Example of the memory cell based on the semiconductor memory device of this invention. Example 1 It is typical sectional drawing which shows the Example from which the memory cell based on the semiconductor memory device of this invention differs. Example 1 It is typical sectional drawing which shows the Example from which the memory cell based on the semiconductor memory device of this invention differs. Example 1 It is typical sectional drawing which shows the Example from which the memory cell based on the semiconductor memory device of this invention differs. Example 1 It is typical sectional drawing which shows the Example from which the memory cell based on the semiconductor memory device of this invention differs. Example 1 It is typical sectional drawing which shows the Example from which the memory cell based on the semiconductor memory device of this invention differs. Example 1 It is typical sectional drawing which shows the Example from which the memory cell based on the semiconductor memory device of this invention differs. Example 1 It is typical sectional drawing which shows the Example from which the memory cell based on the semiconductor memory device of this invention differs. Example 1 It is typical sectional drawing which shows the Example from which the memory cell based on the semiconductor memory device of this invention differs. (Example 2) It is typical sectional drawing which shows the Example from which the memory cell based on the semiconductor memory device of this invention differs. (Example 2) It is typical sectional drawing which shows the Example from which the memory cell based on the semiconductor memory device of this invention differs. (Example 2) It is typical sectional drawing which shows the Example from which the memory cell based on the semiconductor memory device of this invention differs. (Example 2) It is typical sectional drawing which shows the Example from which the memory cell based on the semiconductor memory device of this invention differs. (Example 2) It is typical sectional drawing which shows the Example from which the memory cell based on the semiconductor memory device of this invention differs. (Example 2) It is a schematic process sectional drawing which shows 1 process of the manufacturing method of the memory cell of the three-dimensional structure in one Example of this invention. Example 3 It is a general | schematic process sectional drawing which shows a different process of the manufacturing method of the memory cell of the three-dimensional structure in one Example of this invention. Example 3 It is a general | schematic process sectional drawing which shows a different process of the manufacturing method of the memory cell of the three-dimensional structure in one Example of this invention. Example 3 It is a general | schematic process sectional drawing which shows a different process of the manufacturing method of the memory cell of the three-dimensional structure in one Example of this invention. Example 3 It is a general | schematic process sectional drawing which shows a different process of the manufacturing method of the memory cell of the three-dimensional structure in one Example of this invention. Example 3 It is a general | schematic process sectional drawing which shows a different process of the manufacturing method of the memory cell of the three-dimensional structure in one Example of this invention. Example 3 It is a general | schematic process sectional drawing which shows a different process of the manufacturing method of the memory cell of the three-dimensional structure in one Example of this invention. Example 3 It is a general | schematic process sectional drawing which shows a different process of the manufacturing method of the memory cell of the three-dimensional structure in one Example of this invention. Example 3 It is a general | schematic process sectional drawing which shows a different process of the manufacturing method of the memory cell of the three-dimensional structure in one Example of this invention. Example 3 It is a general | schematic process sectional drawing which shows a different process of the manufacturing method of the memory cell of the three-dimensional structure in one Example of this invention. Example 3 It is a general | schematic process sectional drawing which shows a different process of the manufacturing method of the memory cell of the three-dimensional structure in one Example of this invention. Example 3 It is a general | schematic process sectional drawing which shows a different process of the manufacturing method of the memory cell of the three-dimensional structure in one Example of this invention. Example 3 It is a general | schematic process sectional drawing which shows a different process of the manufacturing method of the memory cell of the three-dimensional structure in one Example of this invention. Example 3 It is a general | schematic process sectional drawing which shows a different process of the manufacturing method of the memory cell of the three-dimensional structure in one Example of this invention. Example 3 It is a general | schematic process sectional drawing which shows a different process of the manufacturing method of the memory cell of the three-dimensional structure in one Example of this invention. Example 3 It is a general | schematic process sectional drawing which shows a different process of the manufacturing method of the memory cell of the three-dimensional structure in one Example of this invention. Example 3 It is a schematic process sectional drawing which shows the manufacturing method of the memory cell of the three-dimensional structure different from the above in one Example of this invention. (Example 4) It is a general | schematic process sectional drawing which shows a different process of the manufacturing method of the memory cell of the three-dimensional structure in one Example of this invention. (Example 4) It is a general | schematic process sectional drawing which shows a different process of the manufacturing method of the memory cell of the three-dimensional structure in one Example of this invention. (Example 4) It is a general | schematic process sectional drawing which shows a different process of the manufacturing method of the memory cell of the three-dimensional structure in one Example of this invention. (Example 4) It is a general | schematic process sectional drawing which shows a different process of the manufacturing method of the memory cell of the three-dimensional structure in one Example of this invention. (Example 4) It is a general | schematic process sectional drawing which shows a different process of the manufacturing method of the memory cell of the three-dimensional structure in one Example of this invention. (Example 4) It is a general | schematic process sectional drawing which shows a different process of the manufacturing method of the memory cell of the three-dimensional structure in one Example of this invention. (Example 4) It is a general | schematic process sectional drawing which shows a different process of the manufacturing method of the memory cell of the three-dimensional structure in one Example of this invention. (Example 4) It is a general | schematic process sectional drawing which shows a different process of the manufacturing method of the memory cell of the three-dimensional structure in one Example of this invention. (Example 4) It is a general | schematic process sectional drawing which shows a different process of the manufacturing method of the memory cell of the three-dimensional structure in one Example of this invention. (Example 4) It is a general | schematic process sectional drawing which shows a different process of the manufacturing method of the memory cell of the three-dimensional structure in one Example of this invention. (Example 4) It is a general | schematic process sectional drawing which shows a different process of the manufacturing method of the memory cell of the three-dimensional structure in one Example of this invention. (Example 4) It is a general | schematic process sectional drawing which shows a different process of the manufacturing method of the memory cell of the three-dimensional structure in one Example of this invention. (Example 4) It is a block diagram which shows the example of the mobile telephone which is embodiment of the portable electronic device using the semiconductor device of this invention. (Example 5) It is a structural sectional view showing a schematic structure of a conventional semiconductor memory device.

Explanation of symbols

10 p-type semiconductor substrate 11 island-like semiconductor layer 13 metal wiring 14 tunnel oxide film 15 floating gate 16 interlayer insulating film 17 control gate 18 source diffusion layer 19 drain diffusion layer 20 interlayer insulating film 100 p-type semiconductor substrate 110 island-like semiconductor layer 200 Tunnel oxide film 210 Silicon oxide film 220 Silicon nitride film 230 Silicon oxide film 250 Device isolation film 300 Floating gate (polycrystalline silicon), charge storage layer 310 Charge storage layer 400 made of an insulating film containing nanocrystal silicon Control gate (polycrystal) silicon)
420 Metal gate 450 Interlayer insulating film 500 Source diffusion layer 600 Drain diffusion layer 610 Diffusion layers 701, 702, 703, 710, 711, 712, 752, 753, 754, 755 having the opposite conductivity type to the drain diffusion layer Oxide film)
801, 810, 851 Insulating film (silicon nitride film)
900 Metal wiring 910 Interlayer insulating film 1000 Mobile phone 1001 Control circuit unit 1002 Operation unit 1003 Control unit 1004 Data memory unit 1005 ROM
1006 RAM
1007 Wiring 1008 Man-machine interface unit 1010 RF (radio frequency) circuit unit 1011 Antenna unit

Claims (15)

An island-like semiconductor layer having an inclined portion or at least one step portion is formed on the semiconductor substrate,
The island-shaped semiconductor layer includes a drain diffusion layer formed thereon,
A source diffusion layer formed on at least a part of the bottom;
A charge storage layer formed on the channel region of the side wall sandwiched between the drain diffusion layer and the source diffusion layer via a gate insulating film;
A control gate formed on the charge storage layer,
When electrons are injected into the charge storage layer, a step portion is formed to facilitate injection of the electrons into the charge storage layer by collision of the electrons moving in the channel region with the electric field from the source diffusion layer to the drain diffusion layer to the wall surface. A semiconductor memory device comprising a step or an inclined portion of an inclined portion.   2. The semiconductor memory device according to claim 1, wherein the stepped portion or the inclined portion is configured such that the diameter of the stepped portion or the inclined portion decreases from the bottom portion to the upper direction. An island-like semiconductor layer formed on a semiconductor substrate;
A drain diffusion layer formed on the top of the island-like semiconductor layer;
A source diffusion layer formed on at least a part of the bottom of the island-shaped semiconductor layer;
A charge storage layer formed through a gate insulating film on a channel region that is at least a partial region on the side wall surrounding the island-shaped semiconductor layer and sandwiched between the drain diffusion layer and the source diffusion layer;
A control gate formed on the charge storage layer;
A semiconductor memory device comprising: a diffusion layer having a conductivity type opposite to that of the drain diffusion layer and disposed in a channel region in contact with the drain diffusion layer.   The semiconductor memory device according to claim 1, wherein the source diffusion layer is formed over the entire bottom of the island-shaped semiconductor layer, whereby the semiconductor substrate and the island-shaped semiconductor layer are electrically separated.   The semiconductor memory device according to claim 1, wherein the charge storage layer is formed of a floating gate using polycrystalline silicon.   4. The semiconductor memory device according to claim 1, wherein the charge storage layer is made of a nitride film-oxide film-nitride film.   The semiconductor memory device according to claim 1, wherein the charge storage layer is made of nanocrystal silicon.   8. The semiconductor memory device according to claim 1, wherein the control gate is made of metal.   The stepped portion or inclined portion formed in the channel region is disposed at a position where the distance from the stepped portion or inclined portion to the drain diffusion layer side is smaller than the distance from the stepped portion or inclined portion to the source diffusion layer side. The semiconductor memory device according to any one of claims 1 to 3.   4. The semiconductor memory device according to claim 3, wherein the diffusion layer disposed in a channel region having a conductivity type opposite to that of the drain diffusion layer and in contact with the drain diffusion layer is shorter than a half length of the island-shaped semiconductor layer.   A portable electronic device comprising the semiconductor memory device according to claim 1. A method of manufacturing a semiconductor memory device comprising an island-like semiconductor layer formed on a substrate and having a stepped portion on a side wall thereof,
A sidewall forming step of forming a sidewall on the sidewall of the island-shaped semiconductor layer;
A manufacturing method including at least a dug-down process in which the substrate surface is further dug using the side wall as a mask, and a new side wall having a step with the already formed side wall is formed in the island-like semiconductor layer. Selectively digging the substrate surface by a predetermined depth to form the uppermost sidewall of the island-shaped semiconductor layer; and
After the step, the sidewall forming step and the dug-down step sequentially performed one or more times so that the side wall of the island-shaped semiconductor layer forms one or more steps.
Forming a gate insulating film on the sidewall of the island-shaped semiconductor layer;
Forming a charge storage layer on the gate insulating film;
Forming an interlayer insulating film on the charge storage layer;
Forming a control gate on the interlayer insulating film;
The manufacturing method according to claim 12, further comprising a step of diffusing impurities in the uppermost part of the island-like semiconductor layer and the substrate surface dug down to form a drain diffusion layer and a source diffusion layer. A method for manufacturing a semiconductor memory device comprising a diffusion layer adjacent to a drain diffusion layer disposed on the top of an island-shaped semiconductor layer formed on a substrate and having a conductivity type opposite to that of the drain diffusion layer,
Depositing a film around the sidewall of the island-like semiconductor layer;
Removing the deposited film so that the drain diffusion layer formed on the uppermost part of the island-like semiconductor layer and the side wall adjacent to the drain diffusion layer are exposed;
A reverse conductivity type diffusion layer forming step comprising: forming a drain diffusion layer and a step of forming an opposite conductivity type diffusion layer adjacent to the drain diffusion layer by injecting impurities into the side wall adjacent to the drain diffusion layer; A manufacturing method including at least. A step of selectively dug down the substrate surface by a predetermined depth to form an island-shaped semiconductor layer;
A step of diffusing impurities into the top of the island-like semiconductor layer and the substrate surface dug down to form a drain diffusion layer and a source diffusion layer, respectively;
The reverse conductivity type diffusion layer forming step of forming a diffusion layer adjacent to the drain diffusion layer and having a conductivity type opposite to that of the drain diffusion layer;
Forming a gate insulating film on the sidewall of the island-shaped semiconductor layer;
Forming a charge storage layer on the gate insulating film;
Forming an interlayer insulating film on the charge storage layer;
The method according to claim 14, further comprising: forming a control gate on the interlayer insulating film.

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