JPWO2006101160A1 - A / D converter - Google Patents

Abstract

A high-precision A / D conversion apparatus and A / D conversion method that can be used up to a high frequency are provided. The A / D converter includes a resistor group 61 that generates a plurality of reference voltages at equal intervals, a plurality of comparators 60 that compare the reference voltage and an input signal, a plurality of latch circuits 62 that latch the output signal of the comparator, and a clock signal Are provided with a plurality of variable delay circuits 64 for delaying the signal by a designated time. Alternatively, the variable delay circuit 64 may be inserted between the comparator 60 and the latch circuit 62. Further, a register 65 for outputting delay amount data and a writing circuit for writing information to the register may be provided. An ultra-high-speed and high-precision A / D converter can be provided, and calibration can be performed by correcting the delay amount stored in the register in response to aging.

Description

  The present invention relates to an A / D conversion device, and more particularly to an A / D conversion device that can be used up to a high frequency and has high accuracy.

  Conventionally, a flash A / D converter has been used as a high-speed A / D converter. Patent Document 1 below discloses an example of a flash type A / D converter. The full flash A / D converter is supplied with an upper reference voltage VRT and a lower reference voltage VRB. A resistor group is connected between the upper reference voltage VRT and the lower reference voltage VRB, and the voltage between the upper reference voltage VRT and the lower reference voltage VRB is divided at equal intervals.

The voltage from the resistor group becomes the comparison reference voltage of the comparator group. For example, 256 comparators numbered 1 to 256 in the comparator group compare the comparison reference voltage with the analog input signal VIN, and 0 or 1 Is output. The output (comparison result) of the comparator group is input to the encoder, and the encoder outputs, for example, an 8-bit digital signal DOUT converted into a binary code.
JP-A-10-108041

For example, a THP (Tomlinson Harashima Precoding) method has recently attracted attention as a signal method used for a high-speed wired transmission device such as a 10 giga LAN transmission device. This THP method is an improvement of the pre-emphasis method. A modulo arithmetic circuit is inserted in the middle of the pre-emphasis circuit using the FIR filter that simulates the transmission path, and the amplitude of the output signal is suppressed within a predetermined range. It is a method to do. Non-Patent Document 1 below discloses a THP waveform adjustment technique.
“Matched-Transmission Technique for Channels With Intersymbol Interference”, IEEE TRANSACTIONS ON COMMUNICATIONS, VOL.COM-20, NO.4 AUGUST 1972, pages 774-780.

  In the THP system, the signal level is suppressed within a predetermined width at the transmitting end, but the signal received via the transmission path is attenuated in absolute value, but the signal value can take a value. It has the property of spreading and spreading over several times the signal width on the transmission side. Therefore, when this signal is converted into a digital signal by the AD converter, it is necessary to convert the widened signal width with a predetermined resolution, and a highly accurate AD converter is required.

  However, when the conventional A / D converter described above is used, there is a problem that if it is operated at a high speed, a conversion error becomes large and a necessary accuracy cannot be obtained. An object of the present invention is to solve the above-described problems and to provide a highly accurate A / D conversion device that can be used up to a high frequency.

  When performing A / D conversion at an ultra-high speed using an integrated A / D converter, the inventor of the present invention has a comparator timing in the case of a hold timing of a sample hold circuit or a flash type A / D conversion circuit. It has been found that a slight shift in the latch timing of the output signal causes a conversion error, and this error increases as the change per unit time in the amplitude of the input signal (slope = differential value) increases.

  The cause of the slight timing shift is estimated to be due to signal delay based on, for example, the circuit configuration in the IC and the wiring arrangement. However, it is very difficult to design an IC by accurately controlling the delay amount of the signal of each circuit in the IC. Therefore, in the present invention, high-speed and high-precision A / D conversion is achieved by adjusting the delay amount of either the A / D conversion signal or the latch pulse input to the plurality of latch circuits for each latch circuit. I got a bowl.

  An A / D conversion device according to the present invention includes a reference voltage generation unit that generates a plurality of reference voltages at equal intervals, a plurality of comparison units that compare the plurality of reference voltages with an input signal, and a plurality of comparison units. The main features include a plurality of latch means for latching the output signal and a plurality of variable delay means for delaying the clock signal by a specified time corresponding to each latch means.

  Alternatively, the A / D converter according to the present invention includes a reference voltage generation unit that generates a plurality of reference voltages at equal intervals, a plurality of comparison units that compare the plurality of reference voltages with an input signal, and the plurality of comparisons. Corresponding to the means, a plurality of variable delay means for delaying the output signal of the comparison means by a specified time and a plurality of latch means for latching the output signals of the plurality of variable delay means are provided. Features.

  Further, the A / D converter described above further includes register means for outputting delay amount data to each of the plurality of variable delay means, and writing means for writing information to the register means. There is. Further, the A / D converter described above is characterized in that the register means stores delay amount data determined using a genetic algorithm.

The A / D conversion device of the present invention has the following effects by the above configuration.
(1) An ultra-high speed and high accuracy A / D converter can be provided.
(2) Calibration can be performed by correcting the delay amount stored in the register corresponding to aging.
(3) Since it is possible to finely adjust the delay after the IC design of the A / D converter, it is not necessary to accurately verify the signal delay at the time of the IC design of the A / D converter, and the circuit design is facilitated. .

It is a block diagram which shows the structure of the whole high-speed digital data transmission apparatus containing the A / D conversion apparatus of this invention. It is a block diagram which shows the structure of the A / D converter of 1st Example of this invention. It is a block diagram which shows the structure of the A / D converter of 2nd Example of this invention. 3 is a block diagram illustrating a configuration example of a variable delay circuit 64. FIG. It is a block diagram which shows the structure of the adjustment system of the A / D converter in this invention. It is a flowchart which shows the processing content of the adjustment system in this invention.

Explanation of symbols

60 ... Comparator 61 ... Resistance group 62 ... Latch circuit 63 ... Decoder 64 ... Variable delay circuit 65 ... Register 66 ... Register write circuit

  The A / D converter of the present invention was developed on the assumption that it is used for an ultrahigh-speed digital data transmission device (LAN) of several gigabps or more using a balanced cable or a coaxial cable represented by a twisted pair cable. However, the A / D conversion device of the present invention is not limited to this, and can be applied to A / D conversion of an arbitrary signal. Example 1 will be described below.

  FIG. 1 is a block diagram showing the overall configuration of a high-speed digital data transmission apparatus including an A / D conversion apparatus according to the present invention. This embodiment consists of a full-duplex data transmitter / receiver of the same configuration connected to both ends of the transmission cable 21. For example, in 10 Gigabit Ethernet (registered trademark), four sets of the transmission apparatus of FIG. 1 are used.

  The transmission circuit 10 includes a code converter 11, a PN signal generation circuit 12, a switch 13, a THP precoder 14, a D / A converter 15, an amplifier 16, and a transmission side training control circuit 17. The code converter 11 divides the transmission data into predetermined bits and outputs one of a plurality of signal levels (voltage values) corresponding to the value of the bit string.

  The THP precoder 14 includes, for example, an adder, a modulo calculator, and an FIR filter. The input signal is input to the adder, and the adder subtracts the output of the FIR filter from the input signal and outputs the result to the modulo calculator. The output signal of the modulo calculator is input to the FIR filter, and the output of the FIR filter is output to the adder. In the FIR filter, the coefficient of the impulse response of the transmission line including the reception side equalizer circuit is set.

  The output of the THP precoder 14 is converted into an analog signal by the DAC 15 and transmitted through the amplifier 16 and the hybrid circuit 20. The transmission-side training control circuit 17 switches the switch 13 to the PN signal generation circuit 12 when the apparatus is turned on, for example, sends a training signal to the transmission line, calculates an appropriate THP coefficient in the reception-side circuit, and receives it. The THP coefficient data returned from the side is received and set in the THP precoder 14. Even during signal transmission, the coefficient of the THP precoder 14 may be adjusted based on the signal evaluation result on the receiving circuit side.

  Next, the receiving circuit will be described. The reception circuit 30 includes a variable gain amplifier 31, an A / D converter 32 according to the present invention, a symbol synchronization circuit 33, an equalizer circuit 34, a level determination circuit 35, a THP decoder 36, a sign reverse conversion circuit 37, and a reception side training control circuit 38. Etc.

  The variable gain amplifier 31 amplifies the received signal so that the level of the output signal of the A / D converter 32 becomes the same signal level as the input signal of the DAC 15 of the transmission circuit. The symbol synchronization circuit 33 regenerates the synchronization signal from the received signal, and the A / D converter 32 of the present invention A / D converts the received signal.

  The equalizer circuit 34 is a known FIR digital filter circuit. The level determination circuit 35 is a circuit that determines in which multi-valued area the received signal is, and the THP decoder 36 is a modulo arithmetic circuit having the same characteristics as the modulo arithmetic unit in the THP precoder. The sign reverse converter 37 reversely converts the output of the THP decoder 36 into the original bit information.

  The reception side training control circuit 38 cooperates with the transmission side training control circuit 17 to adjust the gain of the variable gain amplifier 32 and the equalizer circuit 34 using the training signal. Further, the variable gain amplifier 31, so as to obtain more detailed signal evaluation information such as how much the signal is deviated from the central level of the signal arrangement during data communication and to improve the evaluation value, The adjustable coefficients such as the equalizer circuit 34 and the THP precoder 14 on the transmission side may be adjusted simultaneously based on, for example, a genetic algorithm.

  FIG. 2 is a block diagram showing the configuration of the A / D converter according to the first embodiment of the present invention. The A / D converter 32 is a flash type A / D conversion circuit, and compares the plurality of reference voltages with an input signal, a resistor group 61 as reference voltage generating means for generating a plurality of reference voltages at equal intervals. Corresponding to the comparator 60 as a plurality of comparison means, the latch circuit 62 as a plurality of latch means for latching the output signals of the plurality of comparison means, the encoder 63, and each latch means, the clock signal is delayed by a specified time. A variable delay circuit 64 as a plurality of variable delay means, a register circuit 65 as a register means for outputting delay amount data to each of the plurality of variable delay means, and a register book as a writing means for writing information into the register means Embedded circuit 66 is provided.

  The input signal is inputted in parallel to one input terminal of all the plural (for example, 128) comparators 60. A reference voltage obtained by equally dividing the reference voltage by the resistor group 61 is applied to the other input terminal of the comparator 60. The output of the comparator 60 is latched by a latch circuit 62, converted into, for example, a 7-bit binary code by an encoder 63, and output.

  The variable delay circuit 64 individually delays the clock signal supplied to each latch circuit based on the delay amount data stored in the register 65. As the delay amount data storage element of the register circuit 65, a rewritable nonvolatile memory such as a mask ROM, a fuse ROM or a flash memory, a RAM (flip-flop), or the like can be used.

  The register writing circuit 66 adopts a rewritable memory such as a flash memory as a storage element, and at the time of shipment after manufacturing the A / D converter, or at the time of transmission training after being incorporated in the device, data This is a circuit for writing delay amount data into the register 65 during calibration of other A / D converters during transmission.

  FIG. 4 is a block diagram illustrating a configuration example of the variable delay circuit 64. The input signal is sequentially delayed by the inverters 80 to 85, and the selector 86 selects one of the input signal, the output of the inverter 81, the output of the inverter 83, and the output of the inverter 85 based on the 2-bit delay amount control signal. Output. As an element for delaying a signal, for example, an integration circuit using a resistor and a capacitor, a wiring having a desired length, or the like can be used in addition to a logic circuit.

  The A / D converter according to the first embodiment accurately adjusts the synchronization between the output signal of the comparator 60 that reaches the latch circuit 62 and the clock signal that is the latch pulse in each latch circuit 62 by the configuration as described above. This improves the accuracy of the A / D converter during high-speed operation.

  FIG. 5 is a block diagram showing a configuration of an adjustment system for an A / D converter according to the present invention. The oscillation circuit 70 generates a sine wave analog signal having a desired frequency based on control from a GA (genetic algorithm) adjustment controller (PC) 77. The variable gain amplifier 71 amplifies the sine wave analog signal to a desired amplitude based on the control from the GA adjustment control device 77. This signal is input to an adder 73 through a band pass filter (BPF) 72.

  The DC bias generation circuit 74 generates a desired DC voltage based on the control from the GA adjustment control device 77, and this DC voltage is added to the sine wave analog signal by the adder 73 and output to the A / D converter 32. Is done.

  The timing signal generation circuit 75 detects a zero cross point of a sine wave analog signal, for example, and generates a clock signal after elapse of a time instructed from the GA adjustment controller 77. The A / D converter 32 samples the signal based on this clock signal, performs A / D conversion, and outputs digital output data.

  The buffer circuit 76 latches the digital output data of the A / D converter 32 based on the latch pulse output from the timing signal generation circuit 75 and outputs it to the GA adjustment control device 77. The GA adjustment control device 77 is further configured to be able to write delay amount data to the register circuit 65 via the register write circuit 66 of the A / D converter 32.

  As a circuit for generating an input signal to the A / D converter 32, an analog signal may be generated by controlling a high-speed D / A converter by the GA adjustment controller 77 in addition to the above-described configuration. Good.

  FIG. 6 is a flowchart showing the processing contents of the adjustment system according to the present invention. This process is executed by the GA adjustment controller 77 to determine the contents of the register of the manufactured A / D converter, for example, and the delay amount is adjusted by a genetic algorithm (GA).

  In S10, initialization such as securing a region for the number of individuals is performed, and in S11, an initial population of individuals having a plurality of genes (= delay amount) is generated. The number of genes is the number of all delay amount data (for example, 128). As the initial value of the gene, each value is randomly specified so as to be evenly distributed within a possible range of the delay amount.

  In S12, one of the unevaluated individuals is selected, and the delay amount data, which is the gene value in the individual, is written into the register circuit 65 via the register write circuit 66 in the A / D converter 32.

  In S13, the GA adjustment control device 77 controls the oscillation circuit 70, the variable gain amplifier 71, the DC bias generation circuit 74, and the timing signal generation circuit 75 so that the A / D converter corresponds to a specific measurement point. Add the desired input signal and clock signal.

  For measurement points, for example, a plurality of points that are uniformly distributed on a plane with the horizontal axis representing the voltage range that can be taken by the input signal and the vertical axis representing the range that can be taken by the differential value of the input signal may be used as measurement points. Good.

  In S <b> 14, the output signal is read from the A / D converter 32 via the buffer circuit 76. In S15, it is determined whether or not the measurement has been completed for all measurement points. If the determination result is negative, the process proceeds to S13, but if the determination is affirmative, the process proceeds to S16.

  In S16, an error at each measurement point regarding the individual is obtained, and the mean square value thereof is used as an evaluation value. Therefore, the smaller the value, the better the evaluation. The value of the input signal is obtained by calculation from the signal frequency, amplitude value, DC bias value, and clock timing.

  In S17, it is determined whether or not all the individuals have been evaluated. If the determination result is negative, the process proceeds to S12, but if the determination is affirmative, the process proceeds to S18. The processing of S13 to S15 is initially performed for all individuals, but after the second round, it is performed only for newly generated individuals or individuals whose genes have been changed.

  In S18, an individual selection process is executed. That is, the individuals are arranged in the order of evaluation values, and a predetermined number of individuals with low evaluation are deleted from the population. In S19, a crossover process is executed. That is, a predetermined number of pairs consisting of two parent individuals are randomly selected (copied), and individual genes are copied from one of the two individuals of the pair to create a new child individual. In addition, it is determined at random which parent individual copies each gene. Further, the number of newly generated individuals is the same as the number of deletions in S18.

  In S20, a mutation process is executed. That is, a predetermined number of individuals are selected at random, and a mutation process is executed for a predetermined number of genes randomly selected in each individual to change the delay amount that is the gene at random, and a new individual is Replace with the original individual.

  In S21, it is determined whether or not the evaluation criterion is satisfied. If the determination result is negative, the process proceeds to S12, but if the determination is affirmative, the process ends. That is, it is determined whether or not the best evaluation value is greater than or equal to a predetermined value (the mean square error value is less than or equal to a predetermined value), and when it ends, the gene of the individual with the highest evaluation at that time is adopted as the delay amount To do.

  FIG. 3 is a block diagram showing the configuration of the A / D converter of the second embodiment of the present invention. The A / D converter of the second embodiment is also a flash type A / D conversion circuit, and includes a resistor group 61 which is a reference voltage generating means for generating a plurality of reference voltages at equal intervals, and the plurality of reference voltages and input signals. A plurality of comparators 60 that are compared with each other, a variable delay circuit 64 that is a plurality of variable delay means corresponding to the plurality of comparing means, and delays an output signal of the comparing means by a specified time, A latch circuit 62 that is a plurality of latch means for latching an output signal of the variable delay means, an encoder 63, a register circuit 65 that is a register means for outputting delay amount data to each of the plurality of variable delay means, and the register means A register writing circuit 66 is provided as writing means for writing information.

  The input signal is inputted in parallel to one input terminal of all the plural (for example, 128) comparators 60. A reference voltage obtained by equally dividing the reference voltage by the resistor group 61 is applied to the other input terminal of the comparator 60.

  The output of the comparator 60 is input to the variable delay circuit 64, and the variable delay circuit 64 individually delays the output signal of the comparator 60 based on the delay amount data stored in the register 65. The output signal of the variable delay circuit 64 is latched by each latch circuit 62, converted to, for example, a 7-bit binary code by the encoder 63, and output.

  As the delay amount data storage element of the register circuit 65, a rewritable nonvolatile memory such as a mask ROM, a fuse ROM or a flash memory, a RAM (flip-flop), or the like can be used.

  The register writing circuit 66 adopts a rewritable memory such as a flash memory as a storage element, and at the time of shipment after manufacturing the A / D converter or at the time of transmission training and data after being incorporated in the apparatus. This is a circuit for writing delay amount data into the register 65 during calibration of other A / D converters during transmission.

  The configuration of the variable delay circuit 64 in the A / D converter of the second embodiment and the method for determining the delay amount are the same as those of the A / D converter of the first embodiment. The A / D converter according to the second embodiment accurately adjusts the synchronization between the output signal of the comparator 60 that reaches the latch circuit 62 and the clock signal that is the latch pulse in each latch circuit 62 by the configuration as described above. This can improve the accuracy of the A / D converter during high-speed operation.

  Although the embodiments have been disclosed above, the present invention may be modified as follows. In the embodiment, an example in which the delay amount is adjusted by a genetic algorithm has been disclosed. However, other algorithms may be used, and the delay amount of each variable delay circuit 64 may be determined based on the measurement.

After the A / D converter IC is manufactured and the delay amount of each variable delay circuit 64 is determined, a mask ROM in which the delay amount is stored in advance or desired delay amount data is generated instead of the register 65. An IC for an A / D converter may be manufactured using a fixed wiring pattern. Alternatively, an IC may be manufactured by replacing each variable delay circuit 64 with a fixed delay circuit having a desired delay amount.

Claims (4)

A reference voltage generating means for generating a plurality of reference voltages at equal intervals;
A plurality of comparison means for comparing the plurality of reference voltages with an input signal;
A plurality of latch means for latching output signals of the plurality of comparison means;
An A / D conversion device comprising a plurality of variable delay means for delaying a clock signal by a specified time corresponding to each latch means. A reference voltage generating means for generating a plurality of reference voltages at equal intervals;
A plurality of comparison means for comparing the plurality of reference voltages with an input signal;
Corresponding to the plurality of comparison means, a plurality of variable delay means for delaying the output signal of the comparison means by a specified time, and a plurality of latch means for latching the output signals of the plurality of variable delay means,
An A / D conversion device comprising: And register means for outputting delay amount data to each of the plurality of variable delay means;
The A / D converter according to claim 1, further comprising: a writing unit that writes information to the register unit. 4. The A / D converter according to claim 3, wherein the register means stores delay amount data determined using a genetic algorithm.

Images