JPWO2006059559A1 - Magnetic random access memory, its operation method and its manufacturing method - Google Patents

Abstract

The magnetic random access memory includes a plurality of first wirings extending in a first direction, a plurality of second wirings extending in a second direction different from the first direction, and intersections of the plurality of first wirings and the plurality of second wirings. And a plurality of memory cells. Each of the plurality of memory cells includes a free magnetic layer in which two or more magnetic layers antiferromagnetically coupled via a nonmagnetic layer are stacked, and the direction of the easy axis of magnetization of the free magnetic layer is the first direction And different from the second direction. Data is written to a specific memory cell as one of the plurality of memory cells under a predetermined write condition. The data is repeatedly written into the specific memory cell while resetting the write condition until the data is correctly written into the specific memory cell.

Description

  The present invention relates to a magnetic random access memory, and more particularly to a magnetic random access memory that performs toggle writing or direct writing.

  2. Description of the Related Art A magnetic random access memory (hereinafter referred to as “MRAM”) that stores data by controlling the direction of magnetization of a magnetoresistive effect element (MTJ: Magnetic Tunneling Junction) as a storage element is known. There are several types of MRAM depending on the recording method of the magnetization direction.

  In US Pat. No. 6,545,906 (first conventional example), a toggle type magnetic random access memory (hereinafter referred to as “toggle write”) in which writing is performed by a toggle write mode (hereinafter referred to as “toggle write”) is disclosed. (Hereinafter referred to as “type MRAM”). This toggle type MRAM is different from the conventional typical MRAM in the structure of the memory cell and the principle of the write operation. In particular, the memory cell is highly selective during a write operation. The toggle type MRAM disclosed in US Pat. No. 6,545,906 will be described in detail below.

1 and 2 are cross-sectional views showing the structure of a typical magnetoresistive element used in a toggle type MRAM. The magnetoresistive effect element 125 is provided between the first wiring 110 and the second wiring 101. In order from the first wiring 110 side, an antiferromagnetic layer 109, a pinned layer 112, a barrier layer 105, and a free layer 111 are provided and connected to the second wiring 101. The pinned layer 112 includes a magnetic film 108, a nonmagnetic film 107, and a magnetic film 106. The free layer 111 includes a magnetic film 104, a nonmagnetic film 103, and a magnetic film 102.
The magnetoresistive effect element 125 is characterized in that the magnetic film 104 and the magnetic film 102 having the same film thickness are laminated so as to be antiferromagnetically coupled through the nonmagnetic film 103. The magnetic film 108 and the magnetic film 106 are also laminated via the nonmagnetic film 107. The magnetization directions of the magnetic film 108 and the magnetic film 106 are strongly fixed during manufacturing. The magnetization direction of the magnetic film 104 is defined as the first free layer magnetization direction, and the magnetization direction of the magnetic film 102 is defined as the second free layer magnetization direction. The direction of the first free layer magnetization and the direction of the second free layer magnetization are controlled by a magnetic field generated by a write current flowing through the first wiring 110 and the second wiring 101. Here, the directions of the magnetizations of the first and second free layers are stable in an antiparallel state in which the directions are reversed by 180 °. When the direction of one free layer magnetization is reversed, the direction of the other free layer magnetization is also reversed to maintain the antiparallel state.

The sense operation principle in the toggle type MRAM is the same as the sense operation principle of the conventional typical MRAM. That is, a tunnel current passing through the barrier layer 105 sandwiched between the magnetic film 104 and the magnetic film 106 is detected. When the direction of the first free layer magnetization is parallel to the direction of the second pinned layer magnetization of the magnetic film 106, the tunnel current increases compared to the case of the antiparallel state. That is, the magnetic resistance (MTJ resistance) decreases. The information stored in the memory cell is read using this feature. Here, for convenience of explanation, the case where the magnetic resistance is a high resistance value Rmax (tunnel current min.) Is “1” (FIG. 1), and the case where the magnetic resistance is a low resistance value Rmin (tunnel current max.) Is “0” ( Fig. 2).
The planar layout of the memory cell in the toggle type MRAM is different from that of the conventional typical MRAM. FIG. 3 is a top view showing a planar layout of the magnetoresistive effect element of the toggle type MRAM. In the toggle type MRAM, the magnetization easy axis direction of the magnetoresistive effect element 125 is the X direction in which the first wiring 110 (example: word line) extends and the Y direction in which the second wiring 101 (example: bit line) extends. And different. That is, it is characterized in that it is arranged so as to be in the direction of about 45 ° when viewed from both directions. As a result, a toggle operation described later is facilitated.

Next, the principle of the write operation of a toggle type MRAM different from the conventional typical MRAM will be described. The write operation of the toggle type MRAM differs depending on whether or not the read information and the information to be written are the same when the selected memory cell is read in advance. That is, when the read information (“0” or “1”) and the information to be written (“0” or “1”) are equal, no toggle operation is performed, and the read information If the information to be written is different, a toggle operation is performed. In the toggle operation, the directions of the first and second free layer magnetizations are changed while maintaining the antiparallel relationship.
4 to 6 are diagrams showing a toggle operation principle in the toggle type MRAM. FIG. 4 is a timing chart showing timings of the write current I _WL and the write current I _BL in the toggle operation. 5 and 6 are diagrams showing changes in the directions of the first and second free layer magnetizations in the toggle operation. A thin arrow indicates the direction of the second free layer magnetization, and a thick arrow indicates the direction of the first free layer magnetization. FIG. 5 shows a case where data “1” is written to the magnetoresistive effect element storing data “0”. FIG. 6 shows a case where data “0” is written to the magnetoresistive effect element storing data “1”.
Referring to FIG. 4, in the toggle operation, the write current _IWL is supplied to the first wiring 110 (word line) at time t1. Next, at time t2, the write current _IBL is supplied to the second wiring 101 (bit line). The supply of the write current _{I WL} at the time t3 is stopped, the supply of the write current _{I BL} is stopped at time t4. By a series of current control described above, the rotating magnetic field is applied to the selected cell at the intersection of the second wiring 101 where the first wiring 110 and the write current I _BL of the write current I _WL is supplied is supplied. Thereby, the directions of the first and second free layer magnetizations are rotated (changed). Thus, data is written.
With reference to FIGS. 5 and 6, in the magnetoresistive effect element, at time t1, a magnetic field _HWL is generated by the write current _IWL , and the directions of the first and second free layer magnetizations start to rotate. At time t2, the more field H _BL is generated in the write current I _BL, one orientation of the first and second free layer magnetization is more than hard axis magnetization. At time t3, the magnetic field _HWL disappears, and the other direction of the first and second free layer magnetizations also exceeds the hard axis. At time t4, the magnetic field _HBL disappears. As described above, the directions of the magnetizations of the first and second free layers are rotated once by the rotating magnetic field (H _WL → H _WL + H _BL → H _BL ) in a spin-flop state. That is, when the initial state is “0”, it is rewritten (toggled) to “1”, and when it is “1”, it is rewritten to “0”. Therefore, the direction of each free layer magnetization changes between a “1” state and a “0” state in a toggle manner at each write operation.

FIG. 7 is a graph showing the relationship between the write current I _WL and the write current I _BL and the memory cell (magnetoresistance effect element) to be toggled. The vertical axis represents the write current I _WL and the horizontal axis represents the write current I _BL . Black circles correspond to selected cells, white circles correspond to half-selected cells (one of the write word line and bit line is the same as the selected cell), and crosses correspond to non-selected cells. An area indicated as “TOGGLE” indicates an area where a toggle operation occurs. The region indicated as “No Switching” indicates a region where no toggle operation occurs.
In toggle MRAM, (in the figure, open circle) of the half-selected memory cells arranged either on the second wiring 101 through the first interconnection 110 and on the write current I _BL flowing the write current I _WL is within the Since only a magnetic field in one direction is applied, the possibility of erroneous writing is very low. Therefore, it is not necessary to strictly control the write current value, and the write margin is dramatically improved as compared with the conventional typical MRAM.

US Pat. No. 6,545,906 further has a structure as shown in FIGS. 1 to 3 which is basically similar to a toggle type magnetic MRAM, and is written by a direct write mode (hereinafter referred to as a direct write mode). Also, a technique of a direct mode write MRAM (hereinafter referred to as “direct mode MRAM”) in which “direct write” is performed is also disclosed. However, in the direct mode type MRAM, the magnitude of the first free layer magnetization is set to the second free layer magnetization by giving a slight difference in the thicknesses of the two magnetic films 102 and 104 in the free layer 111, for example. It is made different from the size. Thereby, in the case of a positive write magnetic field, the state of each free layer magnetization only transitions from the state of the memory cell “0” to the state of “1”, and in the case of a negative write magnetic field, from the state of “1”. Only the transition to the “0” state occurs. Here, the positive write magnetic field is, for example, a magnetic field when the write current I _WL is in the X axis positive direction and the write current I _BL is in the Y axis positive direction, and the negative write magnetic field is the write current I _WL is in the X axis. This is a magnetic field in the negative direction when the write current I _BL is in the Y-axis negative direction. In direct writing, unlike the toggle writing, the recording state can be divided only by the direction of the writing magnetic field. That is, it is not necessary to read the recording state in advance like toggle writing.

  However, the toggle type MRAM and the direct mode type MRAM have the following problems. The following description is made assuming a toggle type MRAM, but the essence of the direct mode type MRAM is the same.

FIG. 8 is a graph showing magnetization characteristics of the free layer with respect to an external magnetic field in the easy axis direction. The vertical axis represents the magnetization, and the horizontal axis represents the external magnetic field in the direction of the easy axis. Two arrows shown beside the curves in the figure schematically indicate the directions of the first and second free layer magnetizations. H _f is the flop magnetic field, _{H s} saturation magnetic field, _{H r} represents the return magnetic field. Here, _Hr is a magnetic field that returns from the flop state to the antiparallel state.
If the external magnetic field H applied is from 0 to H _f, antiferromagnetic coupling between the first free layer and the second free layer is maintained, difficult magnetization is induced magnetization M is substantially Therefore, it becomes 0. Accordingly, as indicated by the two arrows in the figure, the direction of the first free layer magnetization and the direction of the second free layer magnetization remain antiparallel. That is, when a write current magnetic field along the easy axis, the magnetic field if smaller than H _f, toggle operation does not occur.
When the external magnetic field H becomes H _f the applied, the magnetization M increases discontinuously. Thereafter, when the external magnetic field H increases from H _f to H _s , the magnetization M changes linearly with respect to the external magnetic field. Accordingly, as indicated by the two arrows in the figure, the direction of the first free layer magnetization and the direction of the second free layer magnetization change according to the magnitude and direction of the external magnetic field. That is, the toggle operation is possible as described above.
When the external magnetic field H is equal to or higher than H _s , the magnetization M is saturated and becomes constant. Accordingly, as indicated by two arrows in the figure, the direction of the first free layer magnetization and the direction of the second free layer magnetization are both aligned with the direction of the external magnetic field. Therefore, after that, when the external magnetic field H returns to 0 and the direction of the first free layer magnetization and the direction of the second free layer magnetization become antiparallel, it is unclear which direction each free layer magnetization is directed to. . Therefore, it is unclear whether or not each free layer magnetization is in a desired direction. That is, a stable toggle operation is impossible.

As described above, the upper limit and the lower limit of the magnetic field where the toggle operation is performed are defined by the saturation magnetic field H _s and the flop magnetic field H _f , respectively. This will be further described with reference to FIG. FIG. 9 is a graph expressing the first quadrant of FIG. 7 with respect to the magnetic field. The vertical axis represents the word line vertical magnetic field generated by the write current _IWL flowing through the word line. The horizontal axis indicates the bit line vertical magnetic field generated by the write current _IBL flowing through the bit line. The horizontal axis in FIG. 8 corresponds to the “magnetization easy axis direction” indicated by the broken line in FIG. 9. The region surrounded by the closed curve B is the “TOGGLE” region in FIG. Closed curve B is the determined curves B1 and B3 the flop field _{H f,} curvilinear B2 Prefecture determined by the saturation magnetic field _{H s.} By the toggle operation, the path of the magnetic field applied to the selected cell becomes R ₁ → R ₂ → R ₃ → R ₄ .

The saturation magnetic field H _s and the flop magnetic field H _{f at} the point R ₀ (FIG. 8) can be written approximately as follows when the free layer 111 is composed of two equivalent magnetic layers 102 and 104.
H _f ≈ (H _k × H _i ) × 0.5 (1)
H _s ≈ H _i (2)
However,
H _k : anisotropic magnetic field of free layer H _i : antiferromagnetic coupling magnetic field between the first free layer and the second free layer, and at least H _i > H _k .

From the viewpoint of operating the MRAM with low power consumption (low write current), it is desirable that the flop magnetic field is small. That is, it is preferable that the curve B1 approaches the vertical axis and the curve B3 approaches the horizontal axis. Further, from the viewpoint of an operation margin for operating a plurality of memory cells in the MRAM in the same manner, it is desirable that the ratio of the saturation magnetic field and the flop magnetic field is large. That is, it is preferable that the area of the closed curve B is widened. In order to satisfy these conditions, it can be seen from the above formulas (1) and (2) that it is preferable to reduce H _k .
Anisotropic magnetic field H _k of the free layer, in order to ensure the thermal agitation resistance, it is necessary to secure a certain size or more. For example, after recording information, H _k needs to satisfy the following equation in order to maintain the recorded state for 10 years.
ΔE / kT = H _k * M _s * Thickness * Area / kT> 54 (3)
However,
ΔE: energy barrier required for the magnetization of two free layers to transition from one antiparallel state to the other antiparallel state M _s : free layer saturation magnetization Thickness: free layer thickness Area: free layer area k : Boltzmann coefficient T: Absolute temperature Therefore, the magnitude of H _k has a lower limit expressed by the equation (3).

Furthermore, the inventors have found that the energy barrier is lowered during the recording operation (writing operation) as a problem peculiar to the toggle type MRAM. FIG. 10 is a graph showing the relationship between the energy barrier and the magnetic field applied to the selected cell during the write operation. The vertical axis is an energy barrier standardized with an energy barrier necessary for retaining data for 10 years. The horizontal axis is the easy magnetization direction of the magnetic field H applied to the selected cell during a write operation normalized by H _k. The solid line shows the energy barrier required for the magnetizations of the two free layers to transition from one antiparallel state to the other antiparallel state. Specifically, as shown in FIG. 11A, an energy barrier for changing the direction of each magnetization from the state shown on the lower side to the state shown on the upper side is shown. A broken line indicates an energy barrier for maintaining a relative orientation relationship between the magnetization directions of the magnetic layers in the free layer during the toggle operation. Specifically, as shown in FIG. 11B, an energy barrier is shown for changing the magnetization direction from the state shown at the lower side to the state shown at the upper side by rotating in the same direction. The dotted line indicates an energy barrier for maintaining the relative orientation relationship between the magnetization directions of the magnetic layers in the free layer during the toggle operation. Specifically, as shown in FIG. 11C, an energy barrier is shown for turning each magnetization direction in the opposite direction from the state shown on the lower side to the state shown on the upper side.
Energy barrier is in the range of the magnetic field from the flop field H _f applied during toggle operation until the saturation magnetic field H _s, shows the characteristics of the convex (dashed + dotted line). When the write magnetic field is near the flop magnetic field H _f (range A ₁ ) or the saturation magnetic field H _s (range A ₂ ), it can be seen that the energy barrier is lower than the necessary energy barrier (= 1). Energy barrier only in the range A ₃ is greater than the energy barrier required.

In the range A _1, toggling takes place by a magnetic field H caused by the write operation. Thereby, the state shown in the lower side of FIG. 11B is obtained. At this time, the energy barrier is below the required energy barrier. Therefore, there is a possibility that the magnetization directions of the first and second free layers rotate in the same direction due to thermal disturbance during the toggle operation, resulting in a state shown on the upper side. In this case, the magnetization directions of the first and second free layers are reversed.
In range A _2, toggling takes place by a magnetic field H caused by the write operation. Thereby, the state shown in the lower side of FIG. 11C is obtained. At this time, the energy barrier is below the required energy barrier. For this reason, there is a possibility that the magnetization directions of the first and second free layers rotate in opposite directions due to thermal disturbance during the toggle operation, resulting in a state shown on the upper side. Also in this case, the magnetization directions of the first and second free layers are reversed.

Thus, as shown in FIG. 10 and FIGS. 11A to 11C, when the magnitude of the magnetic field H of the write operation is in the range A ₁ and A ₂ during the toggle operation, the energy barrier falls below the required energy barrier, and the memory cell There is a high probability that writing will not be performed normally due to a malfunction. That is, as a problem specific to the toggle type MRAM, it has been found that even if a toggle type MRAM having a sufficiently large energy barrier is used, an error may occur accidentally during a write operation.

The following method can be considered as a method for preventing such a malfunction during the write operation.
(A) Increasing the anisotropic magnetic field Hk. Accordingly, since the convex curve in FIG. 10 becomes high, the range A ₃ becomes wide and the ranges A ₁ and A ₂ become narrow. Therefore, even if the energy barrier is lowered during writing, the energy barrier is easily set to a value equal to or higher than that in the held state, and the probability of malfunction can be reduced.
(B) Increase the ratio of the saturation magnetic field to the flop magnetic field. That is, the antiferromagnetic coupling magnetic field H _i is increased. Thereby, the curve of the convex in FIG. 10 because laterally extending, in the range A ₃ becomes wider. Therefore, the operation margin can be widened, and the write operation can be performed in a region where the energy barrier is not lowered.

  However, any of the above methods (a) and (b) is accompanied by an increase in the flop magnetic field and an increase in the write current. That is, power consumption increases. There is a demand for a technique that suppresses the possibility that the first free layer magnetization and the second free layer magnetization are switched by thermal disturbance during the write operation without increasing the flop magnetic field and the write current. There is a need for a technique that prevents malfunction during a write operation without increasing power consumption.

  Such a problem is peculiar to a toggle type MRAM that performs a write operation while generally maintaining an antiparallel state between a plurality of magnetic layers in a free layer. In a conventional typical MRAM different from a toggle type MRAM, there is no need to worry about the direction of magnetization in the free layer during a write operation.

  As a related technique, Japanese Patent Application Laid-Open No. 2003-115577 discloses a recording / reproducing method for a nonvolatile magnetic thin film memory device. The recording / reproducing method of this nonvolatile magnetic thin film memory device is a recording / reproducing method of a nonvolatile magnetic thin film memory device having a substrate, a plurality of memory cells having magnetoresistive elements provided on the substrate, and a transistor. . Before recording information, trial writing of information is performed in the memory cell, and after confirming recording of the trial writing, regular data is recorded. That is, trial writing is performed on the memory cell for trial writing before information is recorded, and normal data writing is performed after a current value at which information can be recorded is confirmed. If the test writing fails, the current value may be changed and the test writing may be performed again.

Accordingly, an object of the present invention is to provide a possibility that the direction of the first free layer magnetization and the direction of the second free layer magnetization are switched by the thermal disturbance during the write operation without increasing the flop magnetic field and the write current. To provide a toggle type and direct mode write type MRAM that can be suppressed, and a method of operating the MRAM.
Another object of the present invention is to provide a toggle type and direct mode write type MRAM that can prevent malfunction during a write operation without increasing power consumption, and a method for operating the MRAM. is there.

In an aspect of the present invention, an operation method of a magnetic random access memory according to the present invention includes a step of writing data to a memory cell, a step of determining whether or not the data is written to a memory cell, A step of rewriting the data in the memory cell when the data is not written. Here, the magnetic random access memory includes a memory cell including a free magnetic layer in which two or more magnetic layers antiferromagnetically coupled via a nonmagnetic layer are stacked, a first wiring extending in a first direction, Second wiring extending in a second direction different from the first direction. The direction of the easy magnetization axis of the free magnetic layer is different from the first direction and the second direction. In the present invention, it is determined whether data has been written, and rewriting is performed in the case of writing failure. Therefore, malfunctions due to thermal disturbance during writing operations can be prevented for toggle type and direct type MRAMs.
In the operation method of the magnetic random access memory described above, the writing step includes executing a read operation on the memory cell and, based on a result of the read operation, the data of the data by a toggle write method with respect to the memory cell. Performing a write operation. According to the present invention, it is possible to prevent a malfunction during a write operation, particularly for a toggle type MRAM. The step of writing includes the step of writing the data to the memory cell by a direct write method. According to the present invention, it is possible to prevent a malfunction during a write operation, particularly for a direct type MRAM.
The operation method of the magnetic random access memory preferably further comprises a step of determining again whether or not the data has been written to the memory cell. In the present invention, after the rewriting performed when writing fails, it is re-determined whether the data has been written. Therefore, it is possible to reliably grasp the malfunction during the toggle writing operation. Preferably, the method further includes the step of repeatedly executing the step of rewriting and the step of determining until the data is written to the memory cell. In the present invention, the write operation is continued until data is written, so that it is possible to more reliably prevent a malfunction during the toggle write operation.
In the magnetic random access memory operation method described above, the step of rewriting preferably includes the step of performing the data write operation again with the same write current as when the data write operation was performed last time. In the case of an accidental error due to a thermal disturbance, writing can be performed by rewriting with the default write current, and there is a high possibility that the accidental error can be eliminated. In the rewriting step, the data may be written with a different write current from the previous data write operation. By performing rewriting with a current value different from the write current of the default value, the current value can be optimized and data can be written more reliably. Further, in the step of rewriting with a different current value, the data write operation may be performed again with a smaller write current than when the previous data write operation was performed. In this case, by rewriting with a current value smaller than the default write current, the current value can be optimized for a memory cell with a small saturation magnetic field, and data can be written more reliably. I can do it. Further, in the step of rewriting with a different current value, the data write operation may be performed again with a larger write current than when the data write operation was performed last time. By rewriting with a current value larger than the default write current, the current value can be optimized for a memory cell with a large saturation magnetic field, and data can be written more reliably.
The magnetic random access memory operation method may further include a step of outputting a signal indicating an alarm when the data is not written even if the write operation is repeated a predetermined number of times. As a result, it can be understood that there are memory cells that cannot be toggle-written in the toggle type and direct mode type MRAM.
Further, when the data is not written even after repeating the write operation a predetermined number of times, a step of registering the memory cell as a defective bit may be further included. As a result, it is possible to operate except memory cells that cannot be toggle-written.

In another aspect of the present invention, a method for manufacturing a magnetic random access memory includes: a step of manufacturing a chip body of a magnetic random access memory; and a write current of a preset current value in the chip body with respect to a memory cell. Writing data, determining whether the data has been written to the memory cell, and rewriting the data to the memory cell if the data is not written, Until the data is written to the memory cell, the step of repeatedly executing the determining step and the rewriting step, current information (n value) indicating the current value when the data is written, and the At least one of the number of times information (n value) indicating the number of write operations until data is written And storing, for a plurality of memory cells to be tested, and a step of performing all of the steps step above. Here, the magnetic random access memory includes a memory cell including a free magnetic layer in which two or more magnetic layers antiferromagnetically coupled via a nonmagnetic layer are stacked, a first wiring extending in a first direction, Second wiring extending in a second direction different from the first direction. The direction of the easy magnetization axis of the free magnetic layer is different from the first direction and the second direction. Since current information indicating the current value at which writing has been performed or frequency information indicating the number of write operations corresponding to the current value is acquired, inspection related to writing in toggle-type and direct-type MRAM at the manufacturing stage is appropriately performed. be able to.
In the method of manufacturing the magnetic random access memory, the writing step includes a step of executing a read operation on the memory cell, and a write of the data to the memory cell by a toggle write method based on a result of the read operation. Performing the operation. The step of rewriting comprises the step of rewriting the data to the memory cell by the toggle writing method when the data is not correctly written. According to the present invention, it is possible to properly perform the inspection relating to the toggle writing at the manufacturing stage, particularly for the toggle type MRAM.
The step of writing may include a step of performing a data write operation on the memory cell by a direct write method. The step of rewriting may include a step of rewriting the data to the memory cell by the direct writing method when the data is not written. As a result, it is possible to appropriately perform inspection relating to toggle writing at the manufacturing stage, particularly for the direct MRAM.
The step of rewriting may include the step of performing the data write operation again on the memory cell with the same write current as when the data write operation was performed last time. In addition, the step of rewriting may include a step of performing the data write operation on the memory cell again with a different write current from the previous data write operation. The step of rewriting with a different current may include the step of rewriting the data to the memory cell with a smaller write current than when the data was written last time.
Further, the method may further include a step of resetting the current value of the write current in the chip body based on the current information (n value) of the plurality of memory cells to be inspected. Since the default value of the write current is reset so as to correspond to the written current value, a toggle type MRAM with a more stable write operation can be manufactured.
Moreover, it is preferable to further comprise a step of classifying the chip body based on the number of times information (n value) of the plurality of memory cells to be inspected. Since classification is performed according to the number of write operations, toggle-type MRAMs classified into classes corresponding to operation speeds can be manufactured.

In another aspect of the present invention, a method for testing a magnetic random access memory includes a step of writing data to a memory cell with a write current having a preset current value in a chip body of the magnetic random access memory; Determining whether the data has been written to the memory cell, rewriting the data to the memory cell if the data has not been written, and writing the data to the memory cell. The step of repeatedly executing the determining step and the rewriting step, the current information (n value) indicating the current value when the data is written, and the writing until the data is written Storing at least one of frequency information (n value) indicating the number of operations, and a plurality of memos to be inspected For cells, and a step of performing all of the steps above. Here, the magnetic random access memory includes a memory cell including a free magnetic layer in which two or more magnetic layers antiferromagnetically coupled via a nonmagnetic layer are stacked, a first wiring extending in a first direction, Second wiring extending in a second direction different from the first direction. The direction of the easy magnetization axis of the free magnetic layer is different from the first direction and the second direction.
Here, the writing step includes a step of executing a read operation on the memory cell and a step of writing the data to the memory cell by a toggle write method based on the result of the read operation. The step of rewriting comprises the step of rewriting the data to the memory cell by the toggle writing method when the data is not written. The step of writing may include a step of performing a data write operation on the memory cell by a direct write method. The step of rewriting may include a step of rewriting the data to the memory cell by the direct writing method when the data is not written.
Further, it is preferable that the step of rewriting includes the step of performing the data write operation on the memory cell again with the same write current as when the data write operation was performed last time. In addition, the step of rewriting may include a step of rewriting the data to the memory cell with a different write current from the previous data write operation. In this case, it is preferable that the step of rewriting with a different write current includes the step of performing the data write operation on the memory cell again with a smaller write current than when the data write operation was performed last time.
The magnetic random access memory inspection method may further include a step of resetting the current value of the write current in the chip body based on the current information (n value) of the plurality of memory cells to be inspected. Good. Further, it is preferable that the method further includes a step of classifying the chip body based on the number of times information (n value) of the plurality of memory cells to be inspected.

In another aspect of the present invention, a magnetic random access memory includes a plurality of first wirings, a plurality of second wirings, a plurality of memory cells, and a write control unit. The plurality of first wirings extend in the first direction. The plurality of second wirings extend in a second direction different from the first direction. The plurality of memory cells are provided corresponding to respective positions where the plurality of first wirings and the plurality of second wirings intersect. The write control unit controls the write operation of the plurality of memory cells. Each of the plurality of memory cells includes a magnetoresistive element. The magnetoresistive element includes a free magnetic layer in which two or more magnetic films are stacked via a nonmagnetic film, and the easy axis direction is different from the first direction and the second direction. When writing data to a selected cell as a memory cell corresponding to a selected first wiring selected from the plurality of first wirings and a selected second wiring selected from the plurality of second wirings, the write control unit selects the selected cell A write operation for writing the data is executed. It is determined whether or not the data has been written to the selected cell. If the data has not been written, the write operation is performed again on the selected cell. In the above magnetic random access memory, the magnitude of the spontaneous magnetization in one direction of the easy axis directions in the free magnetic layer is preferably different from the magnitude of the spontaneous magnetization in the other direction.
In the write operation, the write control unit supplies a first write current to the selected first wiring. Next, a second write current is supplied to the selected second wiring. Thereafter, the first write current is stopped. Next, the second write current is stopped. In the above magnetic random access memory, it is preferable that the write control unit again determines whether or not the data has been written to the selected cell that has performed the write operation again.
In the above magnetic random access memory, the write control unit determines whether or not the data is written to the selected cell until the data is written to the selected cell, and the data is written. If not, it is preferable to repeatedly execute the write operation on the selected cell again. In the magnetic random access memory, when the data is not written, the write control unit preferably performs the write operation again with the same write current as when the previous write operation was performed.
In the magnetic random access memory described above, when the data is not written, the write control unit preferably changes the write current to that different from the previous write operation and performs the write operation again. In the magnetic random access memory, when the data is not written, the write control unit preferably changes the write current to a smaller write current when the previous write operation was performed and performs the write operation again. In the magnetic random access memory, when the data is not written, the write control unit preferably performs the write operation again with the same write current as when the previous write operation was performed. If the data is still not written, it is preferable to perform the write operation again with a different write current from the previous write operation.
In the above magnetic random access memory, it is preferable that the write control unit outputs a signal indicating an alarm when the data is not written even if the write operation is repeated a predetermined number of times. In the magnetic random access memory, when the data is not written even if the write controller repeats the write operation a predetermined number of times, it is preferable to output a signal indicating an alarm for registering the selected cell as a defective bit.

FIG. 1 is a cross-sectional view showing the structure of a typical magnetoresistive element used in a toggle type MRAM. FIG. 2 is a cross-sectional view showing the structure of a typical magnetoresistive effect element used in a toggle type MRAM. FIG. 3 is a top view showing a planar layout of the magnetoresistive effect element of the toggle type MRAM. FIG. 4 is a timing chart of the write current in the toggle operation. FIG. 5 is a diagram illustrating changes in the directions of the first and second free layer magnetizations in the toggle operation. FIG. 6 is a diagram showing a change in the direction of the first and second free layer magnetization in the toggle operation. FIG. 7 is a graph showing the relationship between the write current and the toggled memory cell. FIG. 8 shows the magnetization characteristics of the free layer with respect to the external magnetic field in the easy axis direction. FIG. 9 is a graph expressing the first quadrant of FIG. 7 with respect to the magnetic field. FIG. 10 is a graph showing the relationship between the energy barrier and the magnetic field applied to the selected cell during the write operation. 11A to 11C are diagrams illustrating changes in the directions of the first and second free layer magnetizations in the respective ranges. FIG. 12 is a block diagram showing a configuration of an embodiment of a toggle type MRAM according to the present invention. FIG. 13 is a cross-sectional view showing an example of the configuration of the memory cell in the present invention. FIG. 14 is a cross-sectional view showing an example of the configuration of the magnetoresistive element in the memory cell of the toggle type MRAM of the present invention. FIG. 15 is a top view showing a planar layout of the magnetoresistive effect element in the memory cell of the toggle type MRAM of the present invention. FIG. 16 is a flowchart showing the operation method of the toggle type MRAM of the present invention. FIG. 17 is a flowchart showing a manufacturing method of the toggle type MRAM according to the present invention.

  Embodiments of the MRAM according to the present invention will be described below with reference to the drawings. In the following description, a toggle type MRAM to which the present invention is applied will be described, but the present invention can also be applied to a direct mode type MRAM.

Hereinafter, the configuration of an embodiment of the toggle type MRAM of the present invention will be described with reference to the accompanying drawings.
FIG. 12 is a block diagram showing a configuration of an embodiment of a toggle type MRAM according to the present invention. The toggle type MRAM includes a plurality of write word lines 26, a plurality of read word lines 28, a plurality of bit lines 27, a memory cell array 30, an X decoder 38, a first write current source 39, an X termination circuit 40, a Y decoder 41, a first decoder. 2 includes a write current source 42, a Y termination circuit 44, a sense amplifier 45, a reference potential generation circuit 46, a read determination circuit 50, a counter 51, and a write controller 52.

The write word line 26 is provided so as to extend in the X-axis direction as the first direction, and has one end connected to the X decoder 38 and the other end connected to the X termination circuit 40. The read word line 28 is provided so as to extend in the X-axis direction, and one end is connected to the X decoder 38 and the other end is connected to the X termination circuit 40. The bit line 27 is provided so as to extend in the Y-axis direction as a second direction substantially perpendicular to the X-axis direction, and has one end connected to the Y decoder 41 and the other end connected to the Y termination circuit 44. Yes.
The memory cell array 30 includes a plurality of memory cells 10 arranged in a matrix. The plurality of memory cells 10 are provided corresponding to positions where a plurality of sets of write word lines 26 and read word lines 28 and a plurality of bit lines 27 intersect.
The X decoder 38 selects one read word line 28 from the plurality of read word lines 28 as the selected read word line 28s based on the input of the X address during the read operation of the memory cell 10. During the write operation of the memory cell 10, one write word line 26 is selected from the plurality of write word lines 26 as the selective write word line 26s based on the input of the X address.
First write current source 39, the write operation of the memory cell 10, and supplies the predetermined write current I _WL to the selected write word line 26s. X termination circuit 40, the write operation of the memory cell 10, terminates the write current _{I WL} flowing through the selected write word line 26s. During the read operation of the memory cell 10, and supplies the read current I _R to the selected read word line 28s.
The Y decoder 41 selects one bit line 27 as a selected bit line 27 s from the plurality of bit lines 27 based on the input of the Y address during the read operation and the write operation of the memory cell 10.
A second write current source 42, the write operation of the memory cell 10, and supplies the predetermined write current _{I BL} to the selected bit line 27s. Y termination circuit 44, the write operation of the memory cell 10, terminates the write current _{I BL} flowing through the selected bit line 27s. During the read operation of the memory cell 10, direct the read current I _R from flowing to the selected bit line 27s to the sense amplifier 45.
The reference potential generation circuit 46 outputs a reference potential (eg, the potential of the reference cell) to the sense amplifier 45 when the memory cell 10 is read.
The sense amplifier 45 refers to the potential (= potential of the selected bit line 27s) of the selected cell 10s (the memory cell 10 selected by the selected read word line 28s and the selected bit line 27s) during the read operation of the memory cell 10. The state (data, “0” or “1”) of the selected cell 10 s is detected by comparing the output potential of the potential generation circuit 46.
The read determination circuit 50 compares the data to be written from the write controller 52 with the data read from the sense amplifier 45. If both data are the same, it is determined that the writing is successful. Then, a write signal is output to the write controller 52 in order to execute data write of the next memory cell. When both data are different, it is determined that the writing has failed. Then, a rewrite signal is output to the write controller 52 in order to execute data write to the same memory cell again.
The counter 51 stores the number n of data writes to the same memory cell under the control of the write controller 52.
The write controller 52 includes an X decoder 38, a first write current source 39, an X termination circuit 40, a Y decoder 41, a second write current source 42, and a Y termination circuit 44 based on an address signal and a control signal including data to be written. Controls to perform a toggle write operation. Then, based on the rewrite signal of the read determination circuit 50, the value of the write current is changed to execute the toggle write operation again to the same memory cell. When the read determination circuit 50 outputs a write signal, the toggle write operation of data to the next memory cell is controlled. Current information indicating a current value when data in each memory cell is written in an internal storage unit (not shown), and count information indicating the number of toggle write operations until data is written. Store at least one of them.

FIG. 13 is a cross-sectional view showing an example of the configuration of the memory cell in the present invention. Memory cell 10 includes a magnetoresistive effect element 25 and a MOS transistor 36.
The MOS transistor 36 has a source 36 a, a gate 36 b and a drain 36 c and is embedded in the p-type semiconductor substrate 20. The source 36 a is formed as an N-type diffusion layer of the semiconductor substrate 20 and is grounded via a contact 19-1 and a third metal layer 23 extending on the semiconductor substrate 20. The gate 36 b is provided on the semiconductor substrate 20 via the insulating film 24, and is connected to the read word line 27. The drain 36 c is formed as an N-type diffusion layer of the semiconductor substrate 20, and has a magnetoresistive effect via contacts 19-2 to 19-4 extending on the semiconductor substrate 20, the first and second metal layers 21 and 22, and the lower electrode 18. It is connected to one end of the element 25. The other end of the magnetoresistive effect element 47 is connected to the bit line 27 through the cap layer 5. A write word line 26 is disposed in the vicinity (a position where electrical interaction is possible and magnetic interaction is possible) near the lower side (semiconductor substrate 20 side) of the magnetoresistive effect element 47.
The magnetoresistive effect element 25 will be further described. FIG. 14 is a cross-sectional view showing an example of the configuration of the magnetoresistive element in the memory cell of the toggle type MRAM of the present invention. The magnetoresistive element 25 is provided between the bit line 27 and the write word line 26. A free layer 1, a barrier layer 2, a pinned layer 3, and an antiferromagnetic layer 4 are included. The free layer 1 includes a first magnetic film 11 + first nonmagnetic film 12 + second magnetic film 13 + second nonmagnetic film 14 + third magnetic film 15 + third nonmagnetic film 16 + fourth magnetic film 17 + ... + Nth nonmagnetic film. (N ≧ 2, where N is a natural number) has a structure in which two or more magnetic films are stacked via a nonmagnetic film. Each magnetic film is antiferromagnetically coupled through a nonmagnetic film.
Increasing the number of free layers (N ≧ 3) also has the effect of improving thermal disturbance resistance due to an increase in volume.

  FIG. 15 is a top view showing a planar layout of the magnetoresistive effect element in the memory cell of the toggle type MRAM of the present invention. The magnetization easy axis direction of the free layer 1 of the magnetoresistive effect element 25 is arranged to be approximately 45 ° when viewed from the X direction in which the write word line 26 extends and the Y direction in which the bit line 27 extends. Yes.

Next, an operation method of the toggle type MRAM of the present invention will be described.
FIG. 16 is a flowchart showing the operation method of the toggle type MRAM of the present invention. This operation is executed by data writing in the case of normal use and data writing in the case of inspection.

(1) Step S01
A control signal indicating an instruction to write data to the selected cell 10 s designated by the X address and the Y address is input to the write controller 52. The write controller 52 resets the counter 51 so that n = 0.
However, in the case of a direct mode type MRAM, n = 1.
(2) Step S02
The write controller 52 reads the value n of the counter 51. When n> 0 (S02: Yes), the process proceeds to step S03, and when n = 0 (S02: No), the process proceeds to step S04. However, in the case of a direct mode type MRAM, this step is skipped, and in all cases, the process proceeds to step S03.
(3) Step S03
The write controller 52 writes to the selected cell 10s by a toggle operation. Specifically, the X address is output to the X decoder 38, the Y address is output to the Y decoder 41, and the control signal is output to the first write current source 39, the second write current source 42, the X termination circuit 40, and the Y termination circuit 44, respectively. To do. X decoder 38 supplies the write current _{I WL} to the selected write word line 26s. Then, Y decoder 41, and supplies a write current _{I BL} to the selected bit line 27s. Thereafter, the X decoder 38 stops supplying the write current _IWL . Subsequently, the Y decoder 41 stops supplying the write current _IBL . However, in the case of the direct mode type MRAM, direct mode writing is performed to the selected cell 10s.
(4) Step S04
The write controller 52 reads data written to the selected cell 10s. Specifically, the X address is output to the X decoder 38, the Y address is output to the Y decoder 41, and the control signal is output to the first write current source 39 and the Y termination circuit 44, respectively. X decoder 38 supplies the read current _{I R} to the selected read word line 28s. Read current _{I R} is passed through the selected cell 10s, it flows through the selected bit line 27s selected by Y decoder 41 to the Y termination circuit 44. At that time, the sense amplifier 45 compares the potential of the selected bit line 27 s with the potential of the reference potential generation circuit 46 and outputs the read data.
(5) Step S05
The read determination circuit 50 determines whether the write data received from the write controller 52 and the data read by the sense amplifier 45 are equal. If equal (S05: Yes), a write signal for executing the next data write is output to the write controller 52. The write controller 52 stores a count value n when writing to the memory cell is successful. n corresponds to the number of toggle write attempts. Since n is also related to the write current value (described later), it corresponds to the current value. If they are not equal (S05: No), it is necessary to execute rewriting, and a rewriting signal for that purpose is output to the writing controller 52.
(6) Step S06
The write controller 52 counts up the counter 51 and sets n = n + 1.
(7) Step S07
The write controller 52 determines whether n exceeds a preset maximum value n _max of n (n> n _max ). When n> n _max (S07: Yes), the process proceeds to step S09, and when n ≦ n _max (S07: No), the process proceeds to step S08.
(8) Step S08
The write controller 52 changes the data write condition. The write condition is set as follows, for example, corresponding to the value of n.
n = 1: Write current I _WL = Write current I _BL = Default value n = 2: Write current I _WL = Write current I _BL = Default value n = 3: Write current I _WL = Write current I _BL = Default value × 0 .9
n = 4: write current IWL = write current I _BL = default value × 0.8 n = 5: write current I _WL = write current I _BL = default value × 0.7
n = 6: write current I _WL = write current I _BL = default value × 1.1
n = 7: write current I _WL = write current I _BL = default value × 1.2
………
n = n _max : .........
Thereafter, the process proceeds to step S02. However, the correspondence table between n and the write current is stored in a storage unit (not shown) of the write controller 52.
(9) Step S09
When the writing operation is performed in the inspection before shipping such as the shipping inspection (S09: Yes), the writing controller 52 proceeds to step S10. When it is not carried out by such inspection (S09: No), the process proceeds to step S11.
(10) Step S10
The write controller 52 outputs, via the read determination circuit 50, that the toggle type MRAM is defective, and registers the defect.
(11) Step S11
The write controller 52 outputs, through the read determination circuit 50, a failure sign alarm indicating that there is a defective memory cell in the toggle type MRAM. At this time, n _max may be changed from that at the time of shipping inspection.
As described above, the operation method of the toggle type MRAM of the present invention is executed.

In step S08, an accidental error due to thermal disturbance can be eliminated by making the write current I _WL and the write current I _{BL the} same at n = 2. This is because an accidental error due to a thermal disturbance is likely to be corrected by rewriting the same current. Therefore, first, rewriting is performed with the same default write current.

In step S08, when n = 3 to 5, the write current I _WL and the write current I _BL are lowered to reduce the magnetic field applied to the memory cell. That is, the magnetic field was in range A ₂ of the original Figure 10, will be closer to the range A _3, it is possible to increase the energy barrier. Therefore, it is preferable for a small memory cell in the saturation magnetic field H _s (easily enters the application range A ₂ magnetic field to be) to reduce the write current.

In step S08, increasing the write current I _WL and the write current I _BL at n = 6 to 7 increases the magnetic field applied to the memory cell. That is, the magnetic field was in the range A ₁ of the original Figure 10, will be closer to the range A _3, it is possible to increase the energy barrier. Therefore, it is preferred for big memory cell (magnetic field applied is likely to be caused in the range A ₁₎ of the flop field H _f to increase the write current.

The setting of the write current in step S08 in the operation method of the toggle type MRAM of the present invention is not limited to the above example. For example, the write current I _WL and the write current I _BL may be set to different values, or one may be increased and the other decreased. As a result, a more optimal magnetic field can be set, and the generation amount of malfunction during toggle write operation can be further reduced. As described above, the toggle-type MRAM can change the write current step by step as necessary. This is because it is not necessary to consider the influence of the magnetic field due to the write current on the half-selected cell. In the conventional typical MRAM, since the magnetic field due to the write current is affected by the half-selected cell, the write current once set cannot be changed stepwise as necessary.

In the above example, the count value or write current value stored for each memory cell is managed for each memory cell, but it is averaged for one column or one row or approximated to the average value. May be managed. Alternatively, averaging may be performed for each predetermined block or approximated to a close value and managed.

  In the present invention, the anisotropic magnetic field and the antiferromagnetic coupling magnetic field are determined only by the resistance to thermal disturbance during holding without considering the reduction of the energy barrier during writing. Assuming that a malfunction occurs with a certain probability due to the lowering of the energy barrier during writing, each writing operation is checked to see if it has been written normally. If the frequency of malfunctions due to thermal disturbance is sufficiently low, normal writing can be performed by rewriting several times at most. Furthermore, the probability of normal writing can be increased by changing the current value at the time of rewriting.

Next, a manufacturing method of the toggle type MRAM of the present invention will be described.
FIG. 17 is a flowchart showing a manufacturing method of the toggle type MRAM according to the present invention.
(1) Step S21
A toggle MRAM chip body (not shown) is manufactured by a conventionally known semiconductor manufacturing process. That is, the outline will be described with reference to FIG. 13. First, the MOS transistor 36 is formed on the semiconductor substrate 20. Next, contacts (vias) 19-1 to 19-4 and first to third metal layers 21 to 23 are formed to connect the MOS transistor 36 and the base electrode 18 while the interlayer insulating film is formed. . A write word line 26 is formed. Thereafter, the magnetoresistive element 25 having the antiferromagnetic layer 4, the pinned layer 3, the barrier layer 2, the free layer 1 made of an N (≧ 2) magnetic film, and the cap layer 5 are formed on the lower electrode 18. It is formed. Subsequently, the bit line 27 is formed. A circuit for executing the rewrite algorithm is provided in the periphery of the cell array.
(2) Step S22
The inspection of the toggle MRAM chip body is performed by the inspection device. The inspection method executes the operation method of the toggle type MRAM of the present invention shown in FIG. At that time, Step S09 is Yes.
(3) Step S23
The operation method of the toggle type MRAM in step S22 is executed for all the memory cells to be inspected in the chip body. However, when performing failure registration in step S10, step S22 may be terminated at that time and the process may proceed to step S24.
(4) Step S24
The distribution of values of n the stored toggle MRAM to the write controller 52, the respective current value of the write current toggle MRAM I _WL and the write current I _BL is reset as needed. Then, the toggle type MRAM class is determined.

Here, the resetting of the current values of the write current I _WL and the write current I _BL is performed as follows, for example. When n = 4 in most memory cells, the current values of the write current I _WL and the write current I _BL are reset to the default value × 0.8. By performing such resetting, the value of the write current can be optimized for each toggle type MRAM. Thereby, it is possible to reduce the number of times of re-execution of writing during the writing operation. Such determination and resetting of values for resetting may be performed for each toggle type MRAM or for each manufacturing lot. In that case, the resetting time can be further shortened.

  The class of the toggle type MRAM is classified into a lower-level class when, for example, the value of n varies or when there are many n having a large value. When the values of n are substantially equal, or when there are many small values of n, the class is classified into a higher hierarchy class. In this case, a higher hierarchy class has a higher writing speed. A lower hierarchy class has a slower writing speed.

  As described above, the toggle type MRAM manufacturing method of the present invention is executed.

In the above embodiments, the toggle type MRAM to which the present invention is applied has been described. However, the direct mode type MRAM is similarly formed, and the same effect as that of the toggle type MRAM can be obtained.
According to the present invention, it is possible to prevent malfunction due to thermal disturbance in the toggle writing operation without increasing power consumption.

Claims (29)

Providing a magnetic random access memory;
Here, the magnetic random access memory is
A plurality of first wires extending in a first direction;
A plurality of second wirings extending in a second direction different from the first direction;
A plurality of memory cells formed at intersections of the plurality of first wirings and the plurality of second wirings, and each of the plurality of memory cells is antiferromagnetically coupled through a nonmagnetic layer. Including a free magnetic layer in which two or more magnetic layers are laminated, and the direction of the easy axis of the free magnetic layer is different from the first direction and the second direction,
Writing data to a specific memory cell as one of the plurality of memory cells under a predetermined write condition;
Rewriting the data to the specific memory cell while resetting the write condition until the data is correctly written to the specific memory cell when the data is not correctly written to the specific memory cell. Method of operating magnetic random access memory. The operation method of the magnetic random access memory according to claim 1,
The step of writing comprises:
Reading stored data from the specific memory cell;
A method of operating the magnetic random access memory, comprising: writing the data to the specific memory cell by a toggle writing method based on the read data. The operation method of the magnetic random access memory according to claim 1,
The step of writing comprises:
A method of operating a magnetic random access memory, comprising the step of writing the data to the specific memory cell by a direct write method. The operation method of the magnetic random access memory according to claim 1, wherein the step of repeatedly writing comprises:
Counting the number of times the data has not been correctly written to the specific memory cell;
Resetting the write condition determined based on the count. A method of operating a magnetic random access memory. The operation method of the magnetic random access memory according to claim 4,
The specific memory is associated with a first specific wiring as one of the plurality of first wirings and a second specific wiring as one of the plurality of second wirings, and the write condition is: An operation method of a magnetic random access memory, which is a write current value flowing through a first specific wiring and the second specific wiring. The operation method of the magnetic random access memory according to claim 5,
The resetting step includes:
A method of operating a magnetic random access memory, comprising the step of resetting the same write current value as when the data write operation was performed last time when the count is in the first range. The operation method of the magnetic random access memory according to claim 6,
The resetting step includes:
A method of operating a magnetic random access memory, comprising the step of resetting the write current value smaller than when the data was written last time when the count is in a second range larger than the first range. The operation method of the magnetic random access memory according to claim 6,
The resetting step includes:
A method of operating a magnetic random access memory, comprising the step of resetting the write current value that is larger than the previous data write operation when the count is in a third range that is greater than the first range. The operation method of the magnetic random access memory according to any one of claims 4 to 8,
A method of operating a magnetic random access memory, further comprising the step of outputting a signal indicating an alarm when the count reaches a predetermined value. The operation method of the magnetic random access memory according to any one of claims 4 to 9,
A method of operating a magnetic random access memory, further comprising storing the count in association with the specific memory cell when the data is correctly written. Formed at intersections of a plurality of first wirings extending in a first direction, a plurality of second wirings extending in a second direction different from the first direction, and the plurality of first wirings and the plurality of second wirings. A plurality of memory cells, each of the plurality of memory cells including a free magnetic layer in which two or more magnetic layers coupled antiferromagnetically through a nonmagnetic layer are stacked, and the free magnetic layer The direction of the easy axis of the magnetic random access memory is different from the first direction and the second direction,
Writing data to a specific memory cell as one of the plurality of memory cells under a predetermined write condition;
Repetitively writing the data to the specific memory cell while resetting the write condition until the data is correctly written to the specific memory cell when the data is not correctly written to the specific memory cell;
A method for testing a magnetic random access memory, comprising: storing data related to the write condition as test result data in the memory cell when the data is correctly written to the specific memory cell. The magnetic random access memory inspection method according to claim 11,
The step of writing comprises:
Reading stored data from the specific memory cell;
And a step of writing the data to the specific memory cell by a toggle write method based on the read data. The method of manufacturing a magnetic random access memory according to claim 12,
The writing step includes:
An inspection method for a magnetic random access memory comprising a step of writing the data to the specific memory cell by a direct write method. In the inspection method of the magnetic random access memory according to any one of claims 11 to 13,
The step of repeatedly writing includes:
Counting the number of times the data has not been correctly written to the specific memory cell;
And a step of resetting the write condition determined based on the count. The inspection method of the magnetic random access memory according to claim 14,
The specific memory is associated with a first specific wiring as one of the plurality of first wirings and a second specific wiring as one of the plurality of second wirings, and the write condition is: A method for inspecting a magnetic random access memory, which is a write current value flowing through a first specific wiring and the second specific wiring. The inspection method of the magnetic random access memory according to claim 14 or 15,
A method for inspecting a magnetic random access memory, further comprising the step of registering the specific memory cell as defective when the count reaches a predetermined value. The inspection method of the magnetic random access memory according to claim 14 or 15,
An inspection method for a magnetic random access memory, further comprising the step of resetting the predetermined write condition based on the inspection result data for at least some of the plurality of memory cells. The method for inspecting a magnetic random access memory according to claim 11,
A test method for a magnetic random access memory, further comprising the step of grouping the magnetic random access memory into one of a plurality of classes based on the test result data of the plurality of memory cells. A plurality of first wires extending in a first direction;
A plurality of second wirings extending in a second direction different from the first direction;
A plurality of memory cells formed at intersections of the plurality of first wirings and the plurality of second wirings, and each of the plurality of memory cells is antiferromagnetically coupled through a nonmagnetic layer. Including a free magnetic layer in which two or more magnetic layers are laminated, and the direction of the easy axis of the free magnetic layer is different from the first direction and the second direction,
A write control unit for controlling a data write operation to the plurality of memory cells,
During the data write operation, a first selection wiring is selected from the plurality of first wirings and a second selection wiring is selected from the plurality of second wirings, and the selection cell of the plurality of memory cells is a first selection wiring. Associated with the second selected wiring,
The write control unit
Write data to the selected cell under predetermined write conditions,
A magnetic random access memory in which when the data is not correctly written to the specific memory cell, the data is repeatedly written to the selected cell while resetting the write condition until the data is correctly written. The magnetic random access memory according to claim 19,
A magnetic random access memory in which the magnitude of spontaneous magnetization in one direction of the easy axis direction in the free magnetic layer is different from the magnitude of spontaneous magnetization in the other direction. The magnetic random access memory according to claim 19 or 20,
The write operation is
The write control unit supplies a first write current to the first selection wiring, then supplies a second write current to the second selection wiring, and then stops the first write current, A magnetic random access memory that is an operation of stopping the second write current. The magnetic random access memory according to any one of claims 19 to 21,
The write control unit
A counter that counts the number of times the data has not been written correctly;
A table for defining a relationship between the count and the write condition;
The write control unit
A magnetic random access memory that resets the write condition with reference to the table based on the count and writes the data to the selected memory cell under the reset write condition. The magnetic random access memory according to claim 22,
The magnetic random access memory, wherein the write condition is a write current value flowing through the first selection wiring and the second selection wiring. The magnetic random access memory according to claim 23,
The write control unit
A magnetic random access memory that resets the same write current value as when the previous data write operation was performed when the count is in the first range. 25. The magnetic random access memory according to claim 24.
The write control unit
A magnetic random access memory that resets the write current value smaller than when the data was written last time when the count is in a second range that is larger than the first range. 25. The magnetic random access memory according to claim 24.
The write control unit
A magnetic random access memory that resets the write current value that is larger than that of the previous data write operation when the count is in a third range that is greater than the first range. The magnetic random access memory according to claim 22,
The write control unit
A magnetic random access memory that outputs a signal indicating an alarm when the data is not written even after a predetermined number of write operations. The magnetic random access memory according to claim 22,
The write control unit
A magnetic random access memory that outputs a signal indicating an alarm for registering the selected cell as a defective bit when the data is not written even after a predetermined number of write operations. Manufacturing a magnetic random access memory;
Here, the magnetic random access memory is
A plurality of first wires extending in a first direction;
A plurality of second wirings extending in a second direction different from the first direction;
A plurality of memory cells formed at intersections of the plurality of first wirings and the plurality of second wirings, and each of the plurality of memory cells is antiferromagnetically coupled through a nonmagnetic layer. Including a free magnetic layer in which two or more magnetic layers are laminated, and the direction of the easy axis of the free magnetic layer is different from the first direction and the second direction,
A method for manufacturing a magnetic random access memory, comprising the step of inspecting the magnetic random access memory according to claim 11.

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