JPWO2004075202A1 - Voltage detection circuit, semiconductor device, and voltage detection circuit control method - Google Patents

Abstract

A voltage detection circuit that suppresses voltage fluctuations due to off-leakage current of transistors and accurately detects voltage. The voltage detection circuit (17) includes first and second capacitors (C1, C2), first and second transistors (Tn1, Tn2), a comparator (21), and a control circuit (22). The capacitors (C1, C2) are connected in series, and a divided voltage (div) corresponding to the high voltage (VPP) is generated by the capacitors (C1, C2). When each transistor (Tn1, Tn2) is turned on, the potential of the connection portion (N1) between the first capacitor and the second capacitor is reset to the ground potential. When the potential of the connection portion (N1) reaches a predetermined potential, the second transistor (Tn2) is turned off and then the first transistor (Tn1) is turned off.

Description

The present invention relates to a voltage detection circuit that detects an output voltage of a voltage generation circuit mounted on a semiconductor device, a semiconductor device, and a control method for the voltage detection circuit.
Some semiconductor devices include a voltage generation circuit that generates an internal voltage different from a power supply voltage supplied from the outside and supplies the internal voltage to the internal circuit. The semiconductor device is provided with a voltage detection circuit that detects the output voltage of the voltage generation circuit. Specifically, in the voltage detection circuit, the divided voltage corresponding to the output voltage of the voltage generation circuit is compared with the reference voltage, and it is detected that the output voltage has reached the target voltage level based on the comparison result. In a voltage detection circuit, a voltage detection resistor is generally used as an element for generating a divided voltage. However, since a current always flows through the voltage dividing resistor, a voltage detection circuit using a capacitor instead of the voltage dividing resistor has been put into practical use in a semiconductor device (for example, a nonvolatile memory) that requires low power consumption. . In the voltage detection circuit, a technique for accurately detecting the voltage based on the capacitance ratio is required.

FIG. 13 shows a conventional voltage detection circuit 31, and FIG. 14 shows an operation waveform diagram thereof.
The voltage detection circuit 31 is a circuit for detecting the output voltage VPP of the voltage generation circuit 32 and controlling the voltage VPP to be a target voltage value. The voltage detection circuit 31 includes two capacitors (capacitors) C1 and C2, which are connected in series, a comparator 21, and an NMOS transistor Tn1.
The capacitors C1 and C2 are provided to divide the output voltage VPP of the voltage generation circuit 32. A divided voltage (voltage at the connection portion N1 of the capacitors C1 and C2) div by the capacitors C1 and C2 is supplied to the non-inverting input terminal of the comparator 21, and a reference voltage Vref (for example, 1.3 V) is supplied. It is supplied to the inverting input terminal of the comparator 21.
The drain of the NMOS transistor Tn1 is connected to the connection portion N1 of the capacitors C1 and C2, and the source of the transistor Tn1 is connected to the ground GND. The reset signal RST is supplied to the gate of the NMOS transistor Tn1.
As shown in FIG. 14, at the start of voltage detection by the voltage detection circuit 31, the NMOS transistor Tn1 is turned on by the H level reset signal RST, and the divided voltage div by the capacitors C1 and C2 is initially set to the ground potential (0 V). It becomes. At time t1, the reset signal RST is inverted to L level and the transistor Tn1 is turned off, so that the connection portion N1 of the capacitors C1 and C2 enters a floating state. After time t1, the divided voltage div by the capacitors C1 and C2 changes according to the output voltage VPP. That is, when the output voltage VPP increases with the boosting operation in the voltage generation circuit 32, the divided voltage div also increases with the degree of change corresponding to the capacitance ratio of the capacitors C1 and C2.
The comparator 21 compares the divided voltage div with the reference voltage Vref and outputs an output signal COM having a voltage level corresponding to the comparison result. That is, the comparator 21 outputs the L level output signal COM when the divided voltage div is lower than the reference voltage Vref, and outputs the H level output signal COM when the divided voltage div becomes equal to or higher than the reference voltage Vref. To do. Based on the output signal COM, the output voltage of the voltage generation circuit 32 is controlled to become a target voltage value.
As described above, a voltage detection circuit that performs voltage detection based on a capacitance ratio is disclosed in, for example, Japanese Patent Application Laid-Open No. 2002-51538.
JP 2002-51538 A

By the way, in a nonvolatile semiconductor memory device, data writing and erasing are performed using semiconductor properties of breakdown characteristics and tunneling characteristics. Specifically, in a nonvolatile memory, a high voltage (for example, 10 V) or a negative voltage (for example, −10 V) higher than a power supply voltage (for example, 3 V) is generated by a voltage generation circuit, and the high voltage or the negative voltage is generated as a word. Data is written or erased by applying the voltage to a line or the like.
In the nonvolatile memory, the voltage detection circuit 31 having the circuit configuration shown in FIG. 13 is used to control the output voltage of the voltage generation circuit to a predetermined voltage (high voltage = 10 V, negative voltage = −10 V). Since the voltage detection circuit 31 is configured to detect voltage based on the capacitance ratio, power consumption is reduced compared to a voltage detection circuit that detects voltage based on the resistance ratio.
However, in the voltage detection circuit 31, the output voltage VPP fluctuates due to the tailing current (referred to as subthreshold current or off-leakage current) flowing through the NMOS transistor Tn1 for initializing the divided voltage div. Occurs.
Specifically, when the output voltage VPP of the voltage generation circuit 32 reaches a target voltage value, the divided voltage div in the voltage detection circuit 31 becomes equal to the reference voltage Vref (1.3 V). At this time, the transistor Tn1 is turned off by the L level reset signal RST, but since a divided voltage div equal to the reference voltage Vref is applied between the source and the drain, a minute leak current flows. As described above, the off-leakage current flows through the transistor Tn1, so that the divided voltage div becomes lower than the reference voltage Vref. In this case, since the voltage generation circuit 32 continues the boosting operation even when the output voltage VPP reaches the target voltage value, the output voltage VPP becomes higher than necessary.
Such a phenomenon does not pose a problem if the voltage detection operation time in the voltage detection circuit 31 is relatively short with respect to the decrease in the output voltage VPP due to the off-leakage current. However, a data write operation and an erase operation in the nonvolatile memory require a time (several tens of ms) that is several thousand times longer than a read operation time (several tens of ns). Therefore, in a semiconductor device that requires a long time for the voltage detection operation, such as a nonvolatile memory, there arises a problem that the output voltage VPP of the voltage generation circuit 32 becomes higher than necessary due to the off-leak current of the transistor Tn1. .
An object of the present invention is to provide a voltage detection circuit, a semiconductor device, and a voltage detection circuit control method capable of suppressing voltage fluctuation due to an off-leak current of a transistor and accurately performing voltage detection.

In a first aspect of the present invention, a voltage detection circuit connected to a voltage generation circuit and detecting an output voltage of the voltage generation circuit is provided. The voltage detection circuit receives the output voltage and generates a divided voltage corresponding to the output voltage, and a first capacitor and a second capacitor connected in series, and a first between the first capacitor and the second capacitor. A first transistor connected to the connecting portion; a second transistor connected in series to the first transistor; and a control circuit. When the first transistor and the second transistor are activated, the potential of the first connection portion is initialized to the initial potential. The control circuit is connected to the first transistor and outputs a first control signal for deactivating the first transistor after initialization of the potential of the first connection portion after the second transistor. Generate.
In a second aspect of the present invention, a voltage detection circuit connected to a voltage generation circuit and detecting an output voltage of the voltage generation circuit is provided. A voltage detection circuit receives the output voltage and generates a divided voltage corresponding to the output voltage, and a first capacitor and a second capacitor connected in series, and a connection between the first capacitor and the second capacitor A transistor that initializes the potential of the connection portion to an initial potential, and a control signal that is connected to the transistor and has a negative potential lower than the initial potential when the potential of the connection portion is initialized. And a control circuit that activates the transistor by the control signal.
In a third aspect of the present invention, a voltage detection circuit connected to a voltage generation circuit and detecting a negative voltage generated by the voltage generation circuit is provided. The voltage detection circuit receives the negative voltage and generates a divided voltage corresponding to the negative voltage, and a connection between the first capacitor and the second capacitor connected in series, and the first capacitor and the second capacitor And a transistor that initializes the potential of the connection portion to an initial potential. The gate of the transistor receives a control signal, its source receives the initial potential, and its drain connected to the connection.
In a fourth aspect of the present invention, a voltage detection circuit connected to a voltage generation circuit and detecting an output voltage of the voltage generation circuit is provided. A voltage detection circuit receives the output voltage and generates a divided voltage according to the output voltage, and a connection between the first capacitor and the second capacitor connected in series, and the first capacitor and the second capacitor And a transistor that initializes the potential of the connection portion to an initial potential. The gate of the transistor receives a control signal, its source receives an inverted signal of the control signal, and its drain is connected to the connection.
The voltage detection circuit and the voltage generation circuit shown in the first to fourth aspects are preferably provided in a semiconductor device.
In a fifth aspect of the present invention, a method for controlling a voltage detection circuit is provided. The voltage detection circuit is provided inside the semiconductor device including the voltage generation circuit, and detects a voltage generated by the voltage generation circuit. The voltage detection circuit includes a first capacitor and a second capacitor connected in series, a first transistor connected to a first connection portion between the first capacitor and the second capacitor, and a series connection to the first transistor. And a connected second transistor. The control method uses the first and second capacitors to generate a divided voltage according to the output voltage of the voltage generation circuit, activates the first transistor and the second transistor, and After initializing the potential of the first connection portion to an initial potential, and after initializing the potential of the first connection portion, only the second transistor is deactivated, and the first transistor and the second transistor are When the potential of the first connection portion reaches a predetermined potential according to the output voltage of the voltage generation circuit, Deactivating the first transistor.
In a sixth aspect of the present invention, a method for controlling a voltage detection circuit is provided. The voltage detection circuit is provided inside the semiconductor device including the voltage generation circuit, and detects a voltage generated by the voltage generation circuit. The voltage detection circuit includes a first capacitor and a second capacitor connected in series, and a transistor connected to a connection portion between the first capacitor and the second capacitor. The control method uses the first and second capacitors to generate a divided voltage corresponding to the output voltage of the voltage generation circuit, activates the transistor, and sets the potential of the connection portion to an initial potential. Initializing. The initializing step generates a control signal having a negative potential lower than the initial potential and supplies the control signal to the gate of the transistor.
In a seventh aspect of the present invention, a method for controlling a voltage detection circuit is provided. The voltage detection circuit is provided inside the semiconductor device including the voltage generation circuit, and detects a voltage generated by the voltage generation circuit. The voltage detection circuit includes a first capacitor and a second capacitor connected in series, and a transistor connected to a connection portion between the first capacitor and the second capacitor. The control method includes a step of generating a divided voltage according to the output voltage of the voltage generation circuit using the first and second capacitors, activating the transistor, and setting the potential of the connection portion to an initial potential. And a step of supplying a potential higher than the initial potential to the gate of the transistor to inactivate the transistor after the initialization of the potential of the connection portion.
In an eighth aspect of the present invention, a voltage detection circuit control method is provided. The voltage detection circuit is provided inside the semiconductor device including the voltage generation circuit, and detects a voltage generated by the voltage generation circuit. The voltage detection circuit includes a first capacitor and a second capacitor connected in series, and a transistor connected to a connection portion between the first capacitor and the second capacitor. The control method uses the first and second capacitors to generate a divided voltage corresponding to the output voltage of the voltage generation circuit, activates the transistor, and sets the potential of the connection portion to an initial potential. After the initializing step and initialization of the potential of the connection portion, when the transistor is deactivated, the same potential as or higher than that of the connection portion is supplied to the source of the transistor Steps.

FIG. 1 is a schematic block diagram showing a semiconductor device according to the first embodiment of the present invention.
FIG. 2 is a schematic circuit diagram of a voltage detection circuit in the semiconductor device of FIG.
FIG. 3 is a schematic circuit diagram of the control circuit of FIG.
FIG. 4 is an operation waveform diagram of the voltage detection circuit of FIG.
FIG. 5 is a schematic circuit diagram of a voltage detection circuit according to the second embodiment of the present invention.
FIG. 6 is a schematic circuit diagram of a control circuit in the second embodiment of the present invention.
FIG. 7 is an operation waveform diagram of the voltage detection circuit of FIG.
FIG. 8 is a circuit diagram of a voltage detection circuit according to the third embodiment of the present invention.
FIG. 9 is an operation waveform diagram of the voltage detection circuit of FIG.
FIG. 10 is a circuit diagram of a voltage detection circuit according to the fourth embodiment of the present invention.
FIG. 11 is an operation waveform diagram of the voltage detection circuit of FIG.
FIG. 12 is a circuit diagram of a voltage detection circuit according to the fifth embodiment of the present invention.
FIG. 13 is a schematic circuit diagram of a conventional voltage detection circuit.
FIG. 14 is an operation waveform diagram of the voltage detection circuit of FIG.

Hereinafter, a first embodiment in which the present invention is embodied in a semiconductor memory device will be described with reference to the drawings.
FIG. 1 is a schematic block diagram of the semiconductor memory device 11. The semiconductor memory device 11 is a nonvolatile memory, and includes a memory access logic circuit 12, a memory cell array 13, an operation mode control circuit 14, and a power supply circuit 15. The power supply circuit 15 includes a reset generation circuit 16, a voltage detection circuit 17, and a voltage generation circuit 18.
In the semiconductor memory device 11, the control signal CNTL and the address signal Add from the external device are supplied to the logic circuit 12 for memory access, and the control signal CNTL is supplied to the operation mode control circuit 14.
The logic circuit 12 for memory access includes a latch circuit that latches the address signal Add, a decoder that decodes the address signal Add, and the like. One of a plurality of memory cells provided in the memory cell array 13 is accessed by the decode signal generated by the logic circuit 12. In the present embodiment, the memory cells provided in the memory cell array 13 are nonvolatile memory cells.
The operation mode control circuit 14 controls the power supply circuit 15 based on the control signal CNTL. Examples of the control signal CNTL include signals such as a read command, a write command, and an erase command.
When the supplied control signal CNTL is a write command, the operation mode control circuit 14 activates the high voltage generation unit 19 in the voltage generation circuit 18 in response to the write command. At this time, the high voltage generation unit 19 of the voltage generation circuit 18 generates the high voltage VPP and supplies the high voltage VPP to the memory cell array 13.
When the control signal CNTL is an erase command, the operation mode control circuit 14 activates the negative voltage generator 20 in the voltage generator 18 in response to the erase command. At this time, the negative voltage generation unit 20 of the voltage generation circuit 18 generates the negative voltage VBB and supplies the negative voltage VBB to the memory cell array 13.
In the memory cell array 13, the high voltage VPP and the negative voltage VBB supplied from the voltage generation circuit 18 are supplied to a word line connected to the memory cell, a bit line, a well layer constituting a MOS transistor, or the like. By supplying the high voltage VPP and the negative voltage VBB, data is written into and erased from the memory cell.
In the semiconductor memory device 11, when a data write operation or an erase operation is started, a reset is generated prior to activating the high voltage generator 19 and the negative voltage generator 20 in the voltage generator 18. A reset signal RST is supplied from the circuit 16 to the voltage detection circuit 17. In accordance with the reset signal RST, the voltage detection operation in the voltage detection circuit 17 is initialized.
FIG. 2 shows the voltage detection circuit 17. In the figure, a circuit for detecting the high voltage VPP is shown, and a circuit for detecting the negative voltage VBB is not shown.
The voltage detection circuit 17 includes capacitors C1 and C2 as first and second capacitors, a comparator 21 as a determination circuit, a control circuit 22, and NMOS transistors Tn1 and Tn2 as first and second transistors. The high voltage VPP generated by the high voltage generator 19 is detected. The high voltage generator 19 includes a booster circuit 19a and an NMOS transistor Tn10.
In the voltage detection circuit 17, the configurations of the capacitors C1 and C2 and the comparator 21 are the same as those of the conventional voltage detection circuit 31 shown in FIG. That is, the capacitors C1 and C2 are connected in series, and the high voltage VPP that is the output voltage of the high voltage generator 19 is divided by the capacitors C1 and C2. The comparator 21 compares the divided voltage (voltage at the connection portion N1 of the capacitors C1 and C2) div with the reference voltage Vref (for example, 1.3 V) by the capacitors C1 and C2, and according to the comparison result. An output signal COM having a potential level is generated.
The output signal COM of the comparator 21 is supplied to the gate of the NMOS transistor Tn10 in the high voltage generator 19. The drain of the NMOS transistor Tn10 is connected to the output terminal of the booster circuit 19a, and the source of the NMOS transistor Tn10 is connected to the ground GND. The NMOS transistor Tn10 is turned on / off by the output signal COM of the comparator 21 so that the high voltage VPP supplied from the high voltage generator 19 becomes a target voltage value.
Specifically, when the high voltage VPP by the boosting operation of the booster circuit 19a becomes equal to or higher than a target voltage value (for example, 10V), the divided voltage div by the capacitors C1 and C2 becomes equal to or higher than the reference voltage Vref (for example, 1.3V). Thus, the voltage level of the output signal COM of the comparator 21 is increased. The NMOS transistor Tn10 is turned on by the output signal COM of the comparator 21 so that the high voltage VPP becomes a target voltage value.
In the voltage detection circuit 17 of this embodiment, two NMOS transistors Tn1 and Tn2 are provided as elements for initializing the divided voltage div at the start of voltage detection. The NMOS transistors Tn1 and Tn2 are connected in series between the connection portion (first connection portion) N1 of the capacitors C1 and C2 and the ground GND.
The reset signal (first control signal) RST from the reset generation circuit 16 is supplied to the gate of the NMOS transistor Tn2, and the reset signal (second control signal) RSTA of the control circuit 22 is supplied to the gate of the NMOS transistor Tn1. Is done. In the control circuit 22, the reset signal RSTA is generated based on the reset signal RST and the output signal COM of the comparator 21.
FIG. 3 shows a circuit diagram of the control circuit 22.
The control circuit 22 includes PMOS transistors Tp11 and Tp12, an NMOS transistor Tn11, and inverter circuits 23, 24, and 25. The reset signal RST from the reset generation circuit 16 is supplied to the gate of the PMOS transistor Tp11 via the inverter circuit 23, and the output signal COM of the comparator 21 is supplied to the gate of the NMOS transistor Tn11.
The PMOS transistor Tp11 and the NMOS transistor Tn11 are connected in series, the source of the PMOS transistor Tp11 is connected to the power supply VCC, and the source of the NMOS transistor Tn11 is connected to the ground GND. Further, the drain of the PMOS transistor Tp12 is connected to the connection portion between the transistors Tp11 and Tn11, and the source of the transistor Tp12 is connected to the power supply VCC.
The connection portion of each transistor Tp11, Tp12, Tn11 is connected to the gate of the PMOS transistor Tp12 via the inverter circuit 24, and the potential level of the connection portion of each transistor Tp11, Tp12, Tn11 is inverted by the inverter circuit 24. It is supplied to the gate of the PMOS transistor Tp12. Further, the potential level at the connection portion of each transistor Tp11, Tp12, Tn11 is output as the reset signal RSTA via the two inverter circuits 24, 25.
Next, the operation of the voltage detection circuit 17 in this embodiment will be described.
As shown in FIG. 4, at the start of detection of the high voltage VPP, an H level reset signal RST is output from the reset generation circuit 16. At this time, since the output signal COM of the comparator 21 is at the L level, the PMOS transistor Tp11 is turned on and the NMOS transistor Tn11 is turned off in the control circuit 22. Therefore, an H level reset signal RSTA is output from the control circuit 22.
Accordingly, since the NMOS transistors Tn1 and Tn2 are turned on by the H level reset signals RST and RSTA in the voltage detection circuit 17, the divided voltage div by the capacitors C1 and C2 is set to the ground potential (0 V) as the initial potential. It is initialized.
When the reset signal RST changes to L level at time t1, the PMOS transistor Tp11 in the control circuit 22 is turned off. At this time, since the PMOS transistor Tp12 is on and the NMOS transistor Tn11 is off, the control circuit 22 outputs an H level reset signal RSTA.
Accordingly, in the voltage detection circuit 17, the transistor Tn1 is turned on by the H level reset signal RSTA, and the transistor Tn2 is turned off by the L level reset signal RST. When the transistor Tn2 is turned off, the connection portion N1 of the capacitors C1 and C2 enters a floating state, and the divided voltage div by the capacitors C1 and C2 changes according to the high voltage VPP.
At time t1, the booster circuit 19a of the high voltage generator 19 is activated, and the boosting operation by the booster circuit 19a is started. Therefore, after time t1, the high voltage VPP that is the output voltage of the booster circuit 19a is gradually increased. The divided voltage div generated by the capacitors C1 and C2 is also raised with a degree of change corresponding to the capacity ratio.
Since the transistor Tn1 is turned on from time t1 to time t2 (period in which the divided voltage div is increasing), the potential level of the connection portion (second connection portion) N2 between the transistors Tn1 and Tn2 is the divided voltage. Equal to div.
At time t2, when the high voltage VPP reaches the target voltage value and the divided voltage div becomes the reference voltage Vref, the output signal COM of the comparator 21 changes from L level to H level. At this time, in the control circuit 22, the NMOS transistor Tn11 is turned on by the H level output signal COM. Therefore, the reset signal RSTA output from the control circuit 22 changes from H level to L level.
The transistor Tn1 is turned off by the L level reset signal RSTA. Immediately after time t2, the connection N2 of the transistors Tn1 and Tn2 and the divided voltage div are substantially equal, so that an off-leakage current through the NMOS transistor Tn1 hardly flows. On the other hand, in the NMOS transistor Tn2, since a voltage substantially equal to the divided voltage div is applied between the source and the drain, an off-leak current corresponding to the voltage flows. For this reason, the potential level of the connection portion N2 of the transistors Tn1 and Tn2 gradually decreases.
In the voltage detection circuit 17 of the present embodiment, no off-leakage current flows through the NMOS transistor Tn1 until the potential level of the connection portion N2 of the transistors Tn1 and Tn2 is lowered. Therefore, a sufficient time is secured until the divided voltage div is reduced by the off-leakage current (the high voltage VPP deviates from the target voltage value). Specifically, in the voltage application period in which the high voltage VPP needs to be applied for the data write operation, it is possible to prevent the divided voltage div from decreasing due to the off-leak current, and the data in the semiconductor memory device 11 can be prevented. The reliability of the write characteristics is improved.
Next, features of the voltage detection circuit 17 in the first embodiment of the present invention will be described below.
(1) Two NMOS transistors Tn1 and Tn2 are connected in series to the connection portion N1 of the capacitors C1 and C2, and each transistor Tn1 and Tn2 is turned on (activated), whereby a divided voltage (connection portion N1 Voltage div) is reset to the ground potential. Thereafter, the ground-side transistor Tn2 is turned off (inactivated), and the divided voltage div is increased according to the high voltage VPP. When the divided voltage div reaches the reference voltage Vref, the transistor Tn1 is turned off (non-activated). Activated). In this way, no off-leakage current flows through the NMOS transistor Tn1 until the potential level of the connection portion N2 of the transistors Tn1 and Tn2 is lowered due to the off-leakage current of the transistor Tn2. Therefore, a sufficient time can be secured until the divided voltage div decreases and the high voltage VPP deviates from the target voltage value. Therefore, the voltage detection by the voltage detection circuit 17 can be accurately performed during the high voltage application period in the semiconductor memory device 11.
(2) The control circuit 22 generates a reset signal RSTA for controlling the transistor Tn1 based on the reset signal RST for controlling the transistor Tn2 and the output signal COM of the comparator 21. Specifically, in the control circuit 22, the reset signal RSTA is inverted from the H level to the L level at the timing (time t2 in FIG. 4) when the high voltage VPP reaches the target voltage value and the output signal COM becomes the H level. The In this way, the potential of the connection portion N2 of the transistors Tn1 and Tn2 can be made equal to the reference voltage Vref, so that the timing at which the off-leak current of the transistor Tn1 flows (the time when the divided voltage div starts to decrease) is delayed. Is preferable.
(3) In the semiconductor memory device 11, by generating an appropriate high voltage VPP at the time of data writing, the reliability of data writing characteristics can be improved.
Hereinafter, a second embodiment of the present invention will be described with reference to FIGS. In addition, in this embodiment, about the thing equivalent to the structure of 1st Embodiment mentioned above, the same symbol is attached | subjected to drawing and the description is simplified. Below, it demonstrates centering on difference with 1st Embodiment.
As shown in FIG. 5, in the voltage detection circuit 17a of the present embodiment, the connection portion N2 of the transistors Tn1 and Tn2 is connected to the ground GND via a capacitor C3 as a third capacitor. Further, the drain of the NMOS transistor Tn3 as the third transistor is connected to the connection portion N1 of the capacitors C1 and C2, and the source of the NMOS transistor Tn3 is connected to the ground via the capacitor C4 as the fourth capacitor. . A reset signal RSTAB is supplied to the gate of the NMOS transistor Tn3.
In the voltage detection circuit 17a, the capacitance C3 is added to the connection portion N2 of the transistors Tn1 and Tn2, thereby preventing the divided voltage div from being lowered due to the off-leakage current. Here, the capacitor C3 and the capacitor C4 have the same capacitance value. When the transistor Tn1 is turned off, the capacitor T4 is connected to the connection portion N1 instead of the capacitor C3. Variations in the divided voltage div are prevented.
FIG. 6 shows the control circuit 22a of this embodiment. The control circuit 22a is obtained by adding an inverter circuit 26 and an OR circuit 27 to the control circuit 22 of FIG.
Specifically, the reset signal RSTA output from the inverter circuit 25 is supplied to the first input terminal of the OR circuit 27 via the inverter circuit 26, and the reset signal RST is supplied to the second input terminal of the OR circuit 27. A reset signal RSTAB is output from the output terminal of the OR circuit 27.
Therefore, as shown in FIG. 7, when the reset signals RST and RSTA are at the H level before time t1, the reset signal RSTAB is also at the H level. In this case, in the voltage detection circuit 17a, all the transistors Tn1, Tn2, and Tn3 are turned on, and the divided voltage div is initialized.
From time t1 to t2, since the reset signal RST is at the L level and the reset signal RSTA is at the H level, the reset signal RSTAB is at the L level. Further, at time t2, the reset signal RSTA changes to the L level, so that the reset signal RSTAB changes to the H level.
After time t1 (after the start of voltage detection), the reset signal RSTAB is a signal (inverted control signal) obtained by inverting the logic level with respect to the reset signal RSTA. Based on the reset signal RSTA and the reset signal RSTAB, the transistor Tn1 and the transistor Tn3 are turned on / off, whereby the capacitor C3 and the capacitor C4 are alternately connected to the connection portion N1.
Incidentally, the following relational expression holds at time t2 when the divided voltage div becomes equal to the reference voltage Vref.
C1 × (VPP−Vref) = (C2 + C3) × Vref
Further, when the capacitor C4 is connected instead of the capacitor C3 after time t2, the following relational expression is established.
C1 × (VPP−Vref) = (C2 + C4) × Vref
When the high voltage VPP is obtained from the above relational expressions,
VPP = (C2 + C3) × Vref / C1 + Vref
VPP = (C2 + C4) × Vref / C1 + Vref
It becomes.
Next, features of the second embodiment of the present invention will be described below.
(1) Since the capacitor C3 is added to the connection portion N2 between the transistor Tn1 and the transistor Tn2, the decrease in the potential level of the connection portion N2 due to the off-leakage current of the transistor Tn2 is delayed, the off-leakage current of the transistor Tn1 flows, and the divided voltage div It becomes possible to delay the time when the decrease starts.
(2) When the transistor Tn1 is turned off and the capacitor C3 is disconnected from the connection portion N1 of the capacitors C1 and C2 (time t2), the transistor Tn3 is turned on and the capacitor C4 is connected to the connection portion N1. The fluctuation of the divided voltage div of N1 can be prevented.
Hereinafter, a third embodiment of the present invention will be described with reference to FIGS. In the present embodiment as well, the same symbols are attached to the drawings for those equivalent to the configuration of the first embodiment described above.
As shown in FIG. 8, in the voltage detection circuit 17b of the present embodiment, a PMOS transistor Tp1 is provided as an element for initializing the divided voltage div of the capacitors C1 and C2. A divided voltage div is supplied to the source of the PMOS transistor Tp1, and its drain is connected to the ground GND. The reset signal (control signal) RSTB1 from the control circuit 22b is supplied to the gate of the PMOS transistor Tp1.
The control circuit 22b includes PMOS transistors Tp2 and Tp3, a capacitor C5, and an inverter circuit 28. In the control circuit 22b, the inverter circuit 28 is supplied with a reset signal RST. The output signal of the inverter circuit 28 is supplied to the gate of the PMOS transistor Tp1 through the capacitor C5. A high voltage VPP is supplied to the power supply terminal of the inverter circuit 28. Therefore, the output signal of the inverter circuit 28 has a larger amplitude than the reset signal RST.
The source of the PMOS transistor Tp2 is connected between the gate of the PMOS transistor Tp1 and the capacitor C5, and the drain of the PMOS transistor Tp2 is connected to the low potential side power source VSS. A signal RSTB obtained by inverting the logic level of the reset signal RST is supplied to the gate of the PMOS transistor Tp2.
The drain of the PMOS transistor Tp3 is connected between the gate of the PMOS transistor Tp1 and the capacitor C5, and the source of the PMOS transistor Tp3 is connected to the high potential side power supply VCC. A reset signal RST is supplied to the gate of the PMOS transistor Tp3.
The PMOS transistor Tp2 is a discharge element that discharges the gate of the PMOS transistor Tp1 to a low potential level, and the PMOS transistor Tp3 is a charge element that charges the gate of the PMOS transistor Tp1 to a high potential level.
As shown in FIG. 9, immediately before the start of detection of the high voltage VPP (time t0), the reset signal RST changes from the L level to the H level. At this time, the PMOS transistor Tp2 is turned on and the PMOS transistor Tp3 is turned off. Therefore, the potential level of the gate (reset signal RSTB1) of the PMOS transistor Tp1 is discharged from the high potential side power supply VCC to the potential level of the low potential side power supply VSS, and changes to the negative potential level due to the coupling of the capacitor C5. By turning on the transistor Tp1 with the reset signal RSTB1 at the negative potential level, the potential level of the divided voltage div by the capacitors C1 and C2 is initialized to the ground potential (0 V).
When the reset signal RST is inverted from the H level to the L level at time t1, the PMOS transistor Tp2 is turned off and the PMOS transistor Tp3 is turned on, so that the gate of the PMOS transistor Tp1 (reset signal RSTB1) changes from the negative potential to the high potential side. Charged to the potential level of the power supply VCC. The PMOS transistor Tp1 is completely cut off by the reset signal RSTB1. At this time, the reset signal RSTB1 becomes a voltage higher than the divided voltage div, and the PMOS transistor Tp1 is controlled to be turned off by the signal RSTB1, so that the off-leak current becomes small enough to be ignored.
Next, features of the voltage detection circuit 17b according to the third embodiment of the present invention will be described below.
(1) Since the PMOS transistor Tp1 is used as an element for initializing the divided voltage div of the capacitors C1 and C2, the off-leakage current is reduced to about 1/10 as compared with the case where an NMOS transistor is used. Can do. Therefore, fluctuations in the divided voltage div are suppressed, and voltage detection by the voltage detection circuit 17b can be performed accurately.
(2) When the divided voltage div of each of the capacitors C1 and C2 is reset to the ground potential (0 V) by the PMOS transistor Tp1, even if the gate of the transistor Tp1 is set to the ground potential, it is affected by the threshold characteristics of the transistor Tp1. The divided voltage div cannot be completely reset to the ground potential (0 V). In contrast, in the present embodiment, the control circuit 22b is configured to generate a negative voltage lower than the ground potential by self-boost, and the transistor Tp1 is turned on by the negative voltage reset signal RSRB1 output from the control circuit 22b. (Activated). In this way, the divided voltage div can be reset to the ground potential (0 V) which is an ideal initial potential.
A fourth embodiment embodying the present invention will be described below.
FIG. 10 shows the voltage detection circuit 17c of this embodiment, and FIG. 11 shows an operation waveform diagram of the voltage detection circuit 17c.
The voltage detection circuit 17c is a circuit for detecting the negative voltage VBB generated by the negative voltage generator 20, and includes capacitors C1 and C2, a comparator 21, and a PMOS transistor Tp1. The negative voltage VBB is divided by the capacitors C1 and C2, and the divided voltage div is supplied to the comparator 21. The comparator 21 compares the divided voltage div and the first reference voltage Vref1, and generates an output signal COM corresponding to the comparison result.
The drain of the PMOS transistor Tp1 is connected to the connection portion N1 of the capacitors C1 and C2, and the second reference voltage Vref2 is supplied to the source of the PMOS transistor Tp1. A reset signal RST is supplied to the gate of the PMOS transistor Tp1.
In the fourth embodiment, the first reference voltage Vref1 supplied to the comparator 21 is, for example, 0V, and the second reference voltage Vref2 supplied to the source of the PMOS transistor Tp1 is, for example, 1.3V. That is, the voltage detection circuit 17c is a circuit that starts the voltage detection operation from the potential (1.3V) where the divided voltage div at the connection portion N1 is higher than the ground potential (0V).
Specifically, as shown in FIG. 11, at the start of detection of the negative voltage VBB, an L level reset signal RST is supplied to the gate of the PMOS transistor Tp1. The PMOS transistor Tp1 is turned on by the reset signal RST, and the divided voltage div by the capacitors C1 and C2 is initialized to the second reference voltage Vref2 (1.3 V).
At time t1, the reset signal RST changes to H level, and the PMOS transistor Tp1 is turned off by the reset signal RST, so that the connection portion N1 of the capacitors C1 and C2 enters a floating state. At this time, the negative voltage generation unit 20 of the voltage generation circuit 18 is activated and the voltage value of the negative voltage VBB gradually changes to the negative side. Therefore, the divided voltage div by the capacitors C1 and C2 is also changed to the negative voltage VBB. Will change accordingly.
At time t2, when the negative voltage VBB reaches a target voltage value (for example, −10V) and the divided voltage div decreases to the first reference voltage Vref1 (0V), the output signal COM of the comparator 21 changes from the L level to the H level. Change to level. According to the output signal COM, the negative voltage generator 20 is controlled so that the negative voltage VBB of the negative voltage generator 20 becomes a desired voltage value (for example, −10 V).
Next, features of the voltage detection circuit 17c in the fourth embodiment of the present invention will be described below.
(1) Since the PMOS transistor Tp1 is used as an element for initializing the divided voltage div of the capacitors C1 and C2, the off-leakage current is reduced to about 1/10 as compared with the case where an NMOS transistor is used. Can do. Therefore, the fluctuation of the divided voltage div is suppressed, and the voltage detection by the voltage detection circuit 17c can be accurately performed.
Hereinafter, a fifth embodiment of the present invention will be described with reference to the drawings.
FIG. 12 shows a voltage detection circuit 17d of the fifth embodiment.
The voltage detection circuit 17d is a circuit for detecting the high voltage VPP generated by the high voltage generator 19, and includes capacitors C1 and C2, a comparator 21, an NMOS transistor Tn1, and a CMOS inverter circuit 29.
The high voltage VPP is divided by the capacitors C1 and C2, and the divided voltage div is supplied to the comparator 21. The comparator 21 compares the divided voltage div with the reference voltage Vref (1.3 V), and generates an output signal COM having a potential level according to the comparison result.
The drain of the NMOS transistor Tn1 is connected to the connection portion N1 of the capacitors C1 and C2, and the gate thereof is electrically connected to the source of the NMOS transistor Tn1 via the inverter circuit 29.
The reset signal RST is supplied to the gate of the NMOS transistor Tn1, and the reset signal RST is inverted and supplied to the source of the NMOS transistor Tn1 through the inverter circuit 29. The amplitude of the output signal of the inverter circuit 29 is, for example, 1.8V (H level = 1.8V, L level = 0V).
At the start of detection of the high voltage VPP, the NMOS transistor Tn1 is turned on by the H level reset signal RST. At this time, since the output signal of the inverter circuit 29 is at the L level (ground potential = 0 V), the divided voltage div is initialized to the ground potential.
Thereafter, the NMOS transistor Tn1 is turned off by the L level reset signal RST, and the divided voltage div is changed according to the high voltage VPP. At this time, the output signal of the inverter circuit 29 changes to H level (1.8 V), and the H level signal is supplied to the source of the NMOS transistor Tn1. Therefore, the voltage applied between the source and drain of the NMOS transistor Tn1 is reduced, and the off-leak current in the transistor Tn1 is reduced.
Next, features of the voltage detection circuit 17d according to the fifth embodiment of the present invention will be described below.
(1) When the NMOS transistor Tn1 is turned off (inactivated) after resetting the divided voltage div, a voltage higher than the divided voltage div is supplied to the source of the transistor Tn1. In this way, the off-leakage current in the transistor Tn1 is reduced, so that the voltage detection by the voltage detection circuit 17d can be accurately performed.
Each of the above embodiments may be modified as follows.
In the voltage detection circuits 17 and 17a of the first and second embodiments, a configuration (two-stage configuration) in which two transistors Tn1 and Tn2 are connected in series to the connection portion N1 of the capacitors C1 and C2 is employed. A multistage structure in which transistors are connected in series may be employed. Note that the voltage detection circuit is controlled so that the transistors on the ground GND side are sequentially turned off. Further, when the number of transistors is set to a plurality of stages, the leakage current is reduced, but the speed of resetting the divided voltage div to the ground potential is reduced. Therefore, the number of transistors is set in consideration thereof.
In the voltage detection circuit 17a of the second embodiment, the NMOS transistor Tn3 may be replaced with a PMOS transistor. In this case, the reset signal RSTA is used as a control signal supplied to the gate of the PMOS transistor.
In the fifth embodiment, when the NMOS transistor Tn1 is turned off, a voltage equal to the divided voltage div may be supplied to the source instead of the voltage higher than the divided voltage div.
In each of the embodiments described above, the semiconductor memory device (nonvolatile memory) 11 including the memory cell array 13 as the storage unit is embodied. However, the present invention is not limited to this and is applicable to a semiconductor device not including the memory cell array 13. May be. Of course, the present invention may be applied to a semiconductor memory device other than the nonvolatile memory, such as a DRAM.

[Document Name] Description
[Claims]
1. A voltage detection circuit connected to a voltage generation circuit for detecting an output voltage of the voltage generation circuit, comprising:
  A first capacitor and a second capacitor connected in series to receive the output voltage and generate a divided voltage according to the output voltage;
  A first transistor connected to a first connection between the first capacitor and the second capacitor;
  A second transistor connected in series to the first transistor;
  When the first transistor and the second transistor are activated, the potential of the first connection portion is initialized to an initial potential.
  A control circuit that is connected to the first transistor and generates a first control signal for deactivating the first transistor after the initialization of the potential of the first connection portion after the second transistor;
  A voltage detection circuit comprising:
[Claim 2] A voltage detection circuit connected to the voltage generation circuit for detecting an output voltage of the voltage generation circuit;
A first capacitor and a second capacitor connected in series to receive the output voltage and generate a divided voltage according to the output voltage;
A transistor connected to a connection portion between the first capacitor and the second capacitor, and initializing a potential of the connection portion to an initial potential;
A control circuit connected to the transistor and generating a control signal having a negative potential lower than the initial potential when the potential of the connection portion is initialized, and activating the transistor by the control signal;
A voltage detection circuit comprising:
[Claim 3] A voltage detection circuit connected to the voltage generation circuit for detecting a negative voltage generated by the voltage generation circuit;
A first capacitor and a second capacitor connected in series for receiving the negative voltage and generating a divided voltage according to the negative voltage;
A transistor connected to a connection portion between the first capacitor and the second capacitor, and initializing a potential of the connection portion to an initial potential;
With
A voltage detection circuit in which a gate of the transistor receives a control signal, a source thereof receives the initial potential, and a drain thereof connected to the connection portion.
[Claim 4] A voltage detection circuit connected to the voltage generation circuit for detecting an output voltage of the voltage generation circuit;
A first capacitor and a second capacitor connected in series to receive the output voltage and generate a divided voltage according to the output voltage;
A transistor connected to a connection portion between the first capacitor and the second capacitor, and initializing a potential of the connection portion to an initial potential;
With
A voltage detection circuit in which a gate of the transistor receives a control signal, a source thereof receives an inverted signal of the control signal, and a drain connected to the connection portion.
[Claim 5] A semiconductor device comprising the voltage detection circuit according to claim 1 and the voltage generation circuit.
[Claim 6] A method for controlling a voltage detection circuit provided in a semiconductor device including a voltage generation circuit and detecting a voltage generated by the voltage generation circuit, wherein the voltage detection circuit includes a first capacitor and a second capacitor connected in series. And a first transistor connected to a first connection between the first capacitor and the second capacitor, and a second transistor connected in series to the first transistor, the method comprising:
Using the first and second capacitors to generate a divided voltage according to the output voltage of the voltage generation circuit;
Activating the first transistor and the second transistor to initialize the potential of the first connection portion to an initial potential;
After the initialization of the potential of the first connection portion, only the second transistor is deactivated, and the potential of the second connection portion between the first transistor and the second transistor is set to the first connection portion. Making the potential equal;
Deactivating the first transistor when the potential of the first connection portion reaches a predetermined potential according to the output voltage of the voltage generation circuit;
A method for controlling a voltage detection circuit comprising:
[Claim 7] A method for controlling a voltage detection circuit provided in a semiconductor device including a voltage generation circuit and detecting a voltage generated by the voltage generation circuit, wherein the voltage detection circuit includes a first capacitor and a second capacitor connected in series. And a transistor connected to a connection between the first capacitor and the second capacitor, the method comprising:
Using the first and second capacitors to generate a divided voltage according to the output voltage of the voltage generation circuit;
Activating the transistor and initializing the potential of the connection portion to an initial potential,
The initialization step is a method for controlling a voltage detection circuit that generates a control signal having a negative potential lower than the initial potential and supplies the control signal to the gate of the transistor.
[Claim 8] A method for controlling a voltage detection circuit provided in a semiconductor device including a voltage generation circuit and detecting a voltage generated by the voltage generation circuit, wherein the voltage detection circuit includes a first capacitor and a second capacitor connected in series. And a transistor connected to a connection between the first capacitor and the second capacitor, the method comprising:
Using the first and second capacitors to generate a divided voltage according to the output voltage of the voltage generation circuit;
Activating the transistor to initialize the potential of the connection portion to an initial potential;
Supplying a potential higher than the initial potential to the gate of the transistor after the potential of the connection portion is initialized, and deactivating the transistor;
A method for controlling a voltage detection circuit comprising:
[Claim 9] A method for controlling a voltage detection circuit provided in a semiconductor device including a voltage generation circuit and detecting a voltage generated by the voltage generation circuit, wherein the voltage detection circuit includes a first capacitor and a second capacitor connected in series. And a transistor connected to a connection between the first capacitor and the second capacitor, the method comprising:
Using the first and second capacitors to generate a divided voltage according to the output voltage of the voltage generation circuit;
Activating the transistor to initialize the potential of the connection portion to an initial potential;
After initialization of the potential of the connection portion, when the transistor is deactivated, supplying a potential equal to or higher than that of the connection portion to the source of the transistor;
A method for controlling a voltage detection circuit comprising:
DETAILED DESCRIPTION OF THE INVENTION
[0001]
  (Technical field)
  The present invention relates to a voltage detection circuit that detects an output voltage of a voltage generation circuit mounted on a semiconductor device, a semiconductor device, and a control method for the voltage detection circuit.
  Some semiconductor devices include a voltage generation circuit that generates an internal voltage different from a power supply voltage supplied from the outside and supplies the internal voltage to the internal circuit. The semiconductor device is provided with a voltage detection circuit that detects the output voltage of the voltage generation circuit. Specifically, the voltage detection circuit compares the divided voltage corresponding to the output voltage of the voltage generation circuit with the reference voltage, and detects that the output voltage has reached the target voltage level based on the comparison result. In a voltage detection circuit, a voltage detection resistor is generally used as an element for generating a divided voltage. However, since a current always flows through the voltage dividing resistor, a voltage detection circuit using a capacitor instead of the voltage dividing resistor has been put into practical use in a semiconductor device (for example, a nonvolatile memory) that requires low power consumption. . In the voltage detection circuit, a technique for accurately detecting the voltage based on the capacitance ratio is required.
[0002]
  (Background technology)
  FIG. 13 shows a conventional voltage detection circuit 31, and FIG. 14 shows an operation waveform diagram thereof.
[0003]
  The voltage detection circuit 31 is a circuit for detecting the output voltage VPP of the voltage generation circuit 32 and controlling the voltage VPP to be a target voltage value. The voltage detection circuit 31 includes two capacitors (capacitors) C1 and C2, which are connected in series, a comparator 21, and an NMOS transistor Tn1.
[0004]
  The capacitors C1 and C2 are provided to divide the output voltage VPP of the voltage generation circuit 32. A divided voltage (voltage at the connection portion N1 of the capacitors C1 and C2) div by the capacitors C1 and C2 is supplied to the non-inverting input terminal of the comparator 21, and a reference voltage Vref (for example, 1.3 V) is supplied. It is supplied to the inverting input terminal of the comparator 21.
[0005]
  The drain of the NMOS transistor Tn1 is connected to the connection portion N1 of the capacitors C1 and C2, and the source of the transistor Tn1 is connected to the ground GND. The reset signal RST is supplied to the gate of the NMOS transistor Tn1.
[0006]
  As shown in FIG. 14, at the start of voltage detection by the voltage detection circuit 31, the NMOS transistor Tn1 is turned on by the H level reset signal RST, and the divided voltage div by the capacitors C1 and C2 is initially set to the ground potential (0 V). It becomes. At time t1, the reset signal RST is inverted to L level and the transistor Tn1 is turned off, so that the connection portion N1 of the capacitors C1 and C2 enters a floating state. After time t1, the divided voltage div by the capacitors C1 and C2 changes according to the output voltage VPP. That is, when the output voltage VPP increases with the boosting operation in the voltage generation circuit 32, the divided voltage div also increases with the degree of change corresponding to the capacitance ratio of the capacitors C1 and C2.
[0007]
  The comparator 21 compares the divided voltage div with the reference voltage Vref and outputs an output signal COM having a voltage level corresponding to the comparison result. That is, the comparator 21 outputs an L level output signal COM when the divided voltage div is lower than the reference voltage Vref, and outputs an H level output signal COM when the divided voltage div becomes equal to or higher than the reference voltage Vref. To do. Based on the output signal COM, the output voltage of the voltage generation circuit 32 is controlled to become a target voltage value.
[0008]
  As described above, a voltage detection circuit that performs voltage detection based on a capacitance ratio is disclosed in, for example, Japanese Patent Application Laid-Open No. 2002-51538.
    [Patent Document 1] Japanese Patent Laid-Open No. 2002-51538
[0009]
  By the way, in a nonvolatile semiconductor memory device, data writing and erasing are performed using semiconductor properties of breakdown characteristics and tunneling characteristics. Specifically, in a nonvolatile memory, a high voltage (for example, 10V) or a negative voltage (for example, −10V) higher than a power supply voltage (for example, 3V) is generated by a voltage generation circuit, and the high voltage or the negative voltage is Data is written or erased by applying the voltage to a line or the like.
[0010]
  In the nonvolatile memory, the voltage detection circuit 31 having the circuit configuration shown in FIG. 13 is used to control the output voltage of the voltage generation circuit to a predetermined voltage (high voltage = 10 V, negative voltage = −10 V). Since the voltage detection circuit 31 is configured to detect voltage based on the capacitance ratio, power consumption is reduced compared to a voltage detection circuit that detects voltage based on the resistance ratio.
[0011]
  However, in the voltage detection circuit 31, the output voltage VPP fluctuates due to the tailing current (referred to as subthreshold current or off-leakage current) flowing through the NMOS transistor Tn1 for initializing the divided voltage div. Occurs.
[0012]
  Specifically, when the output voltage VPP of the voltage generation circuit 32 reaches a target voltage value, the divided voltage div in the voltage detection circuit 31 becomes equal to the reference voltage Vref (1.3 V). At this time, the transistor Tn1 is turned off by the L level reset signal RST, but since a divided voltage div equal to the reference voltage Vref is applied between the source and the drain, a minute leak current flows. As described above, the off-leakage current flows through the transistor Tn1, so that the divided voltage div becomes lower than the reference voltage Vref. In this case, since the voltage generation circuit 32 continues the boosting operation even when the output voltage VPP reaches the target voltage value, the output voltage VPP becomes higher than necessary.
[0013]
  Such a phenomenon does not pose a problem if the voltage detection operation time in the voltage detection circuit 31 is relatively short with respect to the decrease in the output voltage VPP due to the off-leakage current. However, a data write operation and an erase operation in the nonvolatile memory require a time (several tens of ms) that is several thousand times longer than a read operation time (several tens of ns). Therefore, in a semiconductor device that requires a long time for the voltage detection operation, such as a nonvolatile memory, there arises a problem that the output voltage VPP of the voltage generation circuit 32 becomes higher than necessary due to the off-leak current of the transistor Tn1. .
[0014]
  An object of the present invention is to provide a voltage detection circuit, a semiconductor device, and a voltage detection circuit control method capable of suppressing voltage fluctuation due to an off-leak current of a transistor and accurately performing voltage detection.
[0015]
  (Disclosure of the Invention)
  In a first aspect of the present invention, a voltage detection circuit connected to a voltage generation circuit and detecting an output voltage of the voltage generation circuit is provided. The voltage detection circuit receives the output voltage and generates a divided voltage corresponding to the output voltage, and a first capacitor and a second capacitor connected in series, and a first between the first capacitor and the second capacitor. A first transistor connected to the connecting portion; a second transistor connected in series to the first transistor; and a control circuit. When the first transistor and the second transistor are activated, the potential of the first connection portion is initialized to the initial potential. The control circuit is connected to the first transistor and outputs a first control signal for deactivating the first transistor after initialization of the potential of the first connection portion after the second transistor. Generate.
[0016]
  In a second aspect of the present invention, a voltage detection circuit connected to a voltage generation circuit and detecting an output voltage of the voltage generation circuit is provided. A voltage detection circuit receives the output voltage and generates a divided voltage corresponding to the output voltage, and a first capacitor and a second capacitor connected in series, and a connection between the first capacitor and the second capacitor A transistor that initializes the potential of the connection portion to an initial potential, and a control signal that is connected to the transistor and has a negative potential lower than the initial potential when the potential of the connection portion is initialized. And a control circuit that activates the transistor by the control signal.
[0017]
  In a third aspect of the present invention, a voltage detection circuit connected to a voltage generation circuit and detecting a negative voltage generated by the voltage generation circuit is provided. The voltage detection circuit receives the negative voltage and generates a divided voltage corresponding to the negative voltage, and a connection between the first capacitor and the second capacitor connected in series, and the first capacitor and the second capacitor And a transistor that initializes the potential of the connection portion to an initial potential. The gate of the transistor receives a control signal, its source receives the initial potential, and its drain connected to the connection.
[0018]
  In a fourth aspect of the present invention, a voltage detection circuit connected to a voltage generation circuit and detecting an output voltage of the voltage generation circuit is provided. A voltage detection circuit receives the output voltage and generates a divided voltage according to the output voltage, and a connection between the first capacitor and the second capacitor connected in series, and the first capacitor and the second capacitor And a transistor that initializes the potential of the connection portion to an initial potential. The gate of the transistor receives a control signal, its source receives an inverted signal of the control signal, and its drain is connected to the connection.
  The voltage detection circuit and the voltage generation circuit shown in the first to fourth aspects are preferably provided in a semiconductor device.
[0019]
  In a fifth aspect of the present invention, a method for controlling a voltage detection circuit is provided. The voltage detection circuit is provided inside the semiconductor device including the voltage generation circuit, and detects a voltage generated by the voltage generation circuit. The voltage detection circuit includes a first capacitor and a second capacitor connected in series, a first transistor connected to a first connection portion between the first capacitor and the second capacitor, and a series connection to the first transistor. And a connected second transistor. The control method uses the first and second capacitors to generate a divided voltage according to the output voltage of the voltage generation circuit, activates the first transistor and the second transistor, and After initializing the potential of the first connection portion to an initial potential, and after initializing the potential of the first connection portion, only the second transistor is deactivated, and the first transistor and the second transistor are When the potential of the first connection portion reaches a predetermined potential according to the output voltage of the voltage generation circuit, Deactivating the first transistor.
[0020]
  In a sixth aspect of the present invention, a method for controlling a voltage detection circuit is provided. The voltage detection circuit is provided inside the semiconductor device including the voltage generation circuit, and detects a voltage generated by the voltage generation circuit. The voltage detection circuit includes a first capacitor and a second capacitor connected in series, and a transistor connected to a connection portion between the first capacitor and the second capacitor. The control method uses the first and second capacitors to generate a divided voltage corresponding to the output voltage of the voltage generation circuit, activates the transistor, and sets the potential of the connection portion to an initial potential. Initializing. The initializing step generates a control signal having a negative potential lower than the initial potential and supplies the control signal to the gate of the transistor.
[0021]
  In a seventh aspect of the present invention, a method for controlling a voltage detection circuit is provided. The voltage detection circuit is provided inside the semiconductor device including the voltage generation circuit, and detects a voltage generated by the voltage generation circuit. The voltage detection circuit includes a first capacitor and a second capacitor connected in series, and a transistor connected to a connection portion between the first capacitor and the second capacitor. The control method includes a step of generating a divided voltage according to the output voltage of the voltage generation circuit using the first and second capacitors, activating the transistor, and setting the potential of the connection portion to an initial potential. And a step of supplying a potential higher than the initial potential to the gate of the transistor to inactivate the transistor after the initialization of the potential of the connection portion.
[0022]
  In an eighth aspect of the present invention, a voltage detection circuit control method is provided. The voltage detection circuit is provided inside the semiconductor device including the voltage generation circuit, and detects a voltage generated by the voltage generation circuit. The voltage detection circuit includes a first capacitor and a second capacitor connected in series, and a transistor connected to a connection portion between the first capacitor and the second capacitor. The control method uses the first and second capacitors to generate a divided voltage corresponding to the output voltage of the voltage generation circuit, activates the transistor, and sets the potential of the connection portion to an initial potential. After the initializing step and initialization of the potential of the connection portion, when the transistor is deactivated, a potential equal to or higher than that of the connection portion is supplied to the source of the transistor. Steps.
[0023]
  (Best Mode for Carrying Out the Invention)
  Hereinafter, a first embodiment in which the present invention is embodied in a semiconductor memory device will be described with reference to the drawings.
[0024]
  FIG. 1 is a schematic block diagram of the semiconductor memory device 11. The semiconductor memory device 11 is a nonvolatile memory, and includes a memory access logic circuit 12, a memory cell array 13, an operation mode control circuit 14, and a power supply circuit 15. The power supply circuit 15 includes a reset generation circuit 16, a voltage detection circuit 17, and a voltage generation circuit 18.
  In the semiconductor memory device 11, the control signal CNTL and the address signal Add from the external device are supplied to the logic circuit 12 for memory access, and the control signal CNTL is supplied to the operation mode control circuit 14.
[0025]
  The logic circuit 12 for memory access includes a latch circuit that latches the address signal Add, a decoder that decodes the address signal Add, and the like. One of a plurality of memory cells provided in the memory cell array 13 is accessed by the decode signal generated by the logic circuit 12. In the present embodiment, the memory cells provided in the memory cell array 13 are nonvolatile memory cells.
[0026]
  The operation mode control circuit 14 controls the power supply circuit 15 based on the control signal CNTL. Examples of the control signal CNTL include signals such as a read command, a write command, and an erase command.
[0027]
  When the supplied control signal CNTL is a write command, the operation mode control circuit 14 activates the high voltage generation unit 19 in the voltage generation circuit 18 in response to the write command. At this time, the high voltage generator 19 of the voltage generator circuit 18 generates the high voltage VPP and supplies the high voltage VPP to the memory cell array 13.
[0028]
  When the control signal CNTL is an erase command, the operation mode control circuit 14 activates the negative voltage generator 20 in the voltage generator 18 in response to the erase command. At this time, the negative voltage generation unit 20 of the voltage generation circuit 18 generates a negative voltage VBB and supplies the negative voltage VBB to the memory cell array 13.
[0029]
  In the memory cell array 13, the high voltage VPP and the negative voltage VBB supplied from the voltage generation circuit 18 are supplied to a word line connected to the memory cell, a bit line, or a well layer constituting a MOS transistor. When the high voltage VPP and the negative voltage VBB are supplied, the data in the memory cell is written and erased.
[0030]
  In the semiconductor memory device 11, when a data write operation or an erase operation is started, a reset is generated prior to activating the high voltage generator 19 and the negative voltage generator 20 in the voltage generator 18. A reset signal RST is supplied from the circuit 16 to the voltage detection circuit 17. In accordance with the reset signal RST, the voltage detection operation in the voltage detection circuit 17 is initialized.
[0031]
  FIG. 2 shows the voltage detection circuit 17. In the figure, a circuit for detecting the high voltage VPP is shown, and a circuit for detecting the negative voltage VBB is not shown.
[0032]
  The voltage detection circuit 17 includes capacitors C1 and C2 as first and second capacitors, a comparator 21 as a determination circuit, a control circuit 22, and NMOS transistors Tn1 and Tn2 as first and second transistors. The high voltage VPP generated by the high voltage generator 19 is detected. The high voltage generator 19 includes a booster circuit 19a and an NMOS transistor Tn10.
[0033]
  In the voltage detection circuit 17, the configurations of the capacitors C1 and C2 and the comparator 21 are the same as those of the conventional voltage detection circuit 31 shown in FIG. That is, the capacitors C1 and C2 are connected in series, and the high voltage VPP that is the output voltage of the high voltage generator 19 is divided by the capacitors C1 and C2. The comparator 21 compares the divided voltage (voltage at the connection portion N1 of the capacitors C1 and C2) div with the reference voltage Vref (for example, 1.3 V) by the capacitors C1 and C2, and according to the comparison result. An output signal COM having a potential level is generated.
[0034]
  The output signal COM of the comparator 21 is supplied to the gate of the NMOS transistor Tn10 in the high voltage generator 19. The drain of the NMOS transistor Tn10 is connected to the output terminal of the booster circuit 19a, and the source of the NMOS transistor Tn10 is connected to the ground GND. The NMOS transistor Tn10 is turned on / off by the output signal COM of the comparator 21 so that the high voltage VPP supplied from the high voltage generator 19 becomes a target voltage value.
[0035]
  Specifically, when the high voltage VPP by the boosting operation of the booster circuit 19a becomes equal to or higher than a target voltage value (for example, 10V), the divided voltage div by the capacitors C1 and C2 becomes equal to or higher than the reference voltage Vref (for example, 1.3V). Thus, the voltage level of the output signal COM of the comparator 21 is increased. The NMOS transistor Tn10 is turned on by the output signal COM of the comparator 21 so that the high voltage VPP becomes the target voltage value.
[0036]
  In the voltage detection circuit 17 of this embodiment, two NMOS transistors Tn1 and Tn2 are provided as elements for initializing the divided voltage div at the start of voltage detection. The NMOS transistors Tn1 and Tn2 are connected in series between the connection portion (first connection portion) N1 of the capacitors C1 and C2 and the ground GND.
[0037]
  The reset signal (first control signal) RST from the reset generation circuit 16 is supplied to the gate of the NMOS transistor Tn2, and the reset signal (second control signal) RSTA of the control circuit 22 is supplied to the gate of the NMOS transistor Tn1. Is done. In the control circuit 22, the reset signal RSTA is generated based on the reset signal RST and the output signal COM of the comparator 21.
[0038]
  FIG. 3 shows a circuit diagram of the control circuit 22.
  The control circuit 22 includes PMOS transistors Tp11 and Tp12, an NMOS transistor Tn11, and inverter circuits 23, 24, and 25. The reset signal RST from the reset generation circuit 16 is supplied to the gate of the PMOS transistor Tp11 via the inverter circuit 23, and the output signal COM of the comparator 21 is supplied to the gate of the NMOS transistor Tn11.
[0039]
  The PMOS transistor Tp11 and the NMOS transistor Tn11 are connected in series, the source of the PMOS transistor Tp11 is connected to the power supply VCC, and the source of the NMOS transistor Tn11 is connected to the ground GND. Further, the drain of the PMOS transistor Tp12 is connected to the connection portion between the transistors Tp11 and Tn11, and the source of the transistor Tp12 is connected to the power source VCC.
[0040]
  The connection portion of each transistor Tp11, Tp12, Tn11 is connected to the gate of the PMOS transistor Tp12 via the inverter circuit 24, and the potential level of the connection portion of each transistor Tp11, Tp12, Tn11 is inverted by the inverter circuit 24. It is supplied to the gate of the PMOS transistor Tp12. Further, the potential level at the connection portion of each transistor Tp11, Tp12, Tn11 is output as the reset signal RSTA via the two inverter circuits 24, 25.
[0041]
  Next, the operation of the voltage detection circuit 17 in this embodiment will be described.
  As shown in FIG. 4, at the start of detection of the high voltage VPP, an H level reset signal RST is output from the reset generation circuit 16. At this time, since the output signal COM of the comparator 21 is at the L level, the PMOS transistor Tp11 is turned on and the NMOS transistor Tn11 is turned off in the control circuit 22. Therefore, an H level reset signal RSTA is output from the control circuit 22.
[0042]
  Accordingly, since the NMOS transistors Tn1 and Tn2 are turned on by the H level reset signals RST and RSTA in the voltage detection circuit 17, the divided voltage div by the capacitors C1 and C2 is set to the ground potential (0 V) as the initial potential. It is initialized.
[0043]
  When the reset signal RST changes to L level at time t1, the PMOS transistor Tp11 in the control circuit 22 is turned off. At this time, since the PMOS transistor Tp12 is on and the NMOS transistor Tn11 is off, the control circuit 22 outputs an H level reset signal RSTA.
[0044]
  Accordingly, in the voltage detection circuit 17, the transistor Tn1 is turned on by the H level reset signal RSTA, and the transistor Tn2 is turned off by the L level reset signal RST. When the transistor Tn2 is turned off, the connection portion N1 of the capacitors C1 and C2 enters a floating state, and the divided voltage div by the capacitors C1 and C2 changes according to the high voltage VPP.
[0045]
  At time t1, the booster circuit 19a of the high voltage generator 19 is activated, and the boosting operation by the booster circuit 19a is started. Therefore, after time t1, the high voltage VPP that is the output voltage of the booster circuit 19a is gradually increased. The divided voltage div generated by the capacitors C1 and C2 is also raised with a degree of change corresponding to the capacity ratio.
[0046]
  Since the transistor Tn1 is turned on from time t1 to time t2 (period in which the divided voltage div is increasing), the potential level of the connection portion (second connection portion) N2 between the transistors Tn1 and Tn2 is the divided voltage. Equal to div.
[0047]
  At time t2, when the high voltage VPP reaches the target voltage value and the divided voltage div becomes the reference voltage Vref, the output signal COM of the comparator 21 changes from L level to H level. At this time, in the control circuit 22, the NMOS transistor Tn11 is turned on by the H level output signal COM. Therefore, the reset signal RSTA output from the control circuit 22 changes from H level to L level.
[0048]
  The transistor Tn1 is turned off by the L level reset signal RSTA. Immediately after time t2, the connection N2 of the transistors Tn1 and Tn2 and the divided voltage div are substantially equal, so that an off-leakage current through the NMOS transistor Tn1 hardly flows. On the other hand, in the NMOS transistor Tn2, since a voltage substantially equal to the divided voltage div is applied between the source and the drain, an off-leak current corresponding to the voltage flows. For this reason, the potential level of the connection portion N2 of the transistors Tn1 and Tn2 gradually decreases.
[0049]
  In the voltage detection circuit 17 of the present embodiment, no off-leakage current flows through the NMOS transistor Tn1 until the potential level of the connection portion N2 of the transistors Tn1 and Tn2 is lowered. Therefore, a sufficient time is ensured until the divided voltage div decreases due to the off-leakage current (the high voltage VPP deviates from the target voltage value). Specifically, in the voltage application period in which the high voltage VPP needs to be applied for the data write operation, it is possible to prevent the divided voltage div from being lowered due to the off-leakage current. The reliability of the write characteristics is improved.
  Next, features of the voltage detection circuit 17 in the first embodiment of the present invention will be described below.
  (1) Two NMOS transistors Tn1 and Tn2 are connected in series to the connection portion N1 of the capacitors C1 and C2, and each transistor Tn1 and Tn2 is turned on (activated), whereby a divided voltage (connection portion N1 Voltage div) is reset to the ground potential. Thereafter, the ground-side transistor Tn2 is turned off (inactivated), the divided voltage div is increased according to the high voltage VPP, and when the divided voltage div reaches the reference voltage Vref, the transistor Tn1 is turned off (not activated). Activated). In this way, no off-leakage current flows through the NMOS transistor Tn1 until the potential level of the connection portion N2 of the transistors Tn1 and Tn2 is lowered due to the off-leakage current of the transistor Tn2. Therefore, a sufficient time can be secured until the divided voltage div decreases and the high voltage VPP deviates from the target voltage value. Therefore, the voltage detection by the voltage detection circuit 17 can be accurately performed during the high voltage application period in the semiconductor memory device 11.
[0050]
  (2) The control circuit 22 generates a reset signal RSTA for controlling the transistor Tn1 based on the reset signal RST for controlling the transistor Tn2 and the output signal COM of the comparator 21. Specifically, in the control circuit 22, the reset signal RSTA is inverted from the H level to the L level at a timing (time t2 in FIG. 4) when the high voltage VPP reaches the target voltage value and the output signal COM becomes the H level. The In this way, the potential of the connection portion N2 of the transistors Tn1 and Tn2 can be made equal to the reference voltage Vref, so that the timing at which the off-leak current of the transistor Tn1 flows (the time when the divided voltage div starts to decrease) is delayed. Is preferable.
[0051]
  (3) In the semiconductor memory device 11, by generating an appropriate high voltage VPP at the time of data writing, the reliability of data writing characteristics can be improved.
[0052]
  Hereinafter, a second embodiment of the present invention will be described with reference to FIGS. In addition, in this embodiment, about the thing equivalent to the structure of 1st Embodiment mentioned above, the same symbol is attached | subjected to drawing and the description is simplified. Below, it demonstrates centering on difference with 1st Embodiment.
[0053]
  As shown in FIG. 5, in the voltage detection circuit 17a of the present embodiment, the connection portion N2 of the transistors Tn1 and Tn2 is connected to the ground GND via a capacitor C3 as a third capacitor. Further, the drain of the NMOS transistor Tn3 as the third transistor is connected to the connection portion N1 of the capacitors C1 and C2, and the source of the NMOS transistor Tn3 is connected to the ground via the capacitor C4 as the fourth capacitor. . A reset signal RSTAB is supplied to the gate of the NMOS transistor Tn3.
[0054]
  In the voltage detection circuit 17a, the capacitance C3 is added to the connection portion N2 of the transistors Tn1 and Tn2, thereby preventing the divided voltage div from being lowered due to the off-leak current. Here, the capacitor C3 and the capacitor C4 have the same capacitance value. When the transistor Tn1 is turned off, the capacitor T4 is connected to the connection portion N1 instead of the capacitor C3. Variations in the divided voltage div are prevented.
[0055]
  FIG. 6 shows the control circuit 22a of this embodiment. The control circuit 22a is obtained by adding an inverter circuit 26 and an OR circuit 27 to the control circuit 22 of FIG.
[0056]
  Specifically, the reset signal RSTA output from the inverter circuit 25 is supplied to the first input terminal of the OR circuit 27 via the inverter circuit 26, and the reset signal RST is supplied to the second input terminal of the OR circuit 27. A reset signal RSTAB is output from the output terminal of the OR circuit 27.
[0057]
  Therefore, as shown in FIG. 7, when the reset signals RST and RSTA are at the H level before time t1, the reset signal RSTAB is also at the H level. In this case, in the voltage detection circuit 17a, all the transistors Tn1, Tn2, and Tn3 are turned on, and the divided voltage div is initialized.
[0058]
  From time t1 to t2, since the reset signal RST is at the L level and the reset signal RSTA is at the H level, the reset signal RSTAB is at the L level. Further, at time t2, the reset signal RSTA changes to the L level, so that the reset signal RSTAB changes to the H level.
[0059]
  After time t1 (after the start of voltage detection), the reset signal RSTAB is a signal (inversion control signal) obtained by inverting the logic level with respect to the reset signal RSTA. Based on the reset signal RSTA and the reset signal RSTAB, the transistor Tn1 and the transistor Tn3 are turned on / off, whereby the capacitor C3 and the capacitor C4 are alternately connected to the connection portion N1.
[0060]
  Incidentally, the following relational expression holds at time t2 when the divided voltage div becomes equal to the reference voltage Vref.
  C1 × (VPP−Vref) = (C2 + C3) × Vref
[0061]
  Further, when the capacitor C4 is connected instead of the capacitor C3 after time t2, the following relational expression is established.
  C1 × (VPP−Vref) = (C2 + C4) × Vref
[0062]
  When the high voltage VPP is obtained from the above relational expressions,
  VPP = (C2 + C3) × Vref / C1 + Vref
  VPP = (C2 + C4) × Vref / C1 + Vref
It becomes.
[0063]
  Next, features of the second embodiment of the present invention will be described below.
  (1) Since the capacitor C3 is added to the connection portion N2 between the transistor Tn1 and the transistor Tn2, the decrease in the potential level of the connection portion N2 due to the off-leakage current of the transistor Tn2 is delayed, and the off-leakage current of the transistor Tn1 flows. It becomes possible to delay the time when the decrease starts.
[0064]
  (2) When the transistor Tn1 is turned off and the capacitor C3 is disconnected from the connection portion N1 of the capacitors C1 and C2 (time t2), the transistor Tn3 is turned on and the capacitor C4 is connected to the connection portion N1. The fluctuation of the divided voltage div of N1 can be prevented.
[0065]
  Hereinafter, a third embodiment of the present invention will be described with reference to FIGS. In the present embodiment as well, the same symbols are attached to the drawings for those equivalent to the configuration of the first embodiment described above.
  As shown in FIG. 8, in the voltage detection circuit 17b of the present embodiment, a PMOS transistor Tp1 is provided as an element for initializing the divided voltage div of the capacitors C1 and C2. A divided voltage div is supplied to the source of the PMOS transistor Tp1, and its drain is connected to the ground GND. The reset signal (control signal) RSTB1 from the control circuit 22b is supplied to the gate of the PMOS transistor Tp1.
[0066]
  The control circuit 22b includes PMOS transistors Tp2 and Tp3, a capacitor C5, and an inverter circuit 28. In the control circuit 22b, the inverter circuit 28 is supplied with a reset signal RST. The output signal of the inverter circuit 28 is supplied to the gate of the PMOS transistor Tp1 through the capacitor C5. A high voltage VPP is supplied to the power supply terminal of the inverter circuit 28. Therefore, the output signal of the inverter circuit 28 has a larger amplitude than the reset signal RST.
[0067]
  The source of the PMOS transistor Tp2 is connected between the gate of the PMOS transistor Tp1 and the capacitor C5, and the drain of the PMOS transistor Tp2 is connected to the low potential side power source VSS. A signal RSTB obtained by inverting the logic level of the reset signal RST is supplied to the gate of the PMOS transistor Tp2.
[0068]
  The drain of the PMOS transistor Tp3 is connected between the gate of the PMOS transistor Tp1 and the capacitor C5, and the source of the PMOS transistor Tp3 is connected to the high potential side power supply VCC. A reset signal RST is supplied to the gate of the PMOS transistor Tp3.
[0069]
  The PMOS transistor Tp2 is a discharge element that discharges the gate of the PMOS transistor Tp1 to a low potential level, and the PMOS transistor Tp3 is a charge element that charges the gate of the PMOS transistor Tp1 to a high potential level.
[0070]
  As shown in FIG. 9, immediately before the start of detection of the high voltage VPP (time t0), the reset signal RST changes from the L level to the H level. At this time, the PMOS transistor Tp2 is turned on and the PMOS transistor Tp3 is turned off. Therefore, the potential level of the gate (reset signal RSTB1) of the PMOS transistor Tp1 is discharged from the high potential side power supply VCC to the potential level of the low potential side power supply VSS, and changes to a negative potential level due to the coupling of the capacitor C5. By turning on the transistor Tp1 with the reset signal RSTB1 at the negative potential level, the potential level of the divided voltage div by the capacitors C1 and C2 is initialized to the ground potential (0 V).
[0071]
  When the reset signal RST is inverted from the H level to the L level at time t1, the PMOS transistor Tp2 is turned off and the PMOS transistor Tp3 is turned on, so that the gate of the PMOS transistor Tp1 (reset signal RSTB1) changes from the negative potential to the high potential side. Charged to the potential level of the power supply VCC. The PMOS transistor Tp1 is completely cut off by the reset signal RSTB1. At this time, the reset signal RSTB1 becomes a voltage higher than the divided voltage div, and the PMOS transistor Tp1 is controlled to be turned off by the signal RSTB1, so that the off-leak current becomes small enough to be ignored.
[0072]
  Next, features of the voltage detection circuit 17b according to the third embodiment of the present invention will be described below.
  (1) Since the PMOS transistor Tp1 is used as an element for initializing the divided voltage div of the capacitors C1 and C2, the off-leakage current is reduced to about 1/10 as compared with the case where an NMOS transistor is used. Can do. Therefore, fluctuations in the divided voltage div are suppressed, and voltage detection by the voltage detection circuit 17b can be performed accurately.
[0073]
  (2) When the divided voltage div of each of the capacitors C1 and C2 is reset to the ground potential (0 V) by the PMOS transistor Tp1, even if the gate of the transistor Tp1 is set to the ground potential, it is affected by the threshold characteristics of the transistor Tp1. The divided voltage div cannot be completely reset to the ground potential (0 V). In contrast, in the present embodiment, the control circuit 22b is configured to generate a negative voltage lower than the ground potential by self-boost, and the transistor Tp1 is turned on by the negative voltage reset signal RSRB1 output from the control circuit 22b. (Activated). In this way, the divided voltage div can be reset to the ground potential (0 V) which is an ideal initial potential.
[0074]
  A fourth embodiment embodying the present invention will be described below.
  FIG. 10 shows the voltage detection circuit 17c of this embodiment, and FIG. 11 shows an operation waveform diagram of the voltage detection circuit 17c.
[0075]
  The voltage detection circuit 17c is a circuit for detecting the negative voltage VBB generated by the negative voltage generator 20, and includes capacitors C1 and C2, a comparator 21, and a PMOS transistor Tp1. The negative voltage VBB is divided by the capacitors C1 and C2, and the divided voltage div is supplied to the comparator 21. The comparator 21 compares the divided voltage div and the first reference voltage Vref1, and generates an output signal COM corresponding to the comparison result.
[0076]
  The drain of the PMOS transistor Tp1 is connected to the connection portion N1 of the capacitors C1 and C2, and the second reference voltage Vref2 is supplied to the source of the PMOS transistor Tp1. A reset signal RST is supplied to the gate of the PMOS transistor Tp1.
[0077]
  In the fourth embodiment, the first reference voltage Vref1 supplied to the comparator 21 is, for example, 0V, and the second reference voltage Vref2 supplied to the source of the PMOS transistor Tp1 is, for example, 1.3V. That is, the voltage detection circuit 17c is a circuit that starts the voltage detection operation from the potential (1.3V) where the divided voltage div at the connection portion N1 is higher than the ground potential (0V).
[0078]
  Specifically, as shown in FIG. 11, at the start of detection of the negative voltage VBB, an L level reset signal RST is supplied to the gate of the PMOS transistor Tp1. The PMOS transistor Tp1 is turned on by the reset signal RST, and the divided voltage div by the capacitors C1 and C2 is initialized to the second reference voltage Vref2 (1.3 V).
[0079]
  At time t1, the reset signal RST changes to H level, and the PMOS transistor Tp1 is turned off by the reset signal RST, so that the connection portion N1 of the capacitors C1 and C2 enters a floating state. At this time, the negative voltage generation unit 20 of the voltage generation circuit 18 is activated, and the voltage value of the negative voltage VBB gradually changes to the negative side. Therefore, the divided voltage div by the capacitors C1 and C2 also becomes the negative voltage VBB. Will change accordingly.
[0080]
  At time t2, when the negative voltage VBB reaches a target voltage value (for example, −10V) and the divided voltage div decreases to the first reference voltage Vref1 (0V), the output signal COM of the comparator 21 changes from L level to H level. Change to level. According to the output signal COM, the negative voltage generator 20 is controlled so that the negative voltage VBB of the negative voltage generator 20 becomes a desired voltage value (for example, −10 V).
[0081]
  Next, features of the voltage detection circuit 17c in the fourth embodiment of the present invention will be described below.
  (1) Since the PMOS transistor Tp1 is used as an element for initializing the divided voltage div of the capacitors C1 and C2, the off-leakage current is reduced to about 1/10 as compared with the case where an NMOS transistor is used. Can do. Therefore, the fluctuation of the divided voltage div is suppressed, and the voltage detection by the voltage detection circuit 17c can be accurately performed.
[0082]
  Hereinafter, a fifth embodiment of the present invention will be described with reference to the drawings.
  FIG. 12 shows a voltage detection circuit 17d of the fifth embodiment.
  The voltage detection circuit 17d is a circuit for detecting the high voltage VPP generated by the high voltage generator 19, and includes capacitors C1 and C2, a comparator 21, an NMOS transistor Tn1, and a CMOS inverter circuit 29.
[0083]
  The high voltage VPP is divided by the capacitors C1 and C2, and the divided voltage div is supplied to the comparator 21. The comparator 21 compares the divided voltage div with the reference voltage Vref (1.3 V), and generates an output signal COM having a potential level according to the comparison result.
[0084]
  The drain of the NMOS transistor Tn1 is connected to the connection portion N1 of the capacitors C1 and C2, and the gate thereof is electrically connected to the source of the NMOS transistor Tn1 via the inverter circuit 29.
[0085]
  The reset signal RST is supplied to the gate of the NMOS transistor Tn1, and the reset signal RST is inverted and supplied to the source of the NMOS transistor Tn1 through the inverter circuit 29. The amplitude of the output signal of the inverter circuit 29 is, for example, 1.8V (H level = 1.8V, L level = 0V).
[0086]
  At the start of detection of the high voltage VPP, the NMOS transistor Tn1 is turned on by the H level reset signal RST. At this time, since the output signal of the inverter circuit 29 is at the L level (ground potential = 0 V), the divided voltage div is initialized to the ground potential.
[0087]
  Thereafter, the NMOS transistor Tn1 is turned off by the L level reset signal RST, and the divided voltage div is changed according to the high voltage VPP. At this time, the output signal of the inverter circuit 29 changes to H level (1.8 V), and the H level signal is supplied to the source of the NMOS transistor Tn1. Therefore, the voltage applied between the source and drain of the NMOS transistor Tn1 is reduced, and the off-leak current in the transistor Tn1 is reduced.
[0088]
  Next, features of the voltage detection circuit 17d according to the fifth embodiment of the present invention will be described below.
  (1) When the NMOS transistor Tn1 is turned off (inactivated) after resetting the divided voltage div, a voltage higher than the divided voltage div is supplied to the source of the transistor Tn1. In this way, the off-leakage current in the transistor Tn1 is reduced, so that the voltage detection by the voltage detection circuit 17d can be accurately performed.
[0089]
  Each of the above embodiments may be modified as follows.
  In the voltage detection circuits 17 and 17a of the first and second embodiments, a configuration (two-stage configuration) in which two transistors Tn1 and Tn2 are connected in series to the connection portion N1 of the capacitors C1 and C2 is employed. A multistage structure in which transistors are connected in series may be employed. Note that the voltage detection circuit is controlled so that the transistors on the ground GND side are sequentially turned off. Further, when the number of transistors is set to a plurality of stages, the leakage current is reduced, but the speed of resetting the divided voltage div to the ground potential is reduced. Therefore, the number of transistors is set in consideration thereof.
[0090]
  In the voltage detection circuit 17a of the second embodiment, the NMOS transistor Tn3 may be replaced with a PMOS transistor. In this case, the reset signal RSTA is used as a control signal supplied to the gate of the PMOS transistor.
  In the fifth embodiment, when the NMOS transistor Tn1 is turned off, a voltage equal to the divided voltage div may be supplied to the source instead of the voltage higher than the divided voltage div.
[0091]
  In each of the embodiments described above, the semiconductor memory device (nonvolatile memory) 11 including the memory cell array 13 as the storage unit is embodied. However, the present invention is not limited to this and is applicable to a semiconductor device not including the memory cell array 13. May be. Of course, the present invention may be applied to a semiconductor memory device other than the nonvolatile memory, such as a DRAM.
[0092]
The technical ideas that can be grasped from the above embodiments are described below.
(Supplementary note 1) A voltage detection circuit that is connected to a voltage generation circuit and detects an output voltage of the voltage generation circuit. The voltage detection circuit receives the output voltage and generates a divided voltage corresponding to the output voltage. A first transistor connected to a first connection between the first capacitor and the second capacitor; a second transistor connected in series to the first transistor; When the one transistor and the second transistor are activated, the potential of the first connection portion is initialized to an initial potential. The potential of the first connection portion is initialized by being connected to the first transistor. And a control circuit for generating a first control signal for deactivating the first transistor after the second transistor.
(Additional remark 2) The said control circuit is after the said 2nd transistor is deactivated, Comprising: When the electric potential of the said 1st connection part reaches a predetermined electric potential according to the said output voltage, the said 1st control The voltage detection circuit according to appendix 1, which generates a signal.
(Additional remark 3) It further has a determination circuit which determines that the output voltage has reached the predetermined voltage by comparing the divided voltage with a reference voltage, and the control circuit controls the second transistor. The voltage detection circuit according to appendix 1, wherein the first control signal is generated according to the second control signal and the output signal of the determination circuit.
(Supplementary Note 4) A third capacitor connected between the second connection portion between the first transistor and the second transistor and the ground, a third transistor connected to the first connection portion, and the first transistor The voltage detection circuit according to appendix 1, further comprising a fourth capacitor connected between the three transistors and the ground.
(Supplementary note 5) The voltage detection circuit according to supplementary note 4, wherein the control circuit generates an inverted signal of the first control signal and supplies the inverted signal to the third transistor.
(Supplementary note 6) The voltage detection circuit according to supplementary note 4, wherein the third capacitor and the fourth capacitor have the same capacitance value.
(Supplementary note 7) A voltage detection circuit that is connected to a voltage generation circuit and detects an output voltage of the voltage generation circuit. The voltage detection circuit receives the output voltage and generates a divided voltage according to the output voltage. A first capacitor and a second capacitor; a transistor connected to a connection between the first capacitor and the second capacitor; and a transistor for initializing a potential of the connection to an initial potential; the transistor connected to the transistor; and the connection A voltage detection circuit comprising: a control circuit that generates a control signal having a negative potential lower than the initial potential and activates the transistor by the control signal when the potential of the unit is initialized.
(Supplementary note 8) The voltage detection circuit according to supplementary note 7, wherein the control circuit includes a charge element that charges a gate of the transistor to a high potential level and a discharge element that discharges the gate to a low potential level.
(Supplementary note 9) The voltage detection circuit according to supplementary note 8, wherein the charge element and the discharge element receive signals of opposite phases.
(Supplementary note 10) The voltage detection circuit according to supplementary note 7, wherein the control circuit includes a capacitor for supplying a negative voltage to the gate of the transistor.
(Additional remark 11) The voltage detection circuit of Additional remark 10 to which the control signal for initializing the electric potential of the said connection part is supplied to the said capacity | capacitance.
(Supplementary note 12) The voltage detection circuit according to supplementary note 7, wherein when the transistor is inactivated, the gate potential of the transistor is made higher than the potential of the connection portion.
(Supplementary note 13) The voltage detection circuit according to any one of supplementary notes 7 to 12, wherein the transistor is a PMOS transistor.
(Supplementary note 14) A voltage detection circuit that is connected to a voltage generation circuit and detects a negative voltage generated by the voltage generation circuit, receives the negative voltage, and generates a divided voltage corresponding to the negative voltage. A first capacitor and a second capacitor connected to each other; a transistor connected to a connection portion between the first capacitor and the second capacitor, and initializing a potential of the connection portion to an initial potential; A voltage detection circuit in which a gate receives a control signal, a source receives the initial potential, and a drain connected to the connection portion.
(Supplementary note 15) The voltage detection circuit according to supplementary note 14, wherein when the transistor is deactivated, the potential of the control signal is set higher than the initial potential.
(Supplementary note 16) The voltage detection circuit according to supplementary note 14 or 15, wherein the transistor is a PMOS transistor.
(Supplementary Note 17) A voltage detection circuit that is connected to a voltage generation circuit and detects an output voltage of the voltage generation circuit, receives the output voltage, and generates a divided voltage corresponding to the output voltage. A first capacitor and a second capacitor, and a transistor connected to a connection portion between the first capacitor and the second capacitor, and initializing a potential of the connection portion to an initial potential. A voltage detection circuit that receives a control signal, a source that receives an inverted signal of the control signal, and a drain that is connected to the connection portion.
(Supplementary note 18) The voltage detection circuit according to supplementary note 17, further comprising an inverter circuit connected between a gate and a source of the transistor, generating the inverted signal, and supplying the inverted signal to the source.
(Supplementary note 19) A semiconductor device comprising the voltage detection circuit according to any one of supplementary notes 1 to 18 and the voltage generation circuit.
(Supplementary note 20) The semiconductor device according to supplementary note 19, further comprising a storage circuit for storing data, wherein the storage circuit writes or erases data using a voltage generated by the voltage generation circuit.
(Additional remark 21) The said memory circuit is a semiconductor device of Additional remark 20 containing a non-volatile memory cell.
(Supplementary note 22) A method for controlling a voltage detection circuit provided in a semiconductor device including a voltage generation circuit and detecting a voltage generated by the voltage generation circuit, wherein the voltage detection circuit includes a first capacitor connected in series And a second capacitor, a first transistor connected to a first connection between the first capacitor and the second capacitor, and a second transistor connected in series to the first transistor, the method comprising: Generating a divided voltage according to the output voltage of the voltage generation circuit using the first and second capacitors, activating the first transistor and the second transistor, and After the step of initializing the potential of the part to the initial potential and the initialization of the potential of the first connection part, only the second transistor is deactivated, and between the first transistor and the second transistor, Second connection Equalizing the potential of the first connection portion with the potential of the first connection portion, and deactivating the first transistor when the potential of the first connection portion reaches a predetermined potential according to the output voltage of the voltage generating circuit And a step of controlling the voltage detection circuit.
(Supplementary Note 23) The method further includes the step of determining whether the output voltage of the voltage generation circuit has reached a target voltage value by comparing a divided voltage by the first capacitor and the second capacitor with a reference voltage. The method for controlling a voltage detection circuit according to appendix 22, wherein the step of deactivating the first transistor comprises deactivating the first transistor according to the determination.
(Supplementary Note 24) The voltage detection circuit further includes a third capacitor connected to the second connection unit, a third transistor connected to the first connection unit, and a fourth capacitor connected to the third transistor. The method further comprising: deactivating the first transistor to electrically disconnect the third capacitor from the first connection; and activating the third transistor, The method for controlling a voltage detection circuit according to appendix 22, further comprising a step of electrically connecting the fourth capacitor to the first connection portion instead of the separated third capacitor.
(Supplementary Note 25) A method for controlling a voltage detection circuit provided in a semiconductor device including a voltage generation circuit and detecting a voltage generated by the voltage generation circuit, wherein the voltage detection circuit includes a first capacitor connected in series And a second capacitor, and a transistor connected to a connection between the first capacitor and the second capacitor, and the method uses the first and second capacitors to increase the output voltage of the voltage generating circuit. And a step of generating a corresponding divided voltage and activating the transistor to initialize the potential of the connection portion to an initial potential. The initializing step includes a negative voltage lower than the initial potential. A control method of a voltage detection circuit that generates a potential control signal and supplies the control signal to the gate of the transistor.
(Supplementary note 26) The supplementary note 25, further comprising a step of controlling a charge element that charges the gate of the transistor to a high potential level and a discharge element that discharges the gate to a low potential level by signals having opposite phases to each other. Control method of voltage detection circuit.
(Supplementary note 27) The method for controlling a voltage detection circuit according to supplementary note 26, further comprising a step of making the gate potential of the transistor higher than the potential of the connection portion when the transistor is deactivated.
(Supplementary Note 28) A method for controlling a voltage detection circuit provided in a semiconductor device including a voltage generation circuit and detecting a voltage generated by the voltage generation circuit, wherein the voltage detection circuit includes a first capacitor connected in series And a second capacitor, and a transistor connected to a connection between the first capacitor and the second capacitor, and the method uses the first and second capacitors to output voltage of the voltage generating circuit. A step of generating a divided voltage in accordance with the step of activating the transistor to initialize the potential of the connection portion to an initial potential, and after initializing the potential of the connection portion, Supplying a higher potential to the gate of the transistor to inactivate the transistor.
(Supplementary note 29) A method for controlling a voltage detection circuit provided in a semiconductor device including a voltage generation circuit and detecting a voltage generated by the voltage generation circuit, wherein the voltage detection circuit includes a first capacitor connected in series And a second capacitor, and a transistor connected to a connection between the first capacitor and the second capacitor, and the method uses the first and second capacitors to increase the output voltage of the voltage generating circuit. A step of generating a corresponding divided voltage, activating the transistor to initialize the potential of the connection portion to an initial potential, and initializing the potential of the connection portion; Supplying a potential equal to or higher than that of the connection to the source of the transistor when the transistor is deactivated.
(Supplementary note 30) The method for controlling a voltage detection circuit according to supplementary note 29, further comprising the step of controlling the source potential of the transistor by an inverted signal of a control signal supplied to a gate of the transistor.
[Brief description of the drawings]
    FIG. 1 is a schematic block diagram showing a semiconductor device according to a first embodiment of the present invention.
    2 is a schematic circuit diagram of a voltage detection circuit in the semiconductor device of FIG. 1;
    FIG. 3 is a schematic circuit diagram of the control circuit of FIG. 2;
    4 is an operation waveform diagram of the voltage detection circuit of FIG. 2;
    FIG. 5 is a schematic circuit diagram of a voltage detection circuit according to a second embodiment of the present invention.
    FIG. 6 is a schematic circuit diagram of a control circuit in a second embodiment of the present invention.
    7 is an operation waveform diagram of the voltage detection circuit of FIG. 5. FIG.
    FIG. 8 is a circuit diagram of a voltage detection circuit according to a third embodiment of the present invention.
    9 is an operation waveform diagram of the voltage detection circuit of FIG. 8. FIG.
    FIG. 10 is a circuit diagram of a voltage detection circuit according to a fourth embodiment of the present invention.
    11 is an operation waveform diagram of the voltage detection circuit of FIG. 10;
    FIG. 12 is a circuit diagram of a voltage detection circuit according to a fifth embodiment of the present invention.
    FIG. 13 is a schematic circuit diagram of a conventional voltage detection circuit.
    14 is an operation waveform diagram of the voltage detection circuit of FIG. 13;

Claims (30)

A voltage detection circuit connected to the voltage generation circuit for detecting an output voltage of the voltage generation circuit;
A first capacitor and a second capacitor connected in series to receive the output voltage and generate a divided voltage according to the output voltage;
A first transistor connected to a first connection between the first capacitor and the second capacitor;
A second transistor connected in series to the first transistor;
When the first transistor and the second transistor are activated, the potential of the first connection portion is initialized to an initial potential.
A control circuit which is connected to the first transistor and generates a first control signal for deactivating the first transistor after the initialization of the potential of the first connection portion after the second transistor; A voltage detection circuit comprising: The control circuit generates the first control signal after the second transistor is deactivated and when the potential of the first connection portion reaches a predetermined potential according to the output voltage. The voltage detection circuit according to claim 1. A determination circuit for determining that the output voltage has reached the predetermined voltage by comparing the divided voltage with a reference voltage;
The voltage detection circuit according to claim 1, wherein the control circuit generates the first control signal in accordance with a second control signal for controlling the second transistor and an output signal of the determination circuit. A third capacitor connected between a second connection between the first transistor and the second transistor and the ground;
A third transistor connected to the first connection portion;
The voltage detection circuit according to claim 1, further comprising: a fourth capacitor connected between the third transistor and the ground. The voltage detection circuit according to claim 4, wherein the control circuit generates an inverted signal of the first control signal and supplies the inverted signal to the third transistor. The voltage detection circuit according to claim 4, wherein the third capacitor and the fourth capacitor have the same capacitance value. A voltage detection circuit connected to the voltage generation circuit for detecting an output voltage of the voltage generation circuit;
A first capacitor and a second capacitor connected in series to receive the output voltage and generate a divided voltage according to the output voltage;
A transistor connected to a connection portion between the first capacitor and the second capacitor and initializing a potential of the connection portion to an initial potential;
A voltage that is connected to the transistor and generates a control signal having a negative potential lower than the initial potential when the potential of the connection portion is initialized, and activates the transistor by the control signal. Detection circuit. The voltage detection circuit according to claim 7, wherein the control circuit includes a charge element that charges a gate of the transistor to a high potential level and a discharge element that discharges the gate to a low potential level. The voltage detection circuit according to claim 8, wherein the charge element and the discharge element receive signals having opposite phases to each other. The voltage detection circuit according to claim 7, wherein the control circuit includes a capacitor for supplying a negative voltage to the gate of the transistor. The voltage detection circuit according to claim 10, wherein a control signal for initializing a potential of the connection portion is supplied to the capacitor. The voltage detection circuit according to claim 7, wherein when the transistor is deactivated, a gate potential of the transistor is set higher than a potential of the connection portion. The voltage detection circuit according to claim 7, wherein the transistor is a PMOS transistor. A voltage detection circuit connected to the voltage generation circuit for detecting a negative voltage generated by the voltage generation circuit;
A first capacitor and a second capacitor connected in series for receiving the negative voltage and generating a divided voltage according to the negative voltage;
A transistor connected to a connection portion between the first capacitor and the second capacitor, and initializing a potential of the connection portion to an initial potential;
A voltage detection circuit in which a gate of the transistor receives a control signal, a source thereof receives the initial potential, and a drain thereof connected to the connection portion. The voltage detection circuit according to claim 14, wherein when the transistor is deactivated, the potential of the control signal is set higher than the initial potential. The voltage detection circuit according to claim 14, wherein the transistor is a PMOS transistor. A voltage detection circuit connected to the voltage generation circuit for detecting an output voltage of the voltage generation circuit;
A first capacitor and a second capacitor connected in series to receive the output voltage and generate a divided voltage according to the output voltage;
A transistor connected to a connection portion between the first capacitor and the second capacitor, and initializing a potential of the connection portion to an initial potential;
A voltage detection circuit in which a gate of the transistor receives a control signal, a source thereof receives an inverted signal of the control signal, and a drain connected to the connection portion. The voltage detection circuit according to claim 17, further comprising: an inverter circuit connected between a gate and a source of the transistor, generating the inverted signal, and supplying the inverted signal to the source. A semiconductor device comprising the voltage detection circuit according to claim 1 and the voltage generation circuit. A storage circuit for storing data;
The semiconductor device according to claim 19, wherein the memory circuit performs data writing or erasing using a voltage generated by the voltage generation circuit. The semiconductor device according to claim 20, wherein the memory circuit includes a nonvolatile memory cell. A method for controlling a voltage detection circuit provided in a semiconductor device including a voltage generation circuit and detecting a voltage generated by the voltage generation circuit, wherein the voltage detection circuit includes a first capacitor and a second capacitor connected in series. And a first transistor connected to a first connection between the first capacitor and the second capacitor, and a second transistor connected in series to the first transistor, the method comprising:
Generating a divided voltage according to the output voltage of the voltage generation circuit using the first and second capacitors;
Activating the first transistor and the second transistor to initialize the potential of the first connection portion to an initial potential;
After the initialization of the potential of the first connection portion, only the second transistor is deactivated, and the potential of the second connection portion between the first transistor and the second transistor is set to the first connection portion. Making the potential equal;
And a step of deactivating the first transistor when a potential of the first connection portion reaches a predetermined potential in accordance with an output voltage of the voltage generation circuit. Determining whether the output voltage of the voltage generation circuit has reached a target voltage value by comparing the divided voltage of the first capacitor and the second capacitor with a reference voltage;
23. The voltage detection circuit control method according to claim 22, wherein inactivating the first transistor comprises inactivating the first transistor according to the determination. The voltage detection circuit further includes a third capacitor connected to the second connection unit, a third transistor connected to the first connection unit, and a fourth capacitor connected to the third transistor, The method further comprises electrically deactivating the first transistor to electrically disconnect the third capacitor from the first connection portion;
The voltage detection circuit according to claim 22, further comprising: activating the third transistor to electrically connect the fourth capacitor to the first connection unit instead of the disconnected third capacitor. Control method. A method for controlling a voltage detection circuit provided in a semiconductor device including a voltage generation circuit and detecting a voltage generated by the voltage generation circuit, wherein the voltage detection circuit includes a first capacitor and a second capacitor connected in series. And a transistor connected to a connection between the first capacitor and the second capacitor, the method comprising:
Using the first and second capacitors to generate a divided voltage according to the output voltage of the voltage generation circuit;
Activating the transistor and initializing the potential of the connection portion to an initial potential,
The initializing step generates a control signal having a negative potential lower than the initial potential, and supplies the control signal to the gate of the transistor. 26. The voltage detection circuit according to claim 25, further comprising a step of controlling a charge element that charges the gate of the transistor to a high potential level and a discharge element that discharges the gate to a low potential level by signals having opposite phases. Control method. 27. The method of controlling a voltage detection circuit according to claim 26, further comprising a step of making the gate potential of the transistor higher than the potential of the connection portion when the transistor is deactivated. A method for controlling a voltage detection circuit provided in a semiconductor device including a voltage generation circuit and detecting a voltage generated by the voltage generation circuit, wherein the voltage detection circuit includes a first capacitor and a second capacitor connected in series. And a transistor connected to a connection between the first capacitor and the second capacitor, the method comprising:
Generating a divided voltage according to the output voltage of the voltage generation circuit using the first and second capacitors;
Activating the transistor to initialize the potential of the connection to an initial potential;
A method of controlling the voltage detection circuit, comprising: after initialization of the potential of the connection portion, supplying a potential higher than the initial potential to the gate of the transistor to deactivate the transistor. A method for controlling a voltage detection circuit provided in a semiconductor device including a voltage generation circuit and detecting a voltage generated by the voltage generation circuit, wherein the voltage detection circuit includes a first capacitor and a second capacitor connected in series. And a transistor connected to a connection between the first capacitor and the second capacitor, the method comprising:
Using the first and second capacitors to generate a divided voltage according to the output voltage of the voltage generation circuit;
Activating the transistor to initialize the potential of the connection to an initial potential;
After the initialization of the potential of the connection portion, when the transistor is deactivated, a voltage detection comprising: supplying the same potential as or higher than the connection portion to the source of the transistor Circuit control method. 30. The method of controlling a voltage detection circuit according to claim 29, further comprising the step of controlling the source potential of the transistor by an inverted signal of a control signal supplied to the gate of the transistor.

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