JP3471718B2 - Semiconductor integrated circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit that regulates the voltage of a booster power supply circuit or a negative booster power supply circuit.

[0002]

2. Description of the Related Art In recent years, a flash memory, which is a non-volatile semiconductor memory device, is required to have a low voltage and a single power source. There is a need for a semiconductor integrated circuit that supplies a voltage.

FIG. 26 is a block diagram showing the structure of a conventional semiconductor integrated circuit. In FIG. 26, the conventional semiconductor integrated circuit has a booster circuit 201 that boosts the power supply voltage V _DD supplied to the semiconductor integrated circuit to a predetermined voltage V _PP.
And a regulator circuit 202 which receives the boosted voltage V _PP as an input and outputs an adjusted output voltage Vo. The regulator circuit 202 further includes a reference voltage generation circuit 203, a differential amplifier circuit 204, an output circuit 205, and a voltage dividing circuit 206.

The reference voltage generation circuit 203 is a booster circuit 20.
The reference voltage Vref is generated by using the boosted voltage V _{PP of} 1 as an input. Further, the reference voltage generation circuit 203 uses the reference voltage Vref.
Can be switched to a plurality of voltages. Differential amplifier circuit 2
The output voltage V _PP of the booster circuit 201 is input to the power supply input terminal of the power supply circuit 04, and the reference voltage Vref generated by the reference voltage generation circuit 203 and the divided voltage Vd from the voltage dividing circuit 206 are input to the voltage 04. Differential amplification is performed by _PP . Output circuit 205
Has a gate connected to the output terminal of the differential amplifier circuit 204,
A P-type MOS whose source and drain are respectively connected to the output end of the booster circuit 201 and the input end of the voltage divider circuit 206.
The output voltage Vo of the regulator circuit 202 is provided with the transistor M10 and the output voltage V _PP of the booster circuit 201 is adjusted based on the output voltage Va of the differential amplifier circuit 204.
Output as. The voltage dividing circuit 206 receives the output voltage Vo of the output circuit 205 and outputs a divided voltage Vd obtained by dividing the output voltage Vo.

The operation of the conventional semiconductor integrated circuit configured as described above will be described below. Boost circuit 20
1 is from the power supply voltage V _DD supplied to the semiconductor integrated circuit,
A boosted voltage V _PP higher than the power supply voltage V _DD is generated and supplied to the regulator circuit 202. Regulator circuit 202
Outputs a predetermined constant voltage Vo obtained by stepping down the boosted voltage V _PP from the output terminal.

In the regulator circuit 202, the reference voltage generating circuit 203 receives the boosted voltage V _PP as an input, and generates and outputs a predetermined reference voltage Vref. Therefore, the reference voltage Vref has any value between the boosted voltage V _PP and the ground potential V _SS . The voltage dividing circuit 206 is the regulator circuit 20.
The output voltage Vo of 2 is Vo / V according to a predetermined voltage division ratio r (r ≧ 1).
The divided voltage Vd divided so that the relation of d = r is obtained is output. The output voltage Vd of the voltage dividing circuit 206 and the reference voltage Vref
Are compared by the differential amplifier circuit 204, and the P-type MO of the output circuit 205 is determined by the output voltage Va of the differential amplifier circuit 204.
The S-transistor M10 is controlled and finally Vd = Vr
Become ef. In this way, the regulator circuit 202
Is the boosted voltage V _PP whose voltage is not always stable,
It is possible to generate the output voltage Vo held at a constant voltage Vo = r · Vref.

Further, the regulator circuit 202 needs to supply different output voltages Vo in different modes such as writing and erasing of the nonvolatile semiconductor memory device. In such a case, by changing the reference voltage Vref depending on each mode, it is possible to realize voltage supply adapted to different modes.

Further, although the above-mentioned conventional technique describes the power supply voltage circuit for boosting, the same applies to a conventional semiconductor integrated circuit for generating a negative voltage. A semiconductor in which 201 is a negative booster circuit and P-type MOS transistor M10 of the output circuit 205 is replaced with an N-type MOS transistor is capable of outputting a constant negative voltage based on a negative reference voltage. It becomes an integrated circuit.

[0009]

However, since the regulator circuit 202 in the conventional semiconductor integrated circuit operates at the output voltage V _PP of the booster circuit 201, a large load is applied to the booster circuit 201. Normally, the booster circuit 201 is a charge pump circuit, and the characteristics of its output current and output voltage are as shown in FIG.

FIG. 27 shows the output current of the charge pump circuit.
It is a figure which shows the characteristic of I _PP and output voltage V _PP , and a horizontal axis shows output current I _PP and a vertical axis shows output voltage V _PP . FIG. 27
As the graph, the output voltage V _PP of the booster circuit 201
Has a characteristic that it decreases as the output current I _PP increases. Therefore, if the load on the booster circuit 201 increases, the output current I _PP increases, and it becomes difficult to obtain a predetermined output voltage V _PP . In particular, in achieving a low power supply voltage, in order to ensure the boosted voltage V _PP over a certain value, it is necessary to increase the number of stages of the charge pump circuit, thereby the output voltage V _PP with respect to the output current I _PP The rate of decrease is further increased. Therefore, the output voltage V _PP of the booster circuit 201
In order to keep the voltage at a predetermined value, it is necessary to increase the capacitance in the booster circuit 201. As a result, the booster circuit 2
There is a problem that the area of 01 increases.

Similarly, also in the conventional semiconductor integrated circuit for generating a negative voltage, the regulator circuit operates with the output voltage of the negative booster circuit, so that a load is applied to the negative booster circuit. Therefore, as in the case of the booster circuit described above, the output current of the negative booster circuit increases, and it becomes difficult for the negative booster circuit to secure a predetermined output voltage. There is a problem that it is necessary to increase the area to increase the capacitance in the negative booster circuit.

The present invention has been made to solve the above problems, and a semiconductor integrated circuit capable of reducing the area of the semiconductor integrated circuit by reducing the scale of the boosting circuit or the negative boosting circuit. The purpose is to provide.

[0013]

In order to achieve the above object, a semiconductor integrated circuit according to the present invention is provided with a negative voltage from a power supply voltage.
A negative booster circuit that generates a pressure and outputs the negative voltage;
Pressure as an input, generate an output voltage from the negative voltage,
The output circuit that outputs the voltage from the output terminal and the power supply voltage
Reference voltage generation circuit that generates a positive reference voltage from
The output voltage of the input circuit and the reference voltage above as input
The potential difference between the input voltage and the reference voltage is
A voltage divider circuit that outputs a divided voltage that has been divided, and the above divided voltage
And the ground potential as two inputs, with a voltage obtained by differential amplification a differential amplifier circuit that be output to the output circuit, the differential amplifier
According to the comparison result of the divided voltage and the ground potential by the circuit.
The output circuit is controlled and the output voltage of the output circuit is
Is held at a predetermined negative voltage .

[0014]

[0015]

[0016]

[0017]

[0018]

[0019]

[0020]

[0021]

[0022]

[0023]

[0024]

[0025]

The semiconductor integrated circuit according to the present invention is characterized in that, in the semiconductor integrated circuit, the voltage dividing circuit is a resistance voltage dividing circuit having a plurality of resistors connected in series.

In the semiconductor integrated circuit according to the present invention, in the semiconductor integrated circuit, the voltage dividing circuit has a plurality of diode-connected transistors in which a gate and a drain are connected and a source and a substrate are connected in series. Connect and on
The divided voltage is the above-mentioned diode with one end connected to the reference voltage.
Built-in structure to output from the other end of the diode-connected transistor
Well, the above reference voltage is the diode connected transistor.
The threshold voltage of the
It is characterized in that the voltage is higher than necessary .

In the semiconductor integrated circuit according to the present invention, in the semiconductor integrated circuit, the voltage dividing circuit is initialized by short-circuiting a plurality of capacitors connected in series and both ends of the plurality of capacitors. It is characterized by comprising a circuit.

The semiconductor integrated circuit according to the present invention is characterized in that, in the semiconductor integrated circuit, the voltage dividing circuit sets the voltage dividing ratio to a different value according to an input control signal. Integrated semiconductor circuit.

Also, in the semiconductor integrated circuit according to the present invention, in the semiconductor integrated circuit, a plurality of the voltage dividing circuits are connected in series between the output terminal of the output circuit and the output terminal of the reference voltage generating circuit. And one or more transistors, one end of which is connected to one of the nodes between the plurality of resistors and the other end of which is connected to the output end of the output circuit, and which receives the control signal as input, A control circuit for applying a control voltage based on the control signal to a control terminal, and an output terminal for extracting a divided voltage, which is connected to any one of the nodes between the plurality of resistors. is there.

Also, in the semiconductor integrated circuit according to the present invention, in the semiconductor integrated circuit, a plurality of the voltage dividing circuits are connected in series between the output terminal of the output circuit and the output terminal of the reference voltage generating circuit. of, the gate and drain are connected, a transistor connected to the source and the substrate and are connected diode, one end connected to one of the nodes between the plurality of transistors, the other end an output terminal of the output circuit One or more voltage dividing control transistors connected to the control circuit, and a control circuit that receives the control signal as an input and applies a control voltage based on the control signal to the control terminal of the voltage dividing control transistor. Of the diode connection above connected to
Connected to the other end of the transistor, it is characterized in that consisted the output terminal to take out the divided voltage.

Further, in the semiconductor integrated circuit according to the present invention, in the semiconductor integrated circuit, a plurality of the voltage dividing circuits are connected in series between the output terminal of the output circuit and the output terminal of the reference voltage generating circuit. And one or more transistors whose one end is connected to any one of the nodes between the plurality of capacitors and whose other end is connected to the output end of the output circuit, and the control signal being input, A control circuit that applies a control voltage based on the control signal to the control terminal, an initialization circuit that short-circuits both ends of the plurality of capacitors to perform initialization, and is connected to one of the nodes between the plurality of capacitors. , And an output terminal for extracting the divided voltage.

In the semiconductor integrated circuit according to the present invention, in the semiconductor integrated circuit, the voltage dividing circuit is connected in series between the output terminal of the output circuit and the output terminal of the reference voltage generating circuit. One first capacitor and one or more transistors having one end connected to the node between the first capacitors, one end connected to the transistor, and the other end connected to the output terminal of the reference voltage generation circuit. Also, a node between the first capacitor and a control circuit that receives the same number of second capacitors as the number of the transistors and the control signal and applies a control voltage based on the control signal to the control terminal of the transistor. And an output terminal connected to the node between the first capacitors for extracting the divided voltage.

Also, in the semiconductor integrated circuit according to the present invention, in the above semiconductor integrated circuit, the output circuit is configured such that the source is connected to the output end of the negative booster circuit, and the drain is the output end of the output circuit. N-type MOS transistor, a source is connected to the output terminal of the negative booster circuit, a drain is connected to the gate of the first N-type MOS transistor, and a source is the power supply voltage. And a drain connected to the second N-type MO.
A P-type MOS transistor connected to the drain of the S-transistor and having a gate connected to the output terminal of the differential amplifier circuit, and a bias circuit for applying a bias voltage to the gate of the second N-type MOS transistor. It is characterized by.

Further, in the semiconductor integrated circuit according to the present invention, in the above semiconductor integrated circuit, the output circuit has a first source connected to an output of the negative booster circuit and a drain serving as an output terminal of the output circuit. An N-type MOS transistor,
A second N-type MOS transistor having a source connected to the output of the negative booster circuit, a gate and a drain connected to the gate of the first N-type MOS transistor, and a source connected to a power supply voltage and a drain connected to The second N-type MO
It is characterized in that it is composed of a P-type MOS transistor connected to the drain of the S transistor and having a gate connected to the output terminal of the differential amplifier circuit.

Further, in the semiconductor integrated circuit according to the present invention, in the semiconductor integrated circuit, the output circuit has a source connected to an output terminal of the negative booster circuit and a drain serving as an output terminal of the output circuit. Second N-type MOS transistor whose source is connected to the output terminal of the negative booster circuit, whose drain is connected to the gate of the first N-type MOS transistor, and whose gate is grounded. And a P-type MOS transistor having a source connected to the power supply voltage, a drain connected to the drain of the second N-type MOS transistor, and a gate connected to the output terminal of the differential amplifier circuit. It is a feature.

Further, the semiconductor integrated circuit according to the present invention has a booster circuit which outputs a boosted voltage obtained by boosting a power supply voltage, and the boosted voltage as an input, which generates an output voltage from the boosted voltage,
A first output circuit that outputs the output voltage from an output terminal, a reference voltage generation circuit that receives the power supply voltage as an input, generates a reference voltage from the power supply voltage, and outputs the reference voltage, and an output voltage of the first output circuit A first voltage divider circuit that outputs a divided voltage obtained by dividing the output voltage by a predetermined voltage dividing ratio, the reference voltage and the divided voltage from the first voltage divider circuit as two inputs. The reference voltage and the divided voltage from the first voltage dividing circuit are differentially amplified by the power supply voltage and output to the first output circuit to control the first output circuit. The output voltage of the first output circuit
A first differential amplifier circuit that holds a positive voltage, a negative booster circuit that generates a negative voltage from a power supply voltage and outputs the negative voltage, and a negative output voltage that receives the negative voltage and that outputs a negative output voltage from the negative voltage. produced, and a second output circuit for outputting the negative output voltage from the output terminal as input and negative output voltage and the reference voltage of the second output circuit, the negative of the second output circuit A second voltage dividing circuit that outputs a divided voltage obtained by dividing the potential difference between the output voltage and the reference voltage by a predetermined dividing ratio, and the divided voltage from the second voltage dividing circuit and the ground potential are 2 The second output circuit is controlled by inputting to the second output circuit a voltage obtained by differentially amplifying the divided voltage from the second voltage dividing circuit and the ground potential with the power supply voltage. to the second differential amplification times for holding the negative output voltage of the second output circuit to a predetermined negative voltage It is characterized in that it comprises and.

[0038]

Also, in the semiconductor integrated circuit according to the present invention, in the semiconductor integrated circuit, the second voltage dividing circuit is provided between the output terminal of the second output circuit and the output terminal of the reference voltage generating circuit. a plurality of serially connected, the gate and drain connections, a transistor connected to the source and the substrate and are connected diode, one end connected to one of the nodes between the plurality of transistors, the other end One or more voltage dividing control transistors connected to the output terminal of the second output circuit and the control signal are input, and a control voltage based on the control signal is applied to the control terminal of the voltage dividing control transistor. Connect the control circuit and the one end to the reference voltage.
Connected to the other end of the diode-connected transistor ,
An output terminal for taking out the divided voltage, is composed of, the reference
The voltage is the threshold voltage of the diode-connected transistor
Is necessary to pass the minimum current to the voltage dividing circuit,
It is characterized in that the voltage is higher .

The semiconductor integrated circuit according to the present invention further comprises a voltage follower circuit which receives the output of the reference voltage generation circuit as an input in the semiconductor integrated circuit.
The second voltage dividing circuit is characterized in that the output voltage of the voltage follower circuit is input as the reference voltage instead of the output of the reference voltage generating circuit.

[0041]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiment 1. Hereinafter, a semiconductor integrated circuit according to the first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of the semiconductor integrated circuit according to the first embodiment. In FIG. 1, the semiconductor integrated circuit includes a booster circuit 1 for boosting a power supply voltage V _DD supplied to the semiconductor integrated circuit to a predetermined voltage V _PP and outputting the boosted voltage V _PP. The regulator circuit 2 outputs Vo. Here, as the booster circuit 1, for example, there is a charge pump circuit. The regulator circuit 2 further includes a reference voltage generation circuit 3, a differential amplifier circuit 4, an output circuit 5,
And a voltage dividing circuit 6.

The reference voltage generation circuit 3 receives the power supply voltage V _DD of the semiconductor integrated circuit as an input and sets a preset reference voltage V _DD.
Generate and output ref. The differential amplifier circuit 4 receives the reference voltage Vref generated by the reference voltage generation circuit 3 and the divided voltage Vd from the voltage dividing circuit 6 as two inputs, and performs differential amplification with the power supply voltage _VDD . The reference voltage generation circuit 3 operates by the power supply voltage V _DD supplied to the semiconductor integrated circuit, which is input to the power supply input terminal (not shown). The output circuit 5 uses the output voltage Va of the differential amplifier circuit 4 as a control voltage to increase the boosted voltage V
An output voltage Vo of the regulator circuit 2 in which _PP is adjusted is generated, and this is output to the outside of the regulator circuit 2. The voltage dividing circuit 6 outputs the divided voltage Vd obtained by dividing the output voltage Vo of the output circuit 5 by a predetermined voltage dividing ratio.

Next, the operation of the semiconductor integrated circuit according to the first embodiment will be described. The booster circuit 1 has a power supply voltage V
_A boosted voltage V _PP higher than the power supply voltage V _DD is generated from _DD and is supplied to the regulator circuit 2. The regulator circuit 2 outputs a predetermined constant voltage Vo obtained by stepping down the boosted voltage V _PP from the output end to the outside.

In the regulator circuit 2, the reference voltage generation circuit 3 generates a preset reference voltage Vref from the power supply voltage V _DD . Therefore, the reference voltage Vref becomes any value between the power supply voltage V _DD and the ground potential V _SS . The voltage dividing circuit 6 receives the output voltage of the regulator circuit 2, that is, the output voltage Vo of the output circuit 5, as an input, and uses this as a predetermined voltage dividing ratio r (r
According to ≧ 1), the divided voltage Vd divided so as to have a relationship of Vo / Vd = r is output.

FIG. 2 is a circuit diagram showing an example of the configuration of the voltage dividing circuit 6. As shown in FIG. 2, resistors 16a, 1 connected in series between the output terminal of the output circuit 5 and the ground potential.
An example of the voltage dividing circuit 6 is a resistance voltage dividing circuit configured by 6b and an output terminal for extracting the divided voltage Vd, which is connected to the node between the resistors 16a and 16b.
The number of resistors connected in series may be two or more.

The output voltage Vd from the voltage dividing circuit 6 and the reference voltage Vref output from the reference voltage generating circuit 3 are input to the differential amplifier circuit 4. Then, the differential amplifier circuit 4
The output voltage Vd of the voltage dividing circuit 6 is compared with the reference voltage Vref,
The output voltage Va differentially amplified using the power supply voltage V _DD is output to the output circuit 5. The output circuit 5 uses the output voltage Va.
Is controlled, and the output voltage Vd of the voltage dividing circuit 6 becomes Vd = Vref. Then, the output circuit 5 outputs the output voltage Vo = r · Vref obtained by stepping down the boosted voltage V _PP . In this way
The output voltage Vo of the regulator circuit 2 is held at a constant voltage Vo = r · Vref. The reference voltage generation circuit 3
Is preset so as to generate the reference voltage Vref with which the desired output voltage Vo is obtained.

FIG. 3 is a circuit diagram showing an example of the configuration of the output circuit 5 of the semiconductor integrated circuit according to the first embodiment. In FIG. 3, the P-type MOS transistor M2 has a source connected to the output terminal of the booster circuit 1 to receive the boosted voltage V _PP , and the bias voltage Vb output from the bias circuit 41 to the gate. Is entered. N-type MOS
The transistor M3 has a source grounded and a drain P
It is connected to the drain of the MOS transistor M2 and the output voltage Va of the differential amplifier circuit 4 is input to the gate.
The P-type MOS transistor M1 has a source with a boosted voltage V _PP.
Is input, the gate is connected to the drain of the P-type MOS transistor M2, and the drain serves as an output terminal for outputting the output voltage Vo. With such a circuit configuration, the output circuit 5 changes the gate voltage of the P-type MOS transistor M1 according to the change of the output voltage Va of the differential amplifier circuit 5, and the P-type MOS transistor M1 is input from the source. The boosted voltage V _PP controlled according to the gate voltage is output as the output voltage Vo. As a result, the output voltage Vo from the output terminal can be controlled by the output voltage Va of the differential amplifier circuit 4, and the boosted voltage V _PP which is not always constant is stepped down by the regulator circuit 2 to obtain a stable predetermined constant voltage Vo. Can be output from the output end to the outside.

As described above, the semiconductor according to the first embodiment
According to the integrated circuit, the power supply voltage V_DDThe reference voltage operated by
By including the pressure generation circuit 3 and the differential amplifier circuit 4,
The boosted voltage V is applied to the voltage generation circuit 3 and the differential amplifier circuit 4._PPTogether with
It is not necessary to supply the voltage, and the output current of the booster circuit 1 can be reduced.
Therefore, the boosted voltage V increases with the increase of the output current of the booster circuit 1. _PP
Can be suppressed. Therefore, the booster circuit 1
It is possible to reduce the capacity used,
The effect of reducing the area of the product circuit is obtained.

Although the output circuit 5 shown in FIG. 3 has been described as the output circuit in the first embodiment, this is an example, and other output circuits may be used.

4 and 5 are circuit diagrams showing another example of the configuration of the output circuit. For example, as shown in FIG.
Even when the bias circuit 41 is removed from the output circuit 5 shown in FIG. 3 and the output circuit 5a in which the gate of the P-type MOS transistor M2 is connected to the drain is used, the same operation as that of the output circuit 5 shown in FIG. Is obtained.

Further, as shown in FIG. 5, the output circuit 5b shown in FIG. 3 is formed by removing the bias circuit 41 and grounding the gate of the P-type MOS transistor M2.
Even if is used, the same operation as that of the output circuit 5 shown in FIG. 3 can be obtained. Thus, the output circuits 5, 5a and 5b shown in FIGS. 3 to 5 have been described as an example of the output circuit, but the output circuit of the present invention operates in the same manner as the output circuits 5, 5a and 5b. The present invention is not limited to these as long as the above can be obtained.

Further, in the first embodiment, the voltage dividing circuit 6 shown in FIG. 2 has been described as the voltage dividing circuit, but this is an example, and another voltage dividing circuit may be used.

6 and 7 are circuit diagrams showing another example of the configuration of the voltage dividing circuit. For example, as shown in FIG.
Between the output terminal of the output circuit 5 and the ground potential, the gate and the drain are connected, and the source and the substrate are connected, so-called diode-connected N-type MOS transistor 26a to
The voltage dividing circuit 6a having a structure in which 26d are connected in series may be used. The divided voltage Vd of the voltage dividing circuit 6a is the N-type MO.
The signal is output from the output terminal connected to one of the nodes between the S transistors 26a to 26d. It should be noted that diode-connected P-type MOS transistors may be used instead of the N-type MOS transistors 26a to 26d.

Further, as shown in FIG. 7, a capacitor 36 connected in series between the output terminal of the output circuit 5 and the ground potential.
a and 36b, an initialization circuit 61 that short-circuits both ends of the initialization circuit 61 to perform initialization, and an output terminal that is connected to a node between the capacitors 36a and 36b and that outputs a divided voltage Vd. Even if 6b is used, the same operation as that of the voltage dividing circuit 5 shown in FIG. 2 can be obtained. Thus, as an example of the voltage dividing circuit, the voltage dividing circuits 6 and 6 shown in FIGS. 2, 6 and 7 are used.
Although description has been made using a and 6b, the voltage dividing circuit of the present invention is not limited to these as long as the same operation as that of the voltage dividing circuits 6, 6a and 6b can be obtained.

Embodiment 2. Hereinafter, a semiconductor integrated circuit according to a second embodiment of the present invention will be described with reference to the drawings. FIG. 8 is a block diagram showing the configuration of the semiconductor integrated circuit according to the second embodiment. In FIG. 8, FIG.
The same reference numerals denote the same or corresponding parts. The semiconductor integrated circuit according to the second embodiment is the same as the semiconductor integrated circuit according to the first embodiment, except for the control signals V _C1 and V _C2.
The regulator circuit 2a is provided with a voltage dividing circuit 7 whose voltage dividing ratio can be changed by.

FIG. 9 shows a voltage dividing circuit 7 according to the second embodiment.
3 is a circuit diagram showing an example of the configuration of FIG. In FIG. 9, the voltage dividing circuit 7 includes a plurality of resistors 17a to 17d connected in series between the output end of the output circuit 5 and the ground potential V _SS , level shift circuits 71a and 71b, and voltage dividing control. P-type MOS
It has transistors 17e and 17f and an output terminal for outputting the divided voltage Vd. Level shift circuits 71a and 71b
Is the output voltage Vo of the regulator circuit 2a.
And the control signals V _C1 and V _C2 from the outside are input. In the P-type MOS transistor 17e for voltage division control, the source is connected to the output terminal of the output circuit 5, the drain is connected to the node between the resistors 17a and 17b, and the gate that is the control terminal is level-shifted. The output of the circuit 71a is input. In the P-type MOS transistor 17f for voltage division control, the source is connected to the output terminal of the output circuit 5, and the drain is connected to the node between the resistors 17b and 17c.
The output of the level shift circuit 71b is input to the gate that is the control end. An output terminal for outputting the divided voltage Vd obtained by dividing is connected to a node between the resistors 17c and 17d. The level shift circuits 71a and 71b have control signals V _C1 and V _C whose H level is V _DD and L level is V _SS.
The level of _C2 is converted so that the H level becomes Vo and the L level becomes V _SS . In this way, the level shift circuit 71a,
71b is used as a control circuit that outputs a control voltage based on the control signals V _C1 and V _C2 , respectively. And
In the voltage dividing circuit 7, by inputting the control signals V _C1 and V _C2 to the level shift circuits 71a and 71b, the P type M
When the OS transistors 17e and 17f are turned on or off and the resistance ratio changes, the voltage division ratio r of the divided voltage Vd can be changed.

Next, the operation of the semiconductor integrated circuit according to the second embodiment will be described. The operation related to the configuration other than the voltage dividing circuit 7 is the same as that of the first embodiment except that the voltage dividing circuit 6 is the voltage dividing circuit 7, and the description thereof is omitted.

The voltage dividing circuit 7 divides the output voltage Vo of the regulator circuit 2a according to the voltage dividing ratio r (r ≧ 1) determined by the control signals V _C1 and V _{C2 in} the relationship of Vo / Vd = r. Output Vd. Then, the control signals V _C1 and V _C2 are changed to change the voltage division ratio r to control the divided voltage Vd.

As described above, the semiconductor integrated circuit according to the second embodiment has the same effects as those of the first embodiment, and the voltage dividing ratio r can be changed by the control signals V _C1 and V _C2. 7 is provided, the control signals V _C1 , V
By changing _C2 , the reference voltage Vre
The output voltage Vo of the regulator circuit 2a can be changed without changing f, and different output voltages Vo used in operation modes such as erasing and writing of the nonvolatile semiconductor memory device are generated from one reference voltage Vref. It becomes possible. As a result, the reference voltage generation circuit 3 does not need to create a plurality of reference voltages Vref, the reference voltage generation circuit 3 can be simplified, the circuit scale can be reduced, and the area of the semiconductor integrated circuit can be further reduced. There is.

Although the voltage dividing circuit 7 shown in FIG. 9 has been described as the voltage dividing circuit in the second embodiment, this is an example, and another voltage dividing circuit may be used. For example, in the voltage dividing circuit 7, the number of resistors connected in series is plural other than four, and the voltage dividing control transistor 17 is used.
The drains of e and 17f may be connected to any of the nodes between different resistors, and an output terminal for taking out the divided voltage Vd may be provided at any of the nodes between the resistors. Also, in the voltage dividing circuit 7, one transistor for controlling the voltage division,
Alternatively, the number may be three or more.

10 to 12 are circuit diagrams showing other examples of the configuration of the voltage dividing circuit. For example, as shown in FIG. 10, a plurality of N-type MOS transistors 27a to 27 connected in series between the output terminal of the output circuit 5 and the ground potential V _SS.
It is also possible to use the voltage dividing circuit 7a provided with d, the level shift circuits 71a and 71b, the P-type MOS transistors 17e and 17f for voltage dividing control, and the output terminal for outputting the divided voltage Vd.

N-type MOS transistors 27a to 27d
Is a diode-connected MOS transistor whose gate and drain are connected and whose source and substrate are connected. The level shift circuits 71a and 71b and the P-type MOS transistors 17e and 17f for voltage division control are the same as those of the voltage division circuit 7 shown in FIG. An output terminal for outputting the divided voltage Vd is connected to the gate and the source of the transistor 27d.

In the voltage dividing circuit 7a, similar to the voltage dividing circuit 7, the P-type MO for voltage dividing control is controlled by the control signals V _C1 and V _C2.
The voltage division ratio r of the divided voltage Vd can be changed by turning on or off the S transistors 17e and 17f. By the way, in the voltage dividing circuit 7, the regulator circuit 2a
A high resistance is required to reduce the current flowing from the output end of the resistor through the resistor, which is disadvantageous in terms of area.
On the other hand, if the N-type MOS transistors 27a to 27d having the same characteristics are used in the voltage dividing circuit 7a, a voltage equal to the divided voltage Vd is applied between the gate and the source of each of the N-type MOS transistors 27a to 27d. become. Further, when the regulator circuit 2a operates, the divided voltage Vd becomes a value equal to the reference voltage Vref. From these,
The reference voltage Vref is applied to the N-type MOS transistors 27a to 27.
By presetting to a voltage slightly higher than the threshold voltage of d,
When the regulator circuit 2a operates, the gate-source voltage of the N-type MOS transistors 27a to 27d becomes a voltage slightly higher than the threshold voltage, and the voltage dividing circuit 7a is operated while the current flowing through the voltage dividing circuit 7a is minimized. You can Therefore, the current from the output of the regulator circuit 2a can be minimized, the scale of the booster circuit 1 can be minimized, and the entire semiconductor integrated circuit can be compared with the case where the voltage divider circuit 7 having a resistor is used. The circuit scale can be further reduced. Note that diode-connected P-type MOS transistors may be used instead of the N-type MOS transistors 27a to 27d.

Further, as shown in FIG. 11, a plurality of capacitors 37a to 37d connected in series between the output terminal of the output circuit 5 and the ground potential V _SS , the initialization circuit 72, and the level shift circuit 71a. , 71b, P-type MOS transistors 17e and 17f for voltage division control, and an output terminal for outputting the divided voltage Vd may be used.

The initialization circuit 72 includes capacitors 37a to 37d.
Initialize by shorting both ends of. Level shift circuit 71
Since a and 71b and P-type MOS transistors 17e and 17f for voltage division control are the same as those of the voltage division circuit 7 shown in FIG. 9, description thereof will be omitted. Capacity 37c and capacity 37d
An output terminal for outputting the divided voltage Vd is connected to a node between the input terminal and the output terminal.

In the voltage dividing circuit 7b, similarly to the voltage dividing circuit 7, the level shift circuits 71a and 71b turn on or off the P-type MOS transistors 17e and 17f for voltage dividing control according to the control signals V _C1 and V _C2. Is determined, and thereafter the capacity is initialized by the initialization circuit 72, whereby the voltage division ratio r of the divided voltage Vd can be changed by the control signals V _C1 and V _C2 . The voltage dividing circuit 7b needs to be initialized as compared with the voltage dividing circuits 7 and 7a, but since the current from the output of the regulator circuit 2a does not have a DC component,
This has the effect of significantly reducing the current flowing through the voltage dividing circuit 7b.

Further, as shown in FIG. 12, a capacitor 47 connected in series between the output terminal of the output circuit 5 and the ground potential V _SS.
a and 47b, and capacitors 47c and 47d whose one ends are grounded,
Level shift circuits 71a and 71b, N-type MOS transistors 17g and 17h for voltage division control, and initialization circuit 72
It is also possible to use a voltage dividing circuit 7c provided with an output terminal for outputting the divided voltage Vd.

The N-type MOS transistor 17g has its gate connected to the output of the level shift circuit 71a, its drain connected to the node between the capacitors 47a and 47b, and its source connected to the non-grounded side of the capacitor 47c. There is.
In the N-type MOS transistor 17h, the gate is connected to the output of the level shift circuit 71b, and the drain is the capacitor 47.
connected to the node between a and 47b, and the source is the capacitor 47
It is connected to the non-grounded side of d. The initialization circuit 72 performs initialization by short-circuiting both ends of each of the capacitors 47a to 47d. The level shift circuits 71a and 71b are similar to the voltage dividing circuit 7 shown in FIG. An output terminal for outputting the divided voltage Vd is connected to a node between the capacitors 47a and 47b.

In the voltage dividing circuit 7c, similarly to the voltage dividing circuit 7, the level shift circuits 71a and 71b turn on or off the N-type MOS transistors 17g and 17h for voltage dividing control according to the control signals V _C1 and V _C2. Is determined, and thereafter, the capacitors 47a to 47d are initialized by the initialization circuit 72, whereby the voltage division ratio r of the divided voltage Vd is controlled by the control signals V _C1 and V _C1 .
It can be changed by _C2 . Similarly to the voltage dividing circuit 7b, the voltage dividing circuit 7c also has the effect of significantly reducing the current from the output of the regulator circuit 2a.

As described above, as an example of the voltage dividing circuit, FIG.
Although the voltage divider circuits 7, 7a, 7b, 7c shown in FIG. 12 have been used for explanation, the voltage divider circuit of the present invention is not limited to the voltage divider circuits 7, 7c.
If the same operation as a, 7b, 7c can be obtained,
It is not limited to these.

Third Embodiment Hereinafter, a semiconductor integrated circuit according to a third embodiment of the present invention will be described with reference to the drawings. FIG. 13 is a block diagram showing the configuration of the semiconductor integrated circuit according to the third embodiment.

In FIG. 13, the same symbols as in FIG. 1 indicate the same or corresponding portions. The semiconductor integrated circuit according to the third embodiment, a negative booster circuit 8 for generating a predetermined negative voltage V _BB from the power supply voltage V _DD supplied to the semiconductor integrated circuit, the negative voltage V _BB generated negative booster circuit 8 Is input, and the regulator circuit 12 which produces | generates and outputs the output voltage Vo is comprised. Here, as the negative booster circuit 8, for example, there is a charge pump circuit that performs negative boosting.
The regulator circuit 12 further includes a reference voltage generation circuit 3
A differential amplifier circuit 4, an output circuit 9, and a voltage dividing circuit 10.

The differential amplifier circuit 4 receives the divided voltage Vd from the voltage dividing circuit 10 and the ground potential V _SS as two inputs, and supplies the power source voltage V
Differential amplification is performed by _DD . The reference voltage generation circuit 3
Operates with the power supply voltage V _DD supplied to the semiconductor integrated circuit, which is input to the power input terminal. The output circuit 9 uses the output voltage Va of the differential amplifier circuit 4 as a control voltage to generate an output voltage Vo in which the negative voltage V _BB generated by the negative booster circuit 8 is adjusted, and outputs this to the outside of the regulator circuit 12. . The voltage dividing circuit 10 includes a reference voltage Vref and a regulator circuit 12
Of the output voltage Vo is input, and a divided voltage Vd obtained by dividing the potential difference between the two with a predetermined dividing ratio is output. The reference voltage generation circuit 3 is similar to the reference voltage generation circuit 3 of the first embodiment, but in the reference voltage generation circuit 3 of the third embodiment, when the output impedance is high, The voltage Vref may be supplied to the voltage dividing circuit 10 with a low impedance via a voltage follower.

Next, the semiconductor integrated circuit according to the third embodiment will be described.
The operation of the road will be described. The negative booster circuit 8 is a positive power source.
Voltage V_DDTo negative voltage V_BBGenerate this regulator
Supply to the circuit 12. The regulator circuit 12 has a negative voltage
V_BBIs input and a predetermined negative constant voltage Vo is output from
Output to the outside. In the regulator circuit 12, see
The illumination voltage generation circuit 3 has a power supply voltage V_DDPreset from
The reference voltage Vref is generated. Therefore, the reference voltage Vref is
Power supply voltage V _DDAnd ground potential V_SSAny value between and
It The voltage dividing circuit 10 outputs the output voltage of the regulator circuit 12.
Of the output voltage Vo of the output circuit 9 and the reference voltage Vref
The potential difference is (Vd-Vo) / (Vref-V) according to the predetermined voltage division ratio r.
d) Output the divided voltage Vd divided so that the relation of r
It

FIG. 14 is a circuit diagram showing an example of the configuration of the voltage dividing circuit 10. As shown in FIG. 14, the output circuit 9
Of the resistors 110a and 110b connected in series between the output terminal of the resistor 110 and the output terminal of the reference voltage generation circuit 3, and the resistor 110a and 110b.
An example of the voltage dividing circuit 10 is a resistance voltage dividing circuit which is connected to the node between a and 110b and is configured with an output terminal for extracting the divided voltage Vd. The number of resistors connected in series may be two or more.

The divided voltage Vd from the voltage dividing circuit 10 and the ground potential V _SS are input to the differential amplifier circuit 4. And
The differential amplifier circuit 4 compares the divided voltage Vd with the ground potential V _SS and differentially amplifies the output voltage Va using the power supply voltage V _DD.
Is output to the output circuit 9. The output circuit 9 is controlled by this output voltage Va, and the divided voltage Vd of the voltage dividing circuit 10 is Vd =
It becomes V _SS . Then, the output circuit 9 outputs the output voltage Vo = −r · Vref obtained by adjusting the negative voltage V _BB . In this way, the output voltage Vo of the regulator circuit 12 is Vo = −
It is held at a constant negative voltage of r · Vref. The reference voltage generation circuit 3 is preset so as to generate the reference voltage Vref with which the desired output voltage Vo is obtained.

FIG. 15 is a circuit diagram showing an example of the structure of the output circuit 9 of the semiconductor integrated circuit according to the third embodiment.
In FIG. 15, the P-type MOS transistor M5 has its source connected to the power supply voltage V _DD and its gate connected to the differential amplifier circuit 4
Output voltage Va is input. The N-type MOS transistor M6 has a drain connected to the drain of the P-type MOS transistor M5, a gate to which the bias voltage Vb of the bias circuit 91 is input, and a source connected to the output terminal of the negative booster circuit 8 to form a negative voltage V _BB. Is entered. In the N-type MOS transistor M4, the source is connected to the output end of the negative booster circuit 8 to receive the negative voltage V _BB , the gate is connected to the drain of the P-type MOS transistor M5, and the drain outputs the output voltage Vo. It is the end. This output circuit 9
Is an N-type by the output of a circuit including an N-type MOS transistor M6 whose gate is supplied with the bias voltage Vb by the bias circuit 91 and a P-type MOS transistor M5 whose gate is supplied with the output voltage Va of the differential amplifier circuit 4. By controlling the MOS transistor M4, the voltage Vo at the output end can be controlled by the output voltage Va of the differential amplifier circuit 4.

As described above, the semiconductor according to the third embodiment
According to the integrated circuit, the power supply voltage V_DDThe reference voltage operated by
By including the pressure generation circuit 3 and the differential amplifier circuit 4,
A negative voltage V is applied to the voltage generation circuit 3 and the differential amplifier circuit 4._BBSupply
Output current of the negative booster circuit 8 can be reduced.
Therefore, as the output current of the negative booster circuit 8 increases, the negative voltage V _BB
Can suppress the rise of. Therefore, the negative booster circuit 8
It is possible to reduce the capacity used for
The effect of reducing the area of the integrated circuit is obtained. The book
In the third embodiment, the output circuit is shown in FIG.
The output circuit 9 to be output is described above, but this is an example.
Therefore, other output circuits may be used.

16 and 17 are circuit diagrams showing another example of the configuration of the output circuit. For example, as shown in FIG. 16, the output circuit 9 shown in FIG.
Even if the output circuit 9a having a configuration in which the gate of the N-type MOS transistor M6 is connected to the drain is used except for the configuration shown in FIG.
An operation similar to that of the output circuit 9 shown by is obtained. Further, as shown in FIG. 17, even if the bias circuit 91 is removed from the output circuit 9 shown in FIG. 15 and the output circuit 9b in which the gate of the N-type MOS transistor M6 is grounded is used,
An operation similar to that of the output circuit 9 shown by 5 is obtained.

Thus, as an example of the output circuit, FIG.
Although the output circuits 9, 9a and 9b shown in FIGS. 5 to 17 are used for explanation, the output circuit of the present invention is
It is not limited to these as long as the same operation as 9b can be obtained. Further, in the third embodiment, the voltage dividing circuit 10 shown in FIG. 14 has been described as the voltage dividing circuit 10, but this is an example, and another voltage dividing circuit may be used.

18 and 19 are circuit diagrams showing another example of the configuration of the voltage dividing circuit. For example, as shown in FIG. 18, a so-called diode connection in which a gate and a drain are connected between an output end of the reference voltage generation circuit 3 and an output end of the output circuit 9 and a source and a substrate are connected to each other N type M
The voltage dividing circuit 10a having a structure in which the OS transistors 120a to 120d are connected in series may be used. The divided voltage Vd of the voltage dividing circuit 10a is equal to the N-type MOS transistor 12
It is output from the output terminal connected to any of the nodes 0a to 120d. The N-type MOS transistor 12
Instead of 0a-120d, diode-connected P-type MOS
A transistor may be used.

Further, as shown in FIG. 19, capacitors 130a and 130b connected in series between the output terminal of the reference voltage generating circuit 3 and the output terminal of the output circuit 9 are short-circuited at both ends thereof. An initialization circuit 191 for performing initialization and a capacitor 130
The same operation as that of the voltage dividing circuit 10 shown in FIG. 14 can be obtained by using the voltage dividing circuit 10b including the output terminal for extracting the divided voltage Vd, which is connected to the node between a and 130b. Thus, as an example of the voltage dividing circuit, the voltage dividing circuits 10, 10a, 1 shown in FIGS. 14, 18, and 19 are used.
However, the voltage dividing circuit of the present invention is not limited to these as long as the same operation as that of the voltage dividing circuits 10, 10a and 10b can be obtained.

Fourth Embodiment Hereinafter, a semiconductor integrated circuit according to a fourth embodiment of the present invention will be described with reference to the drawings. FIG. 20 is a block diagram showing the configuration of the semiconductor integrated circuit according to the fourth embodiment. In FIG. 20,
13 are the same or corresponding circuit diagrams.
The semiconductor integrated circuit according to the fourth embodiment differs from the semiconductor integrated circuit according to the third embodiment in that the control signals V _C1 and V _C1
A regulator circuit 12a using a voltage dividing circuit 11 whose voltage dividing ratio can be changed by _C2 as a voltage dividing circuit is provided.

FIG. 21 is a voltage divider circuit according to the fourth embodiment.
11 is a circuit diagram showing an example of the configuration of FIG. Figure 21 Smell
The voltage dividing circuit 11 is connected to the output terminal of the reference voltage generating circuit 3 and outputs.
A plurality of resistors connected in series with the output terminal of the force circuit 9.
111a-111d and level shift circuits 112a, 1
12b and an N-type MOS transistor 111 for voltage division control
e, 111f and an output end for outputting the divided voltage Vd
Get The level shift circuits 112a and 112b have
The output voltage Vo of each regulator circuit 12a and the external
Control signal V_C1, V_C2Is entered. N for partial pressure control
Type MOS transistor 111e has an output circuit 9 at the source.
Output voltage Vo is input and the drain is connected to the resistor 111b.
111c, which is connected to a node between
The output of the level shift circuit 112a is input to the input terminal. Minute
The N-type MOS transistor 111f for voltage control has a source
The output voltage Vo of the output circuit 9 is input to the
Connected to the node between anti-111c and 111d, and control
The output of the level shift circuit 112b is input to the gate at the end.
I will be forced. A node between the resistors 111a and 111b
An output end for outputting the divided voltage Vd is connected to
It The level shift circuits 112a and 112b are at the H level
Is V_DDAnd L level is V_SSControl signal V which is_C1, V
_C2H level is V_DD, So that the L level becomes Vo
Bell transform. In this way, the level shift circuit 112
a and 112b are control signals V, respectively._C1, V_C2Based on
Used as a control circuit that outputs the control voltage
It Then, in the voltage dividing circuit 11, the control signal V_C1,
V_C2Is input to the level shift circuits 112a and 112b.
As a result, the N-type MOS transistors 111e and 111
If f is turned on or off and the resistance ratio changes,
Thus, the division ratio r of the divided voltage Vd can be changed.

Next, the operation of the semiconductor integrated circuit according to the fourth embodiment will be described. The operation related to the configuration other than the voltage dividing circuit 11 is the same as that of the third embodiment except that the voltage dividing circuit 10 is the voltage dividing circuit 11, and the description thereof is omitted.

The voltage dividing circuit 11 controls the control signal V_C1, V_C2By
According to the determined voltage division ratio r, (Vd-Vo) / (Vref-Vd) = r
Therefore, refer to the output voltage Vo of the regulator circuit 12a.
It outputs the divided voltage Vd which is the potential difference from the reference voltage Vref.
It And the control signal V_C1, V _C2By changing the partial pressure ratio r
The divided voltage Vd is controlled by changing.

As described above, the semiconductor integrated circuit according to the fourth embodiment has the same effects as those of the third embodiment, and the voltage dividing ratio r can be changed by the control signals V _C1 and V _C2. With the provision of 11, the control signal V _C1 ,
By changing V _C2 , the reference voltage V
The output voltage Vo of the regulator circuit 12a can be changed without changing ref, and different negative output voltages Vo used in operation modes such as erasing and writing of the nonvolatile semiconductor memory device can be referred to as one positive reference. It can be generated from the voltage Vref. As a result, the reference voltage generation circuit 3
However, there is no need to create a plurality of reference voltages Vref, the reference voltage generation circuit 3 can be simplified, the circuit scale can be reduced, and the area of the semiconductor integrated circuit can be further reduced.

Although the voltage dividing circuit 11 shown in FIG. 21 has been described as the voltage dividing circuit in the fourth embodiment, this is an example, and another voltage dividing circuit may be used. For example, in the voltage dividing circuit 11, the number of resistors connected in series is plural other than four, and the drains of the voltage dividing control transistors 111e and 111f are connected to any of the nodes between the different resistors, and An output terminal for extracting the divided voltage Vd may be provided at any of the nodes.
Further, the voltage dividing circuit 11 may have one or three or more transistors for voltage dividing control.

22 to 24 are circuit diagrams showing another example of the configuration of the voltage dividing circuit. For example, as shown in FIG. 22, a plurality of N-type MOS transistors 121a to 121d connected in series between the output terminal of the reference voltage generating circuit 3 and the output terminal of the output circuit 9 and the level shift circuit 112a,
112b and N-type MOS transistor 11 for voltage division control
You may use the voltage dividing circuit 11a provided with 1e, 111f and the output terminal which outputs the divided voltage Vd.

N-type MOS transistors 121a to 121
Reference numeral d is a diode-connected MOS transistor in which the gate and the drain are connected and the source and the substrate are connected. The level shift circuits 112a and 112b and the N-type MOS transistors 111e and 111f for voltage division control are
Since it is the same as the voltage dividing circuit 11 shown in FIG. 21, description thereof will be omitted. Transistor 121a and transistor 1
An output terminal for outputting the divided voltage Vd is connected to a node between the terminal 21b and 21b.

In the voltage dividing circuit 11a, the voltage dividing circuit 11
Similarly, the voltage dividing ratio r of the divided voltage Vd can be changed by turning on or off the N-type MOS transistors 117e and 117f by the control signals V _C1 and V _C2 . By the way, in the voltage dividing circuit 11, a high resistance is required in order to reduce the current flowing from the output end of the regulator circuit 12a through the resistance, which is disadvantageous in terms of area. On the other hand, in the voltage dividing circuit 11a, the N-type MOS having the same characteristics is used.
Using the transistors 121a to 121d, the reference voltage Vre
By setting f to a voltage slightly higher than the threshold voltage of the N-type MOS transistors 121a to 121d, the current flowing through the voltage dividing circuit 11a can be minimized as in the case of the voltage dividing circuit 7a according to the second embodiment. Therefore, the scale of the negative booster circuit 8 can be minimized, and the voltage divider circuit 1 having a resistor is provided.
The circuit scale of the entire semiconductor integrated circuit can be further reduced as compared with the case where 1 is used. In addition, N type M
A diode-connected P-type MOS transistor may be used instead of the OS transistors 121a to 121d.

Further, as shown in FIG. 23, a plurality of capacitors 131a to 131d connected in series between the output terminal of the reference voltage generating circuit 3 and the output terminal of the output circuit 9, an initialization circuit 113, Level shift circuits 112a and 112b and N-type MOS transistors 111e and 111f for voltage division control
It is also possible to use a voltage dividing circuit 11b provided with an output terminal for outputting the divided voltage Vd.

The initialization circuit 113 includes capacitors 131a to 13a.
Initialization is performed by short-circuiting both ends of 1d. The level shift circuits 112a and 112b and the N-type MOS transistors 111e and 111f for voltage division control are the same as those of the voltage division circuit 11 shown in FIG. Capacity 1
The divided voltage Vd is applied to the node between 31a and the capacitor 131b.
The output terminal for outputting is connected.

In the voltage dividing circuit 11b, the voltage dividing circuit 11
Similarly, the level shift circuits 112a and 112b change the N-type MOS transistor 111 according to the control signals V _C1 and V _C2.
e, 111f to be turned on or off, and then
By initializing the capacitors 131a to 131d by shorting both ends of the capacitors 131a to 131d by the initialization circuit 113, the voltage division ratio r of the divided voltage Vd can be changed by the control signals V _C1 and V _C2 . The voltage dividing circuit 11b is the voltage dividing circuit 1
Although it is necessary to initialize the circuit as compared with 1, 11a,
Since the current from the output of the regulator circuit 12a has no DC component, the current flowing through the voltage dividing circuit 11b can be significantly reduced.

Further, as shown in FIG. 24, capacitors 141a and 141b connected in series between the output terminal of the reference voltage generating circuit 3 and the output terminal of the output circuit 9, and the reference voltage V at one end.
capacitors 141c and 141d to which ref is input respectively,
A voltage dividing circuit 11c including level shift circuits 112a and 112b, P-type MOS transistors 111g and 111h for voltage dividing control, an initialization circuit 113, and an output terminal for outputting the divided voltage Vd may be used. .

In the P-type MOS transistor 111g, the gate is connected to the output of the level shift circuit 112a, the drain is connected to the node between the capacitors 141a and 141b,
The source is connected to the capacitor 141d. The gate of the P-type MOS transistor 111h has the level shift circuit 11
2b is connected to the output, and the drains have capacitances 141a, 14a.
It is connected to the node between 1b and the source is connected to the capacitor 141c. The initialization circuit 113 includes capacitors 141 a to 1
Both ends of 41d are short-circuited for initialization. The level shift circuits 112a and 112b correspond to the voltage dividing circuit 1 shown in FIG.
Since it is the same as that of 1, the description is omitted. Capacity 141
An output terminal for outputting the divided voltage Vd is connected to the node between a and 141b.

In the voltage dividing circuit 11c, the voltage dividing circuit 11c
Similarly, the level shift circuits 112a and 112b determine whether to turn on or off the N-type MOS transistors 111g and 111h for voltage division control according to the control signals V _C1 and V _C2 , and then the initialization circuit 113 causes the capacitors 141a to 1
By initializing 41d, the voltage division ratio r of the divided voltage Vd can be changed by the control signals V _C1 and V _C2 . Similarly to the voltage dividing circuit 11b, the voltage dividing circuit 11c also has the effect of significantly reducing the current from the output of the regulator circuit 12a.

As described above, as an example of the voltage dividing circuit, FIG.
1 to 24, the voltage dividing circuits 11, 11a, 11b,
Although 11c is used for the description, the voltage dividing circuit of the present invention is not limited to these as long as the same operation as that of the voltage dividing circuits 11, 11a, 11b, 11c can be obtained.

Embodiment 5. Hereinafter, a semiconductor integrated circuit according to a fifth embodiment of the present invention will be described with reference to the drawings. FIG. 25 is a block diagram showing the structure of the semiconductor integrated circuit according to the fifth embodiment. In FIG. 25,
The semiconductor integrated circuit receives a power supply voltage V _DD supplied to the semiconductor integrated circuit to a predetermined voltage V _PP and outputs the booster circuit 1, and a power supply voltage V _DD as an input and a preset reference voltage Vref. Reference voltage generation circuit 3 for generating and outputting
And a negative booster circuit 8 for generating a predetermined negative voltage V _BB from the power supply voltage V _DD, and a boosted voltage V _PP supplied to the output voltage V _PO.
And a negative regulator circuit 22b that receives the negative voltage V _BB as an input and generates an output voltage V _NO . The positive regulator circuit 22a further includes a differential amplifier circuit 4a, an output circuit 5, and a voltage dividing circuit 7
With. The negative regulator circuit 22b further includes a differential amplifier circuit 4b, an output circuit 9, and a voltage dividing circuit 11b.
And a voltage follower circuit 13. Note that the same reference numerals as those in FIGS. 8 and 20 denote the same or corresponding portions, and the description thereof will be omitted.

The voltage follower circuit 13 is composed of a differential amplifier circuit for supplying the reference voltage Vref to the voltage dividing circuit 11 via the voltage follower. Normally, in the negative regulator circuit 22b, the output impedance of the reference voltage generation circuit 3 is high, but the voltage follower circuit 13 lowers the output impedance of the reference voltage generation circuit 3 to supply the reference voltage Vref to the voltage dividing circuit 11. can do.

Next, the operation of the semiconductor integrated circuit according to the fifth embodiment will be described. The reference voltage generation circuit 3 generates a preset reference voltage Vref from the power supply voltage _VDD and outputs it to the positive regulator circuit 22a and the negative regulator circuit 22b. The reference voltage Vref input to the negative regulator circuit 22b is the voltage follower circuit 13
Is input to the voltage dividing circuit 11 via. The operation of the semiconductor integrated circuit other than the above is the same as in the second and fourth embodiments, and the description thereof is omitted.

As described above, according to the semiconductor integrated circuit of the fifth embodiment, the same effects as those of the second and fourth embodiments can be obtained, and the positive regulator circuit 22a and the negative regulator circuit 22b can be formed on one substrate. Since the positive regulator circuit 22a and the negative regulator circuit 22b are configured to operate with the same positive reference voltage Vref, the reference voltage generation circuit 3 can be shared by both, and In comparison with the case where the reference voltage generating circuit 3 is separately provided for the negative regulator circuit, the circuit scale can be reduced and the area of the semiconductor integrated circuit can be reduced.

The output circuit 5 according to the fifth embodiment includes the output circuits 5, 5a and 5b shown in FIGS.
Can be used, but is not limited thereto. Further, as the voltage dividing circuit 7, the voltage dividing circuits 7, 7a, 7b, 7c shown in FIGS. 9 to 12 can be used, but the voltage dividing circuit 7 is not limited to these.

Further, as the output circuit 9 according to the fifth embodiment, the output circuits 9, 9a shown in FIGS.
9b can be used, but is not limited thereto. In addition, as the voltage dividing circuit 11, as shown in FIGS.
It is possible to use the voltage dividing circuits 11, 11a, 11b, 11c indicated by 4, but not limited to these.

[0105]

[0106]

As is apparent from the above description , according to the semiconductor integrated circuit of the present invention , a negative booster circuit that generates a negative voltage from a power supply voltage and outputs the negative voltage, and the negative voltage as an input. An output circuit that generates an output voltage from the negative voltage and outputs the output voltage from an output terminal, and a positive voltage from the power supply voltage.
Of a reference voltage generation circuit that constitutes the raw reference voltage, as input and output voltage and the reference voltage of the output circuit, the output voltage and the reference voltage and the divided voltage potential difference of dividing by a predetermined division ratio of the a voltage dividing circuit for outputting said divided voltage and a ground potential as a second input, a voltage obtained by differential amplification a differential amplifier circuit that be output to the output circuit, the differential amplifier circuit
According to the comparison result of the divided voltage above and the ground potential,
The output circuit is controlled and the output voltage of the output circuit is set to a predetermined value.
By holding the negative voltage of the negative booster circuit, it is not necessary to supply the negative voltage to the reference voltage generation circuit and the differential amplifier circuit, and the output current of the negative booster circuit can be reduced. It is possible to suppress an increase in the negative voltage due to the increase. Therefore, it is possible to reduce the capacitance used in the negative booster circuit, and it is possible to obtain the effect of reducing the area of the semiconductor integrated circuit.

Further, according to the semiconductor integrated circuit of the present invention, by providing the voltage dividing circuit for setting the above voltage dividing ratio to different values according to the input control signal, the control signal can be changed to the conventional one. The output voltage of the regulator circuit can be changed without changing the reference voltage as in the example, and different output voltages used in operation modes such as erase and write of the nonvolatile semiconductor memory device can be changed from the single reference voltage. It becomes possible to generate. Accordingly, the reference voltage generating circuit eliminates the need to generate a plurality of reference voltages, simplifies the reference voltage generating circuit can be further reduced effects the area of semi-conductor integrated circuit can be obtained.

Further, according to the semiconductor integrated circuit of the present invention, by using the voltage dividing circuit provided with a plurality of diode-connected transistors connected in series, the current flowing through the voltage dividing circuit can be minimized. Therefore, the scale of the negative booster circuit can be reduced, so that the circuit scale of the semiconductor integrated circuit can be further reduced.

Further, according to the semiconductor integrated circuit of the present invention, a voltage divider having a plurality of capacitors connected in series and an initialization circuit for performing initialization by short-circuiting both ends of the plurality of capacitors is provided. By using the circuit, the current flowing through the voltage dividing circuit can be reduced, and the area of the semiconductor integrated circuit can be further reduced.

Further, according to the semiconductor integrated circuit of the present invention, the positive regulator circuit and the negative regulator circuit are provided on one substrate so that the positive regulator circuit and the negative regulator circuit operate with the same positive reference voltage. With this configuration, the reference voltage generation circuit can be shared by both, and compared to the case where the reference voltage generation circuit is separately provided for the positive regulator circuit and the negative regulator circuit,
The circuit scale can be reduced and the area of the semiconductor integrated circuit can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a semiconductor integrated circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing an example of a configuration of a voltage dividing circuit according to the first embodiment of the present invention.

FIG. 3 is a circuit diagram showing an example of a configuration of an output circuit according to the first embodiment of the present invention.

FIG. 4 is a circuit diagram showing another example of the configuration of the output circuit according to the first embodiment of the present invention.

FIG. 5 is a circuit diagram showing another example of the configuration of the output circuit according to the first embodiment of the present invention.

FIG. 6 is a circuit diagram showing another example of the configuration of the voltage dividing circuit according to the first embodiment of the present invention.

FIG. 7 is a circuit diagram showing another example of the configuration of the voltage dividing circuit according to the first embodiment of the present invention.

FIG. 8 is a block diagram showing a configuration of a semiconductor integrated circuit according to a second embodiment of the present invention.

FIG. 9 is a circuit diagram showing an example of a configuration of a voltage dividing circuit according to a second embodiment of the present invention.

FIG. 10 is a circuit diagram showing another example of the configuration of the voltage dividing circuit according to the second embodiment of the present invention.

FIG. 11 is a circuit diagram showing another example of the configuration of the voltage dividing circuit according to the second embodiment of the present invention.

FIG. 12 is a circuit diagram showing another example of the configuration of the voltage dividing circuit according to the second embodiment of the present invention.

FIG. 13 is a block diagram showing a configuration of a semiconductor integrated circuit according to a third embodiment of the present invention.

FIG. 14 is a circuit diagram showing an example of a configuration of a voltage dividing circuit according to a third embodiment of the present invention.

FIG. 15 is a circuit diagram showing an example of a configuration of an output circuit according to a third embodiment of the present invention.

FIG. 16 is a circuit diagram showing another example of the configuration of the output circuit according to the third embodiment of the present invention.

FIG. 17 is a circuit diagram showing another example of the configuration of the output circuit according to the third embodiment of the present invention.

FIG. 18 is a circuit diagram showing another example of the configuration of the voltage dividing circuit according to the third embodiment of the present invention.

FIG. 19 is a circuit diagram showing another example of the configuration of the voltage dividing circuit according to the third embodiment of the present invention.

FIG. 20 is a block diagram showing a configuration of a semiconductor integrated circuit according to a fourth embodiment of the present invention.

FIG. 21 is a circuit diagram showing an example of a configuration of a voltage dividing circuit according to a fourth embodiment of the present invention.

FIG. 22 is a circuit diagram showing another example of the configuration of the voltage dividing circuit according to the fourth embodiment of the present invention.

FIG. 23 is a circuit diagram showing another example of the configuration of the voltage dividing circuit according to the fourth embodiment of the present invention.

FIG. 24 is a circuit diagram showing another example of the configuration of the voltage dividing circuit according to the fourth embodiment of the present invention.

FIG. 25 is a block diagram showing a structure of a semiconductor integrated circuit according to a fifth embodiment of the present invention.

FIG. 26 is a block diagram showing a configuration of a conventional semiconductor integrated circuit.

FIG. 27 is a diagram showing the relationship between the output current and the output voltage of the booster circuit.

[Explanation of symbols]

1 Booster circuit 2, 2a, 12, 12a Regulator circuit 3 Reference voltage generation circuit 4, 4a, 4b Differential amplifier circuit 5, 5a, 5b, 9, 9a, 9b Output circuit 6, 6a, 6b, 7, 7a to 7c , 10, 10a, 10
b, 11, 11a to 11c Voltage dividing circuit 8 Negative boosting circuit 13 Voltage follower circuits 16a, 16b, 17a to 17d, 110a, 110
b, 111a to 111d resistor 22a positive regulator circuit 22b negative regulator circuits 26a to 26d, 27a to 27d, 17g, 17h, 1
11e, 111f, 120a to 120d, 121a to 1
21d, M3, M4, M6 N-type MOS transistors 17e, 17f, 111g, 111h, M1, M2, M
5 P-type MOS transistors 36a, 36b, 37a to 37d, 47a to 47d, 1
30a, 130b, 131a to 131d, 141a to 1
41d Capacitance 41, 91 Bias circuit 61, 72, 113, 191 Initialization circuit 71a, 71b, 112a, 112b Level shift circuit

Front page continuation (72) Inventor Tomio Kimura 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (56) References JP-A-5-325580 (JP, A) JP-A-8-17190 (JP , A) JP 10-133754 (JP, A) JP 7-231647 (JP, A) JP 64-23499 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB) Name) G11C 16/30 G11C 11/4074

Claims (15)

(57) [Claims] 1. A negative voltage is generated from a power supply voltage, and the negative voltage is generated.
And a negative booster circuit for outputting the negative voltage, and generating an output voltage from the negative voltage,
An output circuit that outputs the output voltage from an output terminal, and a reference voltage generator that generates a positive reference voltage from the power supply voltage
Circuit, with the output voltage of the output circuit and the reference voltage as input,
The potential difference between the output voltage and the reference voltage is determined by a predetermined voltage division ratio.
A voltage divider circuit that outputs a divided voltage divided by, and the divided voltage and the ground potential are input as two inputs and differentially amplified.
Comprising a differential amplifier circuit which outputs a voltage to the output circuit, the ratio between the divided voltage and the ground potential by the differential amplifier circuit
The output circuit is controlled by the comparison result, and the output circuit is controlled.
A semiconductor integrated circuit characterized in that the output voltage of the device is maintained at a predetermined negative voltage . 2. The semiconductor integrated circuit according to claim 1, wherein the voltage dividing circuit has a resistor having a plurality of resistors connected in series.
A semiconductor integrated circuit , which is an anti-voltage divider circuit. 3. The semiconductor integrated circuit according to claim 1 , wherein the voltage dividing circuit has a gate and a drain connected to each other, and
Diode-connected multiple transformers that connect the
Connect the resistors in series and refer to the divided voltage above at one end
In addition to the above diode-connected transistors connected to voltage
It has a structure to output from the end, the reference voltage of the diode-connected transistor
Threshold voltage required to flow the minimum current in the voltage divider circuit
A semiconductor integrated circuit characterized by having a voltage higher than that. 4. The semiconductor integrated circuit according to claim 1.
And an initialization circuit for performing initialization by dividing the voltage dividing circuit into a plurality of capacitors connected in series and both ends of the plurality of capacitors.
The semiconductor integrated circuit, characterized in that constructed from the. 5. The semiconductor integrated circuit according to claim 1 , wherein the voltage dividing circuit is configured to divide the voltage dividing circuit according to an input control signal.
A semiconductor integrated circuit, wherein the pressure ratio is set to different values . 6. The semiconductor integrated circuit according to claim 2 or claim 5, the dividing circuit, the output end of the output end and a reference voltage generating circuit of the output circuit
And a resistor connected in series between and, and one end of which is connected to one of the nodes between the resistors.
One or more of which the other end is connected to the output end of the above output circuit
, And the control signal as an input to the control end of the transistor.
A control circuit for providing a control voltage based on the control signal and a node connected to one of the nodes between the plurality of resistors.
A semiconductor integrated circuit characterized by comprising an output terminal for extracting a piezoelectric voltage . 7. The semiconductor integrated circuit according to claim 3 , wherein the voltage dividing circuit includes an output terminal of the output circuit and an output terminal of the reference voltage generating circuit.
A plurality of gates and drains connected in series between
Is connected, and the diode connection between the source and the substrate is connected.
One of the following transistors and one of the nodes between the above transistors.
Connected to the other end of the output circuit
One or more voltage-dividing control transistors and the above-mentioned control signal as input, and the above-mentioned voltage-dividing control transistors
A control voltage based on the above control signal is applied to the control end of the
Control circuit and the diode-connected transformer with one end connected to the reference voltage.
Output terminal for extracting divided voltage, which is connected to the other end of the transistor
And a semiconductor integrated circuit comprising: 8. The semiconductor integrated circuit according to claim 4 or claim 5, the dividing circuit, the output end of the output end and a reference voltage generating circuit of the output circuit
And a capacitor connected in series between and, and one end of which is connected to one of the nodes between the capacitors.
One or more of which the other end is connected to the output end of the above output circuit
, And the control signal as an input to the control end of the transistor.
A control circuit that gives a control voltage based on the control signal and an initialization circuit that short-circuits both ends of the plurality of capacitors to perform initialization.
Path and a node connected to one of the
A semiconductor integrated circuit characterized by comprising an output terminal for extracting a piezoelectric voltage . 9. The semiconductor integrated circuit according to claim 4 or 5 , wherein the voltage dividing circuit is connected in series between an output end of the output circuit and an output end of the reference voltage generating circuit. and two of the first capacitor, and one or more transistors having one end connected to a node between said first capacitor, one end is connected to the transistor, the reference photoelectric other end
The transistor connected to the output of the pressure generation circuit
A second capacitor which is the same number provided as input on SL control signal initializes the control circuit, the node between the first capacitor to provide a control voltage based on the control signal to the control terminal of the transistor A semiconductor integrated circuit comprising: an initialization circuit; and an output terminal connected to a node between the first capacitors for extracting a divided voltage. 10. The semiconductor integrated circuit according to claim 1 , wherein the output circuit has a source connected to an output terminal of the negative booster circuit and a drain.
Is a first N-type MOS transistor which is an output terminal of the output circuit.
Transistor and source are connected to the output terminal of the negative booster circuit, and the drain
Is connected to the gate of the first N-type MOS transistor.
A second N-type MOS transistor, a source connected to the power supply voltage, and a drain connected to the second
Connected to the drain of the N-type MOS transistor of
P-type MOS transistor connected to the output terminal of the differential amplifier circuit
And a transistor, the bias to the gate of the second N-type MOS transistor
A semiconductor integrated circuit comprising a bias circuit for applying a voltage . 11. The semiconductor integrated circuit according to claim 1 , wherein in the output circuit, the source is connected to the output of the negative booster circuit, and the drain is
A first N-type MOS transistor used as an output terminal of the output circuit
And the source is connected to the output of the negative booster circuit, and the gate and
Rain is the gate of the first N-type MOS transistor
A second N-type MOS transistor connected to the source , a source connected to the power supply voltage, and a drain connected to the second N-type MOS transistor.
Type MOS transistor is connected to the drain and the gate is
P-type MOS transistor connected to the output terminal of the differential amplifier circuit
The semiconductor integrated circuit, characterized in that consisted with Njisuta. 12. The semiconductor integrated circuit according to claim 1 , wherein the output circuit has a source connected to an output terminal of the negative booster circuit and a drain.
Is a first N-type MOS transistor which is an output terminal of the output circuit.
Transistor and source are connected to the output terminal of the negative booster circuit, and the drain
Connected to the gate of the first N-type MOS transistor
And a second N-type MOS transistor whose gate is at ground potential
Transistor and source are connected to the power supply voltage, and the drain is the second N
Type MOS transistor is connected to the drain and the gate is
P-type M OS tiger connected to the output terminal of the differential amplifier
The semiconductor integrated circuit, characterized in that consisted with Njisuta. 13. A boosted voltage obtained by boosting a power supply voltage is output.
And a booster circuit that receives the boosted voltage as an input and generates an output voltage from the boosted voltage
The first output circuit that outputs the output voltage from the output terminal and the positive voltage from the power supply voltage.
And a reference voltage generating circuit for generating a reference voltage of the first output circuit,
1st which outputs the divided voltage which is divided by a predetermined dividing ratio
Of the voltage dividing circuit, the reference voltage, and the divided voltage from the first voltage dividing circuit.
2 inputs, from the reference voltage and the first voltage divider circuit
The voltage obtained by differentially amplifying the divided voltage with the power supply voltage,
By outputting to the first output circuit,
The output voltage of the first output circuit is controlled by controlling the output circuit.
A first differential amplifier circuit that holds a predetermined positive voltage, and a negative rising circuit that generates a negative voltage from a power supply voltage and outputs the negative voltage.
And a pressure circuit, and inputs the negative voltage, generating a negative output voltage from negative voltage
The second output circuit that outputs the negative output voltage from the output end.
And a negative output voltage of the second output circuit and the reference voltage.
The negative output voltage of the second output circuit and the reference
A voltage-divided piezoelectric that divides the potential difference from the applied voltage by a predetermined voltage division ratio.
A second voltage dividing circuit for outputting a pressure, and a divided voltage from the second voltage dividing circuit and a ground potential
Voltage, the divided voltage from the second voltage divider circuit and the ground potential
And a voltage obtained by differentially amplifying
The second output circuit by outputting to the output circuit of
To control the negative output voltage of the second output circuit to a predetermined value.
The semiconductor integrated circuit characterized by comprising a second differential amplifier circuit, a for holding the negative voltage. 14. The semiconductor integrated circuit according to claim 13 , wherein the second voltage dividing circuit includes an output terminal of the second output circuit and the reference voltage generating circuit.
Multiple gates and drains connected in series with the output
A diode connected to the IN and connected to the source and the substrate.
Connected to a transistor or one of the nodes between the above transistors.
And the other end is connected to the output end of the second output circuit.
One or more voltage dividing control transistors and the voltage dividing control transistor that receives the control signal as an input.
A control voltage based on the above control signal is applied to the control end of the
Control circuit and the diode-connected transformer with one end connected to the reference voltage.
Output terminal for extracting divided voltage, which is connected to the other end of the transistor
If, consists, the reference voltage, the transistor of the diode connection
Threshold voltage required to flow the minimum current in the voltage divider circuit
A semiconductor integrated circuit characterized by having a voltage higher than that. 15. The semiconductor integrated circuit according to claim 13 or 14 , wherein the output voltage of the reference voltage generating circuit is input.
A follower circuit, wherein the second voltage dividing circuit uses the reference voltage as the reference voltage.
Instead of the output of the voltage generation circuit, the voltage follower
A semiconductor integrated circuit , wherein an output voltage of the circuit is input .