JPWO2004023554A1 - Semiconductor integrated circuit test method and semiconductor integrated circuit test support method - Google Patents

Abstract

The method for testing a semiconductor integrated circuit according to the present invention includes a process (S1) of selecting a required test library that defines a test process of the semiconductor integrated circuit, and a test target that is to be tested with respect to the test process defined by the selected test library. A process (S3, S5) for designating individual conditions of a test according to the operation mode of the semiconductor integrated circuit, a process (S6) for generating a test program for realizing a test process in which the individual conditions are designated by a tester, And a process (S7) for testing the semiconductor integrated circuit using the generated test program. The test library functions as a template for instructing a test process for each test operation of the semiconductor integrated circuit. A specific test execution procedure is defined by incorporating individual conditions into this.

Description

  The present invention relates to a test method and a test support method for a semiconductor integrated circuit, for example, a technique effective when applied to a method for testing a semiconductor memory by executing a test program.

A tester is used for a test for detecting a defect of the manufactured semiconductor integrated circuit. Test the tester by running the test program. For example, in the case of a semiconductor memory, a test pattern is written while selecting memory cells in a predetermined order, and a test operation for reading the written data and comparing it with the test pattern is repeated to determine a device failure or pass. The applied voltage, current, signal application interval, etc. at this time are also set as desired to serve as a burn-in test, and various function modes are switched to perform function checks. The specific contents of the test operation are determined according to the configuration and function of the test target semiconductor integrated circuit.
The content of the test realized by the tester is instructed by, for example, a test program creation instruction form in which a semiconductor integrated circuit designer expresses a part of a test specification in a test drawing format. The test program is described in a tester-specific program language specific to the tester by using a text editor, with the test engineer viewing the test drawing and understanding the specifications. The tester dedicated program language has a language specification similar to a general assembler language, and is a description format depending on the tester hardware, and is often different depending on the tester manufacturer / tester model.
However, the test drawing is a list of test condition parameters, and when there is no instruction of the test procedure, it is necessary to grasp the test specifications at that time when feeding back defective tests etc. generated in own product or other products. It has been found by the present inventor that there is a problem that it is difficult and the rapid response to the test program change is delayed.
Also, if there is no test procedure instruction in the test program creation instruction, misunderstanding about the test procedure between the designer of the semiconductor integrated circuit and the test engineer, or a mistake in the program description may result. As a result, the test quality may be degraded and the number of debugging steps may be increased.
Furthermore, the test drawing format facilitates test program creation by a test engineer. For those who do not know the tester-specific program language, the number of man-hours for drawing is increased, the efficiency of program creation is reduced, and test program coding errors are reduced. Also occurs, resulting in a design failure.
In addition, the business form of manufacturing a semiconductor integrated circuit includes a fabless undertaking design of a semiconductor integrated circuit, a fab undertaking the manufacture of a semiconductor integrated circuit, and a semiconductor integrated circuit manufacturing process, in addition to the conventional form in which manufacturing is integrated from design to manufacturing. There are intervening fabs (test fabs or test houses) that undertake testing, IP vendors that distribute circuit data (also called IP module data, etc.) of verified circuits as design parts, and service providers that mediate between fabs and fabless. A new business form has been anticipated, and the present inventors have found that it is necessary to correspond to such a business form with respect to instructions for creating a test program or instructions for a test procedure.
An object of the present invention is to provide a test method for a semiconductor integrated circuit and further a test support method for a semiconductor integrated circuit, which can eliminate the inconvenience caused by the fact that the test procedure instruction is not clarified in the test program creation instruction. There is to do.
Another object of the present invention is to provide a test method for a semiconductor integrated circuit and further a test support method for a semiconductor integrated circuit, which can improve both test quality and test efficiency.
Another object of the present invention is to clarify test program creation instructions or test procedure instructions in a new business form related to semiconductor integrated circuit manufacturing involving a fabless, fab, test fab, IP vendor, or service provider. Another object of the present invention is to provide a test method for a semiconductor integrated circuit, and a test support method for a semiconductor integrated circuit.
The above and other objects and novel features of the present invention will become apparent from the following description of the present specification and the accompanying drawings.

[1] A method for testing a semiconductor integrated circuit according to the present invention includes a process (S1) for selecting a required test library that defines a test process for the semiconductor integrated circuit, and a test process that is defined by the selected test library. Processing (S3, S5) for specifying individual conditions for testing in accordance with the operation mode of the semiconductor integrated circuit to be tested, and processing for generating a test program for realizing the test process in which the individual conditions are specified (S6) And a process (S7) for testing the semiconductor integrated circuit using the generated test program.
The test library includes data defining test preparation, test execution, and test end procedures for a required operation mode of a semiconductor integrated circuit to be tested, for example.
The process of generating the test program is performed, for example, by combining a plurality of program modules that define the operation control sequence of the tester and setting parameters for the program modules.
According to the semiconductor integrated circuit test method, the test library is positioned as a template for instructing a test process for each test operation of the semiconductor integrated circuit. When acquiring the test program necessary for the test, the test conditions specified by the selected template are satisfied by the process of specifying the individual conditions of the test, the tester constraints are satisfied, and the applied voltage required for the test, etc. Customized to satisfy the test conditions. In short, specific test execution procedures are defined by incorporating individual conditions into the test library. By generating a tester test program based on the customized test library data, it is possible to test the semiconductor integrated circuit while satisfying the test process and individual conditions. The designer of the semiconductor integrated circuit may instruct the test engineer about the test specifications by combining the test library and the individual test conditions. The test engineer can convert the test specification into a test program and obtain the required test program. If various test libraries are provided in advance on the test engineer side, the semiconductor integrated circuit designer need only be provided with individual test conditions for the test process.
Since the test specification is created using test process instruction data in a standardized test library, the test method is not unique to a product or a tester but can be developed for general use.
Since the test procedure (test process) and the test conditions to be used (individual test conditions) can be separately set, it contributes to rationalization of test specification creation and correction instruction error reduction.
Furthermore, since the created test program also tends to be standardized, it is expected that the number of coding steps for obtaining the program can be reduced. If the test specifications that can be reused are clarified, it becomes easier to examine the test at the time of product development, and it is also possible to facilitate screening for defects, which contributes to the improvement of test quality.
[2] Next, attention is focused on a method for testing a semiconductor integrated circuit using a fab undertaking both manufacturing and testing of a semiconductor integrated circuit or a fab undertaking a test of a semiconductor integrated circuit. In this case, the test method includes a test library indicating a test process of the semiconductor integrated circuit and a process of receiving individual conditions of the test corresponding to the operation mode of the semiconductor integrated circuit via a computer device connected to the network (25). A process for generating a test program for realizing a test process specified by the received individual test library and specified by the received test library, and a process for testing a semiconductor integrated circuit using the generated test program And including. Thereby, even in a business form in which a fab, a fabless, or the like intervenes, it is possible to clarify a test program creation instruction or a test procedure instruction, and it is possible to improve both the test quality and the test efficiency of the semiconductor integrated circuit.
[3] Next, attention is focused on a test support method for a semiconductor integrated circuit by a service provider or the like that mediates a transaction between a fabless that does not have a semiconductor integrated circuit manufacturing department or a test department and the fab. The test support method includes a first sending process for sending a test library that defines a test process of a semiconductor integrated circuit via a computer device connected to a network, and a test target for the test process that is defined by the test library. And a second transmission process for transmitting the received individual conditions of the test so that the correspondence relationship with the test library can be grasped. The test library is transmitted along with circuit data as an IP module, for example.
In the above method, the first sending process by a service provider or the like is a process for providing a test library for examining a test process of a semiconductor integrated circuit designed using the IP module for the purpose of design support for a fabless and the like. It is. The fabless requests the fab to manufacture the designed semiconductor integrated circuit, and requests the fab or a test house (test fab) for the test. At this time, the fabless gives the individual conditions of the test for the test process defined by the test library to the service provider that performs the mediation. The service provider receives the individual conditions of the test by the reception process, and transmits the received individual conditions by the second transmission process so that the correspondence relationship with the test library can be grasped. The delivery destination is a fab that the service provider arranges or introduces to the fabless.
This makes it possible to clarify test program creation instructions or test procedure instructions even in business forms where service providers intervene between fabs and fabless, and improve both test quality and test efficiency of semiconductor integrated circuits. Is possible.
[4] Another test support method focuses on the second transmission process when the service provider or the like is present. The test support method includes a process of sending a plurality of test libraries indicating a test process of a semiconductor integrated circuit and individual test conditions corresponding to the operation mode of the semiconductor integrated circuit via a computer device connected to a network. In addition, the individual conditions of the transmitted test can be grasped in correspondence with the test library. The destination is, for example, a fab that the service provider arranges or introduces to the fabless.
This makes it possible to clarify test program creation instructions or test procedure instructions even in business forms where service providers intervene between fabs and fabless, and improve both test quality and test efficiency of semiconductor integrated circuits. Is possible.

FIG. 1 is an explanatory view illustrating a method for testing a semiconductor integrated circuit according to the present invention.
FIG. 2 is an explanatory diagram illustrating the standard test library database of the flash memory in a hierarchical manner.
FIG. 3 is an explanatory diagram illustrating the contents of the test process defined by the test library in consideration of the relationship with the standard template.
FIG. 4 is an explanatory diagram illustrating specific contents of test customization.
FIG. 5 is an explanatory diagram exemplarily showing a test execution procedure and a program generated based on the test execution procedure when a flash memory test is assumed.
FIG. 6 is an explanatory diagram schematically showing a state when the memory LSI is tested by causing the tester to execute a test program.
FIG. 7 is an explanatory view showing another example of a method for testing a semiconductor integrated circuit according to the present invention.
FIG. 8 is an explanatory diagram exemplifying a processing flow when designing and manufacturing a semiconductor integrated circuit by an integrated manufacturer.
FIG. 9 is an explanatory diagram illustrating a business form in which a test department separates from a design department or a manufacturing department and mediates a test library and test conditions through a data file or the like via a network such as the Internet.
FIG. 10 is an explanatory diagram illustrating a business form in which a service provider is interposed between a fab and a fabless and a test library and test conditions are mediated by a data file or the like via a network such as the Internet.
FIG. 11 is an explanatory view showing the interface and the contents of the support work by the test support method described in FIG. 9 and FIG.
FIG. 12 is an explanatory diagram illustrating a state in which the fab, the fabless, and the service provider in the business form of FIGS. 9 and 10 are connected to the network.

FIG. 1 illustrates a method for testing a semiconductor integrated circuit according to the present invention. In the test method shown in the figure, a standard test library database 1 in which a plurality of data libraries defining the test process is databased is used. The standard test library database 1 defines a plurality of test libraries that are expanded from the basic template by the test standardization means 2 and in which the test procedure is set for each operation mode of the test target semiconductor integrated circuit.
The standard test library database 1 of an electrically rewritable non-volatile memory, for example, a flash memory, is hierarchically operated for each of erase, read, and write (program) operations as illustrated hierarchically in FIG. There are several test libraries that define the test process. FIG. 2 shows test libraries ERS-RBOPEN, RD-RBOPEN, PGM-RBOPEN which specify test steps when testing is performed with the ready / busy signal output terminal (RB) open, and bad sectors to be tested. Examples include test libraries ERS-BADSCT, RD-BADSCT, and PGM-BADSCT that define the test process to be performed.
The contents of the test process defined by the test library are illustrated in FIG. In particular, FIG. 3 clearly shows the development from the standard template. The test process is roughly divided into test preparation, test execution, and test end procedures. In the basic template, test preparation includes (1) fail memory initialization, (2) power supply voltage setting, (3) voltage condition setting such as signal voltage, (4) timing condition setting, and (5) pin condition setting such as impedance. , (6) Input order setting such as signal, (7) Load condition setting such as output load, and (8) Pattern setting such as test pattern. The test execution is (9) test execution. The test end is (10) voltage condition cancellation, (11) power supply condition cancellation, and (12) fail result processing. The basic template has contents that can be applied not only to the flash memory but also to other memories. One read test library RD-RBOPEN developed specifically for the flash memory includes (5) a test step of setting pin conditions as RB pin open as test preparation. Another test library RD-BADSCT for reading developed specifically for flash memory includes (6) a test process of setting a defective sector (SCT) setting pattern in a register as test preparation. In short, the developed test library defines a test process according to the function and operation mode of the semiconductor integrated circuit.
Returning to the description of the test method in FIG. A test library necessary for the test is selected from the standard test library database 1 (S1). For example, when testing the signal RB for the flash memory in an open state, the test libraries ERS-RBOPEN, RD-RBOPEN, and PGM-RBOPEN in FIG. 2 are selected.
Next, individual test conditions corresponding to the operation mode of the semiconductor integrated circuit to be tested are designated for the test process defined by the selected test library (S2, S3). That is, the operation specification data such as the operation voltage and the operation frequency of the semiconductor integrated circuit to be tested are stored in the product operation specification database 3, and test conditions are selected with reference to the operation specification data (S2). For example, when selecting an operating voltage, a voltage considering burn-in is selected. When selecting a test pattern, the influence of disturbance that may occur due to a circuit configuration, an applied voltage, or the like is taken into consideration. The test process defined by the test library is customized according to the selected test condition (S3). The processing contents so far do not take into account the tester's function and ability. In other words, the processing does not depend on the specific function or ability of the tester.
Next, a process for generating a test program for realizing the test process in which the individual condition is specified by a tester is performed (S4 to S6). That is, a tester constraint condition is given to the result customized in step S3 (S4), and the test condition is confirmed (S5). In short, it is determined whether the test condition does not exceed the capability of the tester to be used in terms of supply voltage / current and operating frequency. If the capacity is exceeded, the test condition is corrected (S5). After confirming the test conditions, a test program is generated based on the test conditions and the test library (S6). The process of generating the test program is performed by a combination of a plurality of program modules that define the operation control sequence of the tester and parameter settings for the program modules. The program module is described using a tester-specific program language, and is selected from the test sequence database 4 and used. As a result, a test program 5 corresponding to the tester is generated and executed to test the semiconductor integrated circuit (S7).
FIG. 4 illustrates the specific contents of the test customization. For example, one test library RD-RBOPEN is selected from the standard test library, and the test condition RD-CDT is incorporated. The test library data in which the test conditions are incorporated specifically defines an actual read test execution procedure and is illustrated as RD-SQC.
The test conditions (individual test conditions) as described above were designed by semiconductor integrated circuit designers to extract test standards and operation definitions from product operation specifications such as data sheets and fine-tuned for defective product screening. Thereafter, a direct value is substituted into a variable symbol in the test library RD-RBOPEN to be described.
A test library in which test conditions represented by RD-SQC are incorporated and which defines a specific test execution procedure (also simply referred to as a test execution procedure) is not particularly limited, but a test number (No.), a library name (for example, RD) -RBOPEN identification name) and test condition name (for example, test condition RD-CDT identification name) correlation list (test label) RD-LST.
The test labels are arranged in the test execution order to define the test operation of the semiconductor integrated circuit. Assuming the test of the flash memory shown in FIG. 5, a series of operations of erasing (ERASE), writing (PROGRAM), and reading for reading (READ) is used as a basic unit to constitute each test. Each test reading (READ) uses a test execution procedure RD-SQC in which specific test conditions are incorporated, and similarly, detailed description is omitted for writing (PROGRAM) and erasing (ERASE). Test execution procedures PGM-SQC and ERS-SQC in which typical test conditions are incorporated are used. The test execution procedure is specified by the correlation list (test label) RD-LST of the read operation. Similarly, the write (PROGRAM) and read (READ) test execution procedures PGM-SQC and ERS-SQC are specified by the test label PGM-LST for the write operation and the test label RD-LST for the read operation.
The test execution procedure PGM-SQC, ERS-SQC, and RD-SQC are checked in step S5 to check whether the test execution procedure PGM-SQC, ERS-SQC, and RD-SQC match the restrictions set for each individual test apparatus (tester). The tester constraint is checked by, for example, checking whether the voltage setting value, waveform timing setting value, file memory maximum capacity, number of test pins, etc. are within the limits with the values described in the tester constraint file.
The test execution procedures PGM-SQC, ERS-SQC, and RD-SQ are used to refer to the corresponding test program module from the test sequence database 4 in the test program generation process of step S6. Provides individual test condition values to be assigned to the test program module. For example, in FIG. 5, a program PGMi (Y test) constituting a part of a test program T-PGM composed of an ID read, an X test, a Y test, and an X test is a test execution procedure PGM-SQC, ERS-SQC, RD. -Generated based on SQ. The test program T-PGM can incorporate a program for controlling the entire test, such as simultaneous test execution control by a tester, communication control with a product handler device, and host transfer of test results.
FIG. 6 schematically shows a state when the memory LSI is tested by causing the tester to execute a test program. In the figure, testers 10 and 11 can test different memory LSIs 12 and 13, respectively. Each tester 10, 11 has test program storage units 10A, 11A, test execution control units 10B, 11B, measurement and characteristic determination units 10C, 11C, and test result storage units 10D, 11D as fail memories. The test program 5 is supplied to the test program storage units 10A and 11A of the testers 10 and 11 via the test update means 14. The supplied test program is executed, and the measurement and characteristic determination units 10C and 11C acquire test results for the internal state obtained thereby, and the test results are temporarily stored in the test result storage units 10D and 11D. And stored in the test result database 15. The test program update unit 14 responds to the necessity of partially correcting the test program according to the test result or the like.
FIG. 7 shows another example of a method for testing a semiconductor integrated circuit according to the present invention. The difference from the test method described with reference to FIG. 1 is that the test execution procedure in which the test conditions are incorporated in the standard test library 1 is stored in the database (test execution procedure database) 18 and the test conditions are summarized at the end. I checked. According to this method, when the test condition is corrected, the test customization setting process S3 is performed, and the corrected test execution procedure is re-registered in the test execution procedure database 18. Since the test execution procedure that does not depend on the tester actually used can be made into a database, it can be used for a general-purpose tester of various specifications.
FIG. 8 illustrates a processing flow in the case where an integrated manufacturer (simply referred to as a manufacturer) of designing and manufacturing a semiconductor integrated circuit performs. For example, a semiconductor integrated circuit manufacturer 20 has a design department, a manufacturing department, and a test department, and performs design processing, wafer process processing, assembly, testing, and shipment of completed chips.
According to the semiconductor integrated circuit test method described above, the test library is positioned as a template for instructing a test process for each test operation of the semiconductor integrated circuit, and when the test program necessary for the test is obtained, With the process of specifying individual conditions, it is possible to realize customization that satisfies the tester's constraints and the test conditions such as applied voltage necessary for the test for the test process defined by the selected template. . As a result, a test program for the tester is generated based on the customized test library data (test execution procedure), so that the semiconductor integrated circuit can be tested while satisfying the test process and individual conditions. Therefore, the designer of the semiconductor integrated circuit has only to give the test specifications to the test engineer by a combination of the test library and the individual test conditions. The test engineer can convert the test specification into a test program and obtain the required test program.
Since the test specification is created using test process instruction data in a standardized test library, the test method is not unique to a product or a tester but can be developed for general use. Since the test process and the test conditions to be used can be separately set and settable, this contributes to rationalization of test specification creation and reduction of mistakes in correction instructions. Furthermore, since the created test program also tends to be standardized, it is expected that the number of coding steps for obtaining the program can be reduced. If the test specifications that can be reused are clarified, it becomes easier to examine the test at the time of product development, and it is also possible to facilitate screening for defects, which contributes to the improvement of test quality.
FIG. 9 illustrates a business form in which a test department separates from a design department or a manufacturing department and mediates the test library and test conditions through a data file via a network such as the Internet. For example, the fabless 21 has a semiconductor integrated circuit design department. In response to a request from the fabless 21, the fab 22 performs wafer process processing, assembly, and testing, and supplies completed chips to the fabless 21. Another fab (wafer fab) 23 performs wafer process processing in response to a request from the fabless 21. A fab (test fab) 24 having a test department receives a wafer manufactured by the fab 23 in response to a request from the fabless 21, performs assembly and testing, and supplies a completed chip to the fabless 21.
The test method in the business form of FIG. 9 will be described. For example, it is assumed that the fabless 21 and the fabs 22 to 24 are connected via the network 25 and the fabless 21 requests the fab 22 or 24 for a test. An information interface for a test required in this request form is performed along a path A in FIG.
In the test of the semiconductor integrated circuit by the fabs 22 and 24 having the test department, the fabs 22 and 24 connected to the network 25 are connected to the target semiconductor integrated circuit via the communication terminal computer device (not shown). The test library and the individual test conditions (test conditions) corresponding to the operation mode of the semiconductor integrated circuit are received from the fabless 21. The fab 22 or 24 incorporates the received individual condition, generates the test execution procedure defined by the received test library, and generates a test program for realizing this by a required tester. The test program generation processing is the same as the processing in steps S3 to S6 in FIG. A test of the semiconductor integrated circuit is performed using the generated test program. Thereby, even in a business form in which a fab, a fabless, or the like intervenes, it is possible to clarify a test program creation instruction or a test procedure instruction, and it is possible to improve both the test quality and the test efficiency of the semiconductor integrated circuit.
FIG. 10 illustrates a business form in which a service provider is interposed between a fab and a fabless, and the test library and test conditions are mediated by a data file via a network such as the Internet.
The service provider 27 mediates the transaction between the fabless 21 and the fab 28. In FIG. 10, the fab 28 is a general term for the wafer fab 28A, the assembly fab 28B, the test fab 28C, and the like. Here, it is assumed that the test library is distributed as a test IP module between the fabless 21, the service provider (for example, IP provider or IP vendor) 27, and the fab 28. For example, when the test fab 28C is established as a business, it is inevitably necessary to reduce the test cost by maintaining the test quality for the fabless 21 that is a customer and by making efforts of the test fab 28C itself. At this time, since the test conditions instructed by the customer fabless 21 cannot be changed, the test fab 28C shortens the test time so as to make the best use of the tester owned by the test fab 28C. As an example, when setting the test pin voltage, the test procedure may be shortened by changing the test procedure in which voltage is sequentially applied with a certain time between a plurality of pins. In such a case, the test method relating to the test procedure is used. This can be positioned as a test support method for a semiconductor integrated circuit by a service provider or the like.
First, attention is focused on a method for supporting a test of a semiconductor integrated circuit by the service provider 27 at the interface of the path B between the fabless 21 and the service provider 27.
The service provider 27 has a front end related to chip design such as circuit design and process design, and a back end related to testing. The back end provides the test IP module. Naturally, the service provider 27 mediates an optimal fab for each IP module. The provision of a back-end test IP module is positioned as test support.
The test support method mainly composed of the service provider 27 includes a first transmission process for transmitting a test library for defining a test process of a semiconductor integrated circuit via a computer device connected to a network, and a test defined by the test library. A process of receiving individual test conditions corresponding to the operation mode of the semiconductor integrated circuit to be tested for the process, and a second transmission process of transmitting the received individual conditions of the test so that the correspondence relationship with the test library can be grasped. ,including. The test library is transmitted along with circuit data as an IP module, for example.
In the above method, the first sending process by the service provider 27 and the like is intended to provide a test library for examining a test process of a semiconductor integrated circuit designed using the IP module for the purpose of design support for the fabless 21 and the like. It is processing to do. The fabless 21 requests the fab 28 to manufacture the designed semiconductor integrated circuit, and requests the test fab 28C to perform the test. At this time, the fabless 21 gives an individual test condition for the test process defined by the test library to the service provider 27 that performs the mediation. The service provider 27 receives the individual conditions of the test, and transmits the received individual conditions in the second transmission process so that the correspondence relationship with the test library can be grasped. This destination is a fab that the service provider 27 arranges or introduces to the fabless 21.
As a result, even in a business form in which the service provider 27 or the like is interposed between the fab 28 and the fabless 21, the test program creation instruction or the test procedure instruction can be clarified, and both the test quality and test efficiency of the semiconductor integrated circuit can be achieved. It becomes possible to improve.
The test support of providing the back-end test IP module by the service provider 27 gives a test library and test conditions for the test fab 28C from a different viewpoint. The test support method according to this aspect is equivalent to paying attention to the second transmission process when the service provider 27 or the like is present. That is, the test support method sends out a plurality of test libraries indicating test steps of the semiconductor integrated circuit and individual test conditions according to the operation mode of the semiconductor integrated circuit via a computer device connected to the network. The individual condition of the test to be sent out can be correlated with the test library. The destination is, for example, a fab that the service provider 27 arranges or introduces to the fabless. The test processing in the fab at this time is the same as the processing of the fabs 22 and 24 that receive the test library and the test conditions at the path A interface in FIG. For example, this enables the fab to define the “loading interval 50 ms” in the READ test execution procedure, optimize the charging interval time, and shorten the charging interval time, thereby realizing a device for reducing the test time.
With the above business form, even in the business form where service providers intervene between fabs and fabless, it is possible to clarify test program creation instructions or test procedure instructions, improving both test quality and test efficiency of semiconductor integrated circuits It becomes possible to make it.
FIG. 11 shows a concrete example of the interface (I / F) and the contents of the support work by the test support method described in FIG. 9 and FIG.
FIG. 12 illustrates a state in which the fabs 22, 23, 24, 28, the fabless 21, and the service provider 27 in the business form of FIGS. 9 and 10 are connected to the network 25. Reference numeral 30 denotes a computer device which means a communication terminal computer device connected to a network. Although not particularly shown, the computer apparatus also has fabs 22, 23, 28, fabless 21, and service provider 27, respectively. Reference numeral 31 denotes a reception buffer for temporarily storing the test library and test conditions received from the service provider 27 or the fabless 21.
Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited thereto, and various modifications can be made without departing from the scope of the invention.
For example, the test procedure of the flash memory illustrated in FIG. 4 is an example, and the present invention does not limit the specific contents of the test procedure. What is necessary is just to determine suitably according to the kind, function, etc. of a semiconductor integrated circuit. Further, the present invention is not limited to a memory LSI, but can be applied to a test of a logic LSI. The present invention can also be applied to a semiconductor integrated circuit having a BIST (Built In Self Test) circuit when a test in a range not covered by the BIST is performed. The present invention is applicable not only to tests after assembly but also to wafer-level tests. In short, in FIG. 9, the fab 23 may be effective when the test method of the present invention is carried out. If various test libraries are provided in advance on the test engineer side, the semiconductor integrated circuit designer need only be provided with individual test conditions for the test process.

  The present invention can be widely applied to a device test of a semiconductor integrated circuit such as a memory LSI such as a flash memory or a dynamic random access memory, or a logic LSI.

Claims (11)

A process of selecting a required test library that defines the test process of the semiconductor integrated circuit;
A process for specifying individual test conditions according to the operation mode of the semiconductor integrated circuit to be tested for the test process defined by the selected test library;
A process for generating a test program for realizing the test process in which the individual conditions are specified by a tester;
And a test method for testing the semiconductor integrated circuit using the generated test program. 2. The semiconductor integrated circuit according to claim 1, wherein the test library comprises data defining a test preparation procedure, a test execution procedure, and a test end procedure for a required operation form of the semiconductor integrated circuit to be tested. Circuit test method. 2. The semiconductor integrated circuit according to claim 1, wherein the process of generating the test program is performed by a combination of a plurality of program modules that define an operation control sequence of the tester and a parameter setting for the program modules. Test method. A test library indicating a test process of a semiconductor integrated circuit and a process of receiving individual conditions of a test corresponding to the operation mode of the semiconductor integrated circuit via a computer device connected to a network;
Processing for generating a test program for realizing the test process specified by the received individual condition and specified by the received test library by a tester;
And a test method for testing the semiconductor integrated circuit using the generated test program. 5. The semiconductor integrated circuit according to claim 4, wherein the computer device is owned by a fab undertaking both manufacturing and testing of the semiconductor integrated circuit, or a fab undertaking testing of the semiconductor integrated circuit. Test method. 5. The semiconductor integrated circuit according to claim 4, wherein the test library comprises data defining test preparation procedures, test execution procedures, and test end procedures for a required operation form of a semiconductor integrated circuit to be tested. Circuit test method. A process of sending a test library defining a test process of a semiconductor integrated circuit via a computer device connected to a network;
A process for receiving individual test conditions corresponding to the operation mode of the semiconductor integrated circuit to be tested for the test process specified by the test library, and the correspondence between the received individual test conditions and the test library can be grasped. A data processing method comprising: a process for sending out the data. 8. The test support method for a semiconductor integrated circuit according to claim 7, wherein the test library is transmitted along with circuit data as an IP module. The computer apparatus is owned by a service provider that mediates a transaction between a fab undertaking manufacturing and testing of a semiconductor integrated circuit or a fab undertaking testing of a semiconductor integrated circuit and a fabless undertaking design of a semiconductor integrated circuit. 8. The test support method for a semiconductor integrated circuit according to claim 7, further comprising: Including a plurality of test libraries indicating a test process of the semiconductor integrated circuit and a test individual condition according to the operation mode of the semiconductor integrated circuit via a computer device connected to the network,
A test support method for a semiconductor integrated circuit, wherein the individual conditions of the test to be sent can be grasped in correspondence with the test library. The computer apparatus is owned by a service provider that mediates a transaction between a fab undertaking manufacturing and testing of a semiconductor integrated circuit or a fab undertaking testing of a semiconductor integrated circuit and a fabless undertaking design of a semiconductor integrated circuit. 11. The semiconductor integrated circuit test support method according to claim 10, further comprising:

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