JPWO2003005368A1 - Semiconductor device and memory module - Google Patents

Abstract

One of the objects of the present invention is to realize a memory capable of performing high-speed burst access at a low cost. For this purpose, the SRAM, DRAM, and control circuit are modularized into one package. The control circuit assigns addresses so that the front part of the burst access is accessed to the SRAM and the rear part of the burst access is accessed to the DRAM. In DRAM, when two chips are mapped to the same address space and refresh is performed alternately, the refresh is hidden and the usability is improved. Thereby, a memory capable of performing high-speed burst access using a large-capacity DRAM is realized at low cost. A large-capacity memory that does not need to be refreshed externally to the DRAM is realized. Furthermore, it is possible to reduce the size by mounting a plurality of semiconductor chips on one sealing body.

Description

Technical field
The list of documents referred to in this specification is as follows, and the documents are referred to by document numbers. [Document 1]: JP-A-3-31946, [Document 2]: JP-A-8-194463, [Document 3]: JP-A-11-176152, [Document 4]: JP-A-10-11348 Publication, [Document 5]: Japanese Patent Publication No. 8-288453.
In [Document 1], a memory bank constituted by a memory element having a high access speed and a memory bank constituted by a memory element having a low access speed are used, and the memory bank accessed at the beginning of the burst transfer has a high speed memory. A method of using a memory bank using elements is described.
[Document 2] describes a memory control system that speeds up burst transfer using a high-speed memory that stores data with a fast transfer order during burst transfer and a low-speed memory that stores data with a slow transfer order.
[Document 3] describes a DRAM that reduces the waiting time until the initial data is read by reading the initial data from the small-capacity memory bank using a small-capacity memory bank and a large-capacity memory bank. Is described.
[Document 4] has two DRAM blocks, stores the same data in duplicate, shifts the refresh timing between the two DRAM blocks, and avoids collision between external access and DRAM refresh Is described. This control is performed by a DRAM controller, and this DRAM controller generates physically independent address signals and control signals for two DRAM blocks.
[Document 5] describes a multi-chip semiconductor device in which a plurality of semiconductor chips are housed or sealed in one semiconductor package. As the plurality of semiconductor chips, a microprocessor chip and a memory chip (DRAM, SRAM, EEPROM) are described as examples.
Prior to the present application, the inventors of the present application examined speeding up of a DRAM and an increase in capacity of a high speed SRAM for a network device. A DRAM generally used in personal computers or the like has a large storage capacity, and is a suitable device for realizing a large-capacity memory system at a low cost. Also, when accessing a group of data at once, a high data transfer rate can be realized by burst transfer. However, so-called first access from the start of access to the first data input / output takes time, and it has not been used so much for applications that require a high-speed response.
A typical example of an application that requires a high-speed response is a network device. Up to now, fast access high-speed SRAMs have been used to transfer a large amount of data divided in packet units with good response. On the other hand, as the performance of network devices has improved in recent years, it has been strongly desired to increase the capacity of SRAM. However, it is difficult to increase the storage capacity while maintaining high-speed first access.
Accordingly, one of the objects of the present invention is to realize a memory having a fast first access and a large storage capacity.
Disclosure of the invention
Examples of typical means of the present invention are as follows. A static random access memory (SRAM), two dynamic random access memories (DRAM), and an access controller are mounted on one sealing body or mounting substrate, and a semiconductor chip is mounted on the sealing body or mounting substrate. An electrode for performing the wiring and an electrode for connecting the sealing body or the mounting substrate to the outside are provided.
When performing burst transfer, the access controller controls memory access so that data read in the first half of the burst is read from the SRAM and data read in the second half is read from the DRAM.
Further, in order to conceal the refresh of the DRAM from outside the semiconductor device, the access controller controls the memory access to the DRAM. When the memory access is performed by the access controller during the first period, the first DRAM is accessed, and when the memory access is performed during the second period, the second DRAM is accessed. .
In the first period, a read / write command for the DRAM is executed for the first DRAM, and the second DRAM is executed with priority on refresh. In the second period, a read / write command for the DRAM may be executed for the second DRAM, and refresh may be preferentially executed for the first DRAM.
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The circuit elements constituting each block of the embodiment are not particularly limited, but are formed on a single semiconductor substrate such as single crystal silicon by a known integrated circuit technology such as CMOS (complementary MOS transistor).
<Example 1>
FIG. 1 shows a first embodiment of a memory module as an example of a semiconductor integrated circuit device to which the present invention is applied. This memory module is composed of two chips. Each chip will be described below.
First, a static random access memory (SRAM) and a control circuit (CTL_LOGIC) are integrated in CHIP1 (SRAM + CTL_LOGIC). The control circuit controls the SRAM and CHIP2 (DRAM1) integrated in CHIP1. CHIP2 (DRAM1) is a dynamic random access memory (DRAM). There are various types of DRAM such as EDO, SDRAM, and DDR because of differences in internal configuration and interface. In this embodiment, an SDRAM is described as an example of a dynamic random access memory that performs reading / writing by a command synchronized with the most typical clock.
A clock (CLK), addresses (A0 to A20), and command signals (/ CS, / OE, / WE) are input to the memory module from the outside. Since these are so-called external access signals, they can be called external access signals. Power is supplied through S-VCC, S-VSS, S-VCCQ, S-VSSQ, D1-VCC, D1-VSS, D1-VCCQ, D1-VSSQ, and I / O0 to I / O15 for data input / output. Are used and are commonly connected to CHIP2 (DRAM1) and CHIP1 (SRAM + CTL_LOGIC). In addition, a wait signal (WAIT) is output according to the operation status.
CHIP1 is an address (D1-A0 to D1-A11) and commands (D1-CKE, D1- / CS, D1- / WE, D1- / RAS, D1- / CAS, D1-DQMU /) required for the operation of CHIP2. DQML). One of the features is that signal terminals for DRAM interface are not directly visible at the input / output nodes between the memory module and the outside.
Here, each command signal will be briefly described. / CS input to CHIP1 is a chip enable signal, / OE is an output enable signal, and / WE is a write enable signal. WAIT is a wait signal output when the response is delayed. The memory module can access the SRAM and DRAM using these command signals, address lines (A0 to A20) and data input / output lines (I / O0 to I / O15). Access to this memory module is performed by a so-called synchronous SRAM interface method.
Access to the SRAM and access to the DRAM are distinguished by the value of the input address. The control circuit (CTL_LOGIC) determines the access destination based on the input address value. The range of addresses for accessing the SRAM and the range of addresses for accessing the DRAM are determined by setting values in advance in a register (REG) provided in the control circuit (CTL_LOGIC).
Address signals and command signals necessary for accessing the DRAM are generated by the control circuit (CTL_LOGIC) and applied to the DRAM. The DRAM needs to be initialized after turning on the power, but the control circuit (CTL_LOGIC) also performs signal generation and timing control necessary for initialization of the DRAM.
When refreshing the DRAM, the control circuit (CTL_LOGIC) can periodically perform a bank active command. In general, the refresh characteristic of DRAM deteriorates at high temperatures, but a DRAM can be used in a wider temperature range by providing a thermometer in the control circuit (CTL_LOGIC) and narrowing the interval between bank active commands at high temperatures.
In so-called burst access in which continuous data is handled by one access, if it is desired to shorten the time from the start of access until the head data is output, the access may be started from the SRAM area. That is, by assigning addresses so that the first half of burst access is performed on the SRAM and the second half of burst access is performed on the DRAM, burst access is started from the SRAM area, and the first data is output after the access is started. The time until it is done can be shortened.
When the access made from the outside overlaps with the refresh timing of the DRAM, or when the burst access is started from the DRAM, the response of the memory module is delayed. In these cases, the memory module can output a wait signal to notify the operation delay to the outside.
According to the embodiment described above, a large-capacity memory module using an inexpensive general-purpose DRAM can be realized while following the synchronous SRAM interface system. In the memory module according to the present invention, it is possible to widen the use temperature range of the DRAM by changing the refresh interval executed in the module according to the temperature, and a large capacity memory module having a wide use temperature range can be realized.
In addition, when performing burst access, the SRAM takes charge of the first half of the burst access and the DRAM takes charge of the second half of the burst access, thereby realizing a high-speed, large-capacity memory module for first access.
Another object of the present invention is to realize a memory module with a small data holding current. For this purpose, the data holding current can be reduced by extending the refresh interval executed inside the module, particularly at low temperatures.
FIG. 2 shows CHIP1 (SRAM + CTL_LOGIC). CHIP1 (SRAM + CTL_LOGIC) is composed of an SRAM and a control circuit (CTL_LOGIC), and the integrated SRAM is a synchronous SRAM that has been generally used. The control circuit (CTL_LOGIC) is a portion other than the SRAM of CHIP1, and is shown as an area surrounded by a broken line in FIG. 2, and is configured by A_CONT, INT, TMP, RC, and COM_GEN. The operation of each circuit block will be described below.
The access controller (A_CONT) (or memory controller) converts an address input from the outside according to a value set in a built-in register (REG), and selects a memory to be accessed. When the SRAM is selected, an address (S-ADD) and a command signal (S- / CS, S- / WE, S- / OE) are sent to the SRAM, and access to the SRAM is started. When DRAM is selected, DRAM addresses (D1-A0 to D1-A11) are generated and command signals (D1-CKE, D1- / CS, D1- / RAS, D1- / CAS, D1). -/ WE, D1-DQMU / DQML) are sent to the DRAM and access is started. In addition, the access controller (A_CONT) controls the overall operation of the DRAM and CHIP1 (SRAM + CTL_LOGIC).
The initialization circuit INT initializes the DRAM when power supply to the DRAM is started. The temperature measurement module (TMP) measures the temperature and outputs a signal corresponding to the measured temperature to RC and A_CONT. RC is a refresh counter that generates an address to be refreshed in accordance with the refresh interval of the DRAM. Further, the refresh interval is changed according to the temperature with reference to the output signal of the temperature measurement module (TMP). The command generator (COM_GEN) generates a command necessary for accessing the DRAM.
Next, the operation of this memory module will be described. In order to perform memory access to CHIP1 (SRAM + CTL_LOGIC), a conventional synchronous SRAM interface is used. When an address signal (A0 to A20) and a command signal (S- / WE, S- / CS, S- / OE) are input in synchronization with the clock CLK, access to the memory is started. The value of the address signal (A0 to A20) input from the outside is converted, and the type of memory to be accessed is determined. The conversion pattern is determined by a value set in advance in a register (REG) in A_CONT.
When the SRAM is accessed, the converted address is output to the S-ADD and sent to the SRAM, and command signals (S- / CS, S- / WE, S- / OE) to the SRAM are output. Thus, access to the SRAM is started. Thereafter, so-called synchronous SRAM is accessed.
Similarly, when the DRAM is accessed, the converted address is output to D1-A0 to D1-A11. Further, command signals (D1-CKE, D1- / CS, D1- / RAS, D1- / CAS, D1- / WE, D1-DQMU / DQML) are also output, and access to the DRAM is started.
FIG. 3 shows an example of a memory map of this memory module. In this example, both the SRAM area and the DRAM area have a storage capacity of 16 Mbit, and the entire memory module realizes a storage capacity of 32 Mbit. In FIG. 3, the vertical direction represents an address, the horizontal direction represents a burst length (BL: BURST LENGTH), and the area represents the storage capacity of the memory module. One square in the figure corresponds to 2B (bytes) which is the same as the number of I / Os.
Here, a case where burst access is executed in this memory module will be described. It is assumed that reading with a burst length of 8 (BL = 8) is executed starting at address 000010 (H) (H represents a hexadecimal number). First, access is started from (1) (000010 (H)) in the SRAM area, and sequentially read (2) (0000011 (H)) and (3) (0000012 (H)). Access is terminated at {circle around (8)} (000017 (H)). A total of 16B is read out by 2B × 8 continuous readings. Of these, 8B from (1) to (4) is read from the SRAM area, and 8B from (5) to (8) is read from the DRAM area.
Since the 8B read performed in the first half of the burst access is performed from the SRAM area, it is possible to execute from the address input to the first data output in a short time. In this memory module, a memory system is configured by combining memories having different access times as described above, and high-speed burst access is realized by assigning high-speed memory to an address that is likely to be the head of burst access. .
When burst access starts from the DRAM area, it takes time until the first data is output after the address is input. In such a case, a wait signal is output, and the memory module can notify the outside that data output is delayed.
FIG. 4 shows timing waveforms when burst reading is performed from the memory module. The CLK frequency is 100 MHz, which is an example using a general-purpose SDRAM and a high-speed SRAM. In the illustrated example, eight consecutive data (01 to 08, 11 to 18) are read from two addresses M0 and M1 input to the memory module. In this burst read, after the address is input, / OE becomes low and the read is started, and the data (01, 11) read first with latency 1 is output. This high-speed reading is realized by using an SRAM as a memory.
The state of access to the SRAM and DRAM 1 used in the module is shown at the bottom of the timing waveform. The addresses (M0, M1) input to the memory module are converted and input to the SRAM and DRAM, respectively. After conversion, the addresses input to the SRAM are S0 and S1. On the other hand, the addresses input to the DRAM are R0, R1, C0, and C1. R0 and R1 are row addresses, and C0 and C1 are column addresses. Similarly, P shown in D1-ADD indicates the input of a precharge command.
In the first half of the burst read, the data (01-04, 11-14) accessed by the SRAM by the addresses S0, S1 is read, and in the second half of the burst read, the data accessed by the DRAM 1 by the addresses R0, C0, R1, C1. (05-08, 15-18) are read out. Burst access with low latency is realized by combining data read from the SRAM and data read from the DRAM.
FIG. 5 shows a timing waveform when the write access is continuously performed. In the illustrated example, data (01 to 08, 11 to 18) is continuously written to the two addresses M0 and M1 input to the memory module 8 times each. In this burst write, after the address is input, / WE becomes high and the write is started, and the first data (01, 11) is written with the latency 1.
The state of access to the SRAM and DRAM 1 used in the module is also shown below the timing waveform. The first half data (01 to 04, 11 to 14) of the burst write is written to the SRAM, and the second half data (05 to 08 and 15 to 18) of the burst write is written to the DRAM 1. The timing of inputting a row address, a column address, and a precharge command to the address (D1-ADD) of the DRAM 1 is different from that at the time of reading, but the latency is small by combining writing to the SRAM and writing to the DRAM as in reading. Burst access is realized.
FIG. 6 is a timing waveform when writing and reading are continuously performed. In DRAM 1, precharge P is executed after completion of eight consecutive data writes by address M 0, and therefore the input of the next row address R 1 is delayed. For this reason, in this memory module, after executing the write access M0, the read access M1 is executed after a necessary cycle is left.
FIG. 7 shows a timing waveform when reading is started from the DRAM area. When data is read from the DRAM, it takes time until the first data is output, so the latency from the input of the address to the output of the first data is as large as 5 cycles. In this example, a wait signal (WAIT) is output from the memory module during the period from the address input to the start of the first data output. This signal allows an external device to know that the data output is delayed.
Also, the wait signal (WAIT) is output in the same manner when the memory access and the DRAM refresh conflict and the response is delayed, and the response delay can be notified to the outside.
FIG. 8 shows a configuration example of the synchronous SRAM in the present embodiment. An X decoder X-DEC, a memory array MA (SRAM), a Y gate Y-GATE, a Y decoder Y-DEC, an input data control circuit D_CTL, a control circuit CONTROL LOGIC, and an input / output buffer for each signal line. The SRAM memory array includes so-called SRAM memory cells each including two inverters cross-coupled. The SRAM is a synchronous SRAM conventionally used. The memory module according to this embodiment can be configured by this SRAM.
FIG. 9 shows a configuration example of the DRAM in the present embodiment. X address buffer X-ADB, refresh counter REF. COUNTER, X decoder X-DEC, memory array MA, Y address buffer Y-ADB, Y address counter Y-AD COUNTER, Y decoder Y-DEC, sense amplifier circuit & Y gate (column switch) SENS AMP. & I / O BUS, input data buffer circuit INPUT BUFFER, output data buffer circuit OUTPUT BUFFER, control circuit & timing generation circuit CONTROL LOGIC & TG. Memory array MA includes a plurality of memory cells provided at intersections of a plurality of word lines and a plurality of data lines. Each of the memory cells is a so-called 1T1C type DRAM memory cell in which a capacitor and a MISFET are connected in series. The DRAM is a conventional general-purpose SDRAM. That is, it includes two independently operable memory banks, and the address input terminal and data input / output terminal for them are shared and used in a time-sharing manner for each bank. This DRAM can constitute the memory module of this embodiment.
FIG. 10 shows an example of mounting the memory module in this embodiment. 10A is a top view and FIG. 10B is a cross-sectional view. In this example, the memory module is composed of CHIP1, CHIP2, PCB, PATH1, PATH2, BONDING PAD, SOLDER BALL, and COVER. CHIP1 and CHIP2 arranged on the upper surface of the PCB substrate are connected to the PCB substrate by PATH1 and PATH2 through the BONDING PAD, respectively. A SOLDER BALL is formed on the lower surface of the PCB substrate, and is connected to a wiring substrate of a device using the memory module. A cover (COVER) made of a resin mold is formed on the upper surface of the memory module to ensure the mechanical strength of the memory module. When a metal cover (COVER) is used, a shielding effect against electromagnetic noise can be obtained. According to this mounting example, it is possible to reduce the wiring length between chips and to configure a memory module with a small wiring load capacity. In addition, since the mounting area is reduced, it is possible to reduce the size and weight of the device using the memory module.
FIG. 11 shows a modified example of the memory module described with reference to FIG. 11A is a top view and FIG. 11B is a cross-sectional view. 10 differs from the mounting example shown in FIG. 10 in the method of arranging and connecting the CHIP2 to the PCB substrate. In this example, SOLDER BUMP is used for the arrangement and connection of the CHIP2 and the PCB board, and the CHIP2 is arranged and connected to the PCB board in a so-called face-down manner. By using SOLDER BUMP, the wiring process can be simplified and the load capacity due to the wiring can be reduced. The rest is the same as the mounting example shown in FIG.
FIG. 12 shows a modified example of the memory module described in FIG. 12A is a top view and FIG. 12B is a cross-sectional view. The method of disposing and connecting CHIP1 to the PCB board is different from the mounting example shown in FIG. In this example, SOLDER BUMP is used for the arrangement and connection of the CHIP1 and the PCB board, and the CHIP1 is arranged and connected to the PCB board in a so-called face-down manner. By using SOLDER BUMP, the wiring process can be simplified and the load capacity due to the wiring can be reduced. The rest is the same as the mounting example shown in FIG.
FIG. 13 shows another example of mounting the memory module in this embodiment. 13A is a top view and FIG. 13B is a cross-sectional view. In this example, the memory module is composed of CHIP1, CHIP2, PCB, PATH3, BONDING PAD, SOLDER BUMP, SOLDER BALL, and COVER. The CHIP 1 disposed on the upper surface of the PCB substrate is connected face-down to the PCB substrate. SOLDER BUMP is used for arrangement and wiring. CHIP2 is arranged on the upper surface of CHIP1, and is connected to the PCB substrate by PATH3 via BONDING PAD. A SOLDER BALL is formed on the lower surface of the PCB substrate, and is connected to a wiring substrate of a device using the memory module. A cover (COVER) made of a resin mold is formed on the upper surface of the memory module to ensure the mechanical strength of the memory module. When a metal cover (COVER) is used, a shielding effect against electromagnetic noise can be obtained. According to this mounting example, it is possible to reduce the wiring length between chips and to configure a memory module with a small wiring load capacity. In addition, since the mounting area is reduced by stacking chips, it is possible to reduce the size and weight of a device using the memory module.
FIG. 14 shows a modified example of the memory module described with reference to FIG. 14A is a top view and FIG. 14B is a cross-sectional view. The arrangement positions of CHIP1 and CHIP2 are interchanged with the implementation example shown in FIG. In the case where the area of CHIP2 is larger than that of CHIP1, this example can be implemented more easily. The rest is the same as the mounting example shown in FIG.
According to the embodiment described above, if a memory module is configured using a high-speed SRAM and a large-capacity DRAM, a fast access high-speed large-capacity burst memory module can be realized at low cost while following the synchronous SRAM interface system. I can do it.
Further, in the memory module according to the present invention, it is possible to widen the use temperature range of the DRAM by changing the interval of refresh executed inside the module depending on the temperature, and a large capacity memory module with a wide use temperature range can be realized.
In the control circuit (CTL_LOGIC) according to the present invention, a DRAM is used. However, since refresh necessary for the DRAM is executed by the control circuit (CTL_LOGIC), it can be used without considering the refresh like the SRAM.
Another object of the present invention is to realize a memory module with a small data holding current. For this purpose, the data holding current can be reduced by extending the refresh interval executed inside the module, particularly at low temperatures.
Further, the mounting method of the present memory module can reduce the device mounting area and reduce the weight in a portable device using the present memory module.
<Example 2>
FIG. 15 shows a second embodiment of a memory module which is an example of a semiconductor integrated circuit device to which the present invention is applied. One of the differences from the first embodiment is that two DRAMs are used to obscure the influence of DRAM refresh from the outside. Therefore, this memory module is composed of three chips. Each chip will be described below.
First, a static random access memory (SRAM) and a control circuit (CTL_LOGIC) are integrated in CHIP4 (SRAM + CTL_LOGIC). The control circuit controls the SRAM and CHIP2 (DRAM1) and CHIP3 (DRAM2) integrated in CHIP4. CHIP2 (DRAM1) and CHIP3 (DRAM2) are dynamic random access memories (DRAMs). There are various types of DRAM such as EDO, SDRAM, and DDR because of differences in internal configuration and interface. Although any DRAM can be used for this memory module, this embodiment will be described taking SDRAM as an example.
A clock (CLK), addresses (A0 to A20), and command signals (/ CS, / OE, / WE) are input to the memory module from the outside. Power supply is through S-VCC, S-VSS, S-VCCQ, S-VSSQ, D1-VCC, D1-VSS, D1-VCCQ, DL-VSSQ, D2-VCC, D2-VSS, D2-VCCQ, D2-VSSQ Supplied. I / O0 to I / O15 are used for data input / output, and a wait signal WAIT is output according to the operation status.
CHIP4 is an address (D1-A0 to D1-A11, D2-A0 to D2-A11) and commands (D1-CKE, D2-CKE, D1- / CS, D2- / CS, D1) necessary for the operation of CHIP2 and CHIP3. -/ WE, D2- / WE, D1- / RAS, D2- / RAS, D1- / CAS, D2- / CAS, D1-DQMU / DQML, D2-DQMU / DQML). One of the features is that signal terminals for DRAM interface are not directly visible at the input / output nodes between the memory module and the outside.
Here, each command signal will be briefly described. / CS input to CHIP1 is a chip enable signal, / OE is an output enable signal, and / WE is a write enable signal. WAIT is a wait signal output when the response is delayed. This memory module can access SRAM and DRAM using these command signals, address lines (A0 to A20) and data input / output lines (I / O to I / O15). Access to this memory module is performed by a so-called synchronous SRAM interface method.
Access to the SRAM and access to the DRAM are distinguished by the value of the input address. The control circuit (CTL_LOGIC) determines the access destination based on the input address value. The range of addresses for accessing the SRAM and the range of addresses for accessing the DRAM are determined by setting values in advance in a register (REG) provided in the control circuit (CTL_LOGIC).
Address signals and command signals necessary for accessing the DRAM are generated by the control circuit (CTL_LOGIC) and applied to the DRAM. The DRAM needs to be initialized after turning on the power, but the control circuit (CTL_LOGIC) also performs signal generation and timing control necessary for initialization of the DRAM.
When refreshing the DRAM, the control circuit (CTL_LOGIC) can periodically perform a bank active command. In general, the refresh characteristic of DRAM deteriorates at high temperatures, but a DRAM can be used in a wider temperature range by providing a thermometer in the control circuit (CTL_LOGIC) and narrowing the interval between bank active commands at high temperatures. Further, in this memory module, by using two DRAMs alternately, the DRAM refresh can be completely hidden from the outside.
In so-called burst access in which continuous data is handled by one access, burst access may be started from the SRAM area in order to increase the speed of first access. That is, burst access is started from the SRAM area by allocating addresses so that the first half of burst access is performed on the SRAM and the second half of burst access is performed on the DRAM, so that the first access can be speeded up.
When burst access is started from the DRAM, the response of this memory module is delayed. In these cases, the memory module can output a wait signal to notify the operation delay to the outside.
According to the embodiment described above, a large-capacity memory module using an inexpensive general-purpose DRAM can be realized while following the synchronous SRAM interface system. In the memory module according to the present invention, it is possible to widen the use temperature range of the DRAM by changing the refresh interval executed in the module according to the temperature, and a large capacity memory module having a wide use temperature range can be realized.
Further, by alternately using the two DRAMs, the DRAM refresh can be completely hidden from the outside, so that a synchronous SRAM compatible memory module that does not deteriorate in performance due to the refresh can be realized.
Furthermore, when burst access is performed, the first half of the burst access is handled by the SRAM, and the second half of the burst access is handled by the DRAM, thereby realizing a high-speed, large-capacity memory module for first access.
Another object of the present invention is to realize a memory module with a small data holding current. For this purpose, the data holding current can be reduced by extending the refresh interval executed inside the module, particularly at low temperatures.
FIG. 16 shows CHIP4 (SRAM + CTL_LOGIC). CHIP4 (SRAM + CTL_LOGIC) is composed of an SRAM and a control circuit (CTL_LOGIC), and the integrated SRAM is a synchronous SRAM that has been generally used. The control circuit (CTL_LOGIC) is a part other than the SRAM of CHIP1, and is shown as an area surrounded by a broken line in FIG. The The operation of each circuit block will be described below.
The access controller (A_CONT) converts an address input from the outside according to a value set in a built-in register (REG), and selects a memory to be accessed. When the SRAM is selected, an address (S-ADD) and a command signal (S- / CS, S- / WE, S- / OE) are sent to the SRAM, and access to the SRAM is started. When a DRAM is selected, DRAM addresses (D1-A0 to D1-A11, D2-A0 to D2-A11) are generated and command signals (D1-CKE, D2-CKE, D1- / CS). D2- / CS, D1- / RAS, D2- / RAS, D1- / CAS, D2- / CAS, D1- / WE, D2- / WE, D1-DQMU / DQML, D2-DQMU / DQML) and DRAM The access is started.
The access controller controls the FIFO, CACHE, and R / W BUFFER to conceal the DRAM refresh from the outside. In addition, the access controller (A_CONT) controls the overall operation of CHIP4 (SRAM + CTL_LOGIC).
The initialization circuit INT initializes the DRAM when power supply to the DRAM is started. The temperature measurement module (TMP) measures the temperature and outputs a signal corresponding to the measured temperature to RC and A_CONT. RC is a refresh counter that generates an address to be refreshed in accordance with the refresh interval of the DRAM. Further, the refresh interval is changed according to the temperature by the output signal of the temperature measurement module (TMP). The command generator (COM_GEN) generates a command necessary for accessing the DRAM.
Next, the operation of this memory module will be described. In order to perform memory access to CHIP4 (SRAM + CTL_LOGIC), a conventional synchronous SRAM interface is used. When an address signal (A0 to A20) and a command signal (S- / WE, S- / CS, S- / OE) are input in synchronization with the clock CLK, access to the memory is started. The value of the address signal (A0 to A20) input from the outside is converted, and the type of memory to be accessed is determined. The conversion pattern is determined by a value set in advance in a register (REG) in A_CONT.
When the SRAM is accessed, the converted address is output to the S-ADD and sent to the SRAM, and command signals (S- / CS, S- / WE, S- / OE) to the SRAM are output. Thus, access to the SRAM is started. Thereafter, so-called synchronous SRAM is accessed.
Similarly, when the DRAM is accessed, the converted address is output to D1-A0 to D1-A11 or D2-A0 to D2-A11. The command signals (D1-CKE, D2-CKE, D1- / CS, D2- / CS, D1- / RAS, D2- / RAS, D1- / CAS, D2- / CAS, DT- / WE, D2- / WE, D1-DQMU / DQML, D2-DQMU / DQML) are also output, and access to the DRAM is started. The two DRAMs have a WORK period in charge of access and a REF. The refresh period is concealed by repeating the period alternately.
First, the case of reading from the DRAM will be described. It is determined from the address and command received by A_CONT that access is to be executed to the DRAM, and COM_GEN is instructed to issue a command to the DRAM. A_CONT converts the received address into a DRAM row address and a column address, and outputs them to the DRAM in the WORK period in charge of access, out of the two DRAMs. The DRAM that has received the command and address outputs data, and the output data is transferred to I / O0 to I / O15 via R / W BUFFER to complete the read access.
Next, a case where data is written to the DRAM will be described. It is determined from the address and command received by A_CONT that access is to be performed to the DRAM, and COM_GEN is instructed to issue a command to the DRAM. Also, A_CONT converts the received address for DRAM and outputs it to the DRAM in the WORK period in charge of access among the two DRAMs. The data to be written is input from I / O0 to I / O15 and once held in the R / W BUFFER, then sent to the DRAM in charge of access for writing. Also, the data to be written and its address are once held in the FIFO, and the other REF. The data is also written to the DRAM during the period after the refresh is completed.
FIG. 17 shows an example of a memory map of this memory module. The difference from the memory map already described in the first embodiment is that two DRAMs (CHIP3 and CHIP4) are mapped to the same address space in the DRAM area and hold the same data. Each DRAM alternately repeats a period in which access is performed (WORK period) and a period in which refresh is preferentially executed (REF. Period). In the example shown here, the DRAM 1 is in the WORK period. Memory access from the outside is executed for the DRAM during the WORK period. Write data is written into the DRAM during the period after the refresh is completed.
FIG. 18 shows the principle of an access control method for concealing the DRAM refresh. The operation of the DRAM according to the present invention can be explained based on the concept that the access to the bank during the REF period is executed with priority.
FIG. 18A schematically shows the priority order of access. In this figure, DRAM 1 is in the WORK period and DRAM 2 is in REF. It is shown that it is during the period. Also, a CACHE that temporarily takes over access, a FIFO that temporarily stores write data, and a refresh request generated from RC are shown.
In the DRAM 1 during the WORK period, only external access (1) is performed. On the other hand, in the DRAM 2 during the REF period, the refresh (2) is first performed with the highest priority. Next, when data is written, data writing (3) held in the FIFO is executed. These operations are executed with the priority determined by the access control circuit (A_CONT).
Assuming that an access with a burst length of 8 times is performed and four of the half of these accesses are performed on the DRAM, 90 ns is required to execute the external access (1), but the refresh (2) is 70 ns. Write-back (3) from the FIFO is executed in 80 ns. This memory module uses this time difference to conceal refresh from the outside.
FIG. 18B shows how the read access is executed. The case where the DRAM 1 is continuously read-accessed during the WORK period is shown. It is assumed that a total of 8 bytes of data with a burst length of 4 is read in one read access. In DRAM 1, only external access (1) is executed in 90 ns, data is read and access is completed. On the other hand, in the DRAM 2, refresh (2) is only executed in 70 ns.
The case where write access is performed is shown in FIG. In one write access, a total of 8 bytes of data with a burst length of 4 are written. The external write access (1) is first executed in the DRAM 1 during the WORK period. At the same time, the write data is once held in the FIFO. In the DRAM 2 during the REF period, the refresh (2) is first performed with the highest priority. Next, data writing (3) held in the FIFO is executed.
Here, the DRAM 1 in the WORK period requires 90 ns for one operation, whereas the DRAM 2 in the REF period completes one refresh operation in 70 ns and the write operation from the FIFO in 80 ns. . Therefore, even if the DRAM 2 performs the refresh operation, the write operation is performed at a speed higher than that of the DRAM 1, so that all data writing in the FIFO can be completed and catch up with the DRAM 1.
FIG. 19 is a flowchart for explaining the overall operation when access to the DRAM occurs. In STEP1, an address is input and the operation starts. In STEP 2, the type of access is determined from the command. Subsequent operations differ depending on the type of access. If the access is read, proceed to STEP3. In STEP 3, data is read from the DRAM during the WORK period, and the operation ends. If the access is a write, go to STEP4. In STEP4, data is written into the DRAM during the WORK period. On the other hand, in STEP 5, the data and address to be written are held in the FIFO. Here, when refreshing is completed in the SDRAM in the REF period, the process proceeds to STEP 6 and the data held in the FIFO is written in the DRAM in the REF period.
FIG. 20 is a flowchart for explaining the operation of the DRAM during the REF period. SETP2 and STEP3 are portions relating to execution of refresh, and STEP4 and STEP5 are portions relating to execution of write-back. In STEP1, the REF period is started, and in next STEP2, it is first determined whether or not there is a refresh request. If there is a refresh request, the process proceeds to STEP 3 where refresh is executed. The number of times of refresh is managed, and refresh of a determined area is performed. When there is no refresh request and when the refresh is completed, the process proceeds to STEP 4 to determine whether there is data stored in the FIFO. If there is data, proceed to STEP 5 and write back to the DRAM. If the writing of the data held in the FIFO is completed in STEP5, or if there is no data in the FIFO in STEP4, the process returns to STEP2.
FIG. 21 shows how two DRAMs are operated in a time-sharing manner in order to conceal the refresh of the DRAM. FIG. 21A shows an example of operation of a DRAM at 75 ° C. or lower, which is a normal operating temperature range. Two DRAMs (DRAM1 and DRAM2) have a WORK period and a REF. The period is repeated alternately. DRAM during the WORK period labeled WORK operates for external access. The first DRAM 1 becomes a WORK period and corresponds to access from the outside. On the other hand, REF. During the period, the DRAM is prioritized for the refresh operation, and when external access is writing, data is written after the refreshing is completed.
The DRAM memory cell normally needs to be refreshed within 64 ms. In the example shown in the figure, the WORK period and the REF. The period is switched, and DRAM1 and DRAM2 are alternately switched to WORK period and REF. The period is repeated four times.
Here, a single REF. The time required for the refresh performed during the period of 8 ms is T1, and the time required for writing back data accumulated in the FIFO as a result of the write access performed during that time is T2. Explain that you can refresh and write back during the period.
Taking a 16 Mbit SDRAM as an example, the memory configuration is 2048 rows × 256 columns × 16 bits × 2 banks, and refreshing may be performed 4096 times (for 2048 rows × 2 banks) in 64 ms. In the example of FIG. 21A, REF. Since there are four periods, one REF. It is sufficient to perform 1024 refreshes, which is a quarter of the period (8 ms). Since the time required for one refresh is 70 ns, T1 = 70 ns × 1024 times = 72 us.
On the other hand, when the maximum value of the write access performed from the outside during 8 ms is obtained, it is assumed that every access is 4 consecutive burst writes, and it is 88889 times (8 ms / 90 ns). This is referred to as REF. The time T2 required for writing back to the DRAM during the period is 7.111 ms (80 ns × 88889 times). Therefore, T1 + T2 = 7.183 ms <8 ms, and REF. It can be seen that refresh and write back can be performed sufficiently during the period.
The refresh can also be executed simultaneously in a plurality of banks in the DRAM during the REF period. In this case, since the number of refreshes executed in the T1 period can be reduced, the T1 period can be shortened. If the T1 period is shortened, the storage capacity of the FIFO can be reduced, and a high-speed memory can be realized by shortening the interval accessed from the outside.
FIG. 21B shows the case where the refresh interval of the DRAM is changed. In general, the refresh characteristics of DRAM deteriorate at high temperatures. Therefore, for example, when the refresh interval is shortened at a high temperature of 75 ° C. or higher, data can be retained, and operation can be performed in a wider temperature range. In this example, the refresh interval is shortened to 48 ms at a high temperature. T1 does not change, but T2 is 5.33 ms, the remaining time Δ is 0.6 ms, and REF. You can refresh and write back during the period.
On the other hand, at low temperatures, the refresh interval can be shortened to reduce the data retention current. In the illustrated example, the refresh interval is doubled to 128 ns at low temperatures. In this case, the REF period is 16 ms. Although T1 is not changed, T2 is 14.22 ms and the remaining time Δ is 1.71 ms. Even if refresh is performed in the T1 period, all data can be written back in the T2 period.
In the present embodiment, the operation unit of the DRAM related to refresh concealment has been described for each chip. However, for example, a bank may be used as the operation unit according to the performance of the memory module and the configuration of the memory chip. Further, the refresh interval of 64 ms is divided into eight periods to be a WORK period and a REF period. However, if further divided, the storage capacity of the FIFO for holding data and addresses can be reduced. On the other hand, if the number of divisions is large, the number of switching between the WORK period and the REF period can be reduced, so that the control circuit accompanying the switching can be simplified.
FIG. 22 is a diagram for explaining the function of CACHE. In FIG. 22A, the WORK period and REF. Shown is the case where write access is made from outside just before the period changes. Here, the external access A (EXT_ACC_A) is performed just before the end of the WORK period of the DRAM 1. In such a case, the WORK period of the DRAM 1 is extended by dT until the end of the write access. On the other hand, the DRAM 2 enters the WORK period as scheduled, and waits for the end of the write access without writing the write data. Data that has not been written to the DRAM 2 is temporarily held in the CACHE. When an access to the same address held in CACHE occurs during the WORK period, read / write is performed on CACHE instead of DRAM 2. If the access is write, REF. Writing to the DRAM 1 during the period is performed via the FIFO as usual. The data held in CACHE is the next REF. Written back to the period. When this write back is completed, the contents of CACHE are cleared.
If the access is a read, the WORK period of the DRAM 1 is only extended by dT until the end of the access.
FIG. 22 (B) shows that one access is a WORK period and REF. The case where it was performed longer than the period, or the case where it could not be covered in the extended period dT was shown. The external access B (EXT_ACC_B) in which the DRAM 1 is started during the WORK period exceeds the extension time dT and continues to the next REF. Access continues during the period. In this case, the access is handed over to CACHE, and the DRAM 1 REF. Enter the period. The DRAM 2 enters a WORK period as scheduled and enters a standby state. In the case of read access, data is transferred from DRAM 1 to CACHE. In the case of write access, when the continued access is completed, the data written in CACHE is written back to DRAM1 and DRAM2. In the write back, each DRAM is REF. When the period starts. When both writebacks are completed, the contents of CACHE are cleared. Thus, using CACHE, the WORK period and REF. Access over a period of time or access over one or more WORK periods can be handled.
The timing waveform of this memory module will be described. The case where the read access is continued, the case where the write read is continued, and the case where the burst start address is in the DRAM area are those shown in FIGS. 4, 6 and 7 already described in the first embodiment. Are the same.
FIG. 23 shows a timing waveform when the writing is continued. The difference from FIG. 5, which is the waveform at the time of continuous writing shown in the first embodiment, is that access to address A1 is started one cycle after the access to address A0 is completed. This insertion of one cycle gives a margin to the operation of the DRAM. It is possible to refresh and write back the DRAM during the period.
FIG. 24 shows an example of mounting the memory module in this embodiment. FIG. 24A is a top view and FIG. 24B is a cross-sectional view. In this example, the memory module is composed of CHIP2, CHIP3, CHIP4, PCB, PATH1, PATH2, BONDING PAD, SOLDER BALL, and COVER. CHIP2 and CHIP3 arranged on the upper surface of the PCB substrate are connected to the PCB substrate by PATH2 via BONDING PAD. Further, the CHIP 4 arranged on the upper surface of the PCB substrate is connected to the PCB substrate by PATH1 and PATH2 through the BONDING PAD. A SOLDER BALL is formed on the lower surface of the PCB substrate, and is connected to a wiring substrate of a device using the memory module. A cover (COVER) made of a resin mold is formed on the upper surface of the memory module to ensure the mechanical strength of the memory module. When a metal cover (COVER) is used, a shielding effect against electromagnetic noise can be obtained. According to this mounting example, it is possible to reduce the wiring length between chips and to configure a memory module with a small wiring load capacity. In addition, since the mounting area is reduced, it is possible to reduce the size and weight of the device using the memory module.
FIG. 25 shows a modified example of the memory module described with reference to FIG. FIG. 25A is a top view and FIG. 25B is a cross-sectional view. 24 differs from the implementation example shown in FIG. 24 in the connection method between CHIP4, CHIP2, and CHIP3. In this example, CHIP4, CHIP2, CHIP3, and PATH5 are used for connection wiring. In addition to simplifying the wiring process, PATH5 that directly connects chips can reduce the load capacity due to wiring. Further, since the number of BONDING PADs arranged on the PCB substrate can be reduced, a memory module can be realized with a smaller area. The rest is the same as the mounting example shown in FIG.
FIG. 26 shows a modified example of the memory module described in FIG. 26A is a top view and FIG. 26B is a cross-sectional view. The arrangement and connection method of CHIP2 and CHIP3 are different from the implementation example shown in FIG. In this example, CHIP2 and CHIP3 arranged on the upper surface of the PCB substrate are connected face-down to the PCB substrate. SOLDER BUMP is used for arrangement and wiring. By using SOLDER BUMP, the wiring process can be simplified and the load capacity due to the wiring can be reduced. Further, since the number of BONDING PADs arranged on the PCB substrate can be reduced, a memory module can be realized with a smaller area. The rest is the same as the mounting example shown in FIG.
FIG. 27 shows a modified example of the memory module described with reference to FIG. FIG. 27A is a top view and FIG. 27B is a cross-sectional view. The CHIP4 arrangement and connection method are different from the implementation example shown in FIG. In this example, the CHIP 4 disposed on the upper surface of the PCB substrate is connected face-down to the PCB substrate. SOLDER BUMP is used for arrangement and wiring. By using SOLDER BUMP, the wiring process can be simplified and the load capacity due to the wiring can be reduced. Further, since the number of BONDING PADs arranged on the PCB substrate can be reduced, a memory module can be realized with a smaller area. The rest is the same as the mounting example shown in FIG.
FIG. 28 shows another example of mounting the memory module in the present embodiment. FIG. 28A is a top view and FIG. 28B is a cross-sectional view. In this example, this memory module is composed of CHIP2, CHIP3, CHIP4, PCB, PATH6, PATH7, BONDING PAD, SOLDER BALL, and COVER. CHIP2 and CHIP3 arranged on the upper surface of the PCB substrate are directly connected to CHIP4 by PATH6 through BONDING PAD. In addition, CHIP4 is arranged on the upper surface of CHIP2 and CHIP3, and CHIP4 is connected to the PCB substrate by PATH6 via BONDING PAD. A SOLDER BALL is formed on the lower surface of the PCB substrate, and is connected to a wiring substrate of a device using the memory module. A cover (COVER) made of a resin mold is formed on the upper surface of the memory module to ensure the mechanical strength of the memory module. When a metal cover (COVER) is used, a shielding effect against electromagnetic noise can be obtained. According to this mounting example, it is possible to reduce the wiring length between chips and to configure a memory module with a small wiring load capacity. In addition, since the mounting area is reduced by stacking chips, it is possible to reduce the size and weight of a device using the memory module.
FIG. 29 shows a modified example of the memory module described with reference to FIG. FIG. 29A is a top view and FIG. 29B is a cross-sectional view. 28, the placement positions of CHIP2, CHIP3, and CHIP4 are interchanged. If the area of CHIP4 is larger than that of CHIP2 and CHIP3, this example can be implemented more easily. CHIP2, CHIP3, and CHIP4 are directly connected by PATH8, and CHIP4 is connected to the PCB board by PATH9. The rest is the same as the mounting example shown in FIG.
As an embodiment of the above memory module, a so-called BGA type package has been taken as an example, but each chip is soldered onto a glass epoxy wiring board like a DIMM (Dual In Line Memory Module) used in a DRAM memory module. It is also possible to use the form of mounting. In this case, the shape is a standard size, but the advantage is that it can be created at a relatively low cost because it uses normal mounting technology.
According to the embodiment described above, the following effects can be expected in addition to the points already described in the first embodiment. That is, in the memory module according to the present invention, the DRAM refresh can be concealed from the outside of the memory module by adjusting the timing of performing the data retention and refreshing in the DRAM, thereby ensuring complete compatibility with the SRAM. I can do it.
As a result, it is possible to use a low-cost and high-speed large-capacity memory module without any change to a system in which an SRAM is conventionally used.
As described above, the main effects obtained by the embodiments of the present invention are as follows. First, by using a combination of a high-speed memory and a large-capacity memory, a high-capacity memory with high burst access speed is realized. Secondly, by controlling access to the DRAM by the controller, a large-capacity memory that does not need to be refreshed from the outside is realized. Thirdly, a memory module with a small mounting area can be provided by mounting a plurality of semiconductor chips on one sealing body.
Industrial applicability
The present invention is suitable for use in a composite memory semiconductor device including SRAM and DRAM used in information equipment (such as a mobile phone).
[Brief description of the drawings]
FIG. 1 is a configuration diagram of a memory module to which the present invention is applied.
FIG. 2 is a block diagram illustrating an example of the CHIP 2 in FIG.
FIG. 3 is an explanatory diagram showing an example of an address map of a memory module to which the present invention is applied.
FIG. 4 is an explanatory diagram showing an example of operation waveforms of the memory module to which the present invention is applied.
FIG. 5 is an explanatory diagram showing an example of operation waveforms of the memory module to which the present invention is applied.
FIG. 6 is an explanatory diagram showing an example of operation waveforms of the memory module to which the present invention is applied.
FIG. 7 is an explanatory diagram showing an example of operation waveforms of the memory module to which the present invention is applied.
FIG. 8 is a block diagram illustrating a configuration example of the SRAM.
FIG. 9 is a block diagram showing a configuration example of the DRAM.
FIG. 10 is an example of a mounting form of the memory module according to the present invention.
FIG. 11 is an example of a mounting form of the memory module according to the present invention.
FIG. 12 is an example of a mounting form of the memory module according to the present invention.
FIG. 13 is an example of a mounting form of the memory module according to the present invention.
FIG. 14 is an example of a mounting form of the memory module according to the present invention.
FIG. 15 is a configuration diagram of a memory module to which the present invention is applied.
FIG. 16 is a block diagram showing a configuration example of CHIP4 in FIG.
FIG. 17 is an explanatory diagram showing an example of an address map of a memory module to which the present invention is applied.
FIG. 18 is an explanatory diagram for explaining a state in which both access to the DRAM and refresh are performed at the same time.
FIG. 19 is a flowchart showing the flow of processing when accessing the DRAM.
FIG. 20 is a flowchart showing an operation flow in the DRAM during the REF period.
FIG. 21 is an explanatory diagram showing an example of a DRAM refresh method.
FIG. 22 shows the WORK period, REF. It is explanatory drawing which shows the method of taking over access at the time of a period switch.
FIG. 23 is an explanatory diagram showing an example of operation waveforms of the memory module to which the present invention is applied.
FIG. 24 is an example of a mounting form of the memory module according to the present invention.
FIG. 25 is an example of a mounting form of the memory module according to the present invention.
FIG. 26 is an example of a mounting form of the memory module according to the present invention.
FIG. 27 is an example of a mounting form of a memory module according to the present invention.
FIG. 28 is an example of a mounting form of the memory module according to the present invention.
FIG. 29 shows an example of a mounting form of the memory module according to the present invention.

Claims (18)

A plurality of first terminals for receiving external access signals;
A second terminal for data input and output;
A first chip including a first memory including a plurality of first memory cells each having a first capacitor and a first MISFET; and a plurality of first nodes for receiving a first access signal to the first memory;
A second memory including a plurality of second memory cells each having two cross-coupled inverters; a plurality of second nodes for receiving a second access signal for the second memory; and the plurality of first nodes A plurality of third nodes coupled to the first chip for supplying the first access signal to the first chip; and the first and second access signals coupled to the second and third nodes and receiving the external access signal A second chip including an access controller forming
When the access controller receives the external access signal to read N bits of continuous data via the plurality of first terminals, the access controller reads the first half of the N bits from the second memory. The second access signal is supplied to the second memory, the first access signal for reading the second N2 bits of the N bits from the first memory is supplied to the first memory, and the N1 bits And a semiconductor device for outputting read data from the second terminal successively in the order of the N2 bits. 2. The semiconductor device according to claim 1, wherein the external access signal has a synchronous SRAM interface to which a command and an address are supplied in synchronization with a clock. 2. The semiconductor device according to claim 1, wherein the first chip is a synchronous DRAM and the second memory is an SRAM. In claim 1,
The semiconductor device further includes a sealing body in which the first and second chips are included,
The plurality of first terminals and the second terminals are semiconductor devices that serve as electrodes for electrical connection to the outside of the sealing body. In Claim 2, the said sealing body contains a board | substrate,
The first and second chips are mounted on the first main surface;
The first main surface of the substrate is covered with a sealing material;
The plurality of first terminals and the second terminals are semiconductor devices formed on a second main surface provided on a side of the substrate facing the first main surface. 5. The semiconductor device according to claim 4, wherein the first and second chips are sealed with resin. A plurality of first terminals for receiving external access signals;
A second terminal for data input and output;
A first chip including a first memory including a plurality of first memory cells having a first read time; and a plurality of first nodes for receiving a first access signal for the first memory;
A second chip including a second memory including a plurality of second memory cells having the first read time; and a plurality of second nodes for receiving a second access signal for the second memory;
A third memory including a plurality of third memory cells having a second read time shorter than the first read time; a plurality of third nodes receiving a third access signal to the third memory; and A plurality of fourth nodes coupled to one node for supplying the first access signal to the first chip; and a plurality of fourth nodes coupled to the plurality of second nodes for supplying the second access signal to the second chip. And a second chip including an access controller coupled to the third to fifth nodes and receiving the external access signal to form the first to third access signals,
When the access controller receives the external access signal to read N bits of continuous data via the plurality of first terminals, the access controller reads the first half of the N bits from the third memory. For supplying the third access signal to the third memory and reading the second N2 bits of the N bits from either the first or second memory. A semiconductor device that outputs to one of the first and second memories and outputs read data from the second terminal in the order of the N1 bit and the N2 bit. 8. The access controller according to claim 7, wherein the access controller outputs the first access signal so as to access the first memory when receiving the external access signal in the first period, and the second period. A semiconductor device that outputs the second access signal so as to access the second memory when receiving the external memory access signal. In claim 8,
In the first period, the access controller can output a read or write command signal for the first memory as the first access signal in response to the external access signal, and can refresh the second memory. A refresh command signal for performing the operation can be output as the second access signal,
In the second period, the access controller can output a read or write command signal for the second memory as the second access signal in response to the external access signal, and can refresh the first memory. A semiconductor device capable of outputting a refresh command signal for performing the first access signal as the first access signal. 8. The semiconductor device according to claim 7, wherein the first memory and the second memory have a period in which the same information is stored redundantly. 8. The semiconductor device according to claim 7, wherein the semiconductor device has a read / write allowable period for the first memory, a first period that is a refresh period for the second memory, and a refresh period for the first memory. A semiconductor device that alternately repeats the second period, which is a read / write allowable period for the second memory. 8. The semiconductor device according to claim 7, wherein each of the first and second chips is a DRAM memory chip, and the external access signal is a synchronous SRAM interface to which a command and an address are supplied in synchronization with a clock. apparatus. In claim 7,
The semiconductor device further includes a sealing body in which the first, second, and third chips are included,
The plurality of first terminals and the second terminals are semiconductor devices that serve as electrodes for electrical connection to the outside of the sealing body. In Claim 13, the said sealing body contains a board | substrate,
The first, second, and third chips are mounted on the first main surface;
The first main surface of the substrate is covered with a sealing material;
The first terminal and the second terminal are semiconductor devices formed on a second main surface provided on a side of the substrate facing the first main surface. A first DRAM chip;
A second DRAM chip;
An SRAM memory array; a plurality of first nodes for supplying a first access signal to the first DRAM chip; a plurality of second nodes for supplying a second access signal to the second DRAM chip; and a third access signal to the SRAM memory array. A chip including a plurality of third nodes for supplying an external access signal and an access controller having a plurality of fourth nodes for receiving external access signals;
When the access controller receives an external access signal instructing access to N bits of continuous data, the third access signal for accessing the first half of the N bits to the SRAM array Is supplied to the SRAM array, and the second or second DRAM chip is used for accessing the N2 bit in the latter half of the N bits to either the first or second DRAM chip. A memory module that outputs to one side of the chip and allows continuous access in the order of the N1 bit and the N2 bit. 16. The memory module according to claim 15, wherein the memory module includes a plurality of first electrodes to which a signal for controlling access to the first and second DRAM chips and the SRAM memory array is supplied as a control signal to the access controller. And a plurality of second electrodes for inputting / outputting data to / from the first and second DRAM chips and the SRAM memory array. 16. The access to the first DRAM chip and the second DRAM chip from the outside of the memory module is performed by an SRAM interface, and the access to the first and second DRAM chips is performed from the outside of the memory module. A memory module that does not have a busy period caused by refresh. 16. The memory module according to claim 15, wherein the first memory and the second memory have overlapping address spaces and have a period in which the same information is stored redundantly.

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