JPWO2002045139A1 - Semiconductor integrated circuit device identification method, semiconductor integrated circuit device manufacturing method, semiconductor integrated circuit device, and semiconductor chip - Google Patents

Abstract

A plurality of identification elements having the same form are formed in the course of the manufacturing process of the semiconductor integrated circuit device. Used as identification information for

Description

構成図が示されている。この実施例では、本体ＬＳＩをＤＲＡＭとＳＲＡＭが混載された大規模システムＬＳＩとし、プログラム専用チップはレーザ切断メタルフューズの使用を前提としている。以下、図３６図を用いて製造工程の流れを説明する。
▲１▼　本体ＬＳＩをプローブ試験テスタにより試験する。ＤＲＡＭやＳＲＡＭの不良メモリセル救済情報、内部電源回路トリミング設定値、ディレイ回路設定値などと一緒に、ＬＳＩ内の識別番号をホストコンピュータに転送する。ホストコンピュータは、送られた情報やその他の製造管理情報などと連結しデータベースに格納する。
▲２▼　本体ＬＳＩウエハをダイシングする。
▲３▼　本体ＬＳＩのみ、マルチチップモジュール基板に仮実装する。本図では、本体ＬＳＩは１つであるが複数であることもある。
▲４▼　選別試験テスタにより本体ＬＳＩから識別番号を読み出し、ホストコンピュータに送る。ホストコンピュータは、識別番号から本体ＬＳＩを認識し、個々の本体ＬＳＩに必要な情報をテスタに返す。必要な情報とは、上記の不良メモリセル救済情報や、本体ＬＳ１識別情報などホストコンピュータによりデータベースで管理されていたものである。これを本体ＬＳＩレジスタ情報と呼ぶ。選別試験テスタは、本体ＬＳＩレジスタ情報を、例えば不良メモリセル救済情報であれば、本体ＬＳＩ内の救済回路の救済アドレスレジスタに格納し、内部電源回路設トリミング定値であれば内部回路内のトリミング値設定レジスタに格納する。
選別試験テスタは、本体ＬＳＩレジスタ情報設定後、プローブ試験ではできないような高速動作試験などを行う。さらにここで新たに不良になったものについては、その不良情報をホストコンピュータに転送する。ホストコンピュータは、送られた不良情報とで採取した情報を合わせ再救済や調整が可能であるか解析し、再びデータベースに格納する。
▲５▼　プログラム専用チップに、本体ＬＳＩに必要なレジスタ情報をプログラムする。さらに必要であれば、製造管理情報や、顧客情報、暗号、機能情報などのプログラムを行う。プログラム専用チップは、１チップに複数の本体ＬＳＩの情報を格納できる。例えば、１００個の本体ＬＳＩ分の容量があるとすると、レーザ切断装置は、ホストコンピュータから１００個の本体ＬＳＩ分の識別番号とレジスタ情報を受け取り、受け取った情報をもとに、１００個のプログラム専用チップに全て同じ１００本体ＬＳＩ分のレジスタ情報をプログラムする。
ここで、プログラム専用チップのフューズ切断時間を見積もってみる。例えば、１個の本体ＬＳＩ当たりのプログラムビット数が１０００ビット、１個のプログラム専用チップに１００本体ＬＳ１分格納（登録）できるとすると、１つのプログラム専用チップは１０万本（１０００×１００）のヒューズを搭載する。最新のレーザ切断装置の能力は、毎秒５０００パルス以上であるので、約２０秒で１０万本すなわち１個のプログラム専用チップの切断が可能である。１００チップでは、２０００秒（３３分）である。また、プログラム専用チップの面積は、１つのフューズの大きさを１５平方マイクロンとすると、フューズ部だけで１．５平方ミリメートル、周辺回路やパッドを含めると約３平方ミリメートルである。
▲６▼　レーザ切断不良チップを除去するため、プローブ検査を行う。なお本工程の前に、チップを保護する保護膜を付ける工程を付加することもある。検査データパターンは、ホストコンピュータから受け取る。ここで、レーザ切断不良チップが発生することもあるので、前記工程▲５▼でプログラムされるチップ数は、１００個よりも多めとする。この数は歩留の実績によって調整する。ここで、プログラム専用チップが本体ＬＳＩより少なく不足した場合、余つた本体ＬＳＩは回収され別のグループに混成される。逆に、プログラム専用チップが余つた場合は廃棄する。いずれにしても損害になるが、貴重な本体ＬＳＩを廃棄するよりは経済的である。
▲７▼　プログラム専用チップをダイシングする。ダイシングされたチップは、工程▲６▼において同一のプログラムがされた１００個と余裕分がピックアップされ、本体ＬＳＩに対応するグループ（ロット）にまとめられる。
▲８▼　プログラム専用チップをマルチチップモジュールパッケージに実装する。この時、前記工程▲４▼と▲６▼で対応付けられたグループが組み合わされなければならない。しかし、個々の本体ＬＳＩとプログラム専用チップを一対一で対応させる必要がないので、従来の組立工程と比べ大幅な工程の変更は必要ない。なお、本実施例では、本組立工程では後の分離

しもこの方法に限定するものではない。
▲９▼　完成したマルチチップモジュールが最終選別試験される。プログラム専用チツプには、上記実施例では、１００チップ分の救済情報が収められて（登録されて）いる。ボード上の本体ＬＳＩが立ち上がる際、本体ＬＳＩとプログラム専用チップの間でデータ交換が行われる。具体的には、本体ＬＳＩから識別番号がプログラム専用チップに送られ、プログラム専用チップは、送られた識別番号と登録された識別番号を比較し、モジュールに実装された本体ＬＳＩを認識し、救済情報など必要なレジスタ情報を本体ＬＳＩに送る。本体ＬＳＩは、送られたレジスタ情報をもとに内部の初期設定を行う。その後、最終試験が行われる。含格したものは、次の封止工程に送られ、不合格のものは、分離工程に送られると同時に、不良情報がホストコンピュータに送られ、再生可能であるか解析される。

る。

れる。

ＳＩから識別番号が読み出され、それに対応する過去のプロープ試験情報、選別試験情報、最終選別試験情報などがホストコンピュータから取り出される。また図示してしないが、この新たな再生可能品について、非再生品と同様にプログラム専用チップが作成され同様の工程を進行する。プログラム専用チップとして、電気的にプログラム可能な素子によるものに置き換えることもできる。この場合、工程数が削減できる。
第３７図には、本願に係る識別番号発生回路を搭載した半導体集積回路装置を回路実装ボードに組み立てる場合の一実施例の製造工程▲１▼ない

▲１▼本体ＬＳＩをプローブ試験テスタにより試験する。ＤＲＡＭやＳＲＡＭの不良メモリセル救済情報、内部電源回路トリミング設定値、ディレイ回路設定値などと一緒に、ＬＳＩ内の識別番号をホストコンピュータに転送する。ホストコンピュータは、送られた情報やその他の製造管理情報などを連携しデータベースに格納する。
▲２▼　本体ＬＳＩウエハをダイシングする。
▲３▼　本体ＬＳＩをパッケージに組み立てる。
▲４▼　第３６図の工程▲４▼と同じ。
▲５▼　第３６図の工程▲５▼と同じ。
▲６▼　プログラム専用チップをダイシングする。ダイシングされたチップは、第３６図の実施例と同様に、本体ＬＳＩに対応するグループ（ロット）にまとめられる。
▲７▼　第３６図の工程▲７▼と同じ。
▲８▼　本体ＬＳＩとプログラム専用チップを回路実装ボードに実装する。この時、前記工程▲４▼と▲６▼とで対応付けられたグループが組み合わされなければならない。しかし、個々の本体ＬＳＩとプログラム専用チップを一対一で対応させる必要がないので、従来の組立工程と比べ大幅な工程の変更は必要ない。
▲９▼　完成したボードが実装試験される。ボード上の本体ＬＳＩが立ち上がる際、本体ＬＳＩとプログラム専用チップの間でデータ交換が行われる。本体ＬＳＩまたはプログラム専用チップおよびボード実装にともなう不具合が確認されたものは、分離工程に送られると同時に、不良情報がホストコンピュータに送られ、再生可能であるか解析される。

れる。

る。今回のレジスタ情報は、前回のレジスタ情報に実装試験結果が加えられたものである。

たプログラム専用チップとともに１つの実装ボードに実装され、以降同様の工程を進行する。

なお、ここに示した実施例は、一実施例にすぎず、適用される製品や既存の生産ラインの形態により変化する。
第３８図には、本願に係る識別番号発生回路を搭載した半導体集積回

▲１▼本体ＬＳＩをプローブ試験テスタにより試験する。ＤＲＡＭやＳＲＡＭの不良メモリセル救済情報、内部電源回路トリミング設定値、ディレイ回路設定値などと一緒に、ＬＳＩ内の識別番号をホストコンピュータに転送する。ホストコンピュータは、送られた情報やその他の製造管理情報などを連携しデータベースに格納する。
▲２▼　本体ＬＳＩウエハをダイシングし、救済可能チップを選別する。
▲３▼　本体ＬＳＩをベビーボードに仮組み立てする。
▲４▼　組み立て不良などをチェック後に、エージングを行う。このとき、ベビーボード上のチップからは識別番号を読み出し、ホストコンピュータからは個々のチップに対応した救済データを取り出、ベビーボード上のチップに格納させる。
▲５▼　テスタによる選別を行う。
▲６▼　ベビーボードから本体ＬＳＩを分離する。
▲７▼　本体ＬＳＩを出荷する。
▲８▼　顧客にて本体ＬＳＩと同時にプログラムデバイスを回路実装ボードに実装する。
▲９▼　本体ＬＳＩから識別番号を取り出す。

上記実装された本体ＬＳＩに対応したデータを受け取り、上記プログラムデバイスに転送されてデータを格納する。通信回線を用いずに例えばＣＤＲＯＭのような電子メディアを使って配布してもよい。

以上の各実施例の半導体集積回路装置の製造方法においては、
（１）　本体ＬＳＩとプログラム専用チップの組み合わせは、プログラム専用チップに登録される本体ＬＳＩ数であるため、一対一の管理が不要となり、生産性が向上するとともに既存の生産設備の変更が少なくて済む。
（２）　プログラム専用チップにレーザ切断フューズが使用できる。メタルフューズの他の電気的プログラミング可能な素子に対しての長所は、標準ＣＭＯＳプロセスに対して変更が小規模、本体ＬＳ１の仕様に合わせた設計変更が容易であり、プロセスの世代に依存しないことなどである。標準プロセスからの変更点は、最終配線層形成とパッシベーション工程である。
（３）　本体ＬＳＩレジスタは、ラッチ回路でよいので面積が小さく、本体ＬＳＩのチップサイズ低減になる。
（４）　本体ＬＳＩにチップ識別番号発生回路を搭載すれば、本体チップにプログラマブル素子プロセスを追加する必要がない。
（５）　プログラム専用チップの置き換え（リペア）ができる。モジュールやポードに実装後に本体ＬＳＩに修正や問題が発生した時、プログラム内容を変更したチップを交換することで対応できる。
（６）　ホストコンピュータを中心とした情報の交換を、ネットワークを利用して実現することで離れた場所の製造工場を使用することができ、経済的な生産活動が可能となる。
第４０図は、ＣＭＯＳインバータの論理しきい値のバラツキを乱数発生器に応用した実施例である。より具体的な実施例として、第３９図のような特定用途向けＬＳＩを用いて説明する。このＬＳＩは、玩具用ロボットの制御のためである。現在、市販されている玩具用ロボットは、特に愛玩用飼育ロボットなどは工場出荷時点では、画一的な性格を持っている。しかし、それを実際の生物や動物に似せるために、例えばオスかメスという性別、気性、運動能力いった先天的あるいは遺伝的な特徴を持たせることで、それを保有する購入者に対し、さらに生き物としての強い感情を抱かさせることができる。
第４０図では、先天的な特徴を、プログラムなしでＬＳＩが製造された時に専用ＬＳＩに持たせるための最も単純な回路である。これは、２進数で４ビットの乱数を出力するもので、各ビットの出力値は個々のＬＳＩごとにランダムに発生する，例えば、Ｄ０はオスかメスを決定する。Ｄ１は気性を、Ｄ２とＤ３は飼い主に対する依存度を４段階で決定する。なお、Ｄ０とＤ１、Ｄ２とＤ３に２種類の回路方式を示しているが、基本的に２つのＣＭＯＳインバータの論理しきい値の違いを取り出すことは変わらない。
このような先天的は個性をロボットに持たせることは、他の方法でも可能ではある。例えば、制御プログラムの中身のパラメータを個々に変更することで可能ではある。しかし、それは製造メーカーによりプログラム、つまり人間によって作られたものであるという感覚が否めない。本実施例で示した方法によると、個々の個性は製造したメーカーにもコントロールできないという、いわば「神の摂理」のようなものが感じられて商品としての価値が高まる。
第４１図は、企業間の電子部品調達市場における不正行為や様々なトラブルを軽減することを目的とした、本願発明に係るチップ識別番号発生回路の利用例の他の構成図が示されている。
工場から出荷される半導体ＬＳＩには、前記のようなチップ識別番号発生回路が組み込まれている。工場すなわちメーカは、出荷品全てのチップ識別番号を採取する。チップ識別番号は、ランダムであるので管理上都合の良いＬＳＩ管理番号と対応させる。さらに各種の管理情報、例えば生産ライン名や製造日などと関連付ける。
第４１図の▲１▼のように顧客Ａに直接納入する場合、製品を梱包したユニット（箱など）番号や顧客番号などの帳票データなどの情報をデータベースの管理情報に追加する。品物を受け取つた顧客Ａは、受け入れ検査時にチップ識別番号を全ＬＳＩまたは抜き取つたＬＳＩから読み出す。次に顧客Ａは、例えばインターネツトなどのネットワークを通じメーカのデータベースにアクセスする。データベースから、入荷したユニツトに含まれるＬＳＩのチップ識別番号を取り出し、入荷したＬＳＩから読み出した識別番号と比較する。識別番号どうしが一致すれば、製品の納入が正しいことが確認できる。この手法は汎用品でも顧客カスタム品でも可能であるが、特にカスタム品の場合有効である。
第４１図において、仲介業者（卸業者）が介入する場合を想定してみる。工場出荷は、上記と同じである。受け取った１次卸業者は、通常梱包を開梱しないが、ユニット番号をメーカのサーバに照会すると同時に、次の納品先情報などを登録する。さらに２次、３次の卸業者も同様にする。最終顧客は、前記▲１▼と同様に入荷したＬＳＩの識別番号をＬＳＩから読み出し、メーカのデータベースに照会する。以上のシステムを構築することで次のような効果が期待できる
（１）納入品の取り違えが防止できる。
（２）仲介業者による中古品の入れ替えなどの不正行為を防止できる。
（３）返品による不良品および中古品の再販を防止できる。
（４）流通ルートの確認ができる。
第４２図には、この発明に係る半導体集積回路装置の他の一実施例の模試的平面図が示されている。同図は、半導体装置の樹脂封止体の上部を除去した状態の模式的平面図であり、ＭＣＰ（Ｍｕｌｔｉ　Ｃｈｉｐ　Ｐａｃｋａｇｅ）型と呼称される半導体装置に適用される。この実施例のＭＣＰ型半導体装置においては、２つの半導体チップを積層して１つのパッケージに組み込んだものである。このうち半導体集積回路装置１０はベースチップとされて第３３図、第３４図等の本体ＬＳＩとされる。そして、その上に搭載された半導体チップ２０が前記プログラム専用チップとされる。この実施例のＱＦＰ型半導体装置３０Ａは、２つの半導体チップ（本体ＬＳＩ１０，フログラム専用チップ）を上下に積層し、この２つの半導体チップを１つの樹脂封止体１７で封止した構成になっている。
本体ＬＳＩ１０及びプログラム専用チップ２０は異なる平面サイズ（外形寸法）で形成され、夫々の平面形状は方形状で形成されている。本実施形態において、本体ＬＳＩ１０の平面形状は例えば４．０５［ｍｍ］×４．１５［ｍｍ］の長方形で形成され、プログラム専用チップ２０の平面形状は例えば１．９９［ｍｍ］×１．２３［ｍｍ］の長方形で形成されている。
本体ＬＳＩ１０及びプログラム専用チップ２０は、例えば、単結晶シリコンからなる半導体基板と、この半導体基板の回路形成面上において絶縁層、配線層の夫々を複数段積み重ねた多層配線層と、この多層配線層を覆うようにして形成された表面保護膜（最終保護膜）とを有する構成となっている。
本体ＬＳＩ１０の互いに対向する回路形成面（一主面）１０Ａ及び裏面（他の主面）のうちの回路形成面１０Ａには、複数のボンディングパッド１１が形成されている。この複数のボンディングパッド１１は、本体ＬＳＩ１０の多層配線層のうちの最上層の配線層に形成されている。最上層の配線層はその上層に形成された表面保護膜で被覆され、この表面保護膜にはボンディングパッド１１の表面を露出するボンディング開口が形成されている。
プログラム専用チップ２０の互いに対向する回路形成面（一主面）２０Ａ及び裏面（他の主面）のうちの回路形成面２０Ａには、複数のボンディングパッド２１が形成されている。この複数のボンディングパッド２１は、プログラム専用チップ２０の多層配線層のうちの最上層の配線層に形成されている。最上層の配線層はその上層に形成された表面保護膜で被覆され、この表面保護膜にはボンディングパッド２１の表面を露出するボンディング開口が形成されている。
本体ＬＳＩ１０のボンディングパッド１１及びプログラム専用チップ２０のボンディングパッド２１の平面形状は、例えば６５［μｍ］×６５［μｍ］の正方形で形成されている。
本体ＬＳＩ１０の複数のボンディングパッド１１は、本体ＬＳＩ１０の４つの辺（互いに対向する２つの長辺（１０Ａ１，１０Ａ２）及び互いに対向する２つの短辺（１０Ａ３，１０Ａ４））に沿って配列されている。プログラム専用チップ２０の複数のボンディングパッド２１は、ＥＥＰＲＯＭ用チップ２０の４つの辺（互いに対向する２つの短辺（２０Ａ１，２０Ａ２）及び互いに対向する２つの長辺（２０Ａ３，２０Ａ４））に沿って配列されている。
プログラム専用チップ２０は、プログラム専用チップ２０の他の主面である裏面が本体ＬＳＩ１０の回路形成面１０Ａと向かい合う状態で本体ＬＳＩ１０の回路形成面１０Ａ上に配置され、接着層１５を介在して本体ＬＳＩ１０の回路形成面１０Ａに接着固定されている。本実施形態において、接着層１５としては例えばポリイミド系の接着用樹脂フィルムを用いている。
本体ＬＳＩ１０は、その裏面がダイパッドと向かい合う状態で、接着層を介在してダイパッドに接着固定されている。ダイパッドには４本の吊りリード６が一体化され、これらのダイパッド５及び４本の吊りリード６で支持体が構成されている。
樹脂封止体１７の平面形状は方形状で形成されている。本実施形態において、樹脂封止体１７の平面形状は例えば１０［ｍｍ］×１０［ｍｍ］の正方形で形成されている。樹脂封止体１７は、低応力化を図る目的として、例えばフェノール硬化剤、シリコーンゴム及びフィラー等が添加されたエポキシ系の樹脂で形成されている。この樹脂封止体１７の形成においては、大量生産に好適なトランスファモールド法が用いられている。トランスファモールド法は、ポット、ランナー、流入ゲート及びキャビティ等を備えた成形金型を使用し、ポットからランナー及び流入ゲートを通してキャビティの内部に樹脂を注入して樹脂封止体を形成する方法である。
本体ＬＳＩ１０の周囲には、樹脂封止体１７の各辺に沿って配列された複数のリード２が配置されている。複数のリード２の夫々は、内部リード部（インナーリード）及びこの内部リード部と一体に形成された外部リード部（アウターリード）を有する構成となっている。各リード２の内部リード部は樹脂封止体１７の内部に位置し、外部リード部は樹脂封止体１７の外部に位置する。即ち、複数のリード２は、樹脂封止体１７の内外に亘って延在している。各リード２の外部リード部は、面実装型リード形状の１つである例えばガルウィング型リード形状に折り曲げ成形されている。
この実施例では、本体ＬＳＩ１０には、前記のようにＣＭＯＳインバータ回路の論理しきい値の大小関係で生成される識別番号発生回路を備えている。このようなＣＭＯＳインバータ回路を用いた場合には、本体ＬＳＩに動作電圧を供給し、識別番号発生回路を動作させるような制御信号の入力が必要である。そのために、簡単な構成ではあるが特別な電源供給装置と信号読み出し装置が必要になる。
半導体集積回路装置が流通経路にあるとき、その識別番号を知りたいて時がしばしば生じ、その環境のもとでは動作電圧の供給ができない場合も考えられる。本願の発明思想は、半導体集積回路装置の製造工程の過程で同一の形態からなる複数の識別要素のプロセスバラツキに対応した物理量の大小関係を判定するものである。半導体集積回路装置では、複数のリードを有し、そのリード幅ｄは一律になるようにプレス等により形成される。
しかしながら、複数のリードの幅ｄ１，ｄ２等はプロセスバラツキが生じるものとなる。そこで、複数のリードのリード幅ｄ１、ｄ２等を光学装置で測定し、その大小比較を行うことにより、前記ＣＭＯＳインバータ回路の論理しきい値と同様にプロセスバラツキを利用した識別番号生成に利用するものである。この構成では、測定装置によりリードのリード幅を複数個測定し、その大小関係を判定することで前記同様な半導体集積回路装置に固有の識別番号を判定することができる。
つまり、半導体集積回路装置の出荷前に前記のように１６本のリードを決めておいて、そのリードの幅、あるいはリード間のピッチ等を測定し、その位置情報と大小関係をデータベース化して保持させる。リード幅ピッチを測定する場合、リード２がパッケージ１７から突出する部分で行うことが望ましい。この測定は、光学装置により単時間で行うことができるから出荷時の識別番号の判定にはさほど時間を要しない。
ＣＭＯＳ回路を搭載しない半導体集積回路装置にも利用できるし、ＣＭＯＳ回路の半導体集積回路装置では、前記ＣＭＯＳインバータ回路の電気的な識別番号と組み合わせて使用するものであってもよい。このような２通りの物理量のバラツキを総合的に判断して識別番号の判定をより確実にすることができる。
第４３図には、この発明に係る識別番号発生回路の他の一実施例の基本的回路図が示されている。前記実施例では、第７図に代表される回路により、複数のＣＭＯＳインバータ回路のバラツキの論理しきい値の順番を識別番号とするものであった。これに対して、この実施例では、２つのＣＭＯＳインバータ回路ＩＮＶ１とＩＮＶ２の論理しきい値の比較結果を識別番号の１ビットにするものである。この考えは、前記第４０図の実施例でも利用されている。
この実施例では、２つのＣＭＯＳインバータ回路ＩＮＶ１とＩＮＶ２の論理しきい値の比較は、次のようにして行われる。インバータ回路ＩＮＶ１の入力端子と出力端子との間には、短絡用のＮチャンネル型ＭＯＳＦＥＴＱ２が設けられる。特に制限されないが、このＣＭＯＳインバータ回路ＩＮＶ１の入力端子と電源電圧ＶＤＤとの間には、Ｐチャンネル型ＭＯＳＦＥＴＱ１が設けられる。これらのＭＯＳＦＥＴＱ１とＱ２のゲートには、識別番号回路イネーブル信号ＥＮが供給される。
上記インバータ回路ＩＮＶ１の出力端子は、上記インバータ回路ＩＮＶ２の入力端子に接続される。このインバータ回路ＩＮＶ２の出力信号は、同様なＣＭＯＳインバータ回路ＩＮＶ３ないしＩＮＶ５の縦列回路からなる増幅回路により２値化されて出力端子ＯＵＴから識別番号出力が形成される。
識別番号回路イネーブル信号ＥＮがロウレベルとき、回路は非活性状態であり、ＭＯＳＦＥＴＱ１がオン状態となりＣＭＯＳインバータ回路ＩＮＶ１の入力端子には電源電圧ＶＤＤに対応したハイレベルが供給される。このとき、ＭＯＳＦＥＴＱ２はオフ状態にされ、インバータ回路ＩＮＶ１の出力信号はロウレベルにされ、以下、インバータ回路列ＩＮＶ２〜ＩＮＶ５により、ハイレベル、ロウレベル…のように順次に反転信号が伝達される。
ＣＭＯＳインバータ回路を構成するＭＯＳＦＥＴは、そのゲートバイアス電圧の印加状態によっては、その特性が不所望に変化してしまう可能性を持つ。Ｐチャンネル型ＭＯＳＦＥＴとＮチャンネル型ＭＯＳＦＥＴとでは、第１９図に対する説明で紹介し、また次の第４４図でも説明するようなＮＢＴＩ現象による影響もあり、Ｐチャンネル型ＭＯＳＦＥＴの方が比較的大きな特性変動を生ずる可能性が高い。
第４３図の識別番号回路の非活性状態時オン状態となるプルアップ動作のＭＯＳＦＥＴＱ１は、初段ＣＭＯＳインバータ回路の貫通電流防止の作用と共に、かかる初段ＣＭＯＳインバータ回路におけるＰチャンネル型ＭＯＳＦＥＴのゲート電位をそのソース電位すなわち電源電位レベルの高電位に維持させることによって、かかるＰチャンネル型ＭＯＳＦＥＴの特性変動を充分に抑える作用を持つ。
識別番号回路が活性化されるとき、つまり識別番号を生成するときには、上記信号ＥＮがハイレベルにされる。これにより、ＣＭＯＳインバータ回路ＩＮＶ１は入力と出力とがＭＯＳＦＥＴＱ２により短絡させられて、その論理しきい値電圧に対応した電圧を生成する。ＣＭＯＳインバータ回路ＩＮＶ１の論理しきい値に対応した電圧は、ＣＭＯＳインバータ回路ＩＮＶ２の入力端子に供給される。ＣＭＯＳインバータ回路ＩＮＶ２は、自身の論理しきい値電圧と上記ＣＭＯＳインバータ回路ＩＮＶ１の論理しきい値に対応した電圧とを比較する。
上記インバータ回路ＩＮＶ１の論理しきい値がインバータ回路ＩＮＶ２のそれより低い時、その出力電位は、インバータ回路ＩＮＶ２の論理しきい値電圧より高くなる。つづく、インバータ回路ＩＮＶ３、ＩＮＶ３、ＩＮＶ５によって上記インバータ回路ＩＮＶ２の出力信号は増幅され、ノードＮ５の電位はＶＳＳ近くになる。上記とは逆にインバータ回路ＩＮＶ１の論理しきい値がインバータ回路ＩＮＶ２のそれより高い時、その出力電位は、インバータ回路ＩＮＶ２の論理しきい値電圧より低くなる。つづく、インバータ回路ＩＮＶ３、ＩＮＶ３、ＩＮＶ５によつて上記インバータ回路ＩＮＶ２の出力信号は増幅され、ノードＮ５の電位はＶＤＤ近くになる。
第４４図には、この発明に係る識別番号発生回路の他の一実施例の回路図が示されている。同図においては、動作に特徴があるので、それを説明するために動作状態１と動作状態２に対応した２つの回路が合わせて示されている。
前記第４３図で説明した実施例のように、２つのＣＭＯＳインバータ回路ＩＮＶ１，ＩＮＶ２の論理しきい値差により識別情報を得るものでは、その差が小さい時でも出力信号の再現性を保証することが重要である。特にＰチャンネル型ＭＯＳＦＥＴのしきい値電圧（ＣＭＯＳインバータ回路の論理しきい値ではない）は、近年のデバイスで顕著になつたＮＢＴＩという現象により変動することを考慮することが必要である。つまり、ＮＢＴＩという現象により上記の２つのＣＭＯＳインバータ回路のうち、一方のＣＭＯＳインバータ回路のＰチャンネル型ＭＯＳＦＥＴのしきい値電圧が変動して、かかるＣＭＯＳインバータ回路の論理しきい値も影響を受けて、上記２つのＣＭＯＳインバータ回路の論理しきい値差が逆転したのでは、それより生成される識別情報の信頼性が低下するという問題が生じる。
この実施例では、かかる識別番号の再現性の保証と、経時変化に対する耐性を高めるためにラッチと帰還経路を加えたものである。つまり、前記のような増幅回路を構成するインバータ回路ＩＮＶ５の出力信号は、スイッチＳＷ１を介してラッチ回路を構成する入力側のＣＭＯＳインバータ回路ＩＮＶ６の入力に伝えられる。このインバータ回路ＩＮＶ６の出力信号はインバータ回路ＩＮＶ７の入力に伝えられ、かかるインバータ回路ＩＮＶ７の出力信号がスイッチＳＷ２を通して上記インバータ回路ＩＮＶ６の入力に帰還される。また、上記インバータ回路ＩＮＶ７の出力信号は、スイッチＳＷ３を介して前記インバータ回路ＩＮＶ１の入力に帰還される。
第４４図の動作状態１は、識別情報を生成する動作が示されており、スイッチＳＷ０がオン状態となってＣＭＯＳインバータ回路ＩＶＮ１の入力と出力とを短絡して論理しきい値電圧に対応した電圧を出力ノードＮ１に生成する。前記のように上記ＣＭＯＳインバータ回路ＩＮＶ１の論理しきい値に対応された電圧がＣＭＯＳインバータ回路ＩＮＶ２に入力されることにより、ＣＭＯＳインバータ回路ＩＮＶ２の出力ノードＮ２には、上記論理しきい値電圧の差に対応した電圧が得られ、増幅回路を構成するＣＭＯＳインバータ回路ＩＮＶ３〜ＩＮＶ５により増幅される。
インバータ回路ＩＮＶ１の論理しきい値がインバータ回路ＩＮＶ２のそれより低い時、ノードＮ２の電位は、ＩＮＶ２の論理しきい値電圧より高くなる。つづく、インバータ回路ＩＮＶ３、ＩＮＶ４、ＩＮＶ５によつてＩＮＶ２の電位と論理しきい値の差は増幅され、ノードＮ５の電位はＶＳＳ近くになる。この時、ラッチ回路のスイッチＳＷ１はオン状態に、スイッチＳＷ２はオフ状態となり、上記オン状態のスイッチＳＷ１を介して増幅信号が伝えられて、インバータ回路ＩＮＶ６の入力ノードＮ６、インバータ回路ＩＮＶ６の出力ノードＮ７、インバータ回路ＩＮＶ７の出力ノードＮ８の電位は、それぞれＶＳＳ、ＶＤＤ，ＶＳＳとなる。
第４４図の動作状態２は、フィードバック動作が示されており、ラッチ回路のスイッチＳＷ１はオフ状態に、スイッチＳＷ２はオン状態となり上記状態が保持される。スイッチＳＷ０がオフ状態にスイッチＳＷ３がオン状態となり、ノードＮ８の保持電圧がＣＭＯＳインバータ回路ＩＶＮ１の入力にフィードバックされる。
これにより、インバータ回路ＩＮＶ１のゲート入力は、ノードＮ８すなわちＶＳＳ電位となる。また、ＩＮＶ２のゲート入力は、ＶＤＤとなる。つまり、インバータ回路ＩＮＶ１のＰチャンネル型ＭＯＳＦＥＴのゲート電位はＶＳＳである。これは、当該Ｐチャンネル型ＭＯＳＦＥＴにとって、ＮＢＴＩを加速させる条件であり、この状態を長く保持すると当該ＭＯＳＦＥＴのしきい値（論理しきい値ではない）電圧は徐々に高くなる傾向となる。必ずしも高くなる確証はないが、少なくとも低くなる条件ではない。インバータ回路ＩＮＶ１のＰチャンネル型ＭＯＳＦＥＴのしきい値が高くなるように変動すると、Ｎチャンネル型ＭＯＳＦＥＴとの関係で相対的にインバータ回路ＩＮＶ１の論理しきい値電圧は低くなる。
一方、インバータ回路ＩＮＶ２のＰチャンネル型ＭＯＳＦＥＴにとつてみると、ゲート電位はＶＤＤであり、これはＮＢＴＩの加速が起こりにくい条件であるため、インバータ回路ＩＮＶ２の論理しきい値電圧の変化は比較的小さい。すなわち、動作状態２が継続されことによってインバータ回路ＩＮＶ１の論理しきい値は低く変動し、インバータ回路ＩＮＶ２のそれを維持するため、相対的にもとのしきいい値の差が拡大されることになる。これにより、論理しきい値の差が小さい場合でも、再現性の低い識別ビットの再現性が上がり、経時変化に対し耐性の高い識別番号発生回路が実現できる。
なお、インバータ回路ＩＮＶ１の論理しきい値がインバータ回路ＩＮＶ２のそれより高い時、ノードＮ２の電位は、ＩＮＶ２の論理しきい値電圧より低くなる。したがって、フィードバック動作においては、ノードＮ８は増幅されてＶＤＤ電位となる。また、ＩＮＶ２のゲート入力は、ＶＳＳとなる。つまり、インバータ回路ＩＮＶ２のＰチャンネル型ＭＯＳＦＥＴのゲート電位はＶＳＳである。これは、当該Ｐチャンネル型ＭＯＳＦＥＴにとって、ＮＢＴＩを加速させる条件であり、前記同様にこの状態を長く保持すると当該ＭＯＳＦＥＴのしきい値（論理しきい値ではない）電圧は徐々に高くなる傾向となる。必ずしも高くなる確証はないが、少なくとも低くなる条件ではない。インバータ回路ＩＮＶ２のＰチャンネル型ＭＯＳＦＥＴのしきい値が高くなるように変動すると、Ｎチャンネル型ＭＯＳＦＥＴとの関係で相対的にインバータ回路ＩＮＶ２の論理しきい値電圧は低くなる。
一方、インバータ回路ＩＮＶ１のＰチャンネル型ＭＯＳＦＥＴにとつてみると、ゲート電位はＶＤＤであり、これはＮＢＴＩの加速が起こりにくい条件であるため、インバータ回路ＩＮＶ１の論理しきい値電圧の変化は比較的小さい。すなわち、動作状態２が継続されことによってインバータ回路ＩＮＶ２の論理しきい値は低く変動し、インバータ回路ＩＮＶ１のそれを維持するため、相対的にもとのしきいい値の差が拡大されることになる。これにより、論理しきい値の差が小さい場合でも、再現性の低い識別ビットの再現性が上がり、経時変化に対し耐性の高い識別番号発生回路が実現できる。
第４４図において、動作状態２が誤った状態にされてしまうことを防ぐ上で、半導体集積回路装置の電源投入毎のような起動時には、半導体集積回路装置における電源リセット回路もしくはイニシャライズ回路のような回路によって先ず第１動作状態が開始され、その後第２動作状態に移行される。これによって、インバータ回路ＩＮＶ６、ＩＮＶ７それ自体の電源起動特性にかかわらずに、適切なフィードバック動作が可能となる。
第４５図には、この発明に係る識別番号発生回路の一実施例の具体的回路図が示されている。この実施例では、前記スイッチＳＷ０〜ＳＷ３としてＮチャンネル型ＭＯＳＦＥＴとＰチャンネル型ＭＯＳＦＥＴとが並列接続されてなるＣＭＯＳスイッチが用いられる。また、インバータ回路ＩＮＶ２と増幅回路を構成する各インバータ回路ＩＮＶ３〜ＩＮＶ５の各入力端子には、ＣＭＯＳスイッチと電源電圧ＶＤＤにプルアップするＰチャンネル型ＭＯＳＦＥＴが設けられる。
そして、フィードバック制御信号ＦＢは、ラッチ回路のスイッチＳＷ１〜ＳＷ３の制御の他に、インバータ回路ＩＮＶ１の入力と出力とを短絡させるスイッチＳＷ０をスイッチ制御にも用いられる。つまり、上記フィードバック信号ＦＢの反転信号を形成するインバータ回路ＩＮＶ１０の出力信号は、前記のようなＣＭＯＳスイッチＳＷ１〜ＳＷ３の制御のための他に、ナンドゲート回路Ｇ１の一方の入力に供給される。このナンドゲート回路Ｇ１の他方の入力には、前記信号ＥＮが供給されており、ナンドゲート回路Ｇ１の出力信号と、インバータ回路ＩＮＶ９で形成された反転信号とによってスイッチＳＷ０の制御を行う。
この実施例回路では、かかる識別番号回路が搭載された半導体集積回路装置又は半導体チップに電源電圧が供給された状態で、信号ＥＮがロウレベルなら、Ｐチャンネル型ＭＯＳＦＥＴＱ１１〜Ｑ１５がオン状態となり、各ＣＭＯＳインバータ回路の入力端子に電源電圧ＶＤＤのようなハイレベルを供給する。このとき、信号ＥＮのロウレベルと、インバータ回路ＩＮＶ８による反転信号のハイレベルにより、各ＣＭＯＳインバータ回路ＩＮＶ２ないしＩＮＶ５の入力端子に設けられたスイッチがオフ状態になっており、各インバータ回路間の縦列接続が切断されているので、入力端子の電圧レベルは、上記ＭＯＳＦＥＴＱ１１〜Ｑ１５のオン状態に対応したハイレベルにされる。
このことは、半導体集積回路装置や半導体チップに電源供給が行われた状態で、識別番号を取り出さない状態でのＣＭＯＳインバータ回路を構成するＰチャンネル型ＭＯＳＦＥＴのしきい値電圧（ＣＭＯＳインバータ回路の論理しきい値ではない）がＮＢＴＩという現象により変動することを防止する上で有益である。
上記信号ＥＮをロウレベルからハイレベルに変化させると、インバータ回路ＩＮＶ１〜ＩＮＶ５を縦列形態に接続させるスイッチがオン状態となり、ゲート回路Ｇ１の出力信号がロウレベルとなってスイッチＳＷ０をオン状態にさせる。これにより、ＣＭＯＳインバータ回路ＩＮＶ１の論理しきい値電圧と、インバータ回路ＩＮＶ２の論理しきい値電圧との差電圧を増幅した信号がインバータ回路ＩＮＶ５の出力から得られる。信号ＦＢがロウレベルのとき、スイッチＳＷ０がオン状態となっており、かかるインバータ回路ＩＮＶ５の出力信号がラッチ回路を構成するインバータ回路ＩＮＶ６，ＩＮＶ７に取り込まれる。
上記の状態で信号ＦＢをロウレベルからハイレベルに変化させると、ラッチ回路ではスイッチＳＷ１がオフ状態になり、スイッチＳＷ２とＳＷ３がオン状態となり上記取り込んだ識別情報を保持し、かつそれに対応した信号をスイッチＳＷ３を通してインバータ回路ＩＮＶ１の入力に帰還させて、インバータ回路ＩＮＶ１〜ＩＮＶ５の入力電圧を設定して前記のようにＮＢＴＩを逆に利用した識別番号の保証ないし安定化を図るようにする。このとき、信号ＦＢのハイレベルによりナンドゲート回路Ｇ１の出力信号がハイレベルに戻り、上記インバータ回路ＩＮＶ１の入力と出力とを短絡させていたスイッチＳＷ０をオフ状態にする。
増幅回路を構成するインバータ回路ＩＮＶ４、ＩＮＶ５等は、その入力電圧が論理しきい値電圧との差電圧が大きいので、前記のようにＮＢＴＩの影響を実質的に受けることはないと考えられる。しかしながら、インバータ回路ＩＮＶ２、ＩＮＶ３等と同じ回路構成とすることにより、半導体集基板上に回路を形成する上で同じ回路セルを用いることができるので後述するソフトＩＰ技術を利用する上で有益となる。
第４６図には、この発明に係る識別番号発生回路の更に他の一実施例の具体的回路図が示されている。この実施例は、前記第４４図等に示したような１ビット別識別番号発生回路を拡張したものである。本実施例は、少ない回路素子により８ビットの識別番号を生成する回路に向けられている。
この実施例では、回路図中の全てのＣＭＯＳインバータ回路の定数およびレイアウト形状は同一である。つまり、単位回路（セル）は、ＣＭＯＳインバータ回路と、その入力端子に設けられたＣＭＯＳスイッチと、その入力端子と出力端子とを短絡するＣＭＯＳスイッチとから構成される。上記入力端子に設けられたＣＭＯＳスイッチにより各単位回路が縦列形態に接続される。同図には４個の単位回路が縦列形態に接続される。４つの単位回路のうち初段回路には、上記ＣＭＯＳスイッチを介して電源電圧が供給される。
上記のような縦列回路が２つ並列に設けられ、対応する位置に配置されたＣＭＯＳインバータ回路の２つのＣＭＯＳスイッチには、選択信号Ｘ０及びその反転信号Ｘ０／〜Ｘ３及びその反転信号Ｘ３／が共通に供給される。これにより、上記単位回路は縦列接続されてなる信号伝達方向と、それと直交する方向にマトリックス状態に配置される。
上記２つの縦列回路の終段回路の出力端子には、スイッチが設けられて、いずれかの縦列回路を選択する選択信号Ｙ０，Ｙ０／及びＹ１，Ｙ１／が供給される。そして、前記のような増幅回路を構成するインバータ回路ＩＮＶ４とＩＮＶ５が設けられて出力端子ＯＵＴから識別番誤出力が出力される。上記インバータ回路ＩＮＶ４の入力には、前記のようなＮＢＴＩ対策のために信号ＰＯＮにより制御されてインバータ回路ＩＮＶ４の入力端子に電源電圧を供給するＰチャンネル型ＭＯＳＦＥＴが設けられる。
第４７図には、前記第４６図の実施例回路の動作を説明するためのタイミング図が示されている。
１）パワーオン信号ＰＯＮがロウレベルの時、選択信号は、Ｘ０〜Ｘ３はロウレベル、その反転信号Ｘ０／〜Ｘ３／はハイレベルであり、Ｙ０とＹ１はロウレベルであり、その反転信号Ｙ０／とＹ１／はハイレベルである。ＣＭＯＳインバータの出力はそれぞれ、ＩＮＶ００、２０及びＩＮＶ０１、ＩＮＶ２１とＩＮＶ４がロウレベル、ＩＮＶ１０、ＩＮＶ３０及びＩＮＶ１１、ＩＮＶ３１及びＩＮＶ５がハイレベルである。
２）パワーオン信号ＰＯＮがハイレベルに遷移すると、選択信号Ｘ０はハイレベル、Ｘ０／はロウレベル、Ｙ０はハイレベル、Ｙ０／はロウレベルとなる。インバータ回路ＩＮＶ００とＩＮＶ０１の入力は、電源電圧ＶＤＤから切断され、それぞれの入力と出力が選択信号Ｘ０のハイレベル、Ｘ０／のロウレベルよりオン状態にされるＣＭＯＳスイッチにより短絡され、インバータ回路ＩＮＶ００とＩＮＶ０１の出力電圧は、論理しきい値に対応した電圧となる。
インバータ回路ＩＮＶ００の論理しきい値ＶＬＴ（ＩＮＶ００）とその次段のインバータ回路ＩＮＶ１０の論理しきい値ＶＬＴ（ＩＮＶ１０）の関係が、ＶＬＴ（ＩＮＶ００）＞ＶＬＴ（ＩＮＶ１０）であれば、インバータ回路ＩＮＶ１０の出力電圧は、インバータ回路ＩＮＶ１０の持つ反転増幅作用により、ＶＳＳ電位側すなわちロウレベル側に大きく振幅する。逆に、ＶＬＴ（ＩＮＶ００）＜ＶＬＴ（ＩＮＶ１０）であれば、ＶＤＤ電位側すなわちハイレベル側に大きく振幅する。インバータ回路ＩＮＶ１０、ＩＮＶ１１の出力振幅は、次段のインバータ回路ＩＮＶ２０〜ＩＮＶ３０、ＩＮＶ２１〜ＩＮＶ３１でさらに増幅される。
インバータ回路ＩＮＶ３０の出力は、選択信号Ｙ０，Ｙ０／で選択されたＣＭＯＳスイッチを通り、さらに２段のＣＭＯＳインバータ回路ＩＮＶ４とＩＮＶ５からなる増幅回路を通り、出力端子ＯＵＴに出力される。結局、ＶＬＴ（ＩＮＶ００）＞ＶＬＴ（ＩＮＶ１０）であれば、出力端子ＯＵＴにはロウレベルが出力され、ＶＬＴ（ＩＮＶ００）＜ＶＬＴ（ＩＮＶ１０）であれば、出力端子ＯＵＴにはハイレベルが出力される。
３）次に選択信号が遷移し、Ｘ０がロウレベル（Ｘ０／がハイレベル）に、Ｘ１がハイレベル（Ｘ０／がロウレベル）になる。インバータ回路ＩＮＶ１０とＩＮＶ１１の入力は、Ｘ１のハイレベル（Ｘ０／のロウレベル）により入力端子に設けられたＣＭＯＳスイッチがオフ状態となって前段インバータ回路ＩＮＶ００とＩＮＶ０１の出力から切断され、それぞれの入力と出力がＣＭＯＳスイッチにより短絡され、インバータ回路ＩＮＶ１０とＩＮＶ１１の出力は、論理しきい値となる。インバータ回路ＩＮＶ１０の論理しきい値ＶＬＴ（ＩＮＶ１０）とその次段のインバータ回路ＩＮＶ１１の論理しきい値ＶＬＴ（ＩＮＶ１１）の関係が、ＶＬＴ（ＩＮＶ１０）＞ＶＬＴ（ＩＮＶ２０）であれば、インバータ回路ＩＮＶ２０の出力電圧は、インバータ回路ＩＮＶ２０の持つ反転増幅作用により、ＶＳＳ電位側すなわちロウレベル側に大きく振幅する。逆に、ＶＬＴ（ＩＮＶ１０）＜ＶＬＴ（ＩＮＶ２０）であれば、インバータ回路ＩＮＶ２０の出力電圧は、インバータ回路ＩＮＶ２０の持つ反転増幅作用により、ＶＤＤ電位側すなわちハイレベル側に大きく振幅する。
上記インバータ回路ＩＮＶ２０、ＩＮＶ２１の出力振幅のそれぞれは、次段のインバータ回路ＩＮＶ３０、ＩＮＶ３１でさらに増幅される。上記インバータ回路ＩＮＶ３０の出力は、選択信号Ｙ０、Ｙ０／で選択されたＣＭＯＳスイッチを通り、さらに２段のＣＭＯＳインバータ回路ＩＮＶ４とＩＮＶ５を通り、出力端子ＯＵＴに出力される。
結局、ＶＬＴ（ＩＮＶ１０）＞ＶＬＴ（ＩＮＶ２０）であれば、出力端子ＯＵＴにハイレベルが出力され、ＶＬＴ（ＩＮＶ１０）＜ＶＬＴ（ＩＮＶ２０）であれば、出力端子ＯＵＴにはロウレベルが出力される。ここで、ＣＭＯＳインバータ回路の論理しきい値の前後の大小関係と、出力端子ＯＵＴの値の対応が、上記２）と３）のケースで逆転している。これは上記ＣＭＯＳスイッチにより接続されるインバータ回路の数、つまりは論理しきい値電圧差を増幅するＣＭＯＳインバータ回路の段数が異なることによるものである。
４）次に選択信号が遷移し、Ｘ１がロウレベル（Ｘ１／がハイレベル）、Ｘ２がハイレベル（Ｘ２／がロウレベル）になる。インバータ回路ＩＮＶ２０とＩＮＶ２１の入力は、前記同様にＣＭＯＳスイッチのオフ状態により前段のインバータ回路ＩＮＶ１０とＩＮＶ１１の出力から切断され、それぞれの入力と出力がＣＭＯＳスイッチにより短絡され、インバータ回路ＩＮＶ２０とＩＮＶ２１の出力は、論理しきい値となる。
以降の動作は、上記２）に準ずる。
５）次に選択信号が遷移し、Ｘがロウレベル（Ｘ２／がハイレベル）、Ｘ３がハイレベル（Ｘ３／がロウレベル）になる。インバータ回路ＩＮＶ３０とＩＮＶ３１の入力は、前記同様にＣＭＯＳスイッチがオフ状態となり、前段のインバータ回路ＩＮＶ２０とＩＮＶ２１の出力から切断され、それぞれの入力と出力がＣＭＯＳスイッチにり短絡され、インバータ回路ＩＮＶ３０とＩＮＶ３１の出力は論理しきい値となる。インバータ回路ＩＮＶ３０の論理しきい値ＶＬＴ（ＩＮＶ３０）とその次段のインバータ回路ＩＮＶ４の論理しきい値ＶＬＴ（ＩＮＶ４）の関係が、ＶＬＴ（ＩＮＶ３０）＞ＶＬＴ（ＩＮＶ４）であれば、インバータ回路ＩＮＶ４の出力電圧は、インバータ回路ＩＮＶ５の持つ反転増幅作用により、ＶＳＳ電位側すなわちロウレベル側に大きく振幅する。逆に、ＶＬＴ（ＩＮＶ３０）＜ＶＬＴ（ＩＮＶ４）であれば、ＶＤＤ電位側すなわちハイレベル側に大きく振幅する。
結局、ＶＬＴ（ＩＮＶ３０）＞ＶＬＴ（ＩＮＶ４）であれば、出力端子ＯＵＴにはハイレベル出力され、ＶＬＴ（ＩＮＶ３０）＜ＶＬＴ（ＩＮＶ４）であれば、出力端子ＯＵＴにはロウレベル出力される。
６）次以降の遷移においては、選択信号Ｙ０がロウレベル（Ｙ０／がハイレベル）で、Ｙ１がハイレベル（Ｙ１／がロウレベル）となり、上記２）〜５）に準ずる動作が行われる。これにより、４×２＝８ビットからなる識別番号出力が行われる。
この実施例では、識別番号を生成するインバータ回路と増幅回路を兼ねているいることと、読み出し動作により識別番号がシリアルに出力されるという特徴を持つ。これにより、回路の簡素化が可能となり、１つの端子からシリアルに識別番号を出力させる場合に適している。
第４８図には、前記図４６の実施例に用いられる単位回路の他の一実施例の回路図が示されている。この実施例は、前記のようなＮＢＴＩ対策が行われるいる。つまり、インバータ回路の入力端子には、前記のようなインバータ回路を縦列接続するためのＣＭＯＳスイッチの他、識別番号回路が非活性状態のときに入力端子を前段回路から切り離すためのＣＭＯＳスイッチが追加される。そして、入力端には入力端子に電源電圧を供給するためのＰチャンネル型ＭＯＳＦＥＴが設けられる。
この実施例の単位回路では、パワーオン信号ＰＯＮがロウレベルのとき、つまり電源電圧が供給されて、識別番号発生回路から識別番号を読み出さない時に、かかる信号ＰＯＮをロウレベルとして、各インバータ回路の入力端子を前記のような選択信号Ｘ０，Ｘ０／等とは無関係に前段回路から切り離して、Ｐチャンネル型ＭＯＳＦＥＴにより電源電圧ＶＤＤを供給するものである。
第４９図には、この発明に係る識別番号発生回路の更に他の一実施例の回路図が示されている。この実施例は、前記第４６図に示した単位回路を１列に縦列接続し、バイナリカウンタとデコーダを用いて選択信号を形成するものである。つまり、バイナリカウンタによりカウントアップクロックを計数し、その計数出力を各単位回路に対応して設けられたデコーダに供給し、前記初段回路から順に選択信号Ｘ０（Ｘ０／）ないしＸｎ（Ｘｎ／）を生成する。
第５０図には、この発明に係る識別番号発生回路の更に他の一実施例の回路図が示されている。この実施例は、前記第４６図に示した単位回路を１列に縦列接続し、シフトレジスタを用いて選択信号を形成するものである。つまり、各単位回路に対応してシフトレジスタ（１段分）を設けて前記選択信号を順次にシフトして初段の単位回路から順に前記のような選択動作を行わせるようにするものである。
第４９図及び第５０図のいずれの実施例でも破線で囲んだものを一つの単位回路とすることで、設計や拡張、実装が容易になる。特に第５０図の実施例回路においては、識別番号のビット数を拡張する場合、単位回路の縦列接続線、シフトクロック及びリセットからなる３種類の信号線を連結するだけでよいので、チップ実装に関して自由度が高いため、後述するようなソフトＩＰに好適である。
第５１図には、この発明が適用される半導体集積回路装置又は半導体チップの一実施例の回路レイアウト図が示されている。同図は、一般的なシステムＬＳＩチップを模したものであり、チップ周辺部には、通常Ｉ／Ｏセル（入出力回路）が設けられ、内蔵回路はシステムＬＳＩの機能に応じた回路が複数個設けられる。
第５２図には、上記Ｉ／Ｏセルの標準的な一実施例のブロック図が示されおり、出力バッファ回路、入力バッファ回路及びこれらに対応して設けられるボンディングパッド（ＰＡＤ）から構成される。上記出力バッファ回路と入力バッファ回路は、入出力制御信号により制御されて入力動作又は出力動作が行われる。
第５３図には、この発明に係る半導体集積回路装置又は半導体チップに設けられるＩ／Ｏセルの一実施例の回路レイアウト図が示されている。この実施例では、出力ＭＯＳＦＥＴを駆動するための出力プリバッファ回路が設けられる。前記第５２図の出力バッファ回路は、上記出力プリバッファ回路と出力ＭＯＳＦＥＴにより構成される。
ワイヤボンディングのためにボンディングＰＡＤは、比較的大きな占有面積を持って形成される。これに適合するように出力ＭＯＳＦＥＴ及び出力プリバッファ回路及び入力バッファ回路がレイアウトされる。これにより、ボンディングパッドのピッチに対応してＩ／Ｏセルを効率よく配置させることができる。
このようにＩ／Ｏセルは、比較的大きな占有面積を持つようにされるので、出力プリバッファ回路又は出力ＭＯＳＦＥＴの一部に斜線を付したように前記実施例に示したような１ビット識別番号発生回路を嵌め込むようにすることができる。
第５４図には、この発明に係る半導体集積回路装置又は半導体チップに設けられる出力バッファ回路の一実施例の回路図が示されている。この実施例では、出力バッファ回路に前記１ビット識別番号発生回路が付け加えられる。
この実施例では、識別番号回路イネーブル信号が活性化した時（その時、正規の出力イネーブルは非活性）、正規出力バッファ回路に並列に設けられたバッファから１ビットの識別番号を出力する。このバッファは、駆動能力が小さくてもよいから正規回路の出力ＭＯＳＦＥＴに比べて小さいサイズのＭＯＳＦＥＴで足りる。この構成においては、識別番号を出力するための特別な出力端子が不要となり、半導体集積回路装置又は半導体チップに設けられた多数の入出力端子又入出力パッドを利用して多ビットからなる識別番号を取り出すようにすることができる。
第５５図には、この発明に係る半導体集積回路装置又は半導体チップに設けられる出力バッファ回路の他の一実施例の回路図が示されている。この実施例でも、出力バッファ回路に前記１ビット識別番号発生回路が付け加えられる。この実施例では、正規出力バッファ回路を利用して識別番号が出力される。つまり、出力プリバッファ回路にゲート回路を追加して正規出力と識別番号とを選択的に出力させるようにするものである。識別番号回路イネーブル信号は、ＬＳＩの専用ピンから生成されてもよいし、特別のＤＦＴ機能によって生成されてもよい。このことは、前記第５４図の実施例でも同様である。
近年、ロジックＬＳＩにおいてＪＴＡＧ（Ｊｏｉｎｔ　Ｔｅｓｔ　Ａｃｔｉｏｎ　Ｇｒｏｕｐ）の採用が広がっている。ＪＴＡＧ規格の中にも、ＬＳＩの識別番号を登録し、読み出すＩＤＣＯＤＥという機能がある。しかし、ビット数が３２ビットと少なく、しかも各ビットがデバイス及び製造メーカーなどを識別するようビット構成が細かく規定されているため、個々のチップの識別番号として使うことはできない。
第５６図には、この発明に係る半導体集積回路装置の一実施例の概略構成図が示されている。この実施例ではＪＴＡＧのインターフェイスを利用して識別番号の出力を行うように工夫されている。
ＪＴＡＧ対応デバイス（半導体集積回路装置）には、半導体集積回路装置本来の機能を行うための内蔵ロジックの他に、バウンダリスキャンレジスタ、インストラクションレジスタ、オプションレジスタ及びバイバスレジスタと、これらを制御するＴＡＰコントローラによって構成されるテストロジックが内蔵される。
テストロジックに対する命令やテストデータ、テスト結果のデータなどの入出力を行うシリアルインターフェイスは、ＴＡＰ（Ｔｓｅｔ　Ａｃｃｅｓｓ　Ｐｏｒｔ）と呼ばれ、５本の信号線を持っている。この信号線を外部のホストコンピュータ等で制御することによりＪＴＡＧテストが実施される。
第５７図には、この発明に係る半導体集積回路装置の基本的にＪＴＡＧセルの一実施例のブロック図が示されている。この実施例では、ＪＴＡＧのバウンダリスキャンレジスタを構成するセルに１ビット識別番号発生回路が組み込まれる。ＪＴＡＧセルは、前記第５１図等のＩ／Ｏセルに組み込まれることもあれば、内蔵ロジックに組み込まれることもある。
バウンダリスキャンレジスタのセルに、内蔵ロジックからの信号と１ビット識別番号発生回路で生成した識別情報とを切り替えて入力させる回路を付加することより、バウンダリスキャンレジスタのシフト動作を利用したシリアル出力を行うようにすることができる。
第５８図には、この発明に係る半導体集積回路装置のバウンダリスキャンレジスタのシフト動作を利用した識別番号のシリアル出力動作の一実施例を説明するための構成図が示されている。
この実施例では、ＬＳＩを３つ（Ａ〜Ｃ）、それぞれのＪＡＴＧセル（バウンダリ・スキャン・レジスタ）が７個、７個、９個とし、各セル中にデータの流れを示すためにデータの番号の数字が付されている。そして、同図には、代表としてＬＳＩ−Ｂに搭載された識別番号発生回路（ＩＤ−ＲＯＭ）からの識別番号を読み出す動作の例が示されている。
状態１は、初期状態でありＪＴＡＧでの動作状態が示されている。
状態２は、例えばＪＴＡＧのプライベート命令により、ＬＳＩ−ＢのＴＤＯが、ＪＴＡＧセルから切り離され、代わって識別番号発生回路ＩＤ−ＲＯＭに接続される。
状態３では、ＪＴＡＧのシフト命令により、識別番号発生回路ＩＤ−ＲＯＭがシフト動作を行って識別番号が、逐次ＴＤＯから出力される。同図においては３ビットの識別番号情報（Ｉ、ＩＩ、ＩＩＩ）が送り出された状態を示している。なお、各ＬＳＩ内のＪＴＡＧセルは、通常と同じく右へシフトしてＬＳＩ−Ｃを通してＬＳＩ−Ｂの識別番号が出力されることになる。
この識別番号を取り出した後は、図示しないけれどもプライベート命令モードから通常自動モードに戻り、ＴＤＯがＪＴＡＧセルに接続され

するが、必要ならその後に通常モードでシフトを繰返すことでセル情報

第５９図は、この発明に係る半導体集積回路装置のバウンダリスキャンレジスタのシフト動作を利用した識別番号のシリアル出力動作の他の一実施例を説明するための構成図が示されている。前記第５８図の実施例と異なるのは、状態３において、ＬＳＩ−ＣのＪＴＡＧセルのみがシフトしていることである。これにより、前記第５９図の実施例において

かたかもＩＤ−ＲＯＭ情報がＬＳＩ−ＢとＬＳＯ−ＣのＪＴＡＧセル情報の間に挿入された結果とすることができる。
第５９図は、この発明に係る半導体集積回路装置のバウンダリスキャンレジスタのシフト動作を利用した識別番号のシリアル出力動作の他の一実施例を説明するための構成図が示されている。この実施例の識別番号発生回路（ＩＤ−ＲＯＭ）は、前記第５７図に示した識別番号発生回路に対応している。
状態１は初期状態である。
状態２では、例えばＪＴＡＧのプライベート命令により、１ビット識別番号発生回路の情報をＬＳＩ−ＢのＪＴＡＧセルに転送する。この時

よって置き換えられるので破壊される。
状態３では、ＪＴＡＧのシフト命令により、ＩＤ−ＲＯＭの識別番号が、逐次ＬＳＩ−ＢのＴＤＯから出力される。
第６１図は、この発明に係る半導体集積回路装置のバウンダリスキャンレジスタのシフト動作を利用した識別番号のシリアル出力動作の他の一実施例を説明するための構成図が示されている。この実施例においては、識別番号専用のシフトレジスタ（ＩＤレジスタ・セル）が組み込まれたものである。
状態１は初期状態である。
状態２では、例えばＪＴＡＧのプライベート命令により、ＬＳＩ−ＢのＴＤＯは、ＪＴＡＧセルから切り離され、別番号専用のシフトレジスタの先頭に接続される。また、識別番号専用のシフトレジスタの最後尾は、ＬＳＩ−ＢのＪＴＡＧセルの先頭が接続される。この時同時に、識別番号専用のシフトレジスタには識別番号がセットされる。
状態３では、ＪＴＡＧのシフト命令により、ＩＤ−ＲＯＭの識別番号が、逐次ＬＳＩ−ＢのＴＤＯから出力される。同時に、ＬＳＩ−ＡのＪＴＡＧセル情報が、ＬＳＩ−ＢのＪＴＡＧセル情報と識別番号専用のシフトレジスタにシフトインされる。
図示しないけれどもさらにシフトをつづけ、ＬＳＩ−Ｂの全ての有効なＪＴＡＧセル情報がシフトアウトされた後、初期状態に戻す。
第６２図には、この発明に係る識別番号発生回路の更に他の一実施例の回路図が示されている。この実施例は、前記のようなＣＭＯＳインバータ回路ＩＮＶ１とＩＮＶ２の論理しきい値電圧差を増幅回路で増幅した識別情報を、ナンドゲート回路からなるラッチ回路に保持させる。つまり、第１書き込み信号ＷＲＩＴＥ１のハイレベルより、上記インバータ回路ＩＮＶ１とＩＮＶ２の論理しきい値電圧差に対応した２値の識別情報をラッチに入力する。
次に、上記第１書き込み信号ＷＲＩＴＥ１をロウレベルにして、上記２値の識別情報をラッチ回路に保持させるとともに、上記インバータ回路ＩＮＶ１、ＩＮＶ２及び増幅回路からなるインバータ回路列には、入力段のインバータ回路ＩＮＶ１の入力にプルアップＭＯＳＦＥＴで形成されたハイレベルを供給する。
次に、第２書き込み信号ＷＲＩＴＥ２と高電圧ＶＰＰとを用いて上記ラッチ回路の保持情報を、例えばヒューズ（ＦＵＳＥや、ＥＥＰＲＯＭ等からなる）不揮発性のプログラマブルデバイスに書き込む。そして、識別番号を必要とするときには、信号ＲＤによりプログラマブルデバイスをアクセスして上記書き込まれた識別番号をリードデータとして出力させる。
この構成は、上記第１書き込み信号ＷＲＩＴＥ１でのインバータ回路ＩＮＶ１とＩＮＶ２の論理しきい値電圧差に対応した識別情報が別の不揮発性回路に記録されるので、前記のようなＮＢＴＩの影響を受けることなく、識別ビットの再現性を維持し、経時変化に対しも耐性の高い識別番号発生回路を得ることができる。
以上の実施例のようにＣＭＯＳインバータ回路の論理しきい値のバラツキを用いた識別番号発生回路では、各素子のしきい値の大きさの順番を識別情報の源としている。
第６３図及び第６４図に４つの識別番号の例が示されている。第６３図は、それらのしきい値の順位をグラフ化したものであり、第６４図において、被識別番号の素子（ＣＭＯＳインバータ回路）は、１６個の素子の中で最も順位が高く、素子１０は最も順位が低い。これは、素子１の論理しきい値が最も高く、素子１０の論理しきい値が最も低いことを意味している。さて、この素子１と素子１０に注目すると、素子１に最も順位が近い素子は素子５であり、素子１０に最も順位が近いものは素子９である。
本願発明に係る識別番号発生回路では、ＣＭＯＳインバータ回路の論理しきい値のバラツキ方を順位化しているので、例えば素子１と素子５の間にどれくらいの論理しきい値電圧の差が存在するかは不明である。同様に素子１０と素子９の間についても不明である。また、それらの差が極めて僅かである場合、試験条件などで素子１と素子５順位が入れ替わる可能性がある。しかし、素子１と素子１０が入れ替わる可能性は極めて低いものと考えられる。それは、第６３図のグラフからも理解することが容易である。
照合時に取得される被識別番号というのは、過去において少なくとも１回以上取得され、データベースに格納されており、被識別番号と非常に類似した形で存在しているはずでる。類似とは、前述のように、本願発明の識別番号発生回路において、経時変化等の影響を受けて完全に識別番号が再現されない場合を考慮したものである。このように一部にＣＭＯＳインバータ回路間でのバラツキ方を順位が入れ替わっても上述のように、第６４図の例では、少なくとも素子１と素子１０の順位に関しては、過去に取得された識別番号も最新の被識別番号もその大小関係は変化していないことが容易に推定できる。
第６５図には、この発明に係る識別番号発生回路で生成された識別番号の高速識別番号照合（検索）アルゴリズムの一実施例を説明するためのフローチャート図が示されている。第６６図には、それに対応した構成図が示されている。
▲１▼被識別番号を読み込みステップでは、”０”と”１”からなる前記１ビット識別番号発生回路においてそれぞれから生成された連続データである。
▲２▼順位解析ステップでは、上記データを順位を表わす数字に変換する。つまり、前記第６４図のような１ビット識別番号発生回路の順位が数字に変換される。
▲３▼最大最小素子抽出ステップでは、順位を解析して、最大順位の素子と最小順位の素子の番号を抽出し記録しておく。
▲４▼において管理台帳から、登録済みの識別番号を一つ取り出す。
▲５▼において、上記の登録済み識別番号の中の、上記で記録した最大と最小の素子番号にあたる素子番号の順位を取り出す。例えば、前記第６４図の例では、識別番号１は最大が１、最小が１０であるが、１と１０という数を比較すると大小の関係が逆転している。これは、順位がバラツキなどによる変動をはるかに越えた現象であるため、被識別番号を識別番号１は異なるチップから採取されたものと容易に推定できる。よって、識別番号１は、不適合と判定され、その後の詳細な照合検査を省略する。
上記において適合と判定されたものは、▲６▼と▲７▼におて詳細検査を行う。基本的に、前記実施例と同様であるため割愛する。最も類似性の高い識別番号を一致候補とする。なお、▲５▼において、順位の大小比較では確率的に適合と、不適合の発生する割合は５割づつであるから、詳細検査が省略される効果もほぼ５割である。
そこで、この実施例では、１組の大小比較であるが、これを２組とすることで、上記効果をさらに２倍にすることが期待できる。ただし、これを増やすと、大小比較の処理自身が増大し効果を押し下げる可能性もあるので、識別番号の桁数や、識別番号の総母数との兼ね合いで選択することが望ましい。
第６７図には、この発明に係る識別番号発生回路を組み込んだ半導体チップの回路設計方法の一実施例のフローチャート図が示されている。この実施例のような回路設計ソフトウェアをデザイン企業や製造専門企業に提供する。あるいは、同一機能をＥＤＡベンダのツールに組み込むようにするものである。
（１）メニューをプルダウンして選択する。
（２）メニューデータが生成される。２回目以後は、このメニューデータを指定するだけで所望のＩＰを選択できる。
（３）メニューデータを分析し、違反などを検出する。
（４）メニューデータに従い、必要な情報を、ローカルデータベースから取り出す。ローカルデータベースにない最新の情報は、インターネット等のネットワークを介し、製造専門会社のデータベース等から取得する。
（５）データベースから収集した情報をもとにに、ソフトＩＰに必要なデータを生成処理を行う。
（６）ソフトＩＰが生成可能か判断する。不可能であれば、ハードＩＰ設計を選択する。
第６８図には、この発明に係る識別番号発生回路を内蔵したＬＳＩ設計方法の一実施例のフローチャート図が示されている。この実施例では、特に制限されないが、特定用途向けＬＳＩ（ＡＳＩＣ）の設計フローに向けられている。
論理合成ツールは、前記第６７図に示した設計フローでのソフトＩＰ生成の判断結果により、真理値表やＲＴＬ記述、状態遷移図などからゲートレベルの論理回路（ネットリスト）を生成する。また、図示していないが、多くの場合、ＲＴＬなどは、ＶＨＤＬやＶｅｒｉｌｏｇ　ＨＤＬ等の機能記述言語をもとに生成される。論理合成の際必要とされるのは、セルライブラリ情報であり、これにはトランジスタレベルの接続情報や、ディレー情報、レイアウト情報などが含まれている。また、通常ＲＴＬなどには、制約情報と呼ばれるタイミング誤差許容値やレイアウト配置間隔、最大信号配線長などの情報が付加されている。ＤＦＴツールはゲートレベルの論理回路にＬＳＩの検査に有効な診断論理を付加し、自動配置配線ツールによって最終的なレイアウトデータを作成する。
セルライブラリに登録されているセルの種類は、インバータやＮＡＮＤ（ナンド）、フリップフロップなどの最も基本的な回路構成要素が主なものである。一般にセルライブラリのデータ、例えばレイアウト情報などは人手により作成される。しかし、規模が大きい物や、例えばメモリのように基本的な機能は変わらないがその構成がわずかづつ異なる物については、自動セル生成ツールやラムコンパイラなどが用いられることがある。
ここで、本願発明でいうハードＩＰとソフトＩＰについて簡単に説明する。現在、半導体産業において、特に特定用途向けＬＳＩ設計製造においては、顧客（例えばゲーム機や自動車メーカなど）から受けた仕様をもとに、設計から製造までを１つの企業で行う総合企業形態と、設計だけを専業とするいわゆるＬＳＩデザイン企業と、製造を専業とするいわゆるファンドリ企業によって分業化される形態に分類される。
また、最近では分業化の流れに乗り、ＩＰを供給する企業（ＩＰベンダ）やそれらの流通市場や、標準化支援団体などが生まれている。ＩＰはＬＳＩの設計効率を向上する上でも重要な存在となってきており、総合企業においても無視できないものとなっている。
ＩＰには、大きくハードＩＰとソフトＩＰと呼ばれるものがある。両者の違いを、ＬＳＩデザイン企業とファンドリ企業による分業形態を対象した場合を比較してみる。ＬＳＩデザイン企業（ファブレス企業）は、顧客の仕様をもとに第６８図のＶＨＤＬやＶｅｒｉｌｏｇ　ＨＤＬ等の機能記述言語を用いたデータや、真理値表やＲＴＬ記述、状態遷移図などのデータ、制約情報などを作成する。ただし、顧客自身が、これらのデータまで作成しＬＳＩデザイン企業に渡す場合もある。
次にＬＳＩデザイン企業は、冒頭で述べた論理合成ツールを使用してネットリストを作成する。論理合成の際に、用いられる回路素子は、セルライブラリに登録されているものに限られる。それらは、製品を製造する製造専門会社が認定したものであり、一般に製造会社が自ら提供するのは、先に述べたインバータ回路やＮＡＮＤゲート回路のような基本的なものである。
ただし実際には、製造専門会社も、自社の競争力をたかめるため、より複雑なものを提供している。しかし、製造専門会社だけで、例えばＰＬＬやＳＲＡＭ、演算回路など複雑で高機能な回路を準備することは困難であるため、それらを設計し供給するＩＰベンダが多く登場する。ＩＰの中でもＰＬＬなどは、回路自身が複雑で、かつ使用するプロセスに特性が大きく依存するため、ＩＰベンダは一般的にハードＩＰという形で供給する。ハードＩＰは、簡単にいうとセルライブラリに、ＩＰベンダが設計したセルレイアウトが登録されるものである。それ故、ハードＩＰベンダはハードＩＰを供給する場合に、製造専門会社はもちろん、そのプロセス世代毎にもＩＰを変更し、製造会社の認定を受け、さらに各ＬＳＩデザイン企業の持つセルライブラリに登録してもらわなければならない。
一方、ソフトＩＰの場合、ＩＰベンダは、先のＶＨＤＬやＶｅｒｉｌｏｇ　ＨＤＬ等の機能記述言語を用いたデータや、真理値表やＲＴＬ記述、状態遷移図などのデータ、制約情報などを、ＬＳＩデザイン企業やファンドリ企業、あるいはその上の顧客に供給するのみである。そのため現在、特定用途向けＬＳＩの市場では、ソフトＩＰの普及が先行しており今後もその優位性は変わらないと考えられる。また、ラムコンパイラもあくまでセルライブラリの部品の作成を自動化するものであり、ハードＩＰの範疇に含まれる。
上記のように、ハードＩＰによる供給形態は、ＩＰの流通や普及の点で劣り、さらにハードＩＰを供給する側にもプロセス毎の設計変更などの負担などの短所がある。対して、この実施例の識別番号発生回路、特に第４９図や第５０図に示したような回路は、その心臓部でさえインバータとパストランジスタのみであり、むろんその他は標準的な論理素子で構成されているためソフトＩＰ化が比較的容易である。例えば、セルライブラリにＣＭＯＳインバータ回路（当然ある）とＣＭＯＳスイッチ（パストランジスタ）が既に登録されていれば、ＲＴＬ記述のみでＩＰを設計企業に供給できる。仮にパストランジスタが標準で登録されていない場合、新たにパストランジスタのみを登録する必要があるが、その規模は極めて小さい。
また、自動配置配線処理は配置や配線の結果が不規則でることが弱点として上げられるが、例えば、２つの識別用インバータが極端に離れた位置に配置されることも起こり得る。すると、回路図の信号Ｐと信号ＰＰの配線長が長くなり、周辺からの雑音の影響を受けやすくなる。これを低減するために、配置配線処理において、配置や信号線長の制限を与えることが有効である。また、この部分だけを、セルライブラリに登録された標準セルを組み合わせて新たなセルとして登録することも有効である。むしろカウンタやデコーダなどは、自動配置配線などで作成した方が効率的である。
近年、ＬＳＩにＩＤ番号や各種の固有情報（以降、これを一般情報と呼ぶ）などを組み込む応用例が増えている。例えば、製品の製造ライン番号や、製造週番号、製品のグレード、製造管理情報であったりする。これらは、一般にレーザフューズやＥＰＲＯＭなどを用いてＩＤ番号をプログラムしている。このプログラムにおいて、当然レーザプログラムのミスはあってはならないし、しかも、レーザフューズ方式は、ほとんどウェハ状態で加工されるが、レーザ工程以降の工程で変化してもならない。その情報が、生命・財産にかかわる内容のものであればなおさら重要である。
しかし、プログラム後ダイシングされチップがひとつひとつばらばらな状態では、レーザプログラム時に書き込まれた一般情報は読み出すことはできても、それが正しいかどうかを確認することは、非常に困難であるという重要な問題がある。その対策として次のようなものが考えられる。一つには、パリティビット付加し、データの変動を検出するものである。パリティ検査のための機能は、チップに内蔵してもよいが、測定器において判定してもよい。
しかし、厳密な意味で、チップに書き込まれているデータを確認したことにはならない。
他の一つは、読み出した情報の信頼性を確保するため、何らかの方法で読み出した一般情報を記録する仕掛けを作り、情報の重複を確認する方法である。この方法では、最悪重複したチップを全て不良品扱いとすることで製品の事故は防ぐことができる。しかし、現実には複数のチップの読み出し情報が重複した場合、どれが正しいものであるか確認は困難であり、チップの管理及び処置が複雑となる。
つまり、先に上げた問題の本質的な解決方法は、いったんばらばらにされたチップを識別し、そのチップの正しい情報を知り得て、それと比較することであると考えられる。
そこで、チップに固有の識別番号を付け加え、その情報を元に正しい番号をデータベース等から得るという発想も考えられるが、それ自体を同じレーザフューズで書き込んでも、それはいたちごっこになるだけである。
一方、情報論（例えば、情報論：瀧康夫著、岩波新書刊）によれば、符号間の距離（例えばハミング距離）が大きければ、それらに雑音が乗っても、元の情報の変化の検出とさらに修復も可能であるということが周知（例えば、誤り訂正符合とその応用：映像情報メディア学会編、オーム社刊）である。ここでは符合とは、レーザフューズで書き込んだ情報であり、雑音とはその一部が変化したことに相当する。
つまり、上記固有情報に、符号間の距離の大きなチップ固有識別番号を加えることで、全体の情報の一部が多少変化しても、他の識別番号すなわちチップと十分区別できるようになる。そこで、本願発明に係る識別番号発生回路の利用が有効となるものである。
第６９図には、この発明に係る識別番号発生回路内蔵の半導体チップを用いた半導体集積回路装置の製造方法の一実施例のフローチャート図が示されている。
一般情報とチップに符号間の距離の大きな固有の識別番号を合わせた情報（以降、これを管理情報と呼ぶ）を指示されたウェハ上のレーザフューズにプログラムする。固有識別番号は、内蔵の識別番号発生回路で生成されたものが用いられる。
一般情報と固有識別番号は、管理情報として、データベース上に保存され管理される。管理情報は、例えば一般情報＋チップの識別番号から構成される。
半導体集積回路装置又はＩＣカードの組み立て後の検査工程では、管理情報を読み出してデータベースを参照し同一の管理情報があるか確認する。同一の管理情報がデータベース内に存在すれば、レーザによるプログラムは正しいと判定される。同一の管理情報がデータベース内に見付からない時は、最も類似した管理情報を抽出する。次に、読み出した情報と抽出した管理情報のそれぞれの一般情報どうしを比較する。
この読み出しの際、一般情報の部分については、例えば電源電圧条件を変えるなど複数の条件で読み出し、固有識別番号については１回のみ読み出すことで、短時間にデータの書き込みが十分安定しているか確認することができる。なお、試験中は高速にデータベース上の管理情報との照合を行う必要がある。例えば、検査が始まる前に予め参照される管理情報のデータを試験装置に付随するワークステーション等に格納しておいてもよい。
上記の方法によって、プログラム情報の迅速で正確な確認が出来るようになる。しかも、固有識別番号の書き込みをレーザフューズ等で逐一行うと、加工時間とチップ面積の増加をもたらす可能性があるが、本願発明に係るＣＭＯＳインバータ回路論理しきい値のバラツキを用いたチップ識別番号発生回路を用いることで、簡単にしかも自動的に固有識別番号を得ることができる。
つまり、レーザプログラムに先立つ、プローブ検査等で取得されたチップ識別番号および、ロットやウェハ等の情報を、管理情報データベースに登録する。指示されたウェハ上のチップに対応する管理情報をレーザフューズへ書き込むというものである。
第７０図には、この発明に係る識別番号発生回路を搭載した半導体チップを用いた半導体集積回路装置の組み立て工程（いわゆる後工程）の一実施例のフローチャート図が示されている。
（１）プローブ検査では、識別番号発生回路によるＩＤ番号、ロット名、ウェハ番号、チップ番号等をデータベースに登録する。
（２）登録時に既に登録されたＩＤ番号に類似した新たなＩＤ番号が発生した場合、何らかの警告を発しチップを処置する。
（３）組み立て試験以降の工程では、既にチップはダイシング工程にてバラバラに分かれているため、識別番号発生回路によるＩＤ番号と、工程番号、当該工程ロット名をデータベースに登録する。
（４）本願に係る識別番号発生回路によって取得できるＩＤ番号は、組み立て工程の機械的、熱的ストレスやバーイン工程の電気的ストレス等で変動する可能性があるため、最新検査工程で取得されたＩＤ番号をデータベースに格納する。
（５）後工程内のチップ追跡の必要がない場合、最終出荷選別工程でのみ識別番号発生回路によるＩＤ番号を取得しデータベースに登録する。
（６）各試験工程で、不良になったチップの既取得ＩＤ番号情報は、削除するか印を付けて以降の検索処理時間を軽減する。
（７）マーキング工程では、製品を製造したラインを示す記号や番号、製造した時期を示す年番号や週番号が刻印されることがある。個別サンプルの識別を行う上で、これらの刻印は検索のための情報となる。そこで、出荷選別２では、識別番号発生回路によるＩＤ番号とこららの刻印情報をデータベースに登録する。共通の刻印情報を持つチップでは、識別番号発生回路によるＩＤ番号は全て独立である必要があるが、異なる刻印情報を持つチップでは、識別番号発生回路によるＩＤ番号に同一あるいは類似しても構わない。すなわち、各チップに搭載する識別番号発生回路によるＩＤ番号の識別能力を抑えることが可能で、識別番号発生回路の規模および識別番号のビット数を削減できる。
（８）各工程毎の識別番号発生回路によるＩＤ番号の登録時に、ＩＤ番号をもとにロットの混入・混合を検出し、何らかの警告を発する。
この実施例では、全ての工程とデータベース間がオンラインで直結しているが、現実には立地条件により通信回線による接続が困難である場合や、通信速度が遅い、バッチ処理が介在するなどの理由でリアルタイム性に欠けるような状況が発生する。そのような場合、いったんローカルなデータベースに蓄える。さらに、即時性が必要でない場合、記憶媒体に保存し、データベースまで輸送するか、現物と一緒に、次工程に搬送する。
各工程の試験装置や処理計算機などの制約などによって、データベースに集められるデータの形式が異なる場合がある。そのような場合、データフォーマットのを変換する処理を、データベース登録直前に挿入すればよい。
第７１図と第７２図には、この発明に係る識別番号発生回路のビット数を減少させる方法の一実施例の構成図が示されている。第７１図には、識別番号発生回路のビット数を低減させる登録方法、第７２図には、その照合方法が示されている。
世の中に半導体集積回路装置等の製品が出荷されユーザで使用中に不良となった場合に、返品され不良原因調査を行う場合にも本願発明に係る識別番号発生回路が有効に機能する。この場合には、出荷時に識別番号を管理するデータベースへ登録し、もし不良で製品が戻ってきた場合にその製造過程のデータを調査する。このときに、不良品がどの管理番号の製品であるかを照合する必要がある。製品の出荷数が多ければ、以下のような状況が発生する。
識別番号の識別可能数は識別番号発生回路のビット数に依存しておりビット数が多ければ識別の確度は向上するが、それだけ識別対象データ数は多くなる。製品の識別を行う上で、識別対象数が多くなれば、比較照合するためにデータベース上の多くのデータを読み出し、かつ照合演算を実行する必要がある。そこで、比較照合処理の時間やシステムへの負荷を軽減するために、第７１図のように識別番号グループを示す情報を別途定義する。これにより第７２図のように照合データ数の範囲を、少なくすることができる。
このような識別番号のビット数を低減させるための識別番号グループは、一般的なロット、マークと呼ばれている情報が使用される。この情報と識別番号との組み合わせで製品がユニークに管理できるように管理することができる。また、出荷後の製品を管理するだけのデータベースにおいては、不良となったチップの情報を削除し管理コストを削減する。の識別グループでデータベース上の膨大なデータの中から照合対象を減らし、処理時間、システム負荷を減らすことができる。
第７３図と第７４図には、この発明に係る半導体集積回路装置に搭載された識別番号発生回路を利用した検査方法を説明するための構成図が示されている。第７３図は、識別番号取得工程が示され、第７４図は、検査工程が示されている。
第７３図に示した製造過程の終了に近い段階で、識別番号発生回路はその機能が利用できるため、何回かの検査工程の前に識別番号取得工程を設け、まず最初に、製品の識別番号と管理番号・品種などの後の工程で必要となるデータをデータベースへ登録する。ただし、識別番号発生に関する最低限の動作が可能なデバイスに限られる。
第７４図に示した以降の各検査工程では、まず製品の識別番号を読み出し、データベース上の識別番号と照合し管理番号を取得する。この管理番号から品種や検査仕様のデータを一意に決定し、検査装置へ転送する。検査装置は個々の製品毎に与えられた検査仕様で検査を行うことができる。この構成の利点は、各検査工程では、品種や検査仕様あるいはその他の付随データを最初の識別番号取得工程のみでデータベースに与えれば、その後の各検査工程あるいは製造工程において与える必要がないため生産の効率を上げることができる。
第７５図には、この発明に係る半導体集積回路装置に搭載された識別番号発生回路を利用し各検査工程で半導体チップ毎の特性データの相関を管理する方法を説明するための構成図が示されている。
半導体製造における各検査工程で得られる特性データ（測定値）は、各工程で得られるが、その特性データの変化を分析することがある。これらの特性データを管理するために識別番号を使用しチップ毎に各工程毎の特性データをデータベースに格納する。この時、データベースの識別番号も、最新の工程で得られた識別番号で更新することで回路の動作変化による識別番号の変化をデータベースに取り込む。
従来は、プローブ検査と完成品検査との相関は、ロット単位に複数チップをグループとして相関を取るしかなかった。今回は各チップ毎に各工程間の特性データ変化の相関を取ることができるため分析の精度を上げることができる。
第７６図には、この発明に係る半導体集積回路装置に搭載された識別番号発生回路を利用し前工程でウェハを自動で管理する方法を説明するための構成図が示されている。
ＴＥＧ上にウェハを識別するための識別番号発生回路を設け、最初の配線工程で、その機能が完成する場合に、個々のウェハをその識別番号で管理することができる。これによりウェハに管理用のタグを付けることが不要であるし、ウェハの製造工程を管理するシステムへの情報入力も不要になる。
識別番号発生回路の機能が有効となり、かつ、それ以降の各工程でそのウェハが処理される製造装置・検査装置に識別番号読み取り機構が付いていれば、読み取った識別番号でデータベースにアクセスすることで、自動でそのウェハの情報を装置に設定することが可能である。また、そのウェハを処理したときの製造条件や検査データをデータベースへ自動で格納することもできる。
識別番号読み取り機構は、パソコンから制御可能な電源と識別番号発生回路を機能させるための信号生成とその出力（識別番号）を読み取れるボードとソフトウエアで構成できる。ＴＥＧと信号の入出力するためのプローブも必要である。
第７７図には、この発明に係る半導体集積回路装置に搭載された識別番号発生回路の識別番号の格納・検索方法を説明するための構成図が示されている。
この実施例では、識別番号の上位Ｎビットを取り出しインデックスとしてデータベース上のテーブルフィールドに格納・管理する方式を採ることにより検索スピードの向上、システムへの負荷低減が行える。比較対象の識別番号とデータベース内の識別番号群との比較方法で、比較対象の識別番号の上位ビットをまず抽出し、この値をデータベース上のインデックス値と一致する条件でテーブルを検索する。次に、ここで得られた識別番号群に対して１件づつ識別番号距離を求めて最小のものを一致識別番号と判定する。これにより、テーブル上の全件の識別番号を比較することなく該当データを見つけ出すことが可能である。
第７８図には、この発明に係る半導体集積回路装置に搭載された識別番号発生回路の識別番号の格納・検索方法の他の例を説明するための構成図が示されている。
識別番号の検索範囲を限定してデータベースの識別番号群と比較する方式を採用することにより検索スピードの向上、システムへの負荷低減が行える。比較対象の識別番号とデータベース内の識別番号群との比較方法で、比較対象の識別番号に対して揺らぎによる許容範囲の上限・下限をデータベース検索条件としてテーブルを検索する。次に、ここで得られた識別番号群に対して１件づつ識別番号距離を求めて最小のものを一致識別番号と判定する。これにより、テーブル上の全件の識別番号を比較することなく該当データを見つけ出すことが可能である。１回目の許容範囲の上限・下限で該当せずにデータが検索できなかった場合は、上限・下限を緩めて再度検索処理を行っていく。
第７９図には、この発明に係る識別番号発生回路を利用した半導体集積回路装置の救済方法の一実施例の構成図が示されている。
▲１▼本体チップのプローブ検査が実施される。この検査によりＤＲＡＭ等の救済データを識別番号発生回路から取り出した識別番号とともにホストコンピュータに送る。
▲２▼ダイシングして完全動作品と救済可能品のみを取り出す。
▲３▼救済データ専用ＥＥＰＲＯＭのプローブ試験を実施する。
▲４▼正常動作品をダイシングし、ストックして置く。
▲５▼本体ＬＳＩと救済データ専用ＥＥＰＲＯＭを同一モジュールに実装する。
▲６▼実装済モジュールの本体ＬＳＩの識別番号を読み出し、対応する救済データを救済データ専用ＥＥＰＲＯＭに書き込む。
▲７▼選別試験を行う。
▲８▼良品ＬＳＩは出荷し、不良ＬＳＩのうち再度救済可能なものはステップ前記▲６▼に戻り、対応する救済データを救済データ専用ＥＥＰＲＯＭに書き込む。
これにより、半導体集積回路装置の救済が簡単にしかも合理的に行うようにすることができる。
なお、半導体集積回路装置の救済の他にも上記識別番号を利用した検査コストの低減が可能である。半ウェハ上に半導体チップが形成された時点で行われるプローブ試験において、例えば、フラッシュメモリのような半導体チップでは、同じ回路機能で動作電圧が３．０Ｖ、２．５Ｖ及び１．８Ｖのように異なるものを別品種として製造するものがある。
このとき、１．８Ｖに対応した電圧設定によりテストを実施し、正しくメモリ動作が行われるか否かの判定が行われる。この判定により良品とされた半導体チップには、その識別番号に１．８Ｖ動作確認の電圧情報が記録される。動作確認の情報は、半導体チップそれ自体に不揮発的に書き込み保持される。そのために、半導体チップ内には、フラッシュメモリからなるような管理メモリが設定される。
上記１．８Ｖで不良となったチップについては、２．５Ｖに電圧設定してメモリ動作が行われるか否かの判定が行われる。この判定により良品とされた半導体チップには、その識別番号に２．５Ｖ動作確認の電圧情報が記録される。そして、上記２．５Ｖで不良となったチップについては、２．５Ｖに電圧設定してメモリ動作が行われるか否かの判定が行われる。この判定により良品とされた半導体チップには、その識別番号に３．０Ｖ動作確認の電圧情報が記録される。この３．０Ｖで不良となったチップは不良チップとして廃棄される。
この実施例においては、例えば上記１．８Ｖで動作するものとされた半導体チップについて、２．５Ｖや３．０Ｖでの動作試験を行うことなく、２．５Ｖや３．０Ｖでの動作が可能なものとして扱われる。同様に、上記２．５Ｖで動作するものとされた半導体チップについて、３．０Ｖでの動作試験を行うことなく３．０Ｖでの動作が可能なものとして扱われる。このため、１．８Ｖで動作するものとされた半導体チップを２．５Ｖや３．０Ｖでの動作させたときに不良となる可能性を持つが、その確率は小さいと考えられるので逐一各電圧での動作を行うことよりもそれを省略してテスト時間の短縮化を図った方が全体としての製造のコストの低減が可能になる。
そして、フラッシュメモリ単体として組み立てるとき、あるいはマイクロプロセッサ等と組み合わせて１つの半導体集積回路装置として組み立てられるとき、上記識別番号からホストコンピュータに記憶された動作電圧情報を得て、適合するものが組み合わられる。このとき、２．５Ｖで動作する半導体集積回路装置は、前記１．８Ｖの動作確認のチップも用いることができ、３．０Ｖで動作する半導体集積回路装置は、前記１．８Ｖと２．５Ｖで動作するチップも用いることができる。
第８０図は、この発明に係る識別番号発生回路を備えた半導体集積回路装置の更に他の実施例のレイアウト図であり、第８１図は第８０図の部分拡大レイアウト図である。第８０図の半導体集積回路装置は、多くの一般的な半導体集積回路装置と同様に、それを構成する半導体チップのほぼ中央に内蔵回路ないし内部回路が配置され、その周辺に外部との信号の授受のための複数の入出力セル（Ｉ／Ｏセル）が配置された構成を採る。
半導体チップの周辺部の４つの角は、一般的な半導体集積回路装置と同様に、Ｉ／Ｏセルが配置されていない空領域となっている。この実施例ではかかる空領域を利用し、その１つに、識別番号発生回路ＣＲＮＣが設けられている。
識別番号発生回路ＣＲＮＣは、半導体チップ上に延長形成される信号及び電源配線層によって内蔵回路と結合される。
後で説明するように、信号及び電源配線は、切断される場合が有る。かかる切断の便宜の上では、かかる信号及び電源配線層は、その数が少ない方が望ましい。そこで実施例では、識別番号発生回路と内蔵回路のインターフェースのための配線は、該識別番号発生回路のための電源配線（ＶＤＤ、ＶＳＳ）と、リセット信号（ＲＥＳ）、クロック信号（ＣＬＫ）、識別番号出力信号（ＯＵＴ）のための３つの信号配線とからなるような少ない数の配線から構成される。第８１図の部分拡大図では、比較的太い線によって電源配線ＶＤＤ、ＶＳＳを表示し、比較的細い線によってリセット信号、クロック信号識別番号出力信号のための信号配線を表示している。図から明らかなように、信号配線は、実質的に電源配線ＶＤＤ，ＶＳＳによって囲まれた状態を持って延長されている。
識別番号発生回路ＣＲＮＣは、上記リセット信号、クロック信号の元で、前記実施例のような総当たり方式を持っての識別番号発生が可能なように構成される。識別番号発生回路ＣＲＮＣの周囲の空領域上には、第８１図のように、かかる回路ＣＲＮＣのリセット信号（ＲＥＳ）、クロック信号（ＣＬＫ）、識別番号出力信号（ＯＵＴ）電源端子ＶＤＤ、ＶＳＳにつながる電極パッドＲＥＳ、ＣＬＫ、ＯＵＴ、ＶＤＤ、ＶＳＳが設けられている。それら電極パッドは、モールドレジンなどのパッケージ部材によって半導体チップをパッケージして構成されたような半導体集積回路装置の外部端子とされるものでなく、プローブニードルと称されるようなコンタクタに適合可能なように、半導体チップ上に構成される。
図示の識別番号発生回路ＣＲＮＣからの識別番号情報は、半導体集積回路装置の電源線、内蔵回路，Ｉ／Ｏセルなどの径路が動作可能であるなら、Ｉ／Ｏセルを介する正常径路を通って外部への読み出しが可能にされる。
ここで、識別番号情報は、製品の来歴調査を含めての多くの必要性に応えられることが望ましい。識別番号情報は、場合によっては、動作不能となった半導体集積回路装置からも得られることが望まれる。
半導体集積回路装置が、不都合なことに、電源電流の異常増大、他の種々要因にによって正常動作しなくなっている場合には、モールドレジンのようなパケージ部材が除去され、半導体チップが露出され、識別番号発生回路ＣＲＮＣと内蔵回路との間の電源及び信号配線層がレーザ切断装置のような装置によって切断除去される。これによって識別番号発生回路ＣＲＮＣは、上記電極パッドのみに接続された状態にされる。言い換えると、該回路ＣＲＮＣは、半導体集積回路装置の内部配線ショート、内部素子破壊等から自由にされ、それ自体独立的に動作可能にされる。そこで、この状態で、上記電極パッドにコンタクタが接触され、かかるコンタクタを介して、識別番号情報の取得が可能となる。
半導体集積回路装置が、半導体チップ上に応力緩和の狙いを持つような絶縁層及び再配置配線のような配線層を介してバンプ電極からなるような複数の外部端子を設けるところのチップ・サイズ・パッケージないしはチップ・スケール・パッケージと称されるようなパッケージ形態を取る場合も、同様に識別番号情報を得ることができる。この場合、通常の外部端子を介して識別番号情報を得ることが困難なときには、バンプ電極、絶縁層の除去によって上記と同じ電極パッド、及び切断すべき配線部分の露出が行われ、配線切断除去の後に、上記電極パッドを介しての識別番号情報の読み出しが行われる。
第８２図は、この発明に係る識別番号発生回路を備えた半導体集積回路装置の他の実施例の構成図であり、第８３図はその回路図である。
この実施例の半導体集積回路装置は、ＭＯＳＦＥＴ等を構成する半導体領域を固定的パターンとしておき、配線により所望の機能の回路を構成するようにする、いわゆるマスタースライス方式のものとされる。半導体集積回路装置を成す半導体チップ上に設定されるＩ／Ｏセルの内、遊休Ｉ／Ｏセル、すなわち該半導体集積回路装置の機能の上からは使用されないＩ／Ｏセルは、識別番号発生回路を構成するものとされる。
１つのＩ／Ｏセルは、図示のように、比較的小さい面積の出力制御回路のための領域、比較的大きい面積の出力ＭＯＳＦＥＴのための領域（出力ＭＯＳ）、及び入出力パッド電極（Ｉ／ＯＰＡＤ）を配置するための領域からなり、その全体は図示のように長方形の平面パターンを成している。
上記出力制御回路のための領域は、比較的小さい面積とされるが、所望の出力制御回路、入力回路を構成可能なように、比較的多数のゲート回路、インバータ回路及びＭＯＳＦＥＴのようなサブ要素を持つ。出力ＭＯＳＦＥＴのための領域は、１つもしくは２つのｐチャンネル型ＭＯＳＦＥＴと１つもしくは２つのＮチャンネル型ＭＯＳＦＥＴとからなるような比較的少ない数のＭＯＳＦＥＴしか持たないが、高い外部負荷駆動能力の点で比較的大きい面積とされる。
上記識別番号発生回路は、遊休Ｉ／Ｏセルにおける出力制御回路のための領域におけるサブ要素によって構成される。上記識別番号発生回路は、かかる出力制御回路のための領域における比較的多数のサブ要素によって、かかる領域に構成可能となる。
第８３図に図示のＰチャンネル型ＭＯＳＦＥＴ及びＮチャンネル型ＭＯＳＦＥＴ、インバータ回路、ＮＡＮＤ回路及びＮＯＲ回路は、全体として、識別番号発生回路の出力を外部に出力させるためのトライステート出力バッファ回路を構成している。かかる出力バッファ回路において、インバータ回路、ＮＡＮＤ回路及びＮＯＲ回路は、出力制御回路のための領域におけるサブ要素によって構成され、出力ＭＯＳＦＥＴは出力ＭＯＳＦＥＴのための領域におけるＭＯＳＦＥＴによって構成される。
上記遊休Ｉ／Ｏセルにおけるトライステート出力バッファ回路の出力は、同セルに設けられる入出力パッド電極（Ｉ／ＯＰＡＤ）に結合される。言い換えると、図示の入出力パッド電極は、識別番号情報専用の出力電極とされる。
上記入出力パッド電極は、半導体集積回路装置における、通常はＮＣ（Ｎｏｎ　Ｃｏｎｎｅｃｔｉｏｎ）ピンと称されるような半導体集積回路装置の空ピンないしは空き端子に、結合される。
この実施例によれば、図中に識別番号回路イネーブルと標記されているイネーブル信号がハイレベルのような有意レベルにされることによって、識別番号発生回路及びトライステート出力バッファ回路が動作状態にされる。識別番号発生回路の動作のために、図中に、出力クロックと標記されている連続クロック信号が供給される。かかる連続クロック信号に応答して入出力パッド電極に准じに識別番号情報が供給される。
第８４図は、この発明に係る識別番号発生回路を備えた半導体集積回路装置の他の実施例の構成図である。この実施例は、近年のような大規模な半導体集積回路装置に有っては、消費電流の増大や動作速度の高速化に対応するような電源強化の点から、遊休Ｉ／Ｏセルが有っても、そのセル領域を電源強化のために転用する、と言うことが考慮されている。
第８４図のレイアウト図では、３つのＩ／Ｏセルが例示されている。かかる３つのＩ／Ｏセルの内、図面の上の方のＩ／Ｏセルは遊休Ｉ／Ｏセルとされ、図面の下の方の他のＩ／Ｏセルは、半導体集積回路装置動作のために動作利用される正規Ｉ／Ｏセルとされる。
遊休Ｉ／Ｏセルにおいて、その入出力パッド電極用の領域には電源パッド電極、すなわち電源等に転用されたパッド電極が設けられている。電源パッド電極は、複数のＩ／Ｏセル、ないしは内蔵回路のための図示しない電源配線層に結合されている。なお、遊休Ｉ／Ｏセル上の電源配線層は、通常、多層配線構造を採る配線層の内のメタルからなるような上層配線層からなると理解されたい。
遊休Ｉ／Ｏセルにおいて、上記第８１図の出力制御回路のための領域と対応する部分には、多層配線層における下層側の配線層による配線によって、上記第８１図の例と同等に、出力クロック信号、識別番号回路イネーブル信号を受け、識別番号出力を形成するところの識別番号発生回路が構成されている。
上記識別番号発生回路と内蔵回路との間の出力クロック信号、識別番号回路イネーブル信号及び識別番号出力のための配線層は、後で説明する配線切断及び端子形成が容易なように、それぞれの一部が比較的上層の配線層を使用するようにされる。
識別番号発生回路の出力信号は、出力セルとして設定される正規Ｉ／Ｏセルの入力側に設けられた出力選択回路の供給される。
これによって、出力セルとして設定される正規Ｉ／Ｏセルは、半導体集積回路装置の通常動作においては、内蔵回路から出力選択回路を介して供給される正規出力データをその入出力パッド電極に出力する。
かかる正規Ｉ／Ｏセルは、識別番号情報を出力すべきときには、識別番号発生回路から出力選択回路を介して供給される識別番号情報をその入出力パッド電極に出力する。
第８５図は、識別番号発生回路の電源端子ＶＤＤ及びグランド端子と称されるような基準電位端子ＶＳＳと、複数のＩ／Ｏセル上を延長されるような電源配線層及び基準電位配線層との結合パターンを示している。上記のＩ／Ｏセル上を延長する電源配線層ＶＤＤ及び基準電位配線層ＶＳＳが電源系強化の意図の元で比較的広い幅を持つようにされる。この実施例では、第８５図のように、比較的幅広の電源配線層に対し細い幅の分岐配線層が設けられ、かかる細い幅の分岐配線層が、識別番号発生回路のための電源配線ＶＤＤ−Ｖと結合される。基準電位配線層と識別番号発生回路の基準電位配線ＶＳＳ−Ｖとの結合も同様にな構成とされる。この構成は、識別番号発生回路と電源配線層及び基準電位配線層との間の次に説明するような分離を用意にする。
電源配線層−基準電位配線層間の短絡等の異常にかかわらずに、識別番号発生回路から識別番号情報を得る必要が生じたときには、第８６図のように、かかる回路の電源端子ＶＤＤ、基準電位端子ＶＳＳにつながる細幅分岐配線層が、レーザ切断技術やフォーカスド・イオン・ビーム（ＦＩＢ）技術のような技術によって切断される。これと共に、識別番号発生回路と内蔵回路との間の前述のような信号線も同様に切断される。
ついで、絶縁膜形成、それに対する開口形成、及び導電層の選択形成がＦＩＢ技術のような公知の技術によって行われる。これによって、識別番号発生回路の電源端子ＶＤＤ、基準電位端子ＶＳＳには、第８６図のように新たな導電層からなる導電気領域が設定される。同時に、上述の信号線に対しても新たな導電層が設定される。
プローブ針と称されるようなコンタクタがそれら導電層に接触され、識別番号発生回路が動作され、識別番号情報が得られることとなる。
第８７図は、この発明に係る識別番号発生回路を備えた半導体集積回路装置の他の実施例の回路図である。
この実施例では、半導体集積回路装置に構成された識別番号発生回路に対して、図示のような２つのダイオード接続のＭＯＳＦＥＴＱ１、Ｑ２、識別番号回路用電源パッド、識別番号専用出力パッド、識別番号専用クロックパッド、及び識別番号専用イネーブルパッドが設けられている。
半導体集積回路装置が正常動作可能である場合には、識別番号発生回路は、半導体集積回路装置の正規電源端子ＶＤＤ、正規電源配線及びダイオード接続ＭＯＳＦＥＴＱ１を介して動作電圧が与えられ、かつ図示しない内蔵回路からのクロック信号、識別番号イネーブル信号に応答して、内蔵回路に識別番号情報を出力する。
正規電源端子ＶＤＤ及びそれにつながる電源配線と、正規基準電位端子ＶＳＳ及びそれにつながる基準電位配線との間の短絡異常などによって、正規端子ＶＤＤ・ＶＳＳ−を介して識別番号発生回路に電源供給ができない場合には、図示の各種パッドを介して必要な電圧、信号がかかる回路に加えられ、かかる回路が動作される。ダイオード接続のＭＯＳＦＥＴＱ１は、識別番号回路用電源パッド及びＭＯＳＦＥＴＱ２を介して該回路に加えられる電源電圧に対して自動的にオフ状態となるようなスイッチ動作をする。これによって正規電源系の異常にかかわらずに識別番号発生回路に給電をすることができる。
上記の各実施例から得られる作用効果は、下記の通りである。
（１）　半導体集積回路装置の製造工程の過程で同一の形態からなる複数の識別要素を形成し、そのプロセスバラツキに対応した複数の識別要素の相互の物理量の大小関係を判定して、半導体集積回路装置の固有の識別情報として用いることにより、簡単な構成で個々の半導体集積回路装置の識別を可能にすることができるという効果が得られる。
（２）　上記に加えて、上記固有の識別情報を上記製造時に識別要素に割り当てられた第１識別情報と、上記判定により得られた上記複数の識別要素の物理量を大小関係の順位情報とを用いることにより、個々の半導体集積回路装置の識別のための情報量を少なくできるから、識別情報を記憶する記憶回路を簡単にできるとともにその判定時間も短縮化できるという効果が得られる。
（３）　上記に加えて、上記識別要素をＮチャンネル型ＭＯＳＦＥＴとＰチャンネル型ＭＯＳＦＥＴからなるＣＭＯＳインバータ回路の入力端子と出力端子とを接続し、その論理しきい値を大小比較を行う物理量とすることにより、ＣＭＯＳ回路等の基本的なデジタル回路で構成できるから格別な製造プロセスの追加なく適用可能な半導体集積回路装置の範囲を広くできるという効果が得られる。
（４）　上記に加えて、上記ＣＭＯＳインバータ回路に対して、物理量としての論理しきい値電圧判定時にのみ動作電圧を印加するようにすることにより、素子特性の劣化の影響を軽減できるので安定的で信頼性の高い識別結果を得ることができるという効果が得られる。
（５）　半導体集積回路装置の製造工程の過程で同一の形態からなる複数の識別要素を形成し、そのプロセスバラツキに対応した物理量を判定し、上記複数の識別要素の相互の物理量の大小関係に基づいて固有の識別情報を生成して製造履歴と附帯させて記憶し、かかる半導体集積回路装置について不良が発生したときに、上記固有の識別情報を基に上記記憶された製造履歴を読み出し不良解析を行って、必要に応じて上記製造工程にフィードバックさせることにより、合理的な製造システムの構築を行うようにすることができるという効果が得られる。
（６）　第１チップを構成する半導体集積回路装置の製造工程の過程で同一の形態からなる複数の識別要素を形成し、そのプロセスバラツキに対応した相互の物理量の大小関係に基づいてかかる第１チップの固有の識別情報を生成し、上記第１チップを構成する半導体集積回路装置の複数に対して、それぞれの電気的特性に応じて複数の動作修飾情報を形成し、上記個々の第１チップの識別情報に対応させて第２チップに書き込み、上記第１チップと第２チップとを組み立てて第１チップの識別情報を基に上記動作修飾情報を第１チップに向けて出力させることにより、マルチチップ構成の半導体集積回路装置を煩雑なチップ管理を行うことなく効率よく製造することができるという効果が得られる。
（７）　上記に加えて、上記第１チップで冗長回路を持つメモリを構成し、上記第２チップを不良アドレスを記障するものとすることにより、簡単な構成で製造歩留りを高くしたメモリ装置を得ることができるという効果が得られる。
（８）　上記に加えて、上記第１チップと第２チップが組み立てられた状態で更に試験を行って不良が発生した場合に、上記第２チップを取り外して、上記第１チップを構成する半導体集積回路装置の別の複数の半導体集積回路装置の纏められる工程に戻すことにより、製造歩留りを改善することができるという効果が得られる。
（９）　上記に加えて、上記第１チップと第２チップとを上記組み立てられた状態での選別の後に一体的に封止することにより、製造歩留りの改善を行ないつつ、半導体集積回路装置の小型化を実現できるという効果が得られる。
（１０）　上記に加えて、上記第１チップと第２チップとを共通の実装基板上に組み立てるようにすることにより、第２チップの取り外しが簡単となって、上記不良が発生した場合の再利用を効果的に行うようにすることができるという効果が得られる。
（１１）　半導体集積回路装置の製造工程の過程で同一の形態として形成された複数の識別要素のプロセスバラツキに対応した相互の物理量の大小関係に基づいて固有の識別情報を持たせることにより、簡単な構成で個々の半導体集積回路装置の識別情報を組み込むことができるという効果が得られる。
（１２）　上記に加えて、上記固有の識別情報を上記製造時に識別要素に割り当てられた第１識別情報と、上記複数の識別要素の物理量を大小関係の順位情報とすることにより、個々の半導体集積回路装置の識別のための情報量を少なくできるから、それを記憶する記憶回路を簡素化できるとともにその判定動作の高速化もできるという効果が得られる。
（１３）　上記に加えて、識別要素をＮチャンネル型ＭＯＳＦＥＴとＰチャンネル型ＭＯＳＦＥＴからなるＣＭＯＳインバータ回路の入力端子と出力端子とを接続し、その論理しきい値を大小判定の物理量として利用することにより、ＣＭＯＳ回路等の基本的なデジタル回路で構成できるから格別な製造プロセスの追加なく適用可能な半導体集積回路装置の範囲を広くできるという効果が得られる。
（１４）　上記に加えて、ＣＭＯＳインバータ回路の入力端子と出力端子とを接続し、その論理しきい値を大小判定を行う回路として、複数のＣＭＯＳインバータ回路の各々にスイッチを設け、２個ずつの組み合わせで総当たりで共通の電圧比較回路に上記論理しきい値電圧を供給して判定することにより、簡単な構成で高い識別能力を実現できるという効果が得られる。
（１５）　上記に加えて、複数のＣＭＯＳインバータ回路の各々に対応して、その入力端子と出力端子とを接続する第１スイッチと、共通の第１回路ノードと入力端子とのを接続する第２スイッチと、出力端子と共通の第２回路ノードとを接続する第３スイッチとを設けて、かかる第１ないし第３スイッチの組み合わせにより、複数のインバータ回路間において２つのＣＭＯＳインバータ回路を１組として総当たりで、一方のＣＭＯＳインバータ回路の入力端子と出力端子とを接続して上記第１の回路ノードに得られて電圧を他方のＣＭＯＳインバータ回路の入力端子に供給して、かかる他方のＣＭＯＳインバータ回路の論理しきい値電圧を参照電圧として電圧比較の出力信号を上記第２の回路ノードに得るようにすることにより、簡単な構成での識別番号の生成を行うようにすることができるという効果が得られる。
（１６）　上記に加えて、上記ＣＭＯＳインバータ回路と第１スイッチないし第３スイッチをＣＭＯＳゲートアレイを構成する素子を用いることにより、配線設計のみにより識別番号発生回路を得ることができるという効果が得られる。
（１７）　上記に加えて、上記ＣＭＯＳインバータ回路に上記物理量としての電圧判定時にのみ動作電圧を供給することにより、素子特性の劣化の影響を軽減できるので安定的で信頼性の高い識別番号を得ることができるという効果が得られる。
（１８）　第１インバータ回路の入力端子と出力端子とを選択的に短絡させる第１スイッチと、上記第１インバータ回路の出力端子が入力端子に接続された第２インバータ回路を設け、その出力信号を受けて増幅回路で増幅してなる識別要素の複数個を設け、上記第１スイッチがオン状態のときの各識別要素からの出力信号により識別番号を生成する識別番号回路を内蔵させることにより、簡単な構成で個々の半導体集チップの識別を可能にすることができるという効果が得られる。
（１９）　上記に加えて、上記インバータ回路をＣＭＯＳインバータ回路とし、上記第１スイッチがオン状態のときの第２インバータ回路の出力信号がその論理しきい値に対してハイレベル側なら上記増幅回路の出力信号を受けてロウレベルを形成し、上記第１スイッチがオン状態のときの第２インバータ回路の出力信号がその論理しきい値に対してロウレベル側なら上記増幅回路の出力信号を受けてハイレベルを形成し、上記第１スイッチがオフ状態にされるフィードバック動作のときに上記第１インバータ回路の入力端子に帰還させるラッチ回路を更に設けることにより、識別番号の再現性と経時変化に対する耐性を高めることができるという効果が得られる。
（２０）　上記に加えて、上記増幅回路を複数個のＣＭＯＳインバータ回路の縦列接続回路とし、上記第１インバータ回路、第２インバータ回路及び増幅回路を構成する各ＣＭＯＳインバータ回路の入力端子のそれぞれにハイレベル側の電圧を与える第３スイッチを設け、上記第１インバータ回路ないし上記増幅回路を構成する各インバータ回路列のそれぞれの相互接続点に第３スイッチを設け、上記識別番号回路が非動作状態のときは上記第２スイッチをオン状態にし、上記第３スイッチをオフ状態にし、上記第１スイッチをオン状態にされた識別情報の増幅時及び上記フィードバック動作時には上記第２スイッチをオフ状態にし、上記第３スイッチをオン状態にすることにより、識別番号の再現性と経時変化に対する耐性をいっそ高めることができるという効果が得られる。
（２１）　第１インバータ回路及び第２インバータ回路のそれぞれの入力端子と出力端子とを短絡させる第１スイッチを設け、上記第１インバータ回路の出力端子を第２インバータ回路の入力端子に接続させる第２スイッチを設け、上記第２インバータ回路の出力端子が入力端子に接続されてなる第３インバータ回路を含んだ増幅回路とを含む複数個の識別要素を用い、上記第１インバータ回路の第１スイッチをオン状態にし、第２インバータ回路の第１スイッチをオフ状態にし、上記第２スイッチをオン状態にしたたときの上記第３インバータ回路を含む上記増幅回路の出力信号により第１識別情報を得て、上記第２インバータ回路の第１スイッチをオン状態にして上記第２スイッチをオフ状態にしたときの上記第３インバータ回路を含む上記増幅回路の出力信号により第２識別情報を得るように識別番号を生成する識別番号回路を内蔵させることにより、回路の簡素化を図りつつ、個々の半導体集チップの識別を可能にすることができるという効果が得られる。
（２２）　上記に加えて、上記第１インバータ回路、第２インバータ回路からなる回路列を上記第１インバータ回路及び第２インバータ回路が対応して並ぶように複数回路列を設け、上記複数回路列の対応する第１スイッチには同じスイッチ制御信号が共通に供給し、複数回路列の上記第２インバータ回路の出力信号のいずれか１つを第３スイッチにより選択して上記増幅回路の初段回路を構成する第３インバータ回路の入力端子に接続することにより、多数の識別情報を効率的に得るようにすることができるという効果が得られる。
（２３）　上記に加えて、上記第１インバータ回路及び第２インバータ回路の入力端子には、入力信号を切断する第４スイッチと、ハイレベル側の電圧を供給する第５スイッチを設け、上記識別番号回路が非動作状態のときは上記第４スイッチをオフ状態にし、上記第５スイッチをオン状態にすることにより、識別番号の再現性と経時変化に対する耐性をいっそ高めることができるという効果が得られる。
（２４）　第１インバータ回路の入力端子と出力端子とを第１スイッチで短絡させ、上記第１インバータ回路の入力端子第２スイッチを設けてなる単位要素の複数個を上記第２スイッチを介して縦列形態にして識別要素列を構成し、上記識別要素列の最終段に対応された上記第１インバータ回路の出力端子を第２インバータ回路を含んだ増幅回路の入力端子に接続し、クロックを計数するバイナリカウンタの計数出力をデコードするデコーダを上記識別要素列の各第１インバータ回路の第１スイッチ及び第２スイッチに対応して設け、上記バイナリカウンタの計数出力に対応して上記識別要素列を初段回路から順に上記第１スイッチを順次オン状態に、第２スイッチは第１スイッチと相補的にオフ状態にして上記第３インバータ回路を含む上記増幅回路の出力信号により上記識別要素列の各第１インバータ回路に対応した複数の識別情報を得て識別番号を生成する識別番号回路を内蔵させることにより、回路の簡素化を図りつつ、個々の半導体集チップの識別を可能にすることができるという効果が得られる。
（２５）　第１インバータ回路の入力端子と出力端子とを第１スイッチで短絡させ、上記第１インバータ回路の入力端子に第２スイッチを設けてなる単位要素の複数個を上記第２スイッチを介して縦列形態にして識別要素列を構成し、上記識別要素列の最終段に対応された上記第１インバータ回路の出力端子を第２インバータ回路を含んだ増幅回路の入力端子に接続し、上記識別要素列の各第１インバータ回路の第１スイッチ及び第２スイッチに対応したシフトビットを有するシフトレジスタを設け、上記シフトレジスタのシフト動作に対応し、上記識別要素列を初段回路から順に上記第１スイッチを順次オン状態に、第２スイッチは第１スイッチと相補的にオフ状態にして上記第３インバータ回路を含む上記増幅回路の出力信号により上記識別要素列の各第１インバータ回路に対応した複数の識別情報を得て識別番号を生成する識別番号回路を内蔵させることにより、回路の簡素化を図りつつ、個々の半導体集チップの識別を可能にすることができるという効果が得られる。
（２６）　第１インバータ回路の入力端子と出力端子とを選択的に短絡させる第１スイッチと、上記第１インバータ回路の出力端子が入力端子に接続された第２インバータ回路を設け、その出力信号を受けて増幅回路で増幅してなる識別要素の複数個を設け、上記第１スイッチがオン状態のときの各識別要素からの出力信号により識別番号を生成する識別番号回路を内蔵させることにより、簡単な構成で個々の半導体集積回路装置の識別を可能にすることができるという効果が得られる。
（２７）　第１インバータ回路の入力端子と出力端子とを第１スイッチで短絡させ、上記第１インバータ回路の入力端子に第２スイッチを設けてなる単位要素の複数個を上記第２スイッチを介して縦列形態にして識別要素列を構成し、上記識別要素列の最終段に対応された上記第１インバータ回路の出力端子を第２インバータ回路を含んだ増幅回路の入力端子に接続し、クロックを計数するバイナリカウンタの計数出力をデコードするデコーダを上記識別要素列の各第１インバータ回路の第１スイッチ及び第２スイッチに対応して設け、上記バイナリカウンタの計数出力に対応して上記識別要素列を初段回路から順に上記第１スイッチを順次オン状態に、第２スイッチは第１スイッチと相補的にオフ状態にして上記第３インバータ回路を含む上記増幅回路の出力信号により上記識別要素列の各第１インバータ回路に対応した複数の識別情報を得て識別番号を生成する識別番号回路を内蔵させることにより、回路の簡素化を図りつつ、個々の半導体集積回路装置の識別を可能にすることができるという効果が得られる。
（２８）　第１インバータ回路の入力端子と出力端子とを第１スイッチで短絡させ、上記第１インバータ回路の入力端子第２スイッチを設けてなる単位要素の複数個を上記第２スイッチを介して縦列形態にして識別要素列を構成し、上記識別要素列の最終段に対応された上記第１インバータ回路の出力端子を第２インバータ回路を含んだ増幅回路の入力端子に接続し、上記識別要素列の各第１インバータ回路の第１スイッチ及び第２スイッチに対応したシフトビットを有するシフトレジスタを設け、上記シフトレジスタのシフト動作に対応し、上記識別要素列を初段回路から順に上記第１スイッチを順次オン状態に、第２スイッチは第１スイッチと相補的にオフ状態にして上記第３インバータ回路を含む上記増幅回路の出力信号により上記識別要素列の各第１インバータ回路に対応した複数の識別情報を得て識別番号を生成する識別番号回路を内蔵させることにより、回路の簡素化を図りつつ、個々の半導体集積回路装置の識別を可能にすることができるという効果が得られる。
（２９）　上記に加えて、ＪＴＡＧ規格に適合されたテスト回路を更に備え、上記識別番号回路で生成された識別番号を上記ＪＴＡＧ規格に適合されたインターフェイスを介して出力させることにより、テスト回路の流用によって回路の簡素化が可能になるという効果が得られる。
（３０）　上記に加えて、上記単位要素、第１スイッチ及び第２スイッチを含んだ識別番号回路は、ソフトＩＰ技術を用いて回路設計及び回路レイアウトを行うようにすることにより、設計コストの低減が可能になるという効果が得られる。
（３１）　第１インバータ回路の入力端子と出力端子とを第１スイッチで短絡させ、上記第１インバータ回路の入力端子に第２スイッチを設けてなる単位要素の複数個を上記第２スイッチを介して縦列形態にして識別要素列を構成し、上記識別要素列の最終段に対応された上記第１インバータ回路の出力端子を第２インバータ回路を含んだ増幅回路の入力端子に接続し、上記識別要素列の各第１インバータ回路の第１スイッチ及び第２スイッチに対応したシフトビットを有するシフトレジスタを設け、上記シフトレジスタのシフト動作に対応し、上記識別要素列を初段回路から順に上記第１スイッチを順次オン状態に、第２スイッチは第１スイッチと相補的にオフ状態にして上記第３インバータ回路を含む上記増幅回路の出力信号により上記識別要素列の各第１インバータ回路に対応した複数の識別情報を得て識別番号を生成する識別番号回路をソフトＩＰ技術を用いて回路設計及び回路レイアウトが行うようにすることにより、半導体集積回路装置の製造コストの低減が可能になるという効果が得られる。
以上本発明者よりなされた発明を実施例に基づき具体的に説明したが、本願発明は前記実施例に限定されるものではなく、その要旨を逸脱しない範囲で種々変更可能であることはいうまでもない。例えば、半導体集積回路装置の製造工程の過程で形成される同一の形態からなる複数の識別要素は、電気的に信号を読み出すものでは半導体集積回路装置に同じ抵抗値になるような抵抗素子や同じ容量値になるようなキャパシタを複数個成形し、その抵抗値や容量値のプロセスバラツキを電流又は電圧の形態で取り出して、識別番号として利用するものであってもよい。
また、半導体集積回路装置のリードの幅あるいはピッチ幅の他に、半導体パッケージ等の表面に同じ長さ又は幅にされた複数の直線を印刷又は刻印し、その幅又はピッチの幅のバラツキを利用するもの等種々の実施形態をとることができる。
上記に例示の抵抗素子は、実施例のＣＭＯＳ構成のような比較的複雑な製造プロセスを要さないでも実施できる。抵抗素子としては、半導体集積回路技術によって構成されるポリシリコン抵抗や、単結晶シリコンに導電型決定不純物を周知のイオンインプランテーション法のような方法によって導入することによって構成するいわゆる拡散抵抗のような半導体抵抗や、金属配線層と同質の金属層からなる金属抵抗を検討することができる。それら抵抗の中では、拡散抵抗は、適切な抵抗値に設定することが容易である点、抵抗値の経時変化が比較的小さい点から、特性バラツキに応じた特定情報を得るために好適である。
抵抗バラツキに対応する特定情報は、例えば、所定のバイアス電流をその時々に対比すべき２つの抵抗素子に流し、その時に２つの抵抗に発生する電圧差を判別して行くような抵抗−電圧変換及び比較判定の技術によって形成することや、複数の抵抗素子によって抵抗ブリッジを構成し、その抵抗ブリッジの出力を判別する技術によって形成することが可能である。抵抗素子に対応する特性情報は、また、上のような技術以外に、抵抗素子を抵抗−電流変換素子として利用し、変換された電流を比較判定する技術によって形成することも可能である。更には、抵抗素子を発振回路の発振周波数決定素子や遅延回路の遅延時間決定素子の一部とすることによって、抵抗素子の特性バラツキを周波数情報や遅延時間情報として利用することも可能である。
抵抗素子を、インバータを構成する信号入力ＭＯＳＦＥＴに対する負荷素子とするような場合には、特性バラツキに応ずる情報は、抵抗素子の特性バラツキと信号入力ＭＯＳＦＥＴの特性バラツキとの両方を反映したものとなる。
抵抗バラツキに対応する特定情報は、必ずしも半導体集積回路装置内のみで形成する必要は無い。必要ならば、半導体集積回路装置を、適宜に特定情報形成モードに移行可能な構成にしておき、そのモードの元で、半導体集積回路装置内の複数の抵抗素子を、半導体集積回路装置に設定されている信号入出力端子のような既存の外部端子にスイッチ的に切換え結合に結合させることもできる。この場合には、抵抗素子の特性バラツキに対応する特定情報は、かかる外部端子に結合する半導体集積回路装置外の回路装置によって形成される。この場合には半導体集積回路装置内の回路素子数の増大を抑制することが出来、また半導体集積回路装置の既存の端子の利用によって、その外部端子数の抑制を図ることもできる。
複数の同じ構成の回路相互、あるいはＭＯＳＦＥＴのような回路素子のリーク電流も特性バラツキを恒久的に維持するものとして経験的に把握される。リーク電流レベルは、抵抗素子の特性バラツキと同様に、電流電圧変換と電圧比較によって検出可能である。リーク電流を形成するものは、上のように互いに同じ構成の回路であっても良いし、ゲート・ソース間が接続されたようなＭＯＳＦＥＴであっても良い。
特定情報のためのリーク電流源の好適なものとしては、半導体集積回路装置の信号出力外部端子もしくは信号入出力外部端子につながる信号出力バッファ回路を掲げることができる。かかる種の信号出力バッファは、それを構成するＭＯＳＦＥＴのような回路素子が比較的大きいサイズとされ、比較的大きいリーク電流を形成することが少なくなく、その測定が比較的容易であるからであり、また既存の外部端子をそのまま利用できるからである。
半導体集積回路装置の外部信号入力端子につながる半導体集積回路装置内の入力保護ダイオードのような素子の耐圧特性も、ミクロ的なバラツキに対応する前述のような特定情報の源とすることができる。半導体集積回路装置の複数の外部端子が、電子システムにおける比較的少ないビット数のバスラインを構成する場合であっても、前述の実施定のような総当り比較の手法によって、著しく多数のものに対して適切に識別可能な情報を形成することが可能である。
半導体集積回路装置の外部端子に結合される半導体集積回路装置内のＭＯＳトランジスタのドレイン接合容量のような容量は、ミクロ的なバラツキを持つ。よってそれもまたバラツキに対応する前述のような特定情報の源とすることができる。
ダイナミック型メモリにおける情報保持時間もミクロ的なバラツキを示す。この場合、ダイナミック型メモリに、特別の構成を付加しないでも、すなわち、固有の識別情報形成のための構成を設定しなくても、複数のメモリアドレスの内の特定の複数のメモリアドレスにおける複数のメモリセルの情報保持時間を計測し、その計測結果に基づいて特定情報とすることが可能である。
マルチチップモジュールのように共通基板に、複数の半導体チップが設けられる場合、個々の半導体チップに固有の識別回路を設定しておき、個々の半導体チップからの固有の識別情報を共通の基板を介して取り出せるようにすることも可能である。個々の半導体チップの固有の識別情報を読み出すために共通基板に必要となる端子の数に制約が有るときには、それぞれの半導体チップにチップ選択制御回路とともに固有の識別情報のための並列−直列変換回路を設定しても良い。この時には、各半導体チップにおける固有の識別情報は、そのチップの選択状態において、並列−直列変換回路によって直列化された上で、各半導体チップから出力され、共通基板を介して読み出される。第３３図のような意味でのプログラム専用チップが設けられる場合には、かかるプログラム専用チップは、共通基板上の異なった種類の複数の半導体チップに対応可能なように構成されても良い。
産業上の利用可能性
この発明は、半導体集積回路装置又は半導体チップに固有の識別情報を割り当てて、個々の半導体集積回路装置又は半導体チップの識別を行うようにした半導体集積回路装置又は半導体チップの識別方法と半導体集積回路装置の製造方法、半導体集積回路装置及び半導体チップに広く利用することができる。
【図面の簡単な説明】
第１図は、この発明に係る識別番号発生回路の一実施例を示す基本的回路図であり、
第２図は、この発明に係る識別番号発生回路の他の一実施例を示す基本的回路図であり、
第３図は、この発明に係る識別番号発生回路の他の一実施例を示す基本的回路図であり、
第４図は、前記第３図の識別番号発生回路の動作の説明図であり、
第５図は、この発明に係る識別番号発生回路の他の一実施例を示す基本的回路図であり、
第６図は、前記第５図の実施例回路を説明するための等価回路図であり、
第７図は、前記第５図の実施例に対応した具体的一実施例を示す回路図であり、
第８図は、前記第７図の実施例回路の動作を説明するためのタイミングチャート図であり、
第９図は、前記第７図の実施例回路の動作の説明図であり、
第１０図は　この発明に係る識別番号発生回路の核になるＣＭＯＳインバータ回路とスイッチＭＯＳＦＥＴからなる単位回路の一実施例を示す変形例であり、
第１１図は、この発明に係る識別番号発生回路の核になるＣＭＯＳインバータ回路とスイッチＭＯＳＦＥＴからなる単位回路の他の一実施例を示す変形例であり、
第１２図は、この発明に係る識別番号発生回路の核になるＣＭＯＳインバータ回路とスイッチＭＯＳＦＥＴからなる単位回路の他の一実施例を示す変形例であり、
第１３図は、この発明に係る識別番号発生回路の核になるＣＭＯＳインバータ回路とスイッチＭＯＳＦＥＴからなる単位回路の他の一実施例を示す変形例であり、
第１４図は、この発明に係る識別番号発生回路の核になるＣＭＯＳインバータ回路とスイッチＭＯＳＦＥＴからなる単位回路の他の一実施例を示す変形例であり、
第１５図は、この発明に係る識別番号発生回路の核になるＣＭＯＳインバータ回路とスイッチＭＯＳＦＥＴからなる単位回路の他の一実施例を示す変形例であり、
第１６図は、この発明に係る識別番号発生回路に用いられるＣＭＯＳインバータ回路の一実施例を示す回路図であり、
第１７図は、この発明に係る識別番号発生回路の他の一実施例を示す回路図であり、
第１８図は、前記第１７図に示した実施例回路の動作を説明するための波形図であり、
第１９図は、この発明に係る識別番号発生回路の他の一実施例を示すブロック図であり、
第２０図は、この発明に係る識別番号発生回路の他の一実施例を示す回路図であり、
第２１図は、この発明に係る半導体集積回路装置の一実施例を示す概略ブロック図であり、
第２２図は、この発明に係る半導体集積回路装置の一実施例を示す素子レイアウト図であり、
第２３図は、前記第２２図に対応した等価回路図であり、
第２４図は、この発明をダイナミック型ＲＡＭに適用した場合の一実施例を示すブロック図であり、
第２５図は、この発明に係る識別番号発生回路を用いた半導体集積回路装置の一実施例を示す概略構成図であり、
第２６図は、この発明に係る識別番号の識別アルゴリズムを説明する説明図であり、
第２７図は、この発明に係る識別番号の識別アルゴリズムを説明する説明図であり、
第２８図は、この発明に係る半導体集積回路装置の識別システムにおける照合アルゴリズムの登録方法の一実施例を示す構成図であり、
第２９図は、この発明に係る半導体集積回路装置の識別システムにおける照合アルゴリズムの照合方法の一実施例を示す構成図であり、
第３０図は、前記第２９図の比較方法の一例を示す説明図であり、
第３１図は、ＣＭＯＳインバータ回路の論理しきい値の順位を用いた場合の比較方法の一例を示す説明図であり、
第３２図は、ＣＭＯＳインバータ回路の論理しきい値の順位を用いた場合の比較方法の一例を示す説明図であり、
第３３図は、この発明が適用される半導体集積回路装置の一実施例を示す構成図であり、
第３４図は、この発明が適用されるマルチチップモジュールの一実施例を示すブロック図であり、
第３５図は、前記図３４のプログラム専用チップの一実施例を示すブロック図であり、
第３６図は、本願に係る識別番号発生回路を搭載した半導体集積回路装置の一実施例の製造工程を説明するための構成図であり、
第３７図は、本願に係る識別番号発生回路を搭載した半導体集積回路装置を回路実装ボードに組み立てる場合の一実施例の製造工程を説明するための構成図であり、
第３８図は、本願に係る識別番号発生回路を搭載した半導体集積回路装置の他の一実施例の製造工程を説明するための構成図であり、
第３９図は、この発明に係る識別番号発生回路が設けられる特定用途向けＬＳＩの一例を示すブロック図であり、
第４０図は、この発明に係るＣＭＯＳインバータの論理しきい値のバラツキを乱数発生器に応用した実施例を示す回路図であり、
第４１図は、企業間の電子部品調達市場における不正行為や様々なトラブルを軽減することを目的とした、本願発明に係るチップ識別番号発生回路の利用例を説明するための構成図であり、
第４２図は、この発明に係る半導体集積回路装置の他の一実施例を示す模試的平面図であり、
第４３図は、この発明に係る識別番号発生回路の他の一実施例を示す基本的回路図であり、
第４４図は、この発明に係る識別番号発生回路の他の一実施例を示す回路図であり、
第４５図は、この発明に係る識別番号発生回路の一実施例を示す具体的回路図であり、
第４６図は、この発明に係る識別番号発生回路の更に他の一実施例を示す具体的回路図であり、
第４７図は、前記第４６図の実施例回路の動作を説明するためのタイミング図であり、
第４８図は、前記図４６の実施例に用いられる単位回路の他の一実施例を示す回路図であり、
第４９図は、この発明に係る識別番号発生回路の更に他の一実施例を示す回路図であり、
第５０図は、この発明に係る識別番号発生回路の更に他の一実施例を示す回路図であり、
第５１図は、この発明が適用される半導体集積回路装置又は半導体チップの一実施例を示す回路レイアウト図であり、
第５２図は、上記Ｉ／Ｏセルの標準的な一実施例を示すブロック図であり、
第５３図は、この発明に係る半導体集積回路装置又は半導体チップに設けられるＩ／Ｏセルの一実施例を示す回路レイアウト図であり、
第５４図は、この発明に係る半導体集積回路装置又は半導体チップに設けられる出力バッファ回路の一実施例を示す回路図であり、
第５５図は、この発明に係る半導体集積回路装置又は半導体チップに設けられる出力バッファ回路の他の一実施例を示す回路図であり、
第５６図は、この発明に係る半導体集積回路装置の一実施例を示す概略構成図であり、
第５７図は、この発明に係る半導体集積回路装置の基本的なＪＴＡＧセルの一実施例を示すブロック図であり、
第５８図は、この発明に係る半導体集積回路装置のバウンダリスキャンレジスタのシフト動作を利用した識別番号のシリアル出力動作の一実施例を説明するための構成図であり、
第５９図は、この発明に係る半導体集積回路装置のバウンダリスキャンレジスタのシフト動作を利用した識別番号のシリアル出力動作の他の一実施例を説明するための構成図であり、
第６０図は、この発明に係る半導体集積回路装置のバウンダリスキャンレジスタのシフト動作を利用した識別番号のシリアル出力動作の他の一実施例を説明するための構成図であり、
第６１図は、この発明に係る半導体集積回路装置のバウンダリスキャンレジスタのシフト動作を利用した識別番号のシリアル出力動作の他の一実施例を説明するための構成図であり、
第６２図は、この発明に係る識別番号発生回路の更に他の一実施例を示す回路図であり、
第６３図は、この発明に係る識別番号の説明図であり、
第６４図は、この発明に係る識別番号の説明図であり、
第６５図は、この発明に係る識別番号発生回路で生成された識別番号の高速識別番号照合（検索）アルゴリズムの一実施例を説明するためのフローチャート図であり、
第６６図は、第６５図の実施例に対応した構成図であり、
第６７図は、この発明に係る識別番号発生回路を組み込んだ半導体チップの回路設計方法の一実施例を示すフローチャート図であり、
第６８図は、この発明に係る識別番号発生回路を内蔵したＬＳＩ設計方法の一実施例を示すフローチャート図であり、
第６９図は、この発明に係る識別番号発生回路内蔵の半導体チップを用いた半導体集積回路装置の製造方法の一実施例のフローチャート図が示されている。
第７０図は、この発明に係る識別番号発生回路を搭載した半導体チップを用いた半導体集積回路装置の組み立て工程の一実施例を示すフローチャート図であり、
第７１図は、この発明に係る識別番号発生回路のビット数を減少させる方法の一実施例を示す構成図であり、
第７２図は、この発明に係る識別番号発生回路のビット数を減少させる方法の一実施例を示す構成図であり、
第７３図は、この発明に係る半導体集積回路装置に搭載された識別番号発生回路を利用した検査方法を説明するための構成図であり、
第７４図は、この発明に係る半導体集積回路装置に搭載された識別番号発生回路を利用した検査方法を説明するための構成図であり、
第７５図は、この発明に係る半導体集積回路装置に搭載された識別番号発生回路を利用し各検査工程で半導体チップ毎の特性データの相関を管理する方法を説明するための構成図であり、
第７６図は、この発明に係る半導体集積回路装置に搭載された識別番号発生回路を利用し前工程でウェハを自動で管理する方法を説明するための構成図であり、
第７７図は、この発明に係る半導体集積回路装置に搭載された識別番号発生回路の識別番号の格納・検索方法を説明するための構成図であり、
第７８図は、この発明に係る半導体集積回路装置に搭載された識別番号発生回路の識別番号の格納・検索方法の他の例を説明するための構成図であり、
第７９図は、この発明に係る識別番号発生回路を利用した半導体集積回路装置の救済方法の一実施例を示す構成図であり、
第８０図は、この発明に係る識別番号発生回路を搭載した半導体集積回路装置の一実施例を示すレイアウト図であり、
第８１図は，第８０図のレイアウト図の部分拡大レイアウト図であり、
第８２図は、この発明に係る識別番号発生回路を搭載した半導体集積回路装置の他の一実施例を示すレイアウト図であり、
第８３図は、第８１図のレイアウトに対応する回路図であり、
第８４図は、この発明に係る識別番号発生回路を搭載した半導体集積回路装置の更に他の一実施例を示す構成図であり、
第８５図は、第８４図の実施例を構成する半導体集積回路装置の部分平面パターン図であり、
第８６図は、第８４図の実施例を構成する半導体集積回路装置の他の部分平面パターン図であり、
第８７図は、この発明に係る識別番号発生回路を搭載した半導体集積回路装置の一実施例を示す回路図である。Technical field
The present invention relates to a method for identifying a semiconductor integrated circuit device, a method for manufacturing a semiconductor integrated circuit device, a semiconductor integrated circuit device, and a semiconductor chip. The present invention relates to a technology for identifying a device or a semiconductor chip.
Background art
If the semiconductor integrated circuit device is provided with unique identification information, various desired use actions can be performed based on the identification information. If unique identification information can be set in a semiconductor integrated circuit device at such a level as one by one, a description will be given after the present inventors have clarified the use of the unique identification information. To provide new manufacturing methods and product management techniques.
In the case where a defect occurs in a stage such as the actual use stage of a semiconductor integrated circuit device, if it is possible to obtain unique identification information from the semiconductor integrated circuit device, it is easy to pursue the factor that caused the defect. I do. For example, a semiconductor manufacturer can grasp information such as a manufacturing time, a manufacturing line, a manufacturing lot, an inspection history, design information, and the like based on identification information unique to a semiconductor integrated circuit device. As a result, it is easy to pursue the cause of the failure, and the countermeasure is also easy.
Marking applied to a package constituting a semiconductor integrated circuit device by an ink printing method or a laser engraving method can be regarded as a kind of identification information. Although such a type of marking is mainly based on the product type name of the semiconductor integrated circuit device, a code display of a manufacturing time such as a year or a week may be included together with the product type name. However, in such a type of marking display, depending on the amount of information that can be displayed thereby, such as individual semiconductor integrated circuit devices that are manufactured in large quantities as industrial products or manufactured over a long period of time, It is difficult to set unique identification information at the level.
It is possible to assume that a programmable element such as a fuse element is set for a semiconductor chip included in a semiconductor integrated circuit device and unique identification information is given to the programmable element. However, such a conceivable technique is that if the original semiconductor integrated circuit device does not require a program element, a new manufacturing process is required for the programmable element, and the semiconductor integrated circuit device However, there is a problem that the manufacturing process becomes complicated and the price rises. If the semiconductor integrated circuit device originally has programmable elements, there is no new manufacturing process complexity. Even in this case, it is necessary to add or change a manufacturing process for writing unique identification information to the programmable element.
In a known technique called a silicon signature, a product type name and unique information are written in a semiconductor integrated circuit device in a form that can be electrically read. However, in such a technique, it is necessary to add or change a manufacturing process for writing the information as described above.
The inventor of the present invention has conducted investigations after carrying out the present invention and found that it is considered to be related to the present invention, which will be described later, in JP-A-6-196435, JP-A-10-055939, and JP-A-11-214274. And Japanese Patent Application Laid-Open Nos. 7-335509 and 7-050233. It is recognized that any of the inventions described in these publications requires a special manufacturing process in order to write unique identification information to each chip. However, in these publications, there is no description about a method of identifying a semiconductor integrated circuit device which does not need to add or change a special manufacturing process unlike the present invention described later.
Accordingly, it is an object of the present invention to provide a semiconductor integrated circuit device or a semiconductor chip capable of identifying individual semiconductor integrated circuit devices or semiconductor chips with a simple configuration and a method for identifying the same. Another object of the present invention is to provide a semiconductor integrated circuit device capable of identifying individual semiconductor integrated circuit devices or semiconductor chips with high reliability. Another object of the present invention is to provide a reasonable method for manufacturing a semiconductor integrated circuit device. The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
Disclosure of the invention
The outline of a representative one of the inventions disclosed in the present application will be briefly described as follows. That is, a plurality of identification elements having the same form are formed in the course of the manufacturing process of the semiconductor integrated circuit device, and the semiconductor integrated circuit device is configured based on the mutual magnitude relationship of physical quantities corresponding to the process variations of the plurality of identification elements. Alternatively, it is used as unique identification information of the semiconductor chip.
BEST MODE FOR CARRYING OUT THE INVENTION
The present invention will be described in more detail with reference to the accompanying drawings.
FIG. 1 is a basic circuit diagram of an embodiment of an identification number generating circuit according to the present invention. The CMOS inverter circuits INV1 to INV4 are configured to have the same characteristics within a practically controllable range in designing and manufacturing a semiconductor integrated circuit device. A specific configuration suitable for the present invention for making a plurality of inverters have the same characteristics as each other will be better understood by referring to FIG. 22 and the description thereof. Therefore, techniques for obtaining the same characteristics will be schematically described below.
It will be understood that the characteristics of a CMOS inverter circuit are roughly determined by the relative conductance of the P-channel MOSFET and the N-channel MOSFET constituting the circuit. From this point of view, it can be understood that a CMOS inverter having the same characteristics can be constituted by MOSFETs having the same ratio W / L between the channel width W and the channel length L but different sizes. However, the influence on the electrical characteristics due to the manufacturing variation of the semiconductor integrated circuit device is different for elements of different sizes.
In the embodiment, each of the plurality of CMOS inverters INV1 to INV4 preferably has the same structure and the same size of the elements constituting each other, that is, the P-channel MOSFETs and the N-channel MOSFETs. It is composed with. Needless to say, these elements are manufactured in accordance with the feature of the semiconductor integrated circuit device that the same elements are collectively manufactured under the same process. As a result, the plurality of CMOS inverters INV1 to INV4 are uniformly affected by manufacturing variations such as variations in processing dimensions in manufacturing the semiconductor integrated circuit device, variations in thickness of various layers, and variations in impurity concentration.
The output voltage of the CMOS inverter circuit whose input and output are short-circuited as shown in FIG. 1 reaches the logical threshold voltage. If all the CMOS inverter circuits have completely the same electrical characteristics, the potentials of the short-circuit nodes of the four inverter circuits INV1 to INV4 become equal. However, this is an ideal state, and there is a slight difference in characteristics in an actual semiconductor device, so that a difference occurs between the input / output short-circuit node potentials of the inverter circuits INV1 to INV4, that is, the logical threshold voltages.
As a cause of the variation of the logic threshold value of the CMOS inverter circuit, it may be considered that the variation of the MOS transistor characteristic is dominant. The causes of variations in MOS transistor characteristics include the gate width of the MOS transistor, the thickness of the gate insulating film, the concentration of conductivity determining impurities and their distribution, and the like. These variations can be divided into a macro part and a micro part. The macro part includes gate width variation among a plurality of wafers in the same lot.
In the present invention, a variation in a microscopic portion is mainly used, and a variation between elements arranged at relatively close positions is used. This is because such microscopic variations are observed as randomly occurring between elements relatively close to each other.
That is, it is considered that the variation of the logical threshold value of the inverter circuits INV1 to INV4 in FIG. 1 is also random. This variation in the logical threshold value is the basis of a solution to the problem to be solved by the present application, namely, "extracting the variation in the characteristic characteristics of the semiconductor element as unique identification information". When a CMOS inverter circuit is used, the variation in the logic threshold can be regarded as the variation of the N-channel type MOS transistor plus the variation of the P-channel type MOS transistor. As a result, the identification number or the identification information can be generated effectively.
In the embodiment shown in FIG. 1, the order of the magnitudes of the logical threshold values of the four inverter circuits INV1 to INV4 is determined. That is, the voltages (corresponding to the logical threshold values) of the short-circuited input / output nodes of the CMOS inverter circuits INV1 to INV4 are selected by the switch and sequentially input to the analog / digital converter ADC, and the quantized measurement is performed. The value (digital signal) is stored in a register, and the magnitude is compared by a digital comparator (not shown).
That is, the digitized logical threshold values of the four CMOS inverter circuits INV1 to INV4 stored in the registers are compared by a comparator or the like, and are arranged in ascending or reverse order. If a processor such as a CPU is mounted on the semiconductor integrated circuit device on which the identification number generating circuit is formed, the magnitude comparison can be performed by software using the processor.
For example, digital values are stored corresponding to the numbers 1 to 4 assigned to the CMOS inverter circuits INV1 to INV4, and the order is determined as 1-3-2-4 by comparing the magnitudes thereof. The identification information is generated based on -3-2-4.
FIG. 2 is a basic circuit diagram of another embodiment of the identification number generating circuit according to the present invention. In this embodiment, an analog comparator COMP is used. In this embodiment, the switches sequentially supply voltages corresponding to the logical threshold values of the CMOS inverter circuits INV1 to INV4 one by one, and compare the voltages with the reference potential of the comparator COMP. This reference voltage is changed stepwise, and the detection level when the comparison result of the comparator changes from low level to high level is stored in a register, and the magnitudes of the logic threshold values of the CMOS inverter circuits INV1 to INV4 are compared. It is a method. In other words, the one in which the reference voltage is the lowest voltage and the output signal of the comparator changes from the low level to the high level is regarded as having the smallest logical threshold value.
In the identification number generation circuits shown in FIGS. 1 and 2, circuits such as a high-resolution analog / digital converter ADC, a comparator COMP, and a staircase voltage generator, that is, circuits not included in digital circuits and logic circuits Is necessary.
FIG. 3 is a basic circuit diagram of another embodiment of the identification number generating circuit according to the present invention. In this embodiment, it is considered that implementation in a form in which a kind of cell substantially constituting a digital circuit or a logic circuit is used can be easily performed. In this embodiment, the logic thresholds of the four CMOS inverter circuits INV1 to INV4 are combined two by two and compared by the comparator COMP. Comparison of the logic threshold values of these CMOS inverter circuits INV1 to INV4 is performed in a round robin (league) format.
FIG. 4 is an explanatory diagram of the operation of the identification number generating circuit of FIG. 3 and shows an example of the brute force comparison result. FIGS. 4 (A) and 4 (B) show a so-called fighting table in which the switches Y1 to Y4 and the switches X1 to X4 are turned on one by one, and are connected to the non-inverting input terminal (+) of the comparator COMP. From the short-circuit node potential (ie, the logical threshold voltage) of the CMOS inverter circuit selected by the switch (Y), the CMOS inverter circuit selected by the switch (X) connected to the inverting input terminal (-) of the comparator COMP. If the result of subtracting the short-circuit node potential is plus (high level), the symbol “+” is entered in the figure, and if the result is minus (low level), the symbol “−” is entered. "*" Is invalid because it is a self match (no match).
Referring to FIG. 4 (A), Y1 has three "+", that is, all wins. Next, Y2 is 2, Y3 is 1, and Y4 is 0 (all defeats). That is, since the order of the magnitude of the logic threshold (VLT) of the CMOS inverter circuit can be determined by the number of “+”, the order is VLT1 (logic threshold of INV1) −VLT2−VLT3−VLT4.
FIG. 4 (B) shows another example. Here, it is assumed that there is a clear difference between the logic threshold values of the respective CMOS inverter circuits. That is, in an actual game, the number of draws and the number of wins may be the same. The draw is indicated by (=). With such a draw (=), Y1 and Y2 have the same rank, and Y3 and Y4 also have the same rank. Further, in this embodiment, 16 comparisons (games) are performed. However, the minimum number of round-robin games by n teams is sufficient to be n (n-1) / 2. Good.
Although the embodiment of FIG. 3 is composed of one comparator and two selection circuits, the configuration is relatively simple as compared with the embodiment of FIG. 1 or FIG. Since such an analog circuit is used, it may be difficult to form it in a semiconductor integrated circuit device such as a gate array or a logic ASIC.
FIG. 5 is a basic circuit diagram of another embodiment of the identification number generating circuit according to the present invention. This embodiment does not use any analog circuits as in the embodiments shown in FIGS. 1 to 3, but shows a basic circuit composed of only a CMOS logic circuit and a MOSFET switch.
The CMOS inverter circuits INV1 to 1NV4 in FIG. Each of the CMOS inverter circuits INV1 to INV4 is provided with four switches. Switches A (A1 to A4) and B (B1 to B4) open and close simultaneously in conjunction with each other. The switches C (C1 to C4) and D (D1 to D4) also open and close in conjunction with each other.
FIG. 6 shows an equivalent circuit corresponding to the open / closed state of the switch for explaining the circuit of the embodiment of FIG. In FIG. 5, switches A1, B1, C2, and D2 are closed (ON state). The input / output of the CMOS inverter circuit INV1 is short-circuited by the switch B1, and the short-circuit node voltage is supplied to the common node P by the switch A1. Further, the potential of the common node P is applied to the input of the CMOS inverter circuit INV2 by the switch C2, and the output of the CMOS inverter circuit INV2 is supplied to the common node PP by the switch D2. The amplifier circuits AMP1 and AMP2 are configured by CMOS inverter circuits having the same shape as INV1 to INV4.
In the equivalent circuit of FIG. 6, the input and output of the CMOS inverter circuit INV1 are short-circuited by the on-switch B1, and the potential of the common node P becomes the logical threshold value of the CMOS inverter circuit INV1 by the on-switch A1. The input of the CMOS inverter circuit INV2 is connected to a common node P by an on-switch C2. If the CMOS inverter circuits INV1 and 1NV2 have completely the same electrical characteristics, the potential of the common node PP to which the output of the CMOS inverter circuit INV2 is connected becomes equal to that of the common node P. Similarly, the output node potentials of the amplifier circuits AMP1 and AMP2 become equal. That is, the inputs and outputs of the four inverters are all equal to the logical threshold voltage of the CMOS inverter circuit INV1. However, this is an ideal state, and there is a slight difference in characteristics in an actual semiconductor element, so that a difference occurs in the potential of each node.
For example, the relationship between the logical threshold value VLT1 of the CMOS inverter circuit INV1 and the logical threshold value VLT2 of the CMOS inverter circuit INV2 is as follows.
When VLT1 <VLT2, the potential of the common node PP> the potential of the common node P. Conversely, when VLT1> VLT2, the potential of the common node PP <the potential of the common node P.
The CMOS inverter circuit is also a high gain inverting amplifier, the gain of which changes at the operating point, and the maximum gain is obtained when the input potential is near the logic threshold value of the CMOS inverter circuit. Generally, the inversion gain near the logic threshold of a CMOS inverter circuit is several tens to one hundred times.
Therefore, the difference between the logic threshold values of the CMOS inverter circuits INV1 and INV2 in FIG. 6 is amplified by the CMOS inverter circuit INV2 at the subsequent stage. That is, the logical threshold voltage generated by the preceding CMOS inverter circuit is compared with the logical threshold voltage of the latter CMOS inverter circuit as a reference voltage, and the magnitude comparison and the amplification operation are performed.
Furthermore, it is also amplified by the amplifier circuits AMP2 and AMP3, and the difference between the logic threshold values of the CMOS inverter circuits INV1 and INV2 is amplified tens of thousands by the CMOS inverter circuit INV2 and the amplifier circuits AMP1 and AMP2. Finally, at the node Q, a CMOS power supply voltage amplitude signal can be obtained. That is, the magnitude comparison result (positive / negative sign) of the logical threshold values of the two CMOS inverter circuits INV1 and INV2 can be detected by the CMOS amplitude signal.
By changing the combination of opening and closing of the switches as shown in FIG. 6, it is possible to easily compare all the CMOS inverter circuits INV1 to INV4 and obtain the result shown in FIG. it can. Thus, the circuit of this embodiment is suitable for comparing the logic threshold of the CMOS inverter circuit.
That is, depending on the combination of the CMOS inverter circuit and the switch, one CMOS inverter circuit may be used as a source of a logical threshold voltage, or may be used as a determination circuit for determining a logical threshold voltage generated by another CMOS inverter circuit. Since it is used, no special comparator is required, and the circuit configuration can be greatly simplified. In addition, since it is composed of all MOSFETs including a CMOS inverter circuit that performs a switching operation, there is no particular difficulty when the semiconductor device is mounted on a semiconductor integrated circuit device such as a gate array or a logic ASIC.
FIG. 7 is a circuit diagram of a specific embodiment corresponding to the embodiment of FIG. The CMOS inverter circuits INV1 to INV4 and the amplifier circuits AMP1 and AMP2 are CMOS inverter circuits having the same shape. In this embodiment, an N-channel MOSFET is used as the switch. Further, a binary counter and a decoder are provided for forming control signals Y1 to Y4 and X1 to X4 of these switches.
The CMOS inverter circuit INV1 will be described below as an example. The control signal X1 is supplied to the gates of a switch MOSFET that short-circuits the input and output of the CMOS inverter circuit INV1 and a switch MOSFET that connects the common node P and the input. The control signal Y1 is supplied to the gates of the switch MOSFET connecting the input of the CMOS inverter circuit INV1 and the common node P and the switch MOSFET connecting the output and the common node PP. Hereinafter, similarly, in each of the CMOS inverter circuits INV2 to INV4, the control signals X2 to X4 and the control signals Y2 to Y4 are supplied to the gates of the corresponding switch MOSFETs.
The binary counter is a 4-bit binary counter that is reset by a reset signal RES and counts the number of pulses by supplying a clock signal CLK. The decoder outputs control signals Y1 to Y4 corresponding to the count output of lower 2 bits. Are formed, and control signals X1 to X4 are formed by the decoder corresponding to the count output of the upper two bits.
FIG. 8 is a timing chart for explaining the operation of the circuit of the embodiment shown in FIG. The reset signal RES is for initializing a binary counter. Here, all outputs of the binary counter are "1" during reset (RES = "H") and immediately after reset. Therefore, as for the output of the decoder, X4 and Y4 are active. At the first rising edge of the clock CLK after the reset is released, the binary counter advances (+1) and becomes all "0". Therefore, the output of the decoder has the control signals X1 and Y1 activated.
Thereafter, the output of the binary counter repeats progress (+1) at the rising timing of the clock signal CLK, and the decoder proceeds as shown in FIG. Of course, it goes without saying that the output of the binary counter returns to “0” again at the 17th rising of the clock signal CLK. However, in this embodiment, since necessary information can be extracted by 16 operations, the 17th and subsequent clock operations are not necessary.
After the reset is released, the counting operation of the binary counter proceeds at every rising of the clock signal CLK, and the information b1 to b16 appearing at the output node OUT each time is as shown in FIG. As described above, the difference between the logical threshold values of the CMOS inverter circuit is amplified by the amplifier circuits AMP1 and AMP2. When VLTQy−VLTQx> 0, the output terminal OUT outputs “H” (high level). , VLTQy−VLTQx <0, the output terminal OUT outputs “L” (low level).
In this way, the results of the four rounds of the CMOS inverter circuits INV1 to INV4 in the round robin battle can be directly used as the identification signals b1 to b16. Of the four CMOS inverter circuits INV1 to INV4 in the round robin battle b1 to b16 in the round robin battle, the self-competition one may be set to a high level or a low level specific level as described later. When the numbers 1 to 4 assigned to the four CMOS inverter circuits are replaced with 2-bit information and the information is arranged in descending order, for example, it is arranged as 1-2-3-4. It is possible to obtain identification information compressed to 1/2 like 8 bits.
FIG. 10 shows a modification of the embodiment of the unit circuit including the CMOS inverter circuit and the switch MOSFET, which is the core of the identification number generation circuit according to the present invention. In the circuit of FIG. 10, each of the four switch MOSFETs (A to D) of FIG. 5 is a CMOS pair type. That is, the N-channel MOSFET and the P-channel MOSFET are connected in parallel, and their gates are supplied with complementary signals X and X /.
When the CMOS switch is used in this manner, the voltage signal transmitted through the switch MOSFET is not limited by the threshold voltage, and therefore, the power supply voltage or the ground potential of the circuit and the above-described logical threshold voltage It is effective for a circuit operating at a low voltage such that a voltage difference or a difference voltage between a power supply voltage or a ground potential of the circuit and a voltage to be output to the common node PP is smaller than the threshold voltage of the switch MOSFET. .
FIG. 11 shows a modification of another embodiment of a unit circuit composed of a CMOS inverter circuit and a switch MOSFET, which is the core of the identification number generation circuit according to the present invention. In the circuit of FIG. 11, the position of the N-channel type switch MOSFET for supplying the input / output short-circuit potential of the CMOS inverter circuit to the common node P is changed. That is, the output side of the CMOS inverter circuit whose input and output are short-circuited and the common node P are connected.
FIG. 12 shows a modification of another embodiment of a unit circuit composed of a CMOS inverter circuit and a switch MOSFET, which is the core of the identification number generating circuit according to the present invention. In the circuit of FIG. 12, two P-channel MOSFETs connected in series between the input of the CMOS inverter circuit and the power supply voltage terminal are provided. Select signals X and Y are supplied to the gates of these P-channel MOSFETs. In this embodiment, when the CMOS inverter circuit is not selected, that is, when both the selection signals X and Y are not activated, the P-channel MOSFET is turned on and the input of the CMOS inverter circuit is set to a high level such as a power supply voltage. It is fixed to prevent a through current in the CMOS inverter circuit. In other words, when the input of the CMOS inverter circuit is set to a floating state, a large through current may flow between the N-channel MOSFET and the P-channel MOSFET of the CMOS inverter circuit due to an intermediate potential. belongs to.
FIG. 13 shows a modification of another embodiment of a unit circuit composed of a CMOS inverter circuit and a switch MOSFET, which is the core of the identification number generating circuit according to the present invention. In the circuit shown in FIG. 13, the switch MOSFET is changed from the N-channel MOSFET as in the above embodiment to the P-channel MOSFET, and the input of the CMOS inverter circuit is fixed at a low level by the N-channel MOSFET when inactive. is there. The selection signal applied to the gate of the N-channel MOSFET in this case is the inverted signal X / and Y /.
FIG. 14 shows a modification of another embodiment of the unit circuit composed of the CMOS inverter circuit and the switch MOSFET, which is the core of the identification number generation circuit according to the present invention. In the circuit shown in FIG. 14, the common node PP is undefined at the time of the above-mentioned self-match (no match), that is, the output of the CMOS inverter circuit is prevented in order to prevent the output from becoming “H” or “L” or unstable. Two N-channel MOSFETs connected in series between an input and the ground potential of the circuit are provided, and the input of the CMOS inverter circuit is fixed at a low level.
Select signals X and Y are supplied to the gates of these N-channel MOSFETs. As a result, during the self-match, the selection signals X and Y become high level, and the ground potential of the circuit is supplied to the input. The short-circuit switch provided between the input and the output of the CMOS inverter circuit is composed of a series circuit of an N-channel MOSFET receiving the selection signal X and a P-channel MOSFET receiving the selection signal Y. Thereby, the input and the output are not short-circuited in the self-match, and a high level corresponding to the fixed low level supplied to the input can be output. In the case of the non-selection, the input is fixed at a high level such as the power supply voltage as in the embodiment of FIG.
FIG. 15 shows a modification of still another embodiment of a unit circuit composed of a CMOS inverter circuit and a switch MOSFET, which is the core of the identification number generation circuit according to the present invention. In the circuit of FIG. 15, the common node PP is undefined at the time of the above-mentioned self-match (no match), that is, the output of the CMOS inverter circuit is prevented in order to prevent the output from becoming “H” or “L” or unstable. The input is fixed at a high level. In order to avoid a short circuit between the input and the output in the self-match in the same manner as described above, the short-circuit switch is composed of a series circuit of an N-channel MOSFET and a P-channel MOSFET as in the embodiment of FIG.
The purpose and effect of avoiding the indefinite level of the common node PP will be described later in detail. Each of the modifications shown in FIGS. 10 to 15 may be implemented in combination. For example, the N-channel type switch MOSFET shown in FIG. 14 may be replaced with a CMOS pair type.
The embodiment of FIGS. 14 and 15 can be used to embed fixed information in the self-match (*) portion of FIG. Originally, the self-competition part was indefinite, strictly speaking, because it was the result of comparing the logic threshold values of each CMOS inverter circuit and the amplifier circuit AMP, so that the information of that part could be ignored or diverted to another. There is no loss of ability. The input of the CMOS inverter circuits INV1 to INV4 is biased to the low level or the high level side by fixing the added series-connected N-channel MOSFET to the ground potential or the power supply voltage as shown in FIGS. The output of the match part can be set arbitrarily.
In recent years, a semiconductor integrated circuit device technology of a form in which a bare chip is mounted on a substrate such as a build-up substrate is also being developed, and in that case, it is no longer possible to specify a product or a shipment time from its appearance. Therefore, it becomes more necessary to insert a fixed number for specifying such a product or shipping time. In other words, in a system-on-a-chip (SOC), which will be described later, what is mounted on a base chip, what features are combined with individual chips, and what kind of chip is The management of single items, such as whether it is better to combine them, becomes more and more important, and the above-mentioned assignment of fixed numbers is useful.
FIG. 16 is a circuit diagram showing one embodiment of a CMOS inverter circuit used in the identification number generating circuit according to the present invention. In general, a CMOS inverter circuit has a P-channel MOSFET and an N-channel MOSFET connected in series between a power supply voltage and a ground potential of the circuit, and has a gate connected in common and used as an input. Can be configured as output. The CMOS inverter circuits INV1 to INV4 and the amplifier circuits AMP1 and AMP2 of the embodiment can be constituted by the two MOSFETs as described above.
On the other hand, in this embodiment, a CMOS inverter circuit is configured using two P-channel MOSFETs and two N-channel MOSFETs. Two N-channel MOSFETs are connected in parallel between the output terminal and the ground potential point of the circuit, and two P-channel MOSFETs are connected in series between the power supply voltage and the output terminal.
In this configuration, the conductance of the N-channel MOSFET is large, and the conductance of the P-channel MOSFET is small. That is, the current flowing through the N-channel MOSFET is set by the small conductance (large on-resistance) of the P-channel MOSFET. Apparently, a constant current can be caused to flow through the N-channel MOSFET, so that the logical threshold voltage of the CMOS inverter circuit is such that the threshold voltages of the two N-channel MOSFETs predominantly act. Become. This makes it possible to make the logical threshold value of the CMOS inverter circuit less susceptible to fluctuations in the power supply voltage.
The configuration in which the P-channel MOSFET operates as a mere high-resistance element and the threshold voltage of the N-channel MOSFET predominantly acts on the logical threshold value as described above is due to the influence of element characteristic deterioration (NBTI) described later. There is also an advantage that it can be hardly affected.
As will be described later, when the identification number generating circuit is configured by a gate array, the element sizes of the N-channel MOSFET and the P-channel MOSFET are determined. The ratio between the element sizes of the N-channel MOSFET and the P-channel MOSFET can be made different, and the logical threshold can be set correspondingly.
FIG. 17 is a circuit diagram of another embodiment of the identification number generating circuit according to the present invention. In this embodiment, a circuit for fixing a part of the identification number to an arbitrary number is shown in the function of generating a random identification number described above. In the embodiment shown in FIG. 7, 24 types of identification numbers could be generated. The number of information bits is 16 bits including the result of the self-match. Briefly describing the circuit of this embodiment, the output node (common node) P of the first-stage CMOS inverter circuit shown in FIG. 6 is forcibly fixed to an arbitrary value. In this case, the order of the first and second stages cannot be interchanged.
In this embodiment, the output node corresponding to the CMOC inverter circuit INV1 is fixed to “H” (= VDD) by the MOSFET Q11 from the embodiment circuit of FIG. 7, and the output node corresponding to the CMOS inverter circuit INV2 is set by the MOSFET Q21. This is fixed at "L" (= VSS). Since the MOSFETs Q11 and Q21 forming the fixed levels "H" and "L" do not become inputs to the common node P, the decode signals Y1 and Y2 are unnecessary. Therefore, the binary counter circuit also has a 3-bit configuration, and the output signals of the decoder circuit are formed like Y3 and Y4.
FIG. 18 is a waveform chart for explaining the operation of the embodiment circuit shown in FIG. There are four selections in the first stage and two selections in the second stage, and a total of eight outputs are obtained. That is, the number of information bits is 8 bits. In this embodiment, as the output signals b1 to b4, "0", "0", "1", and "1" are always output. The remaining b5 to b8 are the result of variations in the logic thresholds of the CMOS inverter circuits Q3 and Q4. In this embodiment, only two types of fixed numbers and a maximum of two types of random identification numbers are generated.
In actual use, the fixed part and the random part can be combined in any size. The fixed part indicates a product code, and the random part indicates a sample number. Further, as a method of inserting the fixed identification number into the information bit string, several more methods can be considered. For example, there is a method of replacing the self-matching portion described in FIGS. 14 and 15, and a method of replacing one of the overlapping matches (a comparison in which the first stage and the second stage are interchanged). When these circuits are actually realized, not only the circuit that generates the identification number, but also which part of the entire registration and verification system bears the function becomes a problem. However, since the registration and collation functions in the entire system are likely to be mainly realized by computer software, advanced functions can be realized relatively easily.
FIG. 19 is a block diagram showing another embodiment of the identification number generating circuit according to the present invention. The logical threshold value judging section, which is substantially shown only by blocks, is operated by a relatively low voltage and stabilized voltage V2 output from a power supply circuit shown in the figure and described below. You.
In other words, a P-channel MOSFET whose gate is constantly supplied with the ground potential of the circuit operates as a load means, and the operating current is supplied to four N-channel MOSFETs in the form of a diode connected in series which function as a constant voltage element. Is to flow. As a result, a constant voltage V1 corresponding to a constant voltage (threshold voltage) between the gate and the source of the serial N-channel MOSFET is formed, and the constant voltage V1 is transmitted through the gate and the source of the N-channel MOSFET. It is supplied as the operating voltage V2 of the threshold value judging section. The voltage supplied to such a logic threshold voltage determination unit is made constant. As a result, the logical threshold values of the CMOS inverter circuits INV1 to INV4 and the like can reduce the influence of the fluctuation of the power supply voltage VDD. As a result, a more stable logic threshold value determination operation can be expected.
In the present invention, it is not essential to make the operating voltage of the logical threshold value determination unit constant. In other words, the present invention does not use the absolute values of the logical threshold voltages of the plurality of CMOS inverter circuits, but sets the identification numbers corresponding to the differences between the logical threshold voltages of the individual CMOS inverter circuits. Things. This is because the fluctuation of the power supply voltage similarly affects the logical threshold voltage of each CMOS inverter circuit, so that the magnitude relationship does not change drastically.
FIG. 19 (B) shows a specific circuit of a measure for protecting the MOSFET from aging. MOS transistors may undesirably fluctuate due to electric field stress whose threshold voltage depends on electric field strength and temperature. In particular, a phenomenon called NBTI (Negative Bias Temperature Instability) is a phenomenon that appears remarkably in a P-channel MOSFET. As a defense measure, a method of increasing the voltage applied to the gate of the PMOS at a time other than the intended time is often used. In this embodiment, the ground potential VSS of the circuit of the logic threshold value judging unit is supplied by an N-channel MOSFET, and the N-channel MOSFET is turned on at the time of the logic threshold judgment operation by the high level of the power supply control signal PON. To supply the ground potential VSS of the circuit. At times other than the logic threshold value judging operation, the power supply control signal PON is set to the low level to turn off the N-channel type MOSFET, and the P-channel type MOSFET is turned on to set the power supply voltage VDD to the ground potential side of the circuit. Supply. As described below, the gate voltage of the P-channel MOSFET is set to a fixed voltage so as to supply the power supply voltage VDD. As a result, in the P-channel MOSFET, the gate, the drain, the source, and the substrate (channel) all have the same potential equal to the power supply voltage VDD, and the variation of the logic threshold value due to the aging of the MOSFET is suppressed as much as possible.
FIG. 20 is a circuit diagram showing another embodiment of the identification number generating circuit according to the present invention. In this embodiment, a series circuit of P-channel MOSFETs is provided at the input of each of the CMOS inverter circuits INV1 to INV4 so as to minimize fluctuations in the logical threshold value due to the aging of the MOSFET. At the time of reset in which the signal RES / is set to the low level, the inputs of the CMOS inverter circuits INV1 to INV4 are fixed to the power supply voltage.
That is, by the low level (logic 0) of the signal RES /, all the output signals of the NAND gate circuits receiving the count outputs B0 to B3 of the binary counter circuit are set to the high level (logic 1). As a result, all the output signals Y1 to Y4 and X1 to X4 of the NOR gate circuit constituting the decoder circuit become low level (logic 0), and are provided between the input of each of the CMOS inverter circuits INV1 to INV4 and the power supply voltage VDD. The series P-channel MOSFET is turned on and fixed at the power supply voltage. Thereby, the power supply voltage VDD is supplied to the gates of the P-channel MOSFETs constituting each of the CMOS inverter circuits INV1 to INV4.
Further, in this embodiment, the inputs of the amplifier circuits AMP1 and AMP2 are also fixed to the power supply voltage VDD by the P-channel MOSFETs that are turned on by the low level of the signal RES /, and are connected to the gates of the P-channel MOSFETs constituting the amplifier circuits. The above voltage is supplied.
Alternatively, all the selection signals Y1 to Y4 may be turned on, and the common input node P may be fixed at the power supply voltage. In any case, a method of controlling the gate voltages of the P-channel MOSFETs constituting the CMOS inverter circuits INV1 to INV4 and the amplifier circuits AMP1 and AMP2, or shutting off all the power supplies of the identification number generation circuit, can be taken. Just fine. However, in the method of shutting off all the power supplies, it is necessary to consider that the element region where the MOSFET forming the identification number generating circuit is formed is electrically separated from other circuits. In other words, it is not desirable that a constant voltage is constantly applied to the substrate gate (channel) of the MOSFET even when the power supply is cut off, from the viewpoint of the deterioration of the element characteristics.
On the other hand, if attention is paid to such NBTI, normal reliability guarantee becomes a problem. That is, by applying the means for avoiding the stress as described above, it becomes impossible to screen for a process defect performed in a so-called burn-in process. There is no problem if the scale of this circuit is considered to be extremely small as compared with the entire LSI, but applications that require screening should be assumed. In this case, there is provided a mode for arbitrarily resetting or canceling the cutoff of the power supply in a burn-in process or the like.
Naturally, it is fully conceivable that the identification number fluctuates due to the stress here. However, after the burn-in process, the final identification number can be collected and re-registered in the database, and the size of the lot handled in the burn-in process is limited to several hundreds to several thousands. Even small fluctuations have little effect.
FIG. 21 is a schematic block diagram showing one embodiment of the semiconductor integrated circuit device according to the present invention. This embodiment is directed to power supply control in a case where the present application identification number generating circuit is mounted on a system LSI. This system LSI is an example using two different power supplies, VDD1 and VDD2.
The identification number generating circuit receives power supply from VDD1 during operation. Here, the operation time is a time period during which there is an identification number read request from the main body LSI circuit unit 1 and the identification number is sent out. In other states, the supply of power is cut off. A signal for controlling power supply is a power control signal, which is input to the power control circuit. The power control circuit includes an N-channel MOSFET and a P-channel MOSFET whose power control signal is connected to the gate. When the power supply control signal is at the high level, the power supply of the identification number generation circuit is fixed at VSS, and the identification number output signal is fixed at the low level. When the power control signal is at the low level, VDD1 is supplied to the identification number generation circuit. The circuits included in the identification number generation circuit section in the figure are, for example, the logic threshold value determination circuit section, the binary counter section, and the decoder section of the CMOS inverter circuit shown in FIG. Further, only the logic threshold value judgment circuit of the CMOS inverter circuit may be provided, and the binary counter and the decoder may be included in the main LSI circuit 1.
FIG. 22 is a layout diagram of an element according to an embodiment suitable for the semiconductor integrated circuit device according to the present invention. Although the configuration in FIG. 1 is not particularly limited, it may be understood as a layout example suitable for a so-called master slice type semiconductor integrated circuit device. In the figure, for the sake of easy understanding, only a plane pattern of an active region constituting a MOS transistor is shown, and a wiring layer pattern such as a metal wiring layer is not shown. Even with such a plane pattern, the essence of the technology is that the MOS transistors dominantly affect the circuit characteristics to be obtained, and that the wiring such as metal wiring has little effect on the circuit characteristics to be obtained. Will be better understood.
Although the basic device structure of the semiconductor integrated circuit device itself is not directly related to the present invention and will not be described in detail, it will be schematically described below.
That is, a semiconductor substrate made of N-type single crystal silicon is used, and an N-type well region and a P-type well region are formed on the surface of the semiconductor substrate by the impurity selective introduction technique. An opening for defining an active region is provided in a so-called field insulating film made of a silicon oxide film provided on the surface of a semiconductor substrate, and heat of silicon is applied to the surface of the N-type well region and the P-type well region exposed to the opening. A gate insulating film is formed by an oxidation method or the like. A gate electrode layer made of a polycrystalline silicon layer is selected on the gate insulating film and the field insulating film. By introducing a P-type impurity using the gate electrode layer and the field insulating film as a substantial impurity introduction mask, a P-type semiconductor region constituting a source region and a drain region of the P-channel MOS transistor is formed on the surface of the N-type well region. ing. Similarly, by introducing an N-type impurity using the gate electrode layer and the field insulating film as a substantial impurity introduction mask, an N-type semiconductor region constituting a source region and a drain region of the N-channel MOS transistor is formed on the surface of the P-type well region. Is formed. For such a basic device structure, a desired wiring layer is formed by a known wiring layer forming technique and an insulating layer forming technique.
In FIG. 22, a relatively small, substantially square pattern constitutes one active area. One unit area is constituted by such a relatively small, substantially rectangular pattern and two elongated patterns parallel to each other, each of which means a gate electrode layer drawn so as to overlap the pattern. For example, a relatively small square pattern with symbols PP, B, and P, which is located at the upper right end of the drawing, and two elongated shapes drawn so as to overlap with each other and with symbols Y0 / and X0 /, respectively. A unit area is constituted by the pattern.
Accordingly, in one active region, two MOS transistors are formed by two parallel gate electrode layers and a source / drain semiconductor region formed on the surface of the active region in a self-aligned manner with respect to the two gate electrode layers. Is formed.
In FIG. 22, a plurality of unit regions for N-channel MOS transistors and a plurality of unit regions for P-channel MOS transistors are arranged in a matrix as shown. In a row of four unit areas for a P-channel MOS transistor located at the uppermost position in the drawing (hereinafter, referred to as a first area row), each unit area has the same plane dimension and the same extension direction. It is configured to have. Each unit region in the four unit region columns (hereinafter, referred to as a second region column) for the N-channel MOS transistors located below the first column also has the same plane dimensions, the same extension direction, It is composed with. The first region row and the second region column are used to configure an inverter and a switch MOS transistor coupled thereto as shown in FIG.
Similarly, the third region column and the fourth region column are used to configure an X decoder unit, and the fifth region column and the sixth region column are configured to configure a Y decoder unit. .
The entirety from the first area row to the sixth area row each having four unit areas in FIG. 22 is also a basic repeating unit. That is, a plurality of basic repeating units shown in FIG. 22 are arranged adjacently in the horizontal direction in FIG. 22 according to the circuit scale to be obtained. According to this configuration, the first area columns in different basic repetition units constitute a single row (also referred to as an entire area row) as a whole in the layout. Similarly, the second and subsequent rows each correspond to the entire area row. Constitute.
The layout shown in FIG. 22 and the above-described repeated layout are preferred examples for forming identification information according to the present invention.
Instead of the layout shown in FIG. 22, a plurality of unit regions that should form the same region row are arranged with a relatively large distance from each other because they are arranged so as to sandwich element regions constituting another circuit. In such cases, the following difficulties arise. That is, a plurality of unit regions are strongly affected by macroscopic fluctuations in pattern dimensions or macroscopic fluctuations in pattern distortion as a result of fluctuations in manufacturing conditions of the semiconductor integrated circuit device, and relatively large patterns are formed. A difference in shape will result.
The mechanical stress applied to the semiconductor chip by mounting the semiconductor chip, for example, is likely to be different depending on the part of the semiconductor chip, so that a plurality of unit areas may be relatively different from each other. Have sex. The increase in operating temperature caused by the supply current flowing through the circuit becomes non-uniform for a plurality of unit regions. There is also a risk that the thickness of the gate insulating film and subtle changes in the concentration of the introduced impurities may become relatively large due to the relative separation of the plurality of unit regions.
In the case of the layout shown in FIG. 22, a plurality of unit areas in the same area row are arranged relatively close to each other, and are configured to have the same size and the same direction as each other. Hardly affected by typical pattern dimensions, pattern distortion, mechanical stress, operating temperature, film thickness, and impurity concentration.
The so-called phase shift mask technique is understood to be an effective technique for miniaturizing circuit elements, wirings, and the like constituting a semiconductor integrated circuit device to a so-called submicron level. In such a phase shift mask technique, asymmetry or distortion of a pattern, such as a difference in left and right shapes of a pattern to be obtained, is caused by a slight change in a phase difference of light when a photosensitive material layer serving as a mask is exposed. May result. In the layout as shown in FIG. 22, it is possible to sufficiently reduce the deviation of the electric characteristics among a plurality of unit regions even if there is such a pattern distortion.
In addition to the difference in configuration from the above viewpoint, the influence of the crystal orientation dependence of carrier mobility in a semiconductor cannot be neglected for the present invention utilizing the above-described microscopic characteristics. In the case of the layout shown in FIG. 22, all of the plurality of gate electrode layers forming the first region column have the same direction and the same pattern, and all of the plurality of gate electrode layers forming the second region column also have the same pattern. Since they are in the same direction and have the same pattern, the MOS transistors belonging to the first region column and the MOS transistors belonging to the second region column have a difference in characteristics based on the crystal orientation described above. Absent.
As described above, the layout shown in FIG. 22 is considered from the viewpoint of design and manufacture of the semiconductor integrated circuit device such that the above-mentioned macro-variation or characteristic deviation is significantly reduced. It will be understood that micro-variations have been considered so as to be appropriately used.
In the case where it is necessary to further sufficiently eliminate the bias in the electrical characteristics of the MOS transistor obtained by the configuration shown in FIG. 22, the end effect of the entire arrangement composed of a plurality of basic repeating units shown in FIG. 22 is eliminated. To set a dummy area. The dummy area is configured to make the end of the entire array equal to the inside of the entire array in terms of layout, and has at least a plurality of unit areas at the end in the basic repeating unit. Can be.
If this type of dummy region is not set, the processing shape of the end may be affected by the configuration of the outside of the end in the entire arrangement, and the semiconductor substrate and its In some cases, the manner of applying a force that may affect the device characteristics such as the stress caused between the surface and the insulating film on the surface is different between the end portion and the other portions. They also cause a bias in electrical characteristics. When the above-described dummy area is set, factors causing the above-described bias of the electric characteristics are sufficiently eliminated.
The dummy region may be a region not used as a circuit, or may be a structure for configuring another circuit that does not require attention to bias in electrical characteristics.
FIG. 23 shows an equivalent circuit diagram corresponding to FIG. 22 and 23, terminal names and element numbers correspond to each other. However, since the decoder section is not particularly limited except that it is arranged below (or above) the CMOS logic threshold value detection circuit, the details are not shown. When the basic repeating units as shown in FIG. 22 are arranged in parallel, the CMOS inverter circuit formed by the elements can have the same shape and surrounding environment as the same adjacent circuit. Similarly, in a layout method other than the gate array method, the basic repetition unit may be laid out so that the CMOS inverter circuit units are combined. In the case where a circuit is formed using such a gate array, according to the embodiment shown in FIG. 16, it is possible to reduce the influence of the power supply voltage fluctuation and to reduce the variation in the threshold voltage of the N-channel MOSFET. It can be predominantly reflected in the threshold.
FIG. 24 is a block diagram showing an embodiment in which the present invention is applied to a dynamic RAM (random access memory; hereinafter simply referred to as DRAM). In this embodiment, the binary counter section and the decoder section are omitted from the identification number generating circuit shown in FIG. Instead of these counters and decoders, row address signals and column address signals of the DRAM in which they are mounted are supplied as signals X and Y formed by the decoders, and the logic threshold of the CMOS inverter circuit is supplied. It is used directly as a selection signal for the value determination circuit. A read mode of the identification number is set for the DRAM, a start signal is generated by the circuit DFT, and the address signals X and Y for the above read are supplied from the outside to replace the memory array selection operation. The identification number generated by the generation circuit is output through the input / output circuit and the DQ pin. In this case, since the input order of the address signals X and Y can be arbitrarily set, it is also possible to specify and read out only the fixed information of the self-match part. Alternatively, the input order of the address signals X and Y may be input as a code so that only a specific one can output a fixed signal or an identification number corresponding to the self-match.
This configuration is similarly applied to other semiconductor storage devices such as static RAMs and flash EPROMs, and semiconductor integrated circuit devices such as CPUs (microprocessors) having address terminals, in addition to DRAMs. be able to.
FIG. 25 is a schematic block diagram of one embodiment of a semiconductor integrated circuit device using the identification number generating circuit according to the present invention. The original purpose of assigning an identification number to a semiconductor integrated circuit device is to assign a unique number to each LSI. As a method of numbering, there is a method using a laser fuse, a flash (FLASH) memory, or the like, but a special process or a programming step is required.
In this embodiment, an identification number generated by the identification number generation circuit of the present invention in a wafer state is read out by a tester and registered in a workstation in association with various data. After each LSI becomes a product and is mounted on an electronic device such as a personal computer PC, the identification number is read from the LSI. At this time, even if the read identification numbers are the same LSI, the operating environment and conditions may be different from those at the time of registration, and there is no guarantee that the identification numbers completely match. However, it can be estimated from the degree of discrepancy between the identification numbers that they are the same or not the same.
The determination algorithm of the identification system in the present application will be described. As described above, the identification numbers in the present embodiment are in the order of the magnitudes of the logic thresholds of the plurality of CMOS inverter circuits. A circuit having four CMOS inverter circuits as in the above embodiment is counted as one unit. For example, the order (the number of permutations) of the logically included values of four CMOS inverter circuits is ₄ P ₄ = 4! = 4 × 3 × 2 × 1 = 24 ways. If the logic threshold values vary completely randomly when two units are used here, the probability that the two-unit CMOS inverter circuits are in the same order is about 4.2% (= 1-23 / 24). It is.
When one unit is constituted by eight CMOS inverter circuits, the number of permutations is eight! = 40,320 patterns. When this is 50 units, the probability that one or more sets in the same order exist is about 3% (= 1− (40320 × 40319 ×... × 40271) / 40320). ⁵⁰ ).
With 16 CMOS inverter circuits per unit, the combination is 16! = 2.09E13. Thus, the permutation of 16 is a tremendous number, and when the logic threshold values of the CMOS inverter circuit vary randomly, there is almost no arrangement of the same arrangement. In fact, when there are 1 million units, it is estimated that the probability that at least one set of units in the same order exists is at least 5% or less (exact calculation is a rough estimation due to the large number of digits and difficulties). That is, roughly, one set per 20 million units. From such calculations, it is considered that about 16 CMOS inverter circuits are required for one unit to complete a practical identification number. Therefore, the following description will be made by taking a 16-CMOS inverter circuit per unit as an example.
If 16 CMOS inverter circuits per unit are realized as shown in FIG. 7, the round robin comparison result is 256 including self-match. Hereinafter, one comparison result output is referred to as one bit.
FIG. 26 is the simplest example in which the logic threshold values of 16 CMOS inverter circuits are continuously arranged in the order of VLTQ1> VLTQ2 >>...> VLTQ16.
FIG. 27 shows an example in which the logic threshold value of the CMOS inverter circuit is random. When the logical threshold value of the second-stage CMOS inverter circuit is higher than the first-stage CMOS inverter circuit, "1" is set, when it is low, "0", and the self-match is undefined "*". As can be seen from the two examples, the bit pattern of OUT of the circuit corresponding to FIGS. 26 and 27 changes to a specific pattern depending on the arrangement of the logic thresholds of the CMOS inverter circuit. That is, it is considered that the simplest method is to directly use the bit pattern of the output OUT as the identification number. The number of bits of the identification number information in this method, that is, the data amount is 256 bits.
The bit pattern is the so-called match result table itself. On the other hand, the idea based on the present application is the order of the magnitudes of the logic threshold values of a plurality of CMOS inverter circuits. If only the information in the order of magnitude is extracted from the match result table, it is considered that the data amount of the information to be handled can be reduced.
The lower and right sides of FIGS. 26 and 27 show the total number excluding the self-match portion of “1” or “0” in the vertical and horizontal directions, for example, FIGS. 26 and 27. Looking at the sum of "1" on the lower side of the figure, the order of the magnitude of the number and the magnitude of the logical threshold value correspond to each other. This is the same as a strong team with a higher number of wins when compared to sports league games such as soccer and baseball. In the case of a CMOS inverter circuit, the higher the logical threshold value, the more "1".
Since the number of wins or the total number of “1” is equivalent to the rank, the total number of “1” can be used to indicate the order of the magnitude of the logical threshold value of the CMOS inverter circuit. . Naturally, there is basically no difference whether the total number of “0” is used or the count including “1” or “0” in the horizontal direction is used. By using this method, the data amount of information bits can be reduced. Each CMOS inverter circuit can have a rank that can be represented by a number from 0 to 15, and therefore requires a 4-bit binary information amount. Since there are 16 CMOS inverter circuits, a total of 64 bits (= 4 × 16) are required. Compared to the comparison result (competition result) table, the data amount can be reduced by a quarter from 256 bits to 64 bits.
Here, the configuration uses 16 CMOS inverter circuits per unit. However, this effect increases as the number of CMOS inverter circuits increases. For example, in a 1-unit 32 CMOS inverter circuit configuration, the comparison result table has 1024 bits, but when using the order, 160 bits (= 5 × 32), which is 1 / 6.5. In other words, the comparison result increases by a factor of four (= 1024/256), but is reduced by a factor of 2.5 (= 160/64) in the information using the ranking. This has the advantage that the amount of data managed by the identification system is small and that the processing time spent for collation can be reduced.
FIGS. 28 and 29 are block diagrams showing one embodiment of the matching algorithm in the identification system of the semiconductor integrated circuit device according to the present invention. Here, a method using the logical threshold comparison result information of the CMOS inverter circuit will be described, but the method using the order of magnitude of the logical threshold has the same overall flow.
FIG. 28 shows a registration method.
{Circle around (1)} The 256-bit CMOS inverter circuit logical threshold comparison result information is read from the identification number generation circuit.
{Circle around (2)} Register it in the identification number management ledger and provide a management number in order to associate it with a database storing information such as measurement data.
(3) Increase the number of registrations by one. Here, it is assumed that the newly registered identification number does not always overlap the registered one, but a procedure such as confirming the overlap with the registered one at the time of new registration and issuing some kind of warning It is also effective to add
FIG. 29 shows a collation method. This system is characterized in that a change in an identification number due to a difference in environment or conditions between registration and collation is allowed.
{Circle around (1)} The 256-bit CMOS inverter circuit logical threshold comparison result information is read from the identification number generation circuit. This is called an identification number.
(2) The registration identification numbers are sequentially taken out from the management ledger.
(3) The registered identification number is compared with the identification number. The comparison method will be described later.
{Circle around (4)} A candidate having a small difference in the comparison result between the registered identification number and the identification number is set as a matching candidate. By repeating the steps (2) to (4), the one with the smallest difference among all the registered identification numbers finally becomes the same leading candidate.
FIG. 30 shows an explanatory diagram of an example of the comparison method of FIG. 29. The identification number is obtained by extracting 24 bits which are a part of the comparison result output of the logic threshold value of the 256-bit CMOS inverter circuit. The identification numbers 1 to 5 are registration identification numbers. The shaded portion therein is a portion different from the bit of the identification number. The right end shows the total number of mismatched bits.
As described with reference to FIG. 8, since the "0" and "1" output patterns of the identification number generation circuit are unique to each unit, it is determined whether the identification numbers are output from the same unit. The determination can be made based on the proportion of matching of the number of bits constituting the pattern. Although the identification number here is merely an example for explanation, the number of mismatch bits of the identification number 5 is 1 and the other numbers are 5 to 17 and the coincidence rate of the identification number 5 is remarkably high. Therefore, the identification number 5 can be set as the most probable candidate.
FIG. 31 and FIG. 32 are explanatory diagrams of an example of a method of comparing identification numbers when the order of the logical threshold value of the CMOS inverter circuit is used. FIG. 31 is shown in the form of a list, and FIG. 32 is shown in the form of a graph. Here, the order of the elements of the identification number, that is, the arrangement of the logical thresholds of the CMOS inverter circuit is assumed to be the same as the element number for the sake of simplicity. The identification number 1 is the same except that the element numbers 8 and 9 are interchanged. Compared with the identification number, the sum of the absolute value of the distance between the two ranks is 2. The identification number 2 has a random rank, and the total of the rank distance is 66 and the average is 4.13. The expected value of the total of the rank distance is theoretically 85 and the average is 5.3. Therefore, it can be said that the identification number 1 having the sum total of the rank distance of 2 and the average of 0.125 is very likely to be extremely the same. In other words, in this method, in order to allow the identification number to fluctuate due to differences in the environment and conditions at the time of registration and verification, the candidate with the smallest difference between the identified number and the registered identification number is regarded as a match candidate. To do.
In the identification number 3 in FIGS. 31 and 32, the order of the element number 1 is shifted by five steps. The element numbers 2 to 6 are one step, and the rest are 0. The sum of the rank distances and the average are 10 and 0.625, respectively. As far as this value is seen, the value is sufficiently lower than the expected value, and therefore, there is a high possibility that it will be a match candidate. However, the fact that the order of the element number 1 is shifted by five steps is considered to be a unlikely phenomenon. If there is a case where a ranking distance equal to or slightly larger than the identification number 3 is present here, the maximum difference between the ranking distances of the individual elements is added to the determination element in order to confirm more accurate identity. It is effective. As a specific example of the criterion, a criterion “the total of the rank distances is 16 or less” is added to a criterion of “the rank distance of each element is 2 or less”. The actual criterion differs depending on the characteristics of the identification number generating circuit and the applied system.
FIGS. 31 and 32 illustrate a case where the number of elements for the identification number, that is, the number of CMOS inverter circuits is 16. There may be a case where it is desired to increase the number of elements for an identification number, for example, in order to satisfy a higher identification ability. To this end, one of the simplest methods is, for example, a method of expanding the configuration as shown in FIG. The number of elements in the configuration shown in FIG. 20 can be increased by setting the CMOS inverter and the switch MOSFET corresponding to the number, setting the number of counter bits corresponding to the number, and setting the decoder. As another method of increasing the number of elements, a method of arranging a plurality of identification number generating circuits mainly including, for example, 16 CMOS inverters in the same semiconductor integrated circuit device can be adopted.
After the semiconductor integrated circuit device LSI is paid out from the previous process, defects are detected by a probe test in a wafer state, a sorting test in a state of being assembled in a package, and the like. In a memory or a logic LSI incorporating a relatively large-scale memory, a so-called redundancy repair technique of replacing a defective memory cell detected during a probe test with a spare memory cell is employed. With the recent miniaturization, higher speed, and higher performance of semiconductor processing technology, it has happened that many product defects are detected in the final sorting process. In addition, the size of the semiconductor integrated circuit device LSI has been increased, and the occurrence of a defect after such a manufacturing process is a problem that causes an increase in cost.
Therefore, there is an increasing demand to repair defects detected in assembled products again. For example, taking a memory section as an example, chips which have become defective in a burn-in process or the like are collected, and the deteriorated bits included in the defective chip are to be repaired again by the remaining spare memory cells.
When examining the re-rescue technology specifically, the following two typical methods can be considered for the rescue technology. The first method is to assign an independent number to each LSI and manage the relief information in the probe inspection process for every memory chip. When performing re-rescue, the chip number is extracted from the memory chip, the rescue information collected in the probe inspection step is extracted from the management computer, and based on this information, unused memory cells are identified and re-rescued. The second method is a method in which the first rescue information is extracted from the memory chip every time the re-rescue is performed. This uses a technique called address roll call.
In order to apply these rescuing techniques, the following techniques are required. In the first method, it is necessary to assign an independent number to each memory chip. This can be realized by programming an identification number at the time of rescue performed after the probe inspection. In both the first and second methods, it is necessary to incorporate an electrically programmable element at the time of repair. As an electrically programmable element, a method in which polysilicon is melted by current, a method in which an insulating film is destroyed by a high electric field, and a method in which a FLASH memory is used can be considered. Side effects such as an increase in the reliability of the device and an increase in peripheral circuits are conceivable.
In each of the above methods, some programming element is mounted in the main body LSI. The inventor of the present application has studied a third method of dividing the two into separate chips from different angles. The feature of the third method is that a dedicated process suitable for the program can be applied to a dedicated chip for the program. The third method also has the following problem.
One is how the main body LSI and the dedicated programming chip correspond. Consider a solution to this problem using a multi-chip module as an example. In the case of a multi-chip module, both chips eventually become one semiconductor integrated circuit device on the module substrate. However, the combination of each chip must be strictly controlled before being assembled into a module. It is not easy to build an LSI manufacturing line that achieves this. Therefore, a method of assigning an identification number to the main body LSI, reading out the identification number of the main body LSI while mounted on the module board, and programming information corresponding to the main body LSI in a dedicated chip for programming can be considered.
For example, when a technique of cutting with a laser irradiation device is used as a programming method, such a laser irradiation cutting device can cut a fuse of a chip in a wafer state, but it is difficult to cut a chip on a package or a module. This is because it is technically difficult to align a fuse coordinate of a chip on a package or a module with a laser beam, and even if it is possible, alignment is required for each individual chip and throughput is extremely low. In the first place, how to read the identification information of the main LSI before the laser irradiation is also a problem. For this reason, the programming-only chip is limited to an electrical program method that can read the identification number of the main body LSI and continuously execute the program on the same device.
Accordingly, a practical form of the third method is that "a program-specific chip having an identification number-attached main body LSI and an electric programming element is mounted and programmed on a multi-chip module". . However, this third method also holds under some restrictions, and is not always the best in LSI production activities, for example, in terms of cost and reliability.
One of the limitations is that the use of a multi-chip module is premised. However, it is even more impractical to use a method of directly combining two chips on a board without using a multichip module.
A second limitation is that a programming element used for a dedicated programming chip must use an electrically programmable process such as a polysilicon fuse, a FLASH memory, or an FRAM. Each of these elements requires a special process, has a large peripheral circuit scale, and may be problematic in terms of reliability. Although there is a programming method using a laser cutting metal fuse as a relatively inexpensive method which has few of these problems, it cannot be said that it is compatible with the third method as described above.
The third problem is a program (engraving) of the identification number of the main LSI. This program also requires a laser fuse and an electric program element. However, if a similar process is added to the main LSI even though the program-dedicated chip is formed as a separate chip, the merit of cost reduction of the main LSI decreases. Therefore, in order to solve these problems, an identification number generation circuit using the variation of the logic threshold value of the CMOS inverter circuit becomes extremely useful.
FIG. 33 is a block diagram showing an embodiment of a semiconductor integrated circuit device to which the present invention is applied. First, a probe inspection of the main body LSI is performed. At this time, for example, if there is a defect in the memory unit mounted on the LSI, relief information for replacing the defective memory cell with a spare memory cell is created. In a general-purpose memory or the like, laser rescue or the like is performed thereafter. In the semiconductor integrated circuit device of this embodiment, the main body LSI is diced and assembled as it is. Further, thereafter, the defect information detected in the steps such as aging and sorting is added to the rescue information at the time of the probe inspection. The final rescue information is written to a dedicated chip for programming. The main LSI and the dedicated program chip are used in combination as a multi-chip module.
FIG. 34 is a block diagram showing one embodiment of the multichip module to which the present invention is applied. The data is transmitted to the serial via the data exchange control circuit between the main body LSI and the dedicated program chip in a serial manner. That is, the identification number generated by the identification number generation circuit of the main body LSI is transmitted to the dedicated program chip through the data exchange control circuit.
In the program-dedicated chip, a plurality of registration numbers (identification numbers) corresponding to one unit and defect rescue information thereof are held as programming data in one-to-one correspondence. In the program-dedicated chip, the identification number transmitted from the main body LSI via the data exchange control circuit is registered in the identification number register via the counter.
The matching circuit compares and matches the identification number with the registered identification number in the programming data. This collation operation is performed in accordance with the algorithm shown in FIGS. 30 to 31 while permitting a change in the identification number due to a difference in environment or conditions between registration and collation. When the matching candidate number is detected, the register data in the programming data is read out to the data reading circuit. Then, the rescue information is transmitted from the dedicated chip to the main body LSI via the data exchange control circuit in the opposite manner to the identification number. This rescue information is subjected to serial / parallel conversion, held in a data register, and used for defect rescue.
Since the program-dedicated chip has defect repair information of a plurality of chips corresponding to one unit, one type of program-dedicated chip is formed for a plurality of main-unit LSIs for one unit and used in common combination. Can be Therefore, there is no need to manufacture, manage, and assemble the main body LSI and the dedicated program chip in a one-to-one correspondence.
FIG. 35 is a block diagram showing an embodiment of a program-only chip. Although not particularly limited, the program-only chip includes an identification number decoding circuit, a verification circuit, a programming data and data reading circuit, and the like. The registration identification number and register data are registered by selective cutting of the fuse by laser irradiation.
The matching circuit corresponds to the determination algorithm shown in FIGS. 30 and 31 and compares the absolute value of the subtraction result with the upper limit value in the comparator 1 using a subtractor to detect deviation. The comparator 2 compares the cumulative distance output from the accumulator based on the minimum cumulative distance that is sequentially replaced, and outputs one matching candidate number from 1 to N together with the deviation detection signal by a determination circuit. The register data is selected based on the matching candidate number and transmitted to the data reading circuit. The data read circuit has an ECC function (error correction function). Thereby, the reliability of the data is improved.
FIG. 36 shows a semiconductor integrated circuit including the identification number generating circuit according to the present invention.

The configuration diagram is shown. In this embodiment, it is assumed that the main body LSI is a large-scale system LSI in which a DRAM and an SRAM are mixed, and that a dedicated chip for programming uses a laser cut metal fuse. Hereinafter, the flow of the manufacturing process will be described with reference to FIG.
(1) The main body LSI is tested by a probe test tester. The identification number in the LSI is transferred to the host computer together with the remedy information of the defective memory cell of the DRAM or the SRAM, the set value of the internal power supply circuit trimming, the set value of the delay circuit, and the like. The host computer connects to the transmitted information and other manufacturing management information and stores the information in a database.
(2) Dicing the main body LSI wafer.
(3) Only the main LSI is temporarily mounted on the multi-chip module substrate. In the figure, there is one main body LSI, but there may be a plurality.
{Circle around (4)} The identification number is read from the main LSI by the screening tester and sent to the host computer. The host computer recognizes the main body LSI from the identification number and returns information necessary for each main body LSI to the tester. Necessary information is information managed by a host computer in a database, such as the above-described defective memory cell rescue information and the main body LS1 identification information. This is called main body LSI register information. The selection test tester stores the main body LSI register information in the rescue address register of the rescue circuit in the main body LSI if the remedy information is, for example, a defective memory cell, or the trimming value in the internal circuit if the trimming value is set to the internal power supply circuit. Store in setting register.
After setting the main LSI register information, the selection test tester performs a high-speed operation test or the like that cannot be performed by a probe test. Further, if a new failure occurs, the failure information is transferred to the host computer. The host computer analyzes the collected information with the sent defect information to determine whether re-repair or adjustment is possible, and stores the result in the database again.
{Circle around (5)} Program information required for the main LSI is programmed in the dedicated chip for programming. If necessary, a program for manufacturing management information, customer information, encryption, function information, and the like is executed. The program-dedicated chip can store information of a plurality of main LSIs in one chip. For example, assuming that there is a capacity for 100 main body LSIs, the laser cutting apparatus receives identification numbers and register information for 100 main body LSIs from the host computer, and based on the received information, 100 program All the dedicated chips are programmed with register information for the same 100 main body LSIs.
Here, the fuse cutting time of the program dedicated chip is estimated. For example, assuming that the number of program bits per one main body LSI is 1000 bits, and that one program dedicated chip can store (register) 100 main body LS1, 100,000 dedicated program chips (1000 × 100) can be stored. Mount a fuse. Since the capacity of the latest laser cutting device is more than 5000 pulses per second, it is possible to cut 100,000 or one program-specific chip in about 20 seconds. For 100 chips, it is 2000 seconds (33 minutes). If the size of one fuse is 15 square microns, the area of the dedicated program chip is 1.5 square millimeters only in the fuse portion, and about 3 square millimeters including peripheral circuits and pads.
{Circle around (6)} A probe test is performed to remove a laser-cut defective chip. Before this step, a step of providing a protective film for protecting the chip may be added. The inspection data pattern is received from the host computer. In this case, the number of chips to be programmed in the step (5) is set to be larger than 100 because a laser cutting defective chip may occur. This number is adjusted according to the yield performance. Here, if the number of dedicated chips for the program is less than the main LSI, the surplus main LSI is collected and mixed into another group. Conversely, if there is an extra chip dedicated to programming, it is discarded. Either way, it is damaging, but it is more economical than discarding a valuable main body LSI.
{Circle around (7)} Dicing a dedicated chip for program. The dicing chips are picked up in the step (6), and the same programmed 100 chips and a margin are collected into a group (lot) corresponding to the main LSI.
{Circle around (8)} Mount the program-specific chip in a multi-chip module package. At this time, the groups associated in steps (4) and (6) must be combined. However, since it is not necessary to make each main unit LSI correspond to the dedicated program chip on a one-to-one basis, there is no need to change the process significantly as compared with the conventional assembly process. Note that, in this embodiment, the separation

However, the present invention is not limited to this method.
(9) The completed multichip module is subjected to the final screening test. In the above embodiment, the rescue information for 100 chips is stored (registered) in the program-dedicated chip. When the main body LSI on the board starts up, data exchange is performed between the main body LSI and the program-dedicated chip. Specifically, the identification number is sent from the main body LSI to the program dedicated chip, and the program dedicated chip compares the sent identification number with the registered identification number, recognizes the main body LSI mounted on the module, and performs rescue. It sends necessary register information such as information to the main LSI. The main body LSI performs internal initialization based on the transmitted register information. Thereafter, a final test is performed. Those with the rating are sent to the next sealing step, and those with rejection are sent to the separation step, and at the same time, the defect information is sent to the host computer and analyzed for reproducibility.

You.

It is.

The identification number is read from the SI, and past probe test information, selection test information, final selection test information, and the like corresponding to the identification number are extracted from the host computer. Although not shown, a program-dedicated chip is created for this new reproducible product in the same manner as for the non-reproducible product, and the same process is performed. As a dedicated chip for programming, it can be replaced with a chip using an electrically programmable element. In this case, the number of steps can be reduced.
FIG. 37 does not show the manufacturing process (1) of the embodiment in which a semiconductor integrated circuit device having the identification number generating circuit according to the present application is assembled on a circuit mounting board.

(1) The main body LSI is tested by a probe test tester. The identification number in the LSI is transferred to the host computer together with the remedy information of the defective memory cell of the DRAM or the SRAM, the set value of the internal power supply circuit trimming, the set value of the delay circuit, and the like. The host computer stores the transmitted information and other manufacturing management information in a database in cooperation with each other.
(2) Dicing the main body LSI wafer.
(3) Assemble the main body LSI into a package.
(4) Same as step (4) in FIG.
(5) Same as step (5) in FIG.
{Circle around (6)} Dicing a dedicated chip for program. The diced chips are grouped into groups (lots) corresponding to the main LSI, as in the embodiment of FIG.
(7) Same as step (7) in FIG.
{Circle around (8)} Mount the main body LSI and the dedicated program chip on the circuit mounting board. At this time, the groups associated in steps (4) and (6) must be combined. However, since it is not necessary to make each main unit LSI correspond to the dedicated program chip on a one-to-one basis, there is no need to change the process significantly as compared with the conventional assembly process.
(9) The completed board is mounted and tested. When the main body LSI on the board starts up, data exchange is performed between the main body LSI and the program-dedicated chip. Those for which a defect due to the mounting of the main body LSI or the program-specific chip and the board are confirmed are sent to a separation step, and at the same time, defect information is sent to a host computer and analyzed for reproducibility.

It is.

You. This register information is obtained by adding the mounting test result to the previous register information.

The chip is mounted on one mounting board together with the dedicated program chip, and the same process is performed thereafter.

It should be noted that the embodiment shown here is merely an example, and varies depending on the product to be applied and the form of an existing production line.
FIG. 38 shows a semiconductor integrated circuit equipped with the identification number generating circuit according to the present invention.

(1) The main body LSI is tested by a probe test tester. The identification number in the LSI is transferred to the host computer together with the remedy information of the defective memory cell of the DRAM or the SRAM, the set value of the internal power supply circuit trimming, the set value of the delay circuit, and the like. The host computer stores the transmitted information and other manufacturing management information in a database in cooperation with each other.
{Circle around (2)} Dicing the main body LSI wafer and selecting rescueable chips.
(3) Temporarily assemble the main body LSI on the baby board.
(4) Aging is performed after checking for a defective assembly. At this time, the identification number is read from the chip on the baby board, rescue data corresponding to each chip is extracted from the host computer, and stored in the chip on the baby board.
(5) Sorting is performed by a tester.
(6) Separate the main unit LSI from the baby board.
(7) Ship the main unit LSI.
(8) The customer mounts the program device on the circuit mounting board simultaneously with the main LSI.
(9) Extract the identification number from the main body LSI.

The data corresponding to the mounted main body LSI is received and transferred to the program device to store the data. The distribution may be performed using electronic media such as a CDROM without using a communication line.

In the manufacturing method of the semiconductor integrated circuit device of each of the above embodiments,
(1) Since the combination of the main body LSI and the program-dedicated chip is the number of main body LSIs registered in the program-dedicated chip, one-to-one management becomes unnecessary, thereby improving productivity and reducing the change of existing production equipment. I'm done.
(2) A laser cutting fuse can be used for a dedicated chip for programming. The advantages of the metal fuse over other electrically programmable elements are that the change is small compared to the standard CMOS process, the design can be easily changed to the specification of the main body LS1, and the process generation does not depend on the generation. And so on. The changes from the standard process are the final wiring layer formation and the passivation step.
(3) Since the main body LSI register may be a latch circuit, the area is small, and the chip size of the main body LSI is reduced.
(4) If the chip identification number generation circuit is mounted on the main body LSI, it is not necessary to add a programmable element process to the main body chip.
(5) It is possible to replace (repair) a dedicated chip for programming. When a correction or a problem occurs in the main body LSI after mounting on a module or a port, it can be dealt with by replacing a chip with a changed program content.
(6) By exchanging information centering on the host computer by using a network, a manufacturing plant in a remote place can be used, and economic production activities can be performed.
FIG. 40 shows an embodiment in which the variation of the logical threshold value of the CMOS inverter is applied to a random number generator. A more specific embodiment will be described using an application-specific LSI as shown in FIG. This LSI is for controlling a toy robot. Currently, commercially available toy robots, especially pet breeding robots, have a uniform character at the time of factory shipment. However, in order to make it resemble a real creature or animal, by giving it a congenital or genetic characteristic, such as gender, temperament, or athletic ability, for example, male or female, it will further We can make strong emotion as creature.
FIG. 40 shows the simplest circuit for providing a dedicated LSI with an innate characteristic when the LSI is manufactured without a program. This is to output a 4-bit random number in binary, and the output value of each bit is randomly generated for each LSI. For example, D0 determines male or female. D1 determines the temper, and D2 and D3 determine the dependence on the owner in four stages. Although two types of circuit schemes are shown for D0 and D1, and D2 and D3, basically, the difference between the logic thresholds of the two CMOS inverters is not changed.
Giving the robot such innate personality is possible in other ways. For example, it is possible by individually changing the parameters of the contents of the control program. However, it cannot be denied that it is programmed by the manufacturer, that is, created by humans. According to the method shown in the present embodiment, the individuality cannot be controlled by the manufacturer, that is, something like "the providence of God" is felt, and the value as a product is increased.
FIG. 41 shows another configuration example of the use of the chip identification number generation circuit according to the present invention for the purpose of reducing fraudulent acts and various troubles in the electronic component procurement market between companies. .
A semiconductor LSI shipped from a factory incorporates the above-described chip identification number generation circuit. The factory or maker collects the chip identification numbers of all the shipped products. Since the chip identification number is random, it is associated with an LSI management number that is convenient for management. Further, it is associated with various management information, for example, a production line name, a production date, and the like.
When the product is directly delivered to the customer A as shown by (1) in FIG. 41, information such as form data such as a unit (box or the like) packed with the product and a customer number is added to the management information of the database. The customer A that has received the goods reads the chip identification number from all LSIs or the extracted LSIs at the time of acceptance inspection. Next, the customer A accesses the manufacturer's database through a network such as the Internet. The chip identification number of the LSI included in the received unit is extracted from the database and compared with the identification number read from the received LSI. If the identification numbers match, it can be confirmed that the delivery of the product is correct. This method can be used for general-purpose products or customer-customized products, but is particularly effective for custom-made products.
In FIG. 41, it is assumed that a middleman (wholesaler) intervenes. Factory shipment is the same as above. The received primary wholesaler usually does not open the packaging, but inquires the unit number to the server of the manufacturer and registers the next delivery destination information and the like. The same applies to the secondary and tertiary wholesalers. The final customer reads the identification number of the received LSI from the LSI in the same manner as in the above (1), and refers to the database of the manufacturer. The following effects can be expected by constructing the above system
(1) Mixing of delivered products can be prevented.
(2) It is possible to prevent fraudulent acts such as replacement of used goods by a middleman.
(3) It is possible to prevent resale of defective products and used products due to returned goods.
(4) The distribution route can be confirmed.
FIG. 42 is a schematic plan view of another embodiment of the semiconductor integrated circuit device according to the present invention. FIG. 1 is a schematic plan view showing a state where an upper portion of a resin sealing body of a semiconductor device is removed, and MCP ( M ulti C hip P The present invention is applied to a semiconductor device called an “acquisition type”. In the MCP type semiconductor device of this embodiment, two semiconductor chips are stacked and incorporated into one package. Among them, the semiconductor integrated circuit device 10 is used as a base chip and a main body LSI as shown in FIGS. Then, the semiconductor chip 20 mounted thereon is used as the program-dedicated chip. The QFP type semiconductor device 30A of this embodiment has a configuration in which two semiconductor chips (main body LSI 10 and a chip dedicated to a program) are vertically stacked, and the two semiconductor chips are sealed with one resin sealing body 17. I have.
The main body LSI 10 and the dedicated program chip 20 are formed in different plane sizes (outer dimensions), and each plane is formed in a square shape. In the present embodiment, the planar shape of the main body LSI 10 is formed, for example, as a rectangle of 4.05 [mm] × 4.15 [mm], and the planar shape of the dedicated program chip 20 is, for example, 1.99 [mm] × 1.23. It is formed in a rectangle of [mm].
The main body LSI 10 and the dedicated program chip 20 include, for example, a semiconductor substrate made of single crystal silicon, a multilayer wiring layer in which insulating layers and wiring layers are stacked in a plurality of stages on a circuit forming surface of the semiconductor substrate, and a multilayer wiring layer. And a surface protective film (final protective film) formed so as to cover the surface.
A plurality of bonding pads 11 are formed on the circuit forming surface (one main surface) 10A of the main body LSI 10 and the circuit forming surface 10A of the back surface (the other main surface). The plurality of bonding pads 11 are formed on the uppermost wiring layer of the multilayer wiring layers of the main body LSI 10. The uppermost wiring layer is covered with a surface protection film formed thereon, and a bonding opening for exposing the surface of the bonding pad 11 is formed in the surface protection film.
A plurality of bonding pads 21 are formed on the circuit forming surface (one main surface) 20A and the circuit forming surface 20A of the back surface (other main surface) of the program-dedicated chip 20 facing each other. The plurality of bonding pads 21 are formed on the uppermost wiring layer of the multilayer wiring layers of the dedicated program chip 20. The uppermost wiring layer is covered with a surface protective film formed thereon, and a bonding opening exposing the surface of the bonding pad 21 is formed in the surface protective film.
The planar shape of the bonding pad 11 of the main body LSI 10 and the bonding pad 21 of the dedicated program chip 20 is formed, for example, as a square of 65 [μm] × 65 [μm].
The plurality of bonding pads 11 of the main body LSI 10 are arranged along four sides of the main body LSI 10 (two long sides (10A1, 10A2) facing each other and two short sides (10A3, 10A4) facing each other). . The plurality of bonding pads 21 of the dedicated program chip 20 are arranged along four sides of the EEPROM chip 20 (two short sides (20A1, 20A2) facing each other and two long sides (20A3, 20A4) facing each other). Are arranged.
The program-specific chip 20 is disposed on the circuit-forming surface 10A of the main-body LSI 10 with the back surface, which is the other main surface of the program-specific chip 20, facing the circuit-forming surface 10A of the main-body LSI 10. It is adhesively fixed to the circuit forming surface 10A of the LSI 10. In the present embodiment, as the adhesive layer 15, for example, a polyimide-based adhesive resin film is used.
The main body LSI 10 is bonded and fixed to the die pad with an adhesive layer interposed therebetween with the back surface facing the die pad. Four suspension leads 6 are integrated with the die pad, and the die pad 5 and the four suspension leads 6 constitute a support.
The planar shape of the resin sealing body 17 is formed in a square shape. In the present embodiment, the planar shape of the resin sealing body 17 is formed, for example, as a square of 10 [mm] × 10 [mm]. The resin sealing body 17 is formed of, for example, an epoxy resin to which a phenol curing agent, silicone rubber, a filler, and the like are added for the purpose of reducing stress. In forming the resin sealing body 17, a transfer molding method suitable for mass production is used. The transfer molding method is a method of using a molding die having a pot, a runner, an inflow gate, a cavity, and the like, and injecting a resin from the pot into the cavity through the runner and the inflow gate to form a resin sealing body. .
A plurality of leads 2 arranged along each side of the resin sealing body 17 are arranged around the main body LSI 10. Each of the leads 2 has an internal lead (inner lead) and an external lead (outer lead) formed integrally with the internal lead. The internal lead portion of each lead 2 is located inside the resin sealing body 17, and the external lead portion is located outside the resin sealing body 17. That is, the plurality of leads 2 extend inside and outside the resin sealing body 17. The external lead portion of each lead 2 is formed by bending into, for example, a gull-wing type lead shape, which is one of the surface mount type lead shapes.
In this embodiment, the main body LSI 10 is provided with the identification number generation circuit generated based on the magnitude relationship between the logic thresholds of the CMOS inverter circuit as described above. When such a CMOS inverter circuit is used, it is necessary to supply an operating voltage to the main body LSI and to input a control signal for operating the identification number generating circuit. For this purpose, a special power supply device and a signal readout device are required although the configuration is simple.
When the semiconductor integrated circuit device is in the distribution channel, it often happens that the identification number is known and the operating voltage cannot be supplied under the environment. The idea of the present application is to judge a magnitude relationship of physical quantities corresponding to process variations of a plurality of identification elements having the same form in a process of manufacturing a semiconductor integrated circuit device. The semiconductor integrated circuit device has a plurality of leads, and the lead width d is formed by pressing or the like so as to be uniform.
However, process variations occur in the widths d1, d2, etc. of the plurality of leads. Therefore, the lead widths d1, d2, etc. of a plurality of leads are measured by an optical device and their magnitudes are compared to be used for generating an identification number using process variation similarly to the logic threshold value of the CMOS inverter circuit. Things. In this configuration, a plurality of lead widths of the leads are measured by the measuring device, and the magnitude relation therebetween is determined, whereby the identification number unique to the semiconductor integrated circuit device similar to the above can be determined.
That is, 16 leads are determined before shipment of the semiconductor integrated circuit device as described above, the width of the leads or the pitch between the leads is measured, and the positional information and the magnitude relationship are stored in a database and held. Let it. When measuring the lead width pitch, it is desirable to perform the measurement at a portion where the lead 2 projects from the package 17. Since this measurement can be performed in a single time by the optical device, it does not take much time to determine the identification number at the time of shipment.
The present invention can be applied to a semiconductor integrated circuit device without a CMOS circuit, and a semiconductor integrated circuit device having a CMOS circuit may be used in combination with an electrical identification number of the CMOS inverter circuit. The determination of the identification number can be made more reliable by comprehensively determining such two types of physical quantity variations.
FIG. 43 is a basic circuit diagram of another embodiment of the identification number generating circuit according to the present invention. In the above-described embodiment, the identification number is determined by the order of the logical threshold value of the variation of the plurality of CMOS inverter circuits by the circuit represented by FIG. On the other hand, in this embodiment, the comparison result of the logical threshold values of the two CMOS inverter circuits INV1 and INV2 is 1 bit of the identification number. This idea is also used in the embodiment of FIG.
In this embodiment, the comparison between the logic threshold values of the two CMOS inverter circuits INV1 and INV2 is performed as follows. An N-channel MOSFET Q2 for short circuit is provided between the input terminal and the output terminal of the inverter circuit INV1. Although not particularly limited, a P-channel MOSFET Q1 is provided between the input terminal of the CMOS inverter circuit INV1 and the power supply voltage VDD. The identification number circuit enable signal EN is supplied to the gates of these MOSFETs Q1 and Q2.
An output terminal of the inverter circuit INV1 is connected to an input terminal of the inverter circuit INV2. The output signal of the inverter circuit INV2 is binarized by an amplifier circuit composed of cascade circuits of similar CMOS inverter circuits INV3 to INV5, and an identification number output is formed from an output terminal OUT.
When the identification number circuit enable signal EN is at low level, the circuit is inactive, the MOSFET Q1 is turned on, and a high level corresponding to the power supply voltage VDD is supplied to the input terminal of the CMOS inverter circuit INV1. At this time, the MOSFET Q2 is turned off, the output signal of the inverter circuit INV1 is set to the low level, and thereafter, the inverted signals are sequentially transmitted from the inverter circuit rows INV2 to INV5 in the order of high level, low level.
The characteristics of the MOSFET constituting the CMOS inverter circuit may be undesirably changed depending on the application state of the gate bias voltage. The P-channel MOSFET and the N-channel MOSFET are relatively large in characteristics due to the influence of the NBTI phenomenon described in FIG. Variations are likely to occur.
43. The pull-up MOSFET Q1 which is turned on when the identification number circuit of FIG. 43 is inactive is used to prevent the through current of the first-stage CMOS inverter circuit and to reduce the gate potential of the P-channel MOSFET in the first-stage CMOS inverter circuit. By maintaining the source potential, that is, the power supply potential level, at a high potential, it has an effect of sufficiently suppressing the characteristic fluctuation of the P-channel MOSFET.
When the identification number circuit is activated, that is, when the identification number is generated, the signal EN is set to the high level. As a result, the input and output of the CMOS inverter circuit INV1 are short-circuited by the MOSFET Q2, and a voltage corresponding to the logical threshold voltage is generated. The voltage corresponding to the logical threshold value of the CMOS inverter circuit INV1 is supplied to the input terminal of the CMOS inverter circuit INV2. The CMOS inverter circuit INV2 compares its own logical threshold voltage with the voltage corresponding to the logical threshold value of the CMOS inverter circuit INV1.
When the logical threshold value of the inverter circuit INV1 is lower than that of the inverter circuit INV2, the output potential becomes higher than the logical threshold voltage of the inverter circuit INV2. Subsequently, the output signal of the inverter circuit INV2 is amplified by the inverter circuits INV3, INV3, and INV5, and the potential of the node N5 becomes close to VSS. Conversely, when the logical threshold value of the inverter circuit INV1 is higher than that of the inverter circuit INV2, the output potential thereof becomes lower than the logical threshold voltage of the inverter circuit INV2. Subsequently, the output signal of the inverter circuit INV2 is amplified by the inverter circuits INV3, INV3, and INV5, and the potential of the node N5 becomes close to VDD.
FIG. 44 is a circuit diagram showing another embodiment of the identification number generating circuit according to the present invention. In the figure, two circuits corresponding to the operation state 1 and the operation state 2 are shown together for explaining the characteristic of the operation.
As in the embodiment described with reference to FIG. 43, in the case where the identification information is obtained by the logical threshold difference between the two CMOS inverter circuits INV1 and INV2, the reproducibility of the output signal is guaranteed even when the difference is small. is important. In particular, it is necessary to consider that the threshold voltage of the P-channel MOSFET (not the logical threshold value of the CMOS inverter circuit) fluctuates due to the phenomenon of NBTI which has become prominent in recent devices. That is, the threshold voltage of the P-channel MOSFET of one of the two CMOS inverter circuits fluctuates due to the phenomenon of NBTI, and the logical threshold value of the CMOS inverter circuit is also affected. If the difference between the logical thresholds of the two CMOS inverter circuits is reversed, there arises a problem that the reliability of the identification information generated thereby is reduced.
In this embodiment, a latch and a feedback path are added in order to guarantee the reproducibility of the identification number and to increase the resistance to aging. That is, the output signal of the inverter circuit INV5 constituting the above-described amplifier circuit is transmitted to the input of the CMOS inverter circuit INV6 on the input side constituting the latch circuit via the switch SW1. The output signal of the inverter circuit INV6 is transmitted to the input of the inverter circuit INV7, and the output signal of the inverter circuit INV7 is fed back to the input of the inverter circuit INV6 through the switch SW2. The output signal of the inverter circuit INV7 is fed back to the input of the inverter circuit INV1 via the switch SW3.
Operation state 1 of FIG. 44 shows an operation of generating identification information, in which the switch SW0 is turned on to short-circuit the input and output of the CMOS inverter circuit IVN1 to correspond to the logical threshold voltage. A voltage is generated at output node N1. As described above, the voltage corresponding to the logical threshold value of the CMOS inverter circuit INV1 is input to the CMOS inverter circuit INV2, so that the difference between the logical threshold voltages is applied to the output node N2 of the CMOS inverter circuit INV2. Are obtained and amplified by the CMOS inverter circuits INV3 to INV5 constituting the amplifier circuit.
When the logical threshold value of the inverter circuit INV1 is lower than that of the inverter circuit INV2, the potential of the node N2 becomes higher than the logical threshold voltage of INV2. Subsequently, the difference between the potential of INV2 and the logic threshold is amplified by the inverter circuits INV3, INV4, and INV5, and the potential of the node N5 becomes close to VSS. At this time, the switch SW1 of the latch circuit is turned on, and the switch SW2 is turned off. The amplified signal is transmitted through the switch SW1 in the on state, and the input node N6 of the inverter circuit INV6 and the output node of the inverter circuit INV6 are output. N7 and the potential of the output node N8 of the inverter circuit INV7 are VSS, VDD, and VSS, respectively.
The operation state 2 in FIG. 44 indicates a feedback operation, in which the switch SW1 of the latch circuit is turned off, the switch SW2 is turned on, and the above state is maintained. The switch SW0 is turned off and the switch SW3 is turned on, and the voltage held at the node N8 is fed back to the input of the CMOS inverter circuit IVN1.
Thereby, the gate input of the inverter circuit INV1 becomes the node N8, that is, the VSS potential. Further, the gate input of INV2 becomes VDD. That is, the gate potential of the P-channel MOSFET of the inverter circuit INV1 is VSS. This is a condition for accelerating NBTI for the P-channel MOSFET. If this state is maintained for a long time, the threshold voltage (not the logical threshold) of the MOSFET tends to gradually increase. There is no assurance that it will be higher, but at least it is not. When the threshold value of the P-channel MOSFET of the inverter circuit INV1 fluctuates to be higher, the logical threshold voltage of the inverter circuit INV1 becomes relatively lower in relation to the N-channel MOSFET.
On the other hand, as for the P-channel MOSFET of the inverter circuit INV2, the gate potential is VDD, which is a condition under which the acceleration of NBTI is unlikely to occur, so that the change in the logical threshold voltage of the inverter circuit INV2 is relatively small. small. That is, the logic threshold value of the inverter circuit INV1 changes to be low due to the continuation of the operation state 2, and the difference of the original threshold value is relatively enlarged to maintain that of the inverter circuit INV2. Become. As a result, even when the difference between the logic threshold values is small, the reproducibility of the identification bits having low reproducibility is improved, and an identification number generating circuit having high resistance to aging can be realized.
Note that when the logical threshold value of the inverter circuit INV1 is higher than that of the inverter circuit INV2, the potential of the node N2 becomes lower than the logical threshold voltage of INV2. Therefore, in the feedback operation, the node N8 is amplified to the VDD potential. The gate input of INV2 is VSS. That is, the gate potential of the P-channel MOSFET of the inverter circuit INV2 is VSS. This is a condition for accelerating NBTI for the P-channel MOSFET. If this state is maintained for a long time, the threshold voltage (not the logical threshold) of the MOSFET tends to gradually increase as described above. . There is no assurance that it will be higher, but at least it is not. When the threshold value of the P-channel MOSFET of the inverter circuit INV2 fluctuates so as to increase, the logical threshold voltage of the inverter circuit INV2 relatively decreases in relation to the N-channel MOSFET.
On the other hand, as for the P-channel MOSFET of the inverter circuit INV1, the gate potential is VDD, which is a condition under which the acceleration of NBTI is unlikely to occur. Therefore, the change in the logical threshold voltage of the inverter circuit INV1 is relatively small. small. In other words, the logical threshold value of the inverter circuit INV2 fluctuates low due to the continuation of the operation state 2, and the difference between the original threshold values is relatively enlarged to maintain that of the inverter circuit INV1. Become. As a result, even when the difference between the logic threshold values is small, the reproducibility of the identification bits having low reproducibility is improved, and an identification number generating circuit having high resistance to aging can be realized.
In FIG. 44, in order to prevent the operation state 2 from being changed to an erroneous state, a power supply reset circuit or an initialization circuit such as a power supply reset circuit or an initialization circuit in the semiconductor integrated circuit device is used when the semiconductor integrated circuit device is started up every time the power is turned on. The circuit first starts the first operating state and then transitions to the second operating state. As a result, an appropriate feedback operation can be performed regardless of the power supply startup characteristics of the inverter circuits INV6 and INV7 themselves.
FIG. 45 is a specific circuit diagram of one embodiment of the identification number generating circuit according to the present invention. In this embodiment, CMOS switches in which an N-channel MOSFET and a P-channel MOSFET are connected in parallel are used as the switches SW0 to SW3. In addition, a CMOS switch and a P-channel MOSFET that is pulled up to the power supply voltage VDD are provided at each input terminal of each of the inverter circuits INV3 to INV5 constituting the inverter circuit INV2 and the amplifier circuit.
The feedback control signal FB is used not only for controlling the switches SW1 to SW3 of the latch circuit but also for controlling the switch SW0 for short-circuiting the input and output of the inverter circuit INV1. That is, the output signal of the inverter circuit INV10 that forms the inverted signal of the feedback signal FB is supplied to one input of the NAND gate circuit G1 in addition to the control of the CMOS switches SW1 to SW3 as described above. The signal EN is supplied to the other input of the NAND gate circuit G1, and the switch SW0 is controlled by the output signal of the NAND gate circuit G1 and the inverted signal formed by the inverter circuit INV9.
In the circuit of this embodiment, when the power supply voltage is supplied to the semiconductor integrated circuit device or the semiconductor chip on which the identification number circuit is mounted and the signal EN is at a low level, the P-channel MOSFETs Q11 to Q15 are turned on, and each CMOS A high level such as the power supply voltage VDD is supplied to the input terminal of the inverter circuit. At this time, the switches provided at the input terminals of the CMOS inverter circuits INV2 to INV5 are turned off by the low level of the signal EN and the high level of the inverted signal by the inverter circuit INV8, and the cascade connection between the inverter circuits is performed. Is disconnected, the voltage level of the input terminal is set to a high level corresponding to the ON state of the MOSFETs Q11 to Q15.
This means that the threshold voltage (the logic of the CMOS inverter circuit) of the P-channel MOSFET constituting the CMOS inverter circuit in a state where the identification number is not taken out when the power is supplied to the semiconductor integrated circuit device or the semiconductor chip. (Not the threshold value) is prevented from fluctuating due to the NBTI phenomenon.
When the signal EN is changed from the low level to the high level, the switches for connecting the inverter circuits INV1 to INV5 in the cascade form are turned on, and the output signal of the gate circuit G1 is turned to the low level to turn on the switch SW0. Thus, a signal obtained by amplifying a difference voltage between the logical threshold voltage of the CMOS inverter circuit INV1 and the logical threshold voltage of the inverter circuit INV2 is obtained from the output of the inverter circuit INV5. When the signal FB is at the low level, the switch SW0 is in the ON state, and the output signal of the inverter circuit INV5 is taken into the inverter circuits INV6 and INV7 constituting the latch circuit.
When the signal FB is changed from the low level to the high level in the above state, the switch SW1 is turned off, the switches SW2 and SW3 are turned on in the latch circuit, and the acquired identification information is held, and the corresponding signal is output. By feeding back to the input of the inverter circuit INV1 through the switch SW3, the input voltages of the inverter circuits INV1 to INV5 are set to assure or stabilize the identification number using the NBTI in reverse as described above. At this time, the output signal of the NAND gate circuit G1 returns to the high level due to the high level of the signal FB, and the switch SW0 that short-circuits the input and output of the inverter circuit INV1 is turned off.
Since the input voltages of the inverter circuits INV4, INV5, etc. constituting the amplifying circuit have a large difference voltage from the logical threshold voltage, it is considered that the NBTI is not substantially affected as described above. However, by using the same circuit configuration as the inverter circuits INV2, INV3, etc., the same circuit cell can be used to form a circuit on the semiconductor integrated substrate, which is advantageous in using the soft IP technology described later. .
FIG. 46 is a specific circuit diagram of still another embodiment of the identification number generating circuit according to the present invention. This embodiment is an extension of the 1-bit identification number generating circuit as shown in FIG. 44 and the like. The present embodiment is directed to a circuit that generates an 8-bit identification number with a small number of circuit elements.
In this embodiment, the constants and layout shapes of all the CMOS inverter circuits in the circuit diagram are the same. That is, the unit circuit (cell) includes a CMOS inverter circuit, a CMOS switch provided at the input terminal thereof, and a CMOS switch for short-circuiting the input terminal and the output terminal. Each unit circuit is connected in cascade by a CMOS switch provided at the input terminal. In the figure, four unit circuits are connected in a cascade. A power supply voltage is supplied to the first-stage circuit of the four unit circuits via the CMOS switch.
Two cascaded circuits as described above are provided in parallel, and two CMOS switches of a CMOS inverter circuit arranged at corresponding positions receive a selection signal X0 and its inverted signals X0 / to X3 and its inverted signal X3 /. Supplied in common. Thus, the unit circuits are arranged in a matrix in a signal transmission direction connected in cascade and in a direction orthogonal to the signal transmission direction.
A switch is provided at the output terminal of the final stage circuit of the two cascade circuits, and selection signals Y0, Y0 / and Y1, Y1 / for selecting one of the cascade circuits are supplied. Inverter circuits INV4 and INV5 constituting the above-described amplifier circuit are provided, and an erroneous identification number output is output from the output terminal OUT. The input of the inverter circuit INV4 is provided with a P-channel MOSFET which is controlled by the signal PON and supplies a power supply voltage to the input terminal of the inverter circuit INV4 for the above-mentioned NBTI measure.
FIG. 47 is a timing chart for explaining the operation of the embodiment of FIG. 46.
1) When the power-on signal PON is at a low level, the selection signals X0 to X3 are at a low level, their inverted signals X0 / to X3 / are at a high level, Y0 and Y1 are at a low level, and their inverted signals Y0 / and Y1 are at a low level. / Is high level. In the outputs of the CMOS inverter, INV00, 20, and INV01, INV21 and INV4 are at a low level, and INV10, INV30 and INV11, INV31, and INV5 are at a high level.
2) When the power-on signal PON transitions to a high level, the selection signal X0 goes to a high level, X0 / goes to a low level, Y0 goes to a high level, and Y0 / goes to a low level. The inputs of the inverter circuits INV00 and INV01 are disconnected from the power supply voltage VDD, and the respective inputs and outputs are short-circuited by a CMOS switch that is turned on from the high level of the selection signal X0 and the low level of X0 /, and the inverter circuits INV00 and INV01 are shorted. Is a voltage corresponding to the logical threshold value.
If the relationship between the logical threshold value VLT (INV00) of the inverter circuit INV00 and the logical threshold value VLT (INV10) of the inverter circuit INV10 at the next stage is VLT (INV00)> VLT (INV10), the inverter circuit INV10 The output voltage has a large amplitude on the VSS potential side, that is, on the low level side due to the inverting amplification effect of the inverter circuit INV10. Conversely, if VLT (INV00) <VLT (INV10), the amplitude greatly increases toward the VDD potential, that is, toward the high level. The output amplitudes of the inverter circuits INV10 and INV11 are further amplified by the next-stage inverter circuits INV20 to INV30 and INV21 to INV31.
The output of the inverter circuit INV30 passes through a CMOS switch selected by the selection signals Y0, Y0 /, further passes through an amplifier circuit including two-stage CMOS inverter circuits INV4 and INV5, and is output to an output terminal OUT. After all, if VLT (INV00)> VLT (INV10), a low level is output to the output terminal OUT, and if VLT (INV00) <VLT (INV10), a high level is output to the output terminal OUT.
3) Next, the selection signal transits, and X0 goes low (X0 / is high) and X1 goes high (X0 / is low). The inputs of the inverter circuits INV10 and INV11 are disconnected from the outputs of the preceding inverter circuits INV00 and INV01 when the CMOS switch provided at the input terminal is turned off by the high level of X1 (low level of X0 /), and The output is short-circuited by the CMOS switch, and the output of the inverter circuits INV10 and INV11 becomes a logical threshold. If the relation between the logical threshold value VLT (INV10) of the inverter circuit INV10 and the logical threshold value VLT (INV11) of the inverter circuit INV11 at the next stage is VLT (INV10)> VLT (INV20), the relation of the inverter circuit INV20 is satisfied. The output voltage has a large amplitude on the VSS potential side, that is, on the low level side due to the inverting amplification effect of the inverter circuit INV20. Conversely, if VLT (INV10) <VLT (INV20), the output voltage of the inverter circuit INV20 has a large amplitude on the VDD potential side, that is, on the high level side, due to the inverting amplification effect of the inverter circuit INV20.
Each of the output amplitudes of the inverter circuits INV20 and INV21 is further amplified by the next-stage inverter circuits INV30 and INV31. The output of the inverter circuit INV30 passes through the CMOS switch selected by the selection signals Y0, Y0 /, further passes through two-stage CMOS inverter circuits INV4 and INV5, and is output to the output terminal OUT.
After all, if VLT (INV10)> VLT (INV20), a high level is output to the output terminal OUT, and if VLT (INV10) <VLT (INV20), a low level is output to the output terminal OUT. Here, the correspondence between the magnitude before and after the logical threshold value of the CMOS inverter circuit and the value of the output terminal OUT is reversed in the cases 2) and 3). This is because the number of inverter circuits connected by the CMOS switches, that is, the number of CMOS inverter circuits for amplifying the logical threshold voltage difference is different.
4) Next, the selection signal transits, and X1 goes low (X1 / goes high) and X2 goes high (X2 / goes low). Similarly, the inputs of the inverter circuits INV20 and INV21 are disconnected from the outputs of the inverter circuits INV10 and INV11 in the preceding stage due to the OFF state of the CMOS switch, the respective inputs and outputs are short-circuited by the CMOS switches, and the outputs of the inverter circuits INV20 and INV21. Is a logical threshold.
The subsequent operation conforms to the above 2).
5) Next, the selection signal transits, and X goes low (X2 / goes high) and X3 goes high (X3 / goes low). As described above, the inputs of the inverter circuits INV30 and INV31 are turned off by the CMOS switch, disconnected from the outputs of the inverter circuits INV20 and INV21 in the preceding stage, the respective inputs and outputs are short-circuited by the CMOS switches, and the inverter circuits INV30 and INV31 are turned off. Is a logical threshold. If the relation between the logical threshold value VLT (INV30) of the inverter circuit INV30 and the logical threshold value VLT (INV4) of the inverter circuit INV4 at the next stage is VLT (INV30)> VLT (INV4), the relation of the inverter circuit INV4 is satisfied. The output voltage has a large amplitude on the VSS potential side, that is, on the low level side, due to the inverting amplification effect of the inverter circuit INV5. Conversely, if VLT (INV30) <VLT (INV4), the amplitude greatly increases toward the VDD potential, that is, toward the high level.
After all, if VLT (INV30)> VLT (INV4), a high-level output is output to the output terminal OUT, and if VLT (INV30) <VLT (INV4), a low-level output is output to the output terminal OUT.
6) In the subsequent transition, the selection signal Y0 is at the low level (Y0 / is at the high level), and Y1 is at the high level (Y1 / is at the low level), and the operations according to the above 2) to 5) are performed. As a result, an identification number consisting of 4 × 2 = 8 bits is output.
This embodiment is characterized in that it serves as both an inverter circuit for generating an identification number and an amplification circuit, and that the identification number is serially output by a read operation. This makes it possible to simplify the circuit, and is suitable for a case where an identification number is serially output from one terminal.
FIG. 48 is a circuit diagram of another embodiment of the unit circuit used in the embodiment of FIG. In this embodiment, the above-mentioned NBTI countermeasures are taken. In other words, in addition to the CMOS switch for cascading the inverter circuits as described above, a CMOS switch for disconnecting the input terminal from the preceding circuit when the identification number circuit is inactive is added to the input terminal of the inverter circuit. Is done. The input end is provided with a P-channel MOSFET for supplying a power supply voltage to the input terminal.
In the unit circuit of this embodiment, when the power-on signal PON is at the low level, that is, when the power supply voltage is supplied and the identification number is not read from the identification number generation circuit, the signal PON is set to the low level and the input terminal of each inverter circuit is set. Is separated from the preceding circuit irrespective of the selection signals X0, X0 / and the like, and the power supply voltage VDD is supplied by a P-channel MOSFET.
FIG. 49 is a circuit diagram showing still another embodiment of the identification number generating circuit according to the present invention. In this embodiment, the unit circuits shown in FIG. 46 are connected in cascade in one column, and a selection signal is formed using a binary counter and a decoder. That is, the count-up clock is counted by the binary counter, the count output is supplied to the decoder provided corresponding to each unit circuit, and the selection signals X0 (X0 /) to Xn (Xn /) are sequentially output from the first stage circuit. Generate.
FIG. 50 is a circuit diagram showing still another embodiment of the identification number generating circuit according to the present invention. In this embodiment, the unit circuits shown in FIG. 46 are connected in cascade in one column, and a selection signal is formed using a shift register. That is, a shift register (for one stage) is provided corresponding to each unit circuit, and the selection signal is sequentially shifted so that the above-described selection operation is performed in order from the first unit circuit.
In any of the embodiments shown in FIGS. 49 and 50, design, expansion, and mounting are facilitated by using the one enclosed by a broken line as one unit circuit. In particular, in the circuit of the embodiment shown in FIG. 50, when extending the number of bits of the identification number, it is only necessary to connect three types of signal lines consisting of cascade connection lines of unit circuits, shift clocks, and resets. Since it has a high degree of freedom, it is suitable for soft IP as described later.
FIG. 51 is a circuit layout diagram of an embodiment of a semiconductor integrated circuit device or a semiconductor chip to which the present invention is applied. The figure simulates a general system LSI chip. Usually, an I / O cell (input / output circuit) is provided in a peripheral portion of the chip, and a plurality of circuits according to the function of the system LSI are provided as built-in circuits. Are provided.
FIG. 52 shows a block diagram of a standard embodiment of the above-mentioned I / O cell, which is composed of an output buffer circuit, an input buffer circuit, and a bonding pad (PAD) provided corresponding thereto. . The output buffer circuit and the input buffer circuit perform an input operation or an output operation under the control of an input / output control signal.
FIG. 53 is a circuit layout diagram of an embodiment of an I / O cell provided in a semiconductor integrated circuit device or a semiconductor chip according to the present invention. In this embodiment, an output prebuffer circuit for driving an output MOSFET is provided. The output buffer circuit shown in FIG. 52 includes the output prebuffer circuit and the output MOSFET.
The bonding pad is formed with a relatively large occupied area for wire bonding. The output MOSFET, output prebuffer circuit, and input buffer circuit are laid out so as to conform to this. Thus, the I / O cells can be efficiently arranged corresponding to the pitch of the bonding pads.
As described above, since the I / O cell has a relatively large occupied area, the 1-bit identification as shown in the above-described embodiment is indicated by hatching a part of the output pre-buffer circuit or the output MOSFET. A number generation circuit can be fitted.
FIG. 54 is a circuit diagram showing one embodiment of an output buffer circuit provided in a semiconductor integrated circuit device or a semiconductor chip according to the present invention. In this embodiment, the 1-bit identification number generating circuit is added to the output buffer circuit.
In this embodiment, when the identification number circuit enable signal is activated (the normal output enable is inactive at that time), a 1-bit identification number is output from a buffer provided in parallel with the normal output buffer circuit. Since the buffer may have a small driving capability, a MOSFET having a smaller size than the output MOSFET of the normal circuit is sufficient. In this configuration, a special output terminal for outputting the identification number becomes unnecessary, and the identification number consisting of multiple bits is provided by using a large number of input / output terminals or input / output pads provided on the semiconductor integrated circuit device or the semiconductor chip. Can be taken out.
FIG. 55 is a circuit diagram showing another embodiment of the output buffer circuit provided in the semiconductor integrated circuit device or semiconductor chip according to the present invention. Also in this embodiment, the 1-bit identification number generating circuit is added to the output buffer circuit. In this embodiment, the identification number is output using the normal output buffer circuit. That is, a gate circuit is added to the output prebuffer circuit to selectively output the normal output and the identification number. The identification number circuit enable signal may be generated from a dedicated pin of the LSI, or may be generated by a special DFT function. This is the same in the embodiment shown in FIG.
In recent years, the adoption of JTAG (Joint Test Action Group) in logic LSIs has been widespread. The JTAG standard also has an IDCODE function for registering and reading LSI identification numbers. However, since the number of bits is as small as 32 bits, and each bit is specified in detail so as to identify a device and a manufacturer, it cannot be used as an identification number of an individual chip.
FIG. 56 is a schematic configuration diagram of one embodiment of the semiconductor integrated circuit device according to the present invention. In this embodiment, it is devised to output an identification number using a JTAG interface.
A JTAG-compatible device (semiconductor integrated circuit device) includes a boundary scan register, an instruction register, an option register, a bypass register, and a TAP controller that controls these, in addition to the built-in logic for performing the original functions of the semiconductor integrated circuit device. Built-in test logic.
A serial interface for inputting / outputting an instruction to the test logic, test data, test result data, and the like is called a TAP (Tset Access Port) and has five signal lines. The JTAG test is performed by controlling this signal line with an external host computer or the like.
FIG. 57 is a block diagram showing basically one embodiment of a JTAG cell of the semiconductor integrated circuit device according to the present invention. In this embodiment, a 1-bit identification number generation circuit is incorporated in a cell constituting a JTAG boundary scan register. The JTAG cell may be incorporated in the I / O cell shown in FIG. 51 or the like, or may be incorporated in the built-in logic.
A serial output using the shift operation of the boundary scan register is performed by adding, to the cells of the boundary scan register, a circuit for switching and inputting a signal from the built-in logic and the identification information generated by the 1-bit identification number generation circuit. You can do so.
FIG. 58 is a configuration diagram for explaining an embodiment of the serial number output operation of the identification number utilizing the shift operation of the boundary scan register of the semiconductor integrated circuit device according to the present invention.
In this embodiment, there are three LSIs (A to C) and seven, seven, and nine JATG cells (boundary scan registers), and data is shown in each cell to indicate the flow of data. The number of the number is attached. FIG. 4 shows an example of an operation of reading an identification number from an identification number generation circuit (ID-ROM) mounted on LSI-B as a representative.
State 1 is an initial state, and indicates an operation state in JTAG.
In the state 2, the TDO of the LSI-B is disconnected from the JTAG cell by a JTAG private instruction, for example, and is connected to the identification number generation circuit ID-ROM.
In state 3, the identification number generation circuit ID-ROM performs a shift operation according to the JTAG shift instruction, and the identification numbers are sequentially output from the TDO. The figure shows a state in which 3-bit identification number information (I, II, III) has been sent. Note that the JTAG cell in each LSI is shifted rightward as usual, and the identification number of the LSI-B is output through the LSI-C.
After taking out the identification number, although not shown, the mode returns from the private instruction mode to the normal automatic mode, and the TDO is connected to the JTAG cell.

However, if necessary, repeat the shift in normal mode,

FIG. 59 is a block diagram for explaining another embodiment of the serial number output operation of the identification number utilizing the shift operation of the boundary scan register of the semiconductor integrated circuit device according to the present invention. The difference from the embodiment of FIG. 58 is that in state 3, only the JTAG cell of the LSI-C is shifted. As a result, in the embodiment of FIG.

It can be as a result of inserting ID-ROM information between JTAG cell information of LSI-B and LSO-C.
FIG. 59 is a block diagram for explaining another embodiment of the serial number output operation of the identification number utilizing the shift operation of the boundary scan register of the semiconductor integrated circuit device according to the present invention. The identification number generation circuit (ID-ROM) of this embodiment corresponds to the identification number generation circuit shown in FIG.
State 1 is an initial state.
In state 2, the information of the 1-bit identification number generating circuit is transferred to the JTAG cell of LSI-B by, for example, a JTAG private instruction. At this time

It is destroyed because it is replaced.
In state 3, the ID number of the ID-ROM is sequentially output from the TDO of the LSI-B according to the JTAG shift instruction.
FIG. 61 is a block diagram for explaining another embodiment of the serial number output operation using the shift operation of the boundary scan register of the semiconductor integrated circuit device according to the present invention. In this embodiment, a shift register (ID register cell) dedicated to an identification number is incorporated.
State 1 is an initial state.
In the state 2, the TDO of the LSI-B is disconnected from the JTAG cell and connected to the head of a shift register dedicated to another number, for example, by a JTAG private instruction. The tail of the shift register dedicated to the identification number is connected to the head of the JTAG cell of the LSI-B. At the same time, the identification number is set in the shift register dedicated to the identification number.
In state 3, the ID number of the ID-ROM is sequentially output from the TDO of the LSI-B according to the JTAG shift instruction. At the same time, the JTAG cell information of the LSI-A is shifted into the shift register dedicated to the JTAG cell information of the LSI-B and the identification number.
Although not shown, the shift is further continued, and after all the valid JTAG cell information of the LSI-B is shifted out, the state is returned to the initial state.
FIG. 62 is a circuit diagram showing still another embodiment of the identification number generating circuit according to the present invention. In this embodiment, identification information obtained by amplifying the logical threshold voltage difference between the CMOS inverter circuits INV1 and INV2 as described above by an amplifier circuit is held in a latch circuit composed of a NAND gate circuit. That is, from the high level of the first write signal WRITE1, binary identification information corresponding to the logical threshold voltage difference between the inverter circuits INV1 and INV2 is input to the latch.
Next, the first write signal WRITE1 is set to a low level to hold the binary identification information in the latch circuit, and the inverter circuit train including the inverter circuits INV1 and INV2 and the amplifier circuit includes an input-stage inverter circuit. A high level formed by a pull-up MOSFET is supplied to the input of INV1.
Next, using the second write signal WRITE2 and the high voltage VPP, the information held in the latch circuit is written into, for example, a nonvolatile programmable device such as a fuse (FUSE, EEPROM, or the like). When the identification number is required, the programmable device is accessed by the signal RD, and the written identification number is output as read data.
In this configuration, since the identification information corresponding to the logical threshold voltage difference between the inverter circuits INV1 and INV2 in the first write signal WRITE1 is recorded in another nonvolatile circuit, it is affected by the NBTI. Thus, it is possible to obtain an identification number generating circuit that maintains the reproducibility of the identification bits and has high resistance to aging.
In the identification number generation circuit using the variation of the logic threshold value of the CMOS inverter circuit as in the above embodiment, the order of the magnitude of the threshold value of each element is used as the source of the identification information.
FIGS. 63 and 64 show examples of four identification numbers. FIG. 63 is a graph showing the order of the threshold values. In FIG. 64, the element with the identification number (CMOS inverter circuit) has the highest order among the 16 elements, and 10 is the lowest. This means that the logical threshold value of the element 1 is the highest and the logical threshold value of the element 10 is the lowest. Now, focusing on the element 1 and the element 10, the element closest to the element 1 is the element 5 and the element closest to the element 10 is the element 9.
In the identification number generating circuit according to the present invention, the variation of the logic threshold value of the CMOS inverter circuit is ranked, so that, for example, how much the logic threshold voltage difference exists between element 1 and element 5 Is unknown. Similarly, the area between the element 10 and the element 9 is unknown. If the difference between them is extremely small, the order of the element 1 and the element 5 may be changed depending on test conditions. However, the possibility that the element 1 and the element 10 are interchanged is considered to be extremely low. It is easy to understand from the graph of FIG.
The identification number acquired at the time of collation has been acquired at least once in the past, stored in the database, and should exist in a form very similar to the identification number. "Similar" means that, as described above, in the identification number generating circuit of the present invention, the case where the identification number is not completely reproduced due to the influence of aging or the like is considered. As described above, in the example of FIG. 64, at least the order of the elements 1 and 10 is at least the identification number obtained in the past even if the order of the variation between the CMOS inverter circuits is partially changed. It can be easily estimated that the magnitude relation of the latest identification number has not changed.
FIG. 65 is a flowchart for explaining one embodiment of a high-speed identification number collation (search) algorithm for the identification numbers generated by the identification number generating circuit according to the present invention. FIG. 66 shows a configuration diagram corresponding thereto.
{Circle around (1)} In the step of reading the identification number, the 1-bit identification number generation circuit composed of "0" and "1" is continuous data generated from each of them.
{Circle around (2)} In the rank analyzing step, the data is converted into a number representing the rank. That is, the order of the 1-bit identification number generating circuit as shown in FIG. 64 is converted into a number.
{Circle around (3)} In the maximum / minimum element extraction step, the order is analyzed to extract and record the numbers of the element of the maximum order and the element of the minimum order.
In step (4), one registered identification number is extracted from the management ledger.
In (5), the order of the element numbers corresponding to the maximum and minimum element numbers recorded above among the registered identification numbers is extracted. For example, in the example of FIG. 64, the identification number 1 has a maximum of 1 and a minimum of 10, but when the numbers 1 and 10 are compared, the relationship between the magnitudes is reversed. Since this is a phenomenon in which the order far exceeds the fluctuation due to the variation or the like, the identification number can be easily estimated that the identification number 1 is obtained from a different chip. Therefore, the identification number 1 is determined to be non-conforming, and the subsequent detailed collation inspection is omitted.
Those that are determined to be suitable in the above are subjected to detailed inspections in (6) and (7). Basically, it is omitted because it is the same as the above embodiment. The identification number having the highest similarity is set as a matching candidate. In (5), in the comparison of ranks, the proportion of occurrences of probability matching and non-matching is 50%, so that the effect of omitting the detailed inspection is almost 50%.
Thus, in this embodiment, one set of magnitude comparisons is used. By using two sets of comparisons, the effect can be expected to be further doubled. However, if the number is increased, the size comparison process itself may increase and the effect may be degraded. Therefore, it is desirable to select the number in consideration of the number of digits of the identification number and the total number of identification numbers.
FIG. 67 is a flow chart of one embodiment of a method for designing a circuit of a semiconductor chip incorporating an identification number generating circuit according to the present invention. The circuit design software as in this embodiment is provided to a design company or a manufacturing company. Alternatively, the same function is incorporated in an EDA vendor's tool.
(1) Pull down the menu and select it.
(2) Menu data is generated. After the second time, a desired IP can be selected only by specifying this menu data.
(3) Analyze menu data to detect violations and the like.
(4) Extract necessary information from the local database according to the menu data. The latest information not in the local database is obtained from a database of a specialized manufacturing company through a network such as the Internet.
(5) Based on the information collected from the database, a process for generating data necessary for the soft IP is performed.
(6) Determine whether a soft IP can be generated. If not, choose a hard IP design.
FIG. 68 is a flow chart of one embodiment of an LSI design method incorporating an identification number generating circuit according to the present invention. In this embodiment, although not particularly limited, the present invention is directed to a design flow of an application-specific LSI (ASIC).
The logic synthesis tool generates a gate-level logic circuit (netlist) from a truth table, an RTL description, a state transition diagram, and the like, based on the determination result of the soft IP generation in the design flow shown in FIG. 67. Although not shown, in many cases, RTL or the like is generated based on a functional description language such as VHDL or Verilog HDL. What is required at the time of logic synthesis is cell library information, which includes connection information at the transistor level, delay information, layout information, and the like. In addition, information such as a timing error allowable value, a layout arrangement interval, and a maximum signal wiring length, which are called constraint information, are added to the normal RTL or the like. The DFT tool adds diagnostic logic effective for LSI inspection to a gate-level logic circuit, and creates final layout data using an automatic placement and routing tool.
The types of cells registered in the cell library are mainly the most basic circuit components such as inverters, NANDs (Nands), and flip-flops. Generally, data of a cell library, for example, layout information is manually created. However, an automatic cell generation tool, a ram compiler, or the like may be used for a large-scale device or a device whose basic function does not change but has a slightly different configuration, such as a memory.
Here, the hard IP and the soft IP referred to in the present invention will be briefly described. At present, in the semiconductor industry, particularly in application-specific LSI design and manufacture, there is a comprehensive company form in which a single company handles everything from design to manufacture based on specifications received from customers (for example, game consoles and car manufacturers). It is classified into a form of division of labor by a so-called LSI design company that specializes only in design and a so-called foundry company that specializes in manufacturing.
In recent years, along with the trend of division of labor, companies that supply IP (IP vendors), their distribution markets, and standardization support organizations have been created. IP has become an important factor in improving the design efficiency of LSIs, and cannot be ignored even in general companies.
There are two main types of IP called hard IP and soft IP. The difference between the two is compared with the case of division of labor between an LSI design company and a foundry company. The LSI design company (fabless company) uses data such as VHDL and Verilog HDL shown in FIG. 68 based on the customer's specifications, data such as truth table, RTL description, state transition diagram, and the like. Create information. However, there are cases where the customer himself creates these data and passes them to an LSI design company.
Next, the LSI design company creates a netlist using the logic synthesis tool described at the beginning. Circuit elements used in logic synthesis are limited to those registered in the cell library. These are certified by a specialized manufacturing company that manufactures products, and generally provided by the manufacturer themselves are basic ones such as the above-described inverter circuit and NAND gate circuit.
In practice, however, specialized manufacturing companies also offer more complexities to enhance their competitiveness. However, it is difficult for a manufacturing company alone to prepare complicated and high-performance circuits such as PLLs, SRAMs, and arithmetic circuits, and many IP vendors that design and supply these circuits appear. Of the IPs, PLLs and the like are generally supplied in the form of hard IPs because circuits themselves are complicated and characteristics greatly depend on a process to be used. In a hard IP, a cell layout designed by an IP vendor is simply registered in a cell library. Therefore, when supplying a hard IP, a hard IP vendor changes the IP not only for a manufacturing company but also for each process generation, is certified by the manufacturing company, and is registered in a cell library of each LSI design company. I have to get it.
On the other hand, in the case of soft IP, an IP vendor provides data using a functional description language such as VHDL or Verilog HDL, data such as a truth table, an RTL description, a state transition diagram, and constraint information to an LSI design company. Or foundry companies, or customers above them. For this reason, in the market for application-specific LSIs, the spread of soft IP is ahead of the market, and it is considered that its superiority will not change in the future. The ram compiler also automates the creation of cell library components and is included in the category of hard IP.
As described above, the supply form using the hard IP is inferior in the distribution and spread of the IP, and the side that supplies the hard IP also has disadvantages such as a burden of design change for each process. On the other hand, the identification number generating circuit of this embodiment, particularly the circuit as shown in FIGS. 49 and 50, is only an inverter and a pass transistor even at the heart thereof, and of course, the others are standard logic elements. Since it is configured, it is relatively easy to make a soft IP. For example, if a CMOS inverter circuit (of course) and a CMOS switch (pass transistor) are already registered in the cell library, the IP can be supplied to the design company only by the RTL description. If the pass transistor is not registered as a standard, only the pass transistor needs to be newly registered, but its scale is extremely small.
In the automatic placement and routing process, irregularities in placement and routing are raised as weak points. For example, two identification inverters may be placed at extremely distant positions. Then, the wiring length of the signal P and the signal PP in the circuit diagram becomes long, and the signal P becomes susceptible to noise from the surroundings. In order to reduce this, it is effective to limit the arrangement and the signal line length in the arrangement and wiring process. It is also effective to register only this part as a new cell by combining standard cells registered in the cell library. Rather, it is more efficient to create counters and decoders by automatic placement and routing.
2. Description of the Related Art In recent years, an application example of incorporating an ID number, various kinds of unique information (hereinafter, referred to as general information), and the like into an LSI has been increasing. For example, it may be a production line number of a product, a production week number, a product grade, and production management information. These are generally programmed with an ID number using a laser fuse or EPROM. In this program, of course, there should be no mistake in the laser program, and the laser fuse method is processed almost in a wafer state, but should not be changed in the steps after the laser step. It is even more important if the information is about life and property.
However, in the case where chips are diced after programming and the chips are separated one by one, it is very difficult to confirm whether or not the general information written during laser programming can be read, but it is very difficult to confirm that it is correct. There is. The following can be considered as countermeasures. One is to add a parity bit and detect data fluctuation. The function for the parity check may be built in the chip, or may be determined by a measuring instrument.
However, in a strict sense, it does not mean that the data written on the chip has been confirmed.
Another method is to create a mechanism for recording general information read out by some method in order to ensure the reliability of the read information and confirm duplication of information. In this method, accidents of products can be prevented by treating all the worst duplicated chips as defective products. However, in reality, when readout information of a plurality of chips is duplicated, it is difficult to confirm which information is correct, and the management and treatment of the chips become complicated.
In other words, the essential solution to the above problem would be to identify the chip that was once broken apart, get the correct information for that chip, and compare it.
Therefore, it is conceivable to add a unique identification number to a chip and obtain a correct number from a database or the like based on the information. However, even if the same is written with the same laser fuse, it is only a trick.
On the other hand, according to the information theory (for example, information theory: written by Yasuo Taki, published by Iwanami Shinsho), if the distance between codes (for example, the Hamming distance) is large, the change in the original information can be detected even when noise is applied to them. (For example, error correction code and its application: edited by the Institute of Image Information and Television Engineers, published by Ohmsha). Here, the sign is information written by the laser fuse, and the noise corresponds to a change in a part of the information.
That is, by adding a chip unique identification number having a large distance between codes to the unique information, even if a part of the entire information slightly changes, it is possible to sufficiently distinguish the identification information from other identification numbers, that is, chips. Thus, the use of the identification number generating circuit according to the present invention is effective.
FIG. 69 is a flowchart showing one embodiment of a method of manufacturing a semiconductor integrated circuit device using a semiconductor chip having a built-in identification number generating circuit according to the present invention.
Information (hereinafter, referred to as management information) obtained by combining the general information and the chip with a unique identification number having a large distance between codes is programmed in the laser fuse on the designated wafer. A unique identification number generated by a built-in identification number generation circuit is used.
The general information and the unique identification number are stored and managed on a database as management information. The management information is composed of, for example, general information + chip identification number.
In the inspection process after assembling the semiconductor integrated circuit device or the IC card, the management information is read out, and the database is referred to to confirm whether the same management information exists. If the same management information exists in the database, it is determined that the program by the laser is correct. If the same management information is not found in the database, the most similar management information is extracted. Next, the general information of the read information and the general information of the extracted management information are compared.
In this reading, the general information portion is read under a plurality of conditions such as changing the power supply voltage condition, and the unique identification number is read only once, thereby confirming whether data writing is sufficiently stable in a short time. can do. During the test, it is necessary to quickly check the management information on the database. For example, data of management information referred to in advance before the inspection starts may be stored in a workstation or the like attached to the test apparatus.
The above method enables quick and accurate confirmation of program information. In addition, if the writing of the unique identification number is performed one by one with a laser fuse or the like, the processing time and the chip area may be increased. However, the chip identification number using the variation of the logic threshold value of the CMOS inverter circuit according to the present invention is used. By using the generating circuit, the unique identification number can be obtained easily and automatically.
That is, the chip identification number and the information such as the lot and the wafer acquired by the probe inspection or the like prior to the laser program are registered in the management information database. The management information corresponding to the specified chip on the wafer is written into the laser fuse.
FIG. 70 is a flowchart showing one embodiment of an assembling process (so-called post-process) of a semiconductor integrated circuit device using a semiconductor chip on which the identification number generating circuit according to the present invention is mounted.
(1) In the probe inspection, an ID number, a lot name, a wafer number, a chip number, and the like by the identification number generation circuit are registered in a database.
(2) When a new ID number similar to the already registered ID number is generated at the time of registration, a warning is issued and the chip is treated.
(3) In the steps after the assembly test, the chips are already separated in the dicing step, so the ID number by the identification number generation circuit, the step number, and the step lot name are registered in the database.
(4) The ID number that can be obtained by the identification number generation circuit according to the present application may fluctuate due to mechanical and thermal stress in the assembling process, electrical stress in the burn-in process, and the like. The ID number is stored in the database.
(5) If there is no need to track the chips in the subsequent process, the ID number is acquired by the identification number generation circuit only in the final shipment selection process and registered in the database.
(6) In each test process, the acquired ID number information of the defective chip is deleted or marked to reduce the search processing time thereafter.
(7) In the marking process, a symbol or number indicating a line where a product is manufactured, and a year number or a week number indicating a manufacturing time may be imprinted. In identifying individual samples, these inscriptions serve as information for searching. Therefore, in the shipping selection 2, the ID number by the identification number generating circuit and the engraving information are registered in the database. In a chip having common engraving information, all ID numbers by the identification number generation circuit need to be independent, but in a chip having different engraving information, the ID number may be the same or similar to the ID number by the identification number generation circuit. . That is, it is possible to suppress the ID number identification capability of the identification number generation circuit mounted on each chip, and it is possible to reduce the size of the identification number generation circuit and the number of bits of the identification number.
(8) At the time of registering the ID number by the identification number generating circuit for each process, a lot is detected based on the ID number, and a warning is issued.
In this embodiment, all processes and the database are directly connected online. However, in reality, it is difficult to connect via a communication line due to location conditions, the communication speed is slow, and batch processing is involved. Situation that lacks real-time performance. In such a case, store it in a local database. Further, when immediacy is not required, the data is stored in a storage medium and transported to a database, or transported to the next process together with the actual product.
The format of the data collected in the database may be different due to a limitation of a test device or a processing computer in each process. In such a case, the process of converting the data format may be inserted immediately before registration in the database.
FIGS. 71 and 72 are block diagrams showing one embodiment of a method for reducing the number of bits of the identification number generating circuit according to the present invention. FIG. 71 shows a registration method for reducing the number of bits of the identification number generation circuit, and FIG. 72 shows a collation method thereof.
When a product such as a semiconductor integrated circuit device is shipped to the world and becomes defective during use by a user, the identification number generating circuit according to the present invention effectively functions also when the product is returned and the cause of the defect is investigated. In this case, the identification number is registered at the time of shipping in a database for managing the data, and if the product returns due to a defect, the data of the manufacturing process is examined. At this time, it is necessary to check which control number the defective product is. If the number of products shipped is large, the following situation occurs.
The identifiable number of identification numbers depends on the number of bits of the identification number generating circuit. If the number of bits is large, the accuracy of identification is improved, but the number of data to be identified increases accordingly. When the number of objects to be identified increases in identifying a product, it is necessary to read a large amount of data on a database and execute a collation operation for comparison and collation. Therefore, in order to reduce the time for the comparison and collation processing and the load on the system, information indicating the identification number group is separately defined as shown in FIG. Thus, the range of the number of collation data can be reduced as shown in FIG.
For the identification number group for reducing the number of bits of such identification numbers, information called general lots and marks is used. The product can be managed uniquely by the combination of this information and the identification number. In a database that only manages products after shipment, information on defective chips is deleted to reduce management costs. Can reduce the number of objects to be collated from the vast amount of data in the database, thereby reducing processing time and system load.
FIGS. 73 and 74 are configuration diagrams for explaining an inspection method using an identification number generation circuit mounted on a semiconductor integrated circuit device according to the present invention. FIG. 73 shows an identification number acquiring step, and FIG. 74 shows an inspection step.
At the stage near the end of the manufacturing process shown in FIG. 73, since the function of the identification number generation circuit can be used, an identification number acquisition step is provided before several inspection steps, and first, the identification of the product is performed. The data required in the subsequent process, such as the number, control number, and product type, are registered in the database. However, it is limited to devices that can perform the minimum operation for generating an identification number.
In each of the subsequent inspection steps shown in FIG. 74, first, the identification number of the product is read out, collated with the identification number on the database, and the management number is obtained. The data of the product type and the inspection specification are uniquely determined from the management number and transferred to the inspection device. The inspection device can perform the inspection according to the inspection specification given for each product. The advantage of this configuration is that, in each inspection process, if the product type, inspection specification or other accompanying data is provided to the database only in the first identification number acquisition process, it is not necessary to provide the data in each subsequent inspection process or manufacturing process. Efficiency can be increased.
FIG. 75 is a block diagram for explaining a method for managing the correlation of the characteristic data of each semiconductor chip in each inspection step using the identification number generation circuit mounted on the semiconductor integrated circuit device according to the present invention. Have been.
The characteristic data (measured value) obtained in each inspection step in semiconductor manufacturing is obtained in each step, and a change in the characteristic data may be analyzed. An identification number is used to manage these characteristic data, and characteristic data for each process is stored in a database for each chip. At this time, the identification number of the database is also updated with the identification number obtained in the latest process, so that a change in the identification number due to a change in the operation of the circuit is captured in the database.
Conventionally, the correlation between the probe inspection and the finished product inspection had to be obtained by grouping a plurality of chips for each lot. This time, the correlation of the characteristic data change between each process can be obtained for each chip, so that the analysis accuracy can be improved.
FIG. 76 is a block diagram for explaining a method for automatically managing a wafer in a previous process using an identification number generation circuit mounted on a semiconductor integrated circuit device according to the present invention.
An identification number generating circuit for identifying a wafer is provided on the TEG, and when the function is completed in the first wiring step, each wafer can be managed by the identification number. This eliminates the need to attach a management tag to the wafer, and eliminates the need to input information to a system that manages the wafer manufacturing process.
If the function of the identification number generation circuit is enabled and the manufacturing equipment / inspection equipment that processes the wafer in each subsequent process has an identification number reading mechanism, access the database with the read identification number. Thus, it is possible to automatically set information on the wafer in the apparatus. Further, manufacturing conditions and inspection data when the wafer is processed can be automatically stored in a database.
The identification number reading mechanism can be constituted by a board and software capable of reading a power supply controllable from a personal computer and a signal for operating the identification number generation circuit and its output (identification number). A probe for inputting and outputting signals to and from the TEG is also required.
FIG. 77 is a configuration diagram for explaining a method of storing and retrieving the identification number of the identification number generation circuit mounted on the semiconductor integrated circuit device according to the present invention.
In this embodiment, the retrieval speed can be improved and the load on the system can be reduced by adopting a method of taking out the upper N bits of the identification number and storing and managing it as an index in a table field on the database. In the method of comparing the identification number to be compared with the group of identification numbers in the database, the upper bits of the identification number to be compared are first extracted, and the table is searched under the condition that this value matches the index value in the database. Next, the identification number distance is obtained for the obtained identification number group one by one, and the smallest one is determined as the matching identification number. Thereby, it is possible to find the corresponding data without comparing the identification numbers of all the cases on the table.
FIG. 78 is a block diagram for explaining another example of the method of storing and retrieving the identification number of the identification number generation circuit mounted on the semiconductor integrated circuit device according to the present invention.
By adopting a method of limiting the search range of the identification number and comparing with the identification number group of the database, the search speed can be improved and the load on the system can be reduced. A table is searched using a method for comparing the identification number of the comparison target with the group of identification numbers in the database, using the upper and lower limits of the allowable range due to fluctuations in the identification number of the comparison target as database search conditions. Next, the identification number distance is obtained for the obtained identification number group one by one, and the smallest one is determined as the matching identification number. Thereby, it is possible to find the corresponding data without comparing the identification numbers of all the cases on the table. If the data cannot be retrieved because it does not fall within the upper and lower limits of the first allowable range, the upper and lower limits are relaxed and the retrieval process is performed again.
FIG. 79 is a block diagram showing one embodiment of a method for repairing a semiconductor integrated circuit device using an identification number generating circuit according to the present invention.
(1) The probe inspection of the main body chip is performed. By this inspection, the rescue data of the DRAM or the like is sent to the host computer together with the identification number extracted from the identification number generation circuit.
{Circle around (2)} Dicing is performed to take out only the fully operated product and the rescue product.
{Circle around (3)} Perform a probe test of the EEPROM dedicated to the rescue data.
{Circle around (4)} Dicing the normal operation product and stock it.
{Circle around (5)} The main body LSI and the EEPROM dedicated to the rescue data are mounted on the same module.
{Circle around (6)} The identification number of the main body LSI of the mounted module is read, and the corresponding rescue data is written in the rescue data dedicated EEPROM.
(7) Perform a sorting test.
{Circle around (8)} The non-defective LSI is shipped, and among the defective LSIs, those which can be rescued again return to step (6) and write the corresponding rescue data into the EEPROM dedicated to the rescue data.
As a result, the semiconductor integrated circuit device can be easily and rationally relieved.
In addition to the rescue of the semiconductor integrated circuit device, it is possible to reduce the inspection cost using the identification number. In a probe test performed when a semiconductor chip is formed on a half wafer, for example, in a semiconductor chip such as a flash memory, the operating voltage is 3.0 V, 2.5 V, and 1.8 V with the same circuit function. There are products that produce different products as different varieties.
At this time, a test is performed with a voltage setting corresponding to 1.8 V, and it is determined whether or not the memory operation is correctly performed. In the semiconductor chip determined to be non-defective by this determination, voltage information for confirming 1.8 V operation is recorded in the identification number. The operation confirmation information is written and held in the semiconductor chip itself in a nonvolatile manner. For this purpose, a management memory such as a flash memory is set in the semiconductor chip.
For the chip that failed at 1.8 V, it is determined whether or not the memory operation is performed by setting the voltage to 2.5 V. In the semiconductor chip determined to be non-defective by this determination, voltage information for confirming the operation of 2.5 V is recorded in the identification number. Then, for the chip failed at 2.5 V, it is determined whether or not the memory operation is performed by setting the voltage to 2.5 V. In the semiconductor chip determined as non-defective by this determination, voltage information for confirming the operation of 3.0 V is recorded in the identification number. The chip failed at 3.0 V is discarded as a defective chip.
In this embodiment, for example, a semiconductor chip that operates at 1.8 V can operate at 2.5 V or 3.0 V without performing an operation test at 2.5 V or 3.0 V. Is treated as Similarly, a semiconductor chip that operates at 2.5 V is treated as capable of operating at 3.0 V without performing an operation test at 3.0 V. For this reason, there is a possibility that a semiconductor chip which operates at 1.8 V will be defective when operated at 2.5 V or 3.0 V, but the probability is considered to be small. Omitting the operation and shortening the test time rather than performing the operation described above can reduce the manufacturing cost as a whole.
Then, when assembling as a single flash memory, or when assembling as one semiconductor integrated circuit device in combination with a microprocessor or the like, the operating voltage information stored in the host computer is obtained from the above identification number, and suitable ones are combined. . At this time, the semiconductor integrated circuit device operating at 2.5 V can also use the above-mentioned 1.8 V operation-confirmed chip, and the semiconductor integrated circuit device operating at 3.0 V uses the 1.8 V and 2.5 V A chip that operates on a.
FIG. 80 is a layout diagram of still another embodiment of the semiconductor integrated circuit device provided with the identification number generating circuit according to the present invention, and FIG. 81 is a partially enlarged layout diagram of FIG. In the semiconductor integrated circuit device shown in FIG. 80, like many general semiconductor integrated circuit devices, a built-in circuit or an internal circuit is arranged substantially at the center of a semiconductor chip constituting the semiconductor integrated circuit device, and signals for external signals are arranged around the semiconductor chip. A configuration in which a plurality of input / output cells (I / O cells) for transmission and reception are arranged is adopted.
The four corners of the peripheral portion of the semiconductor chip are empty areas where no I / O cells are arranged, as in a general semiconductor integrated circuit device. In this embodiment, such an empty area is used, and one of them is provided with an identification number generating circuit CRNC.
The identification number generation circuit CRNC is connected to the built-in circuit by a signal and power supply wiring layer formed to extend on the semiconductor chip.
As will be described later, the signal and power lines may be disconnected. For the convenience of such cutting, it is desirable that the number of such signal and power supply wiring layers is small. Therefore, in this embodiment, the wiring for the interface between the identification number generation circuit and the built-in circuit includes power supply wiring (VDD, VSS) for the identification number generation circuit, a reset signal (RES), a clock signal (CLK), and an identification. It is composed of a small number of wires such as three signal wires for the number output signal (OUT). In the partially enlarged view of FIG. 81, the power supply lines VDD and VSS are indicated by relatively thick lines, and the signal lines for the reset signal and the clock signal identification number output signal are indicated by relatively thin lines. As is apparent from the figure, the signal wiring is extended so as to be substantially surrounded by the power supply wirings VDD and VSS.
The identification number generation circuit CRNC is configured to be able to generate an identification number using a brute force method as in the above-described embodiment, based on the reset signal and the clock signal. As shown in FIG. 81, a reset signal (RES), a clock signal (CLK), an identification number output signal (OUT) and power supply terminals VDD and VSS of the circuit CRNC are provided on an empty area around the identification number generation circuit CRNC. Connected electrode pads RES, CLK, OUT, VDD, and VSS are provided. These electrode pads are not used as external terminals of a semiconductor integrated circuit device formed by packaging a semiconductor chip with a package member such as a mold resin, but can be adapted to a contactor called a probe needle. Thus, it is configured on a semiconductor chip.
The identification number information from the identification number generation circuit CRNC shown in the figure passes through a normal path through the I / O cell if the path of the power supply line, the built-in circuit, the I / O cell, etc. of the semiconductor integrated circuit device is operable. External reading is enabled.
Here, it is desirable that the identification number information can meet many needs including a product history check. In some cases, it is desired that the identification number information be obtained from a disabled semiconductor integrated circuit device.
If the semiconductor integrated circuit device is inconveniently malfunctioning due to an abnormal increase in power supply current or other various factors, a package member such as a mold resin is removed, and the semiconductor chip is exposed. The power supply and signal wiring layers between the identification number generating circuit CRNC and the built-in circuit are cut and removed by a device such as a laser cutting device. As a result, the identification number generating circuit CRNC is connected to only the electrode pads. In other words, the circuit CRNC is free from internal wiring short-circuits, internal element destruction, and the like of the semiconductor integrated circuit device, and can operate independently. Then, in this state, a contactor is brought into contact with the electrode pad, and the identification number information can be obtained via the contactor.
A chip size in which a semiconductor integrated circuit device is provided with a plurality of external terminals such as bump electrodes via a wiring layer such as a relocation wiring and an insulating layer having a purpose of relaxing stress on a semiconductor chip. Similarly, in the case of a package form called a package or a chip scale package, identification number information can be obtained. In this case, when it is difficult to obtain the identification number information through a normal external terminal, the same electrode pad as described above and the wiring portion to be cut are exposed by removing the bump electrode and the insulating layer. After that, the identification number information is read out via the electrode pad.
FIG. 82 is a block diagram of another embodiment of a semiconductor integrated circuit device provided with an identification number generating circuit according to the present invention, and FIG. 83 is a circuit diagram thereof.
The semiconductor integrated circuit device of this embodiment is of a so-called master slice type in which a semiconductor region constituting a MOSFET or the like is used as a fixed pattern and a circuit having a desired function is constituted by wiring. Among the I / O cells set on the semiconductor chip constituting the semiconductor integrated circuit device, an idle I / O cell, that is, an I / O cell which is not used from the function of the semiconductor integrated circuit device, is an identification number generating circuit. .
As shown, one I / O cell includes a region for an output control circuit having a relatively small area, a region (output MOS) for an output MOSFET having a relatively large area, and an input / output pad electrode (I / O). OPAD), and the entire area forms a rectangular planar pattern as shown.
Although the area for the output control circuit has a relatively small area, a relatively large number of gate elements, inverter circuits, and sub-elements such as MOSFETs are provided so that a desired output control circuit and input circuit can be formed. have. The area for the output MOSFET has only a relatively small number of MOSFETs, such as one or two p-channel MOSFETs and one or two N-channel MOSFETs, but has a high external load driving capability. And a relatively large area.
The identification number generation circuit is constituted by sub-elements in an area for an output control circuit in an idle I / O cell. The identification number generating circuit can be configured in such a region by a relatively large number of sub-elements in the region for such an output control circuit.
The P-channel MOSFET and the N-channel MOSFET, the inverter circuit, the NAND circuit and the NOR circuit shown in FIG. 83 constitute a tri-state output buffer circuit for outputting the output of the identification number generating circuit to the outside as a whole. ing. In such an output buffer circuit, the inverter circuit, the NAND circuit, and the NOR circuit are configured by sub-elements in a region for an output control circuit, and the output MOSFET is configured by a MOSFET in a region for an output MOSFET.
The output of the tristate output buffer circuit in the idle I / O cell is coupled to an input / output pad electrode (I / OPAD) provided in the idle I / O cell. In other words, the illustrated input / output pad electrodes are output electrodes dedicated to identification number information.
The input / output pad electrode is coupled to a vacant pin or a vacant terminal of the semiconductor integrated circuit device, usually called an NC (Non Connection) pin in the semiconductor integrated circuit device.
According to this embodiment, the identification number generating circuit and the tri-state output buffer circuit are brought into operation by setting the enable signal, which is marked as identification number circuit enable in the drawing, to a significant level such as a high level. You. For the operation of the identification number generating circuit, a continuous clock signal labeled as an output clock is supplied in the figure. In response to the continuous clock signal, the identification number information is supplied according to the input / output pad electrodes.
FIG. 84 is a block diagram of another embodiment of a semiconductor integrated circuit device provided with an identification number generating circuit according to the present invention. This embodiment has an idle I / O cell in a large-scale semiconductor integrated circuit device in recent years in order to enhance power supply to cope with an increase in current consumption and an increase in operation speed. However, it is considered that the cell region is diverted to strengthen the power supply.
In the layout diagram of FIG. 84, three I / O cells are illustrated. Of these three I / O cells, the I / O cell at the top of the drawing is an idle I / O cell, and the other I / O cell at the bottom of the drawing is used for semiconductor integrated circuit device operation. Are used as normal I / O cells.
In the idle I / O cell, a power supply pad electrode, that is, a pad electrode diverted to a power supply or the like is provided in a region for the input / output pad electrode. The power supply pad electrode is coupled to a plurality of I / O cells or a power supply wiring layer (not shown) for a built-in circuit. It should be understood that the power supply wiring layer on the idle I / O cell is generally formed of an upper wiring layer made of metal in a wiring layer having a multilayer wiring structure.
In the idle I / O cell, a portion corresponding to the area for the output control circuit in FIG. 81 is provided with a wiring by a lower wiring layer in the multilayer wiring layer in the same manner as in the example in FIG. 81. An identification number generating circuit for receiving a clock signal and an identification number circuit enable signal and forming an identification number output is configured.
The output clock signal, the identification number circuit enable signal, and the wiring layer for outputting the identification number between the identification number generation circuit and the built-in circuit are provided with respective ones so as to facilitate the wiring cutting and terminal formation described later. The part uses a relatively high wiring layer.
The output signal of the identification number generation circuit is supplied to an output selection circuit provided on the input side of a normal I / O cell set as an output cell.
As a result, the normal I / O cell set as an output cell outputs normal output data supplied from the built-in circuit via the output selection circuit to the input / output pad electrode in the normal operation of the semiconductor integrated circuit device. .
When outputting the identification number information, the normal I / O cell outputs the identification number information supplied from the identification number generation circuit via the output selection circuit to the input / output pad electrode.
FIG. 85 shows a reference potential terminal VSS called a power supply terminal VDD and a ground terminal of an identification number generation circuit, and a power supply wiring layer and a reference potential wiring layer extended over a plurality of I / O cells. 3 shows a binding pattern of the above. The power supply wiring layer VDD and the reference potential wiring layer VSS extending above the I / O cells have relatively wide widths with the intention of strengthening the power supply system. In this embodiment, as shown in FIG. 85, a relatively wide power supply wiring layer is provided with a narrow width branch wiring layer, and the narrow width branch wiring layer is provided with a power supply wiring VDD for an identification number generating circuit. -V. The connection between the reference potential wiring layer and the reference potential wiring VSS-V of the identification number generating circuit has the same configuration. This configuration facilitates the following separation between the identification number generation circuit and the power supply wiring layer and the reference potential wiring layer.
When it is necessary to obtain identification number information from the identification number generation circuit regardless of an abnormality such as a short circuit between the power supply wiring layer and the reference potential wiring layer, as shown in FIG. 86, the power supply terminal VDD of the circuit and the reference potential The narrow branch wiring layer connected to the terminal VSS is cut by a technique such as a laser cutting technique or a focused ion beam (FIB) technique. At the same time, the above-mentioned signal line between the identification number generating circuit and the built-in circuit is similarly disconnected.
Next, formation of an insulating film, formation of an opening in the insulating film, and selective formation of a conductive layer are performed by a known technique such as the FIB technique. Thus, a conductive region made of a new conductive layer is set in the power supply terminal VDD and the reference potential terminal VSS of the identification number generation circuit as shown in FIG. 86. At the same time, a new conductive layer is set for the signal lines described above.
A contactor called a probe needle is brought into contact with these conductive layers, an identification number generating circuit is operated, and identification number information is obtained.
FIG. 87 is a circuit diagram of another embodiment of the semiconductor integrated circuit device provided with the identification number generating circuit according to the present invention.
In this embodiment, two diode-connected MOSFETs Q1 and Q2, a power pad for an identification number circuit, an output pad exclusively for an identification number, and an identification number exclusive circuit for an identification number generating circuit configured in a semiconductor integrated circuit device are shown. A clock pad and an identification number dedicated enable pad are provided.
When the semiconductor integrated circuit device can operate normally, the identification number generating circuit is supplied with an operating voltage via the normal power supply terminal VDD, the normal power supply wiring, and the diode-connected MOSFET Q1 of the semiconductor integrated circuit device, and has a built-in circuit (not shown). The identification number information is output to the built-in circuit in response to the clock signal and the identification number enable signal from the circuit.
When power cannot be supplied to the identification number generation circuit via the regular terminals VDD / VSS- due to a short circuit abnormality between the regular power supply terminal VDD and the power supply wiring connected thereto and the normal reference potential terminal VSS and the reference potential wiring connected thereto. , Necessary voltages and signals are applied to the circuit through various pads shown in the figure, and the circuit is operated. The diode-connected MOSFET Q1 performs a switching operation such that the power supply voltage applied to the circuit via the identification number circuit power supply pad and the MOSFET Q2 is automatically turned off. Thus, power can be supplied to the identification number generation circuit regardless of the abnormality of the normal power supply system.
The operational effects obtained from the above embodiments are as follows.
(1) A plurality of identification elements having the same form are formed in the course of the manufacturing process of a semiconductor integrated circuit device, and the magnitude relationship between the physical quantities of the plurality of identification elements corresponding to the process variation is determined, and semiconductor integration is performed. By using the information as unique identification information of the circuit device, it is possible to obtain an effect that individual semiconductor integrated circuit devices can be identified with a simple configuration.
(2) In addition to the above, the first identification information in which the unique identification information is assigned to the identification element at the time of the manufacturing, and the physical quantities of the plurality of identification elements obtained by the determination are ranked information of magnitude relation. By using this, the amount of information for identifying each semiconductor integrated circuit device can be reduced, so that the effect of simplifying the storage circuit for storing the identification information and shortening the determination time can be obtained.
(3) In addition to the above, the discriminating element is a connection between an input terminal and an output terminal of a CMOS inverter circuit composed of an N-channel MOSFET and a P-channel MOSFET, and the logical threshold value is a physical quantity for comparing the magnitude. As a result, an effect can be obtained that the range of applicable semiconductor integrated circuit devices can be widened without adding a special manufacturing process because the semiconductor integrated circuit device can be constituted by a basic digital circuit such as a CMOS circuit.
(4) In addition to the above, by applying the operating voltage to the CMOS inverter circuit only at the time of determining the logical threshold voltage as a physical quantity, it is possible to reduce the influence of the deterioration of the element characteristics and to stably perform the operation. Thus, an effect that a highly reliable identification result can be obtained is obtained.
(5) A plurality of identification elements having the same form are formed in the course of the manufacturing process of the semiconductor integrated circuit device, a physical quantity corresponding to the process variation is determined, and the magnitude relation between the physical quantities of the plurality of identification elements is determined. Based on the unique identification information, the unique identification information is generated and stored together with the manufacturing history. When a failure occurs in the semiconductor integrated circuit device, the stored manufacturing history is read based on the unique identification information to analyze the failure. And feeding back to the above-mentioned manufacturing process as needed, an effect that a rational manufacturing system can be constructed can be obtained.
(6) A plurality of identification elements having the same form are formed in the course of the manufacturing process of the semiconductor integrated circuit device constituting the first chip, and the first identification element is formed based on the magnitude relationship between the mutual physical quantities corresponding to the process variation. Generating unique identification information of the chip, forming a plurality of pieces of operation modification information for a plurality of semiconductor integrated circuit devices constituting the first chip according to their respective electrical characteristics, By writing the second chip in correspondence with the identification information of the first chip, assembling the first chip and the second chip, and outputting the operation modification information to the first chip based on the identification information of the first chip, An advantage is obtained in that a semiconductor integrated circuit device having a multi-chip configuration can be efficiently manufactured without performing complicated chip management.
(7) In addition to the above, a memory device with a simple configuration and a high manufacturing yield is provided by configuring a memory having a redundant circuit with the first chip, and making the second chip obstruct a defective address. Can be obtained.
(8) In addition to the above, in the case where a defect is caused by performing a further test in a state where the first chip and the second chip are assembled, the semiconductor chip constituting the first chip is removed by removing the second chip. By returning to the step of integrating a plurality of semiconductor integrated circuit devices of the integrated circuit device, the effect that the manufacturing yield can be improved can be obtained.
(9) In addition to the above, by integrally sealing the first chip and the second chip after the selection in the assembled state, the manufacturing yield can be improved and the semiconductor integrated circuit device can be improved. The effect that size reduction can be achieved is obtained.
(10) In addition to the above, by assembling the first chip and the second chip on a common mounting substrate, the removal of the second chip becomes easy, and the above-mentioned failure occurs again. The effect that the use can be performed effectively can be obtained.
(11) By providing unique identification information based on a magnitude relationship between physical quantities corresponding to process variations of a plurality of identification elements formed as the same form in the process of manufacturing a semiconductor integrated circuit device, The advantage is that the identification information of each semiconductor integrated circuit device can be incorporated with a simple configuration.
(12) In addition to the above, individual semiconductors can be obtained by using the unique identification information as first identification information assigned to the identification element at the time of manufacture and the physical quantities of the plurality of identification elements as rank information of magnitude relation. Since the amount of information for identifying the integrated circuit device can be reduced, the storage circuit for storing the information can be simplified and the speed of the determination operation can be increased.
(13) In addition to the above, a discriminating element is connected between an input terminal and an output terminal of a CMOS inverter circuit composed of an N-channel MOSFET and a P-channel MOSFET, and its logical threshold value is used as a physical quantity for judging magnitude. Thereby, since it can be constituted by a basic digital circuit such as a CMOS circuit, it is possible to obtain an effect that the range of applicable semiconductor integrated circuit devices can be expanded without adding a special manufacturing process.
(14) In addition to the above, as a circuit for connecting an input terminal and an output terminal of a CMOS inverter circuit and determining a logical threshold value of the CMOS inverter circuit, a switch is provided in each of the plurality of CMOS inverter circuits, and two switches are provided. By applying the logical threshold voltage to the common voltage comparison circuit for the round robin in the combination of the above and making the determination, it is possible to obtain the effect of realizing high discrimination ability with a simple configuration.
(15) In addition to the above, corresponding to each of the plurality of CMOS inverter circuits, a first switch connecting an input terminal and an output terminal thereof, and a first switch connecting a common first circuit node and an input terminal. Two switches and a third switch for connecting the output terminal to the common second circuit node, and a combination of the first to third switches forms one set of two CMOS inverter circuits between the plurality of inverter circuits. By connecting the input terminal and the output terminal of one CMOS inverter circuit and supplying the voltage obtained at the first circuit node to the input terminal of the other CMOS inverter circuit, By obtaining an output signal for voltage comparison at the second circuit node using the logic threshold voltage of the inverter circuit as a reference voltage, a simple configuration is achieved. Thus, it is possible to obtain an effect that the identification number can be generated in the step (c).
(16) In addition to the above, by using the CMOS inverter circuit and the first switch to the third switch using the elements constituting the CMOS gate array, an effect is obtained that an identification number generation circuit can be obtained only by wiring design. Can be
(17) In addition to the above, by supplying an operating voltage to the CMOS inverter circuit only at the time of determining the voltage as the physical quantity, the influence of the deterioration of the element characteristics can be reduced, so that a stable and highly reliable identification number is obtained. The effect that it can be obtained is obtained.
(18) A first switch for selectively short-circuiting an input terminal and an output terminal of the first inverter circuit, and a second inverter circuit having an output terminal of the first inverter circuit connected to the input terminal, and an output signal thereof By providing a plurality of identification elements which are amplified by an amplifier circuit in response to the received signals, an identification number circuit for generating an identification number based on an output signal from each identification element when the first switch is turned on is built in, The effect is obtained that the individual semiconductor chip can be identified with a simple configuration.
(19) In addition to the above, if the inverter circuit is a CMOS inverter circuit, and the output signal of the second inverter circuit when the first switch is on is higher than the logical threshold value, the amplifier circuit To form a low level in response to the output signal of the amplifying circuit when the output signal of the second inverter circuit when the first switch is on is low with respect to its logical threshold. By providing a latch circuit which forms a level and feeds back to the input terminal of the first inverter circuit at the time of a feedback operation in which the first switch is turned off, the reproducibility of the identification number and the resistance to aging are improved. The effect of being able to increase is obtained.
(20) In addition to the above, the amplifier circuit is a cascade connection circuit of a plurality of CMOS inverter circuits, and the input terminals of the first inverter circuit, the second inverter circuit, and the input terminals of each CMOS inverter circuit constituting the amplifier circuit are respectively provided. A third switch for applying a high-level voltage is provided, and a third switch is provided at each interconnection point of each of the inverter circuits forming the first inverter circuit or the amplifier circuit, and the identification number circuit is in a non-operating state. In the case of, the second switch is turned on, the third switch is turned off, and the second switch is turned off at the time of amplification of the identification information whose first switch is turned on and the feedback operation, By turning on the third switch, the reproducibility of the identification number and the resistance to aging can be further improved. The effect that can be obtained is obtained.
(21) A first switch for short-circuiting an input terminal and an output terminal of each of the first inverter circuit and the second inverter circuit, and a second switch for connecting an output terminal of the first inverter circuit to an input terminal of the second inverter circuit. A first switch of the first inverter circuit using a plurality of identification elements including a second switch, and an amplifier circuit including a third inverter circuit in which an output terminal of the second inverter circuit is connected to an input terminal. Is turned on, the first switch of the second inverter circuit is turned off, and the first identification information is obtained from the output signal of the amplifier circuit including the third inverter circuit when the second switch is turned on. And including the third inverter circuit when the first switch of the second inverter circuit is turned on and the second switch is turned off. By incorporating an identification number circuit for generating an identification number so as to obtain the second identification information from the output signal of the amplifier circuit, it is possible to identify the individual semiconductor chip while simplifying the circuit. The effect that can be obtained is obtained.
(22) In addition to the above, a plurality of circuit rows are provided such that the first inverter circuit and the second inverter circuit are arranged in a row corresponding to the first inverter circuit and the second inverter circuit. The same switch control signal is commonly supplied to the corresponding first switches, and any one of the output signals of the second inverter circuits in a plurality of circuit rows is selected by the third switch, and the first stage circuit of the amplifier circuit is selected. By connecting to the input terminal of the third inverter circuit to be constituted, it is possible to obtain an effect that a large number of identification information can be efficiently obtained.
(23) In addition to the above, the input terminals of the first inverter circuit and the second inverter circuit are provided with a fourth switch for cutting off an input signal and a fifth switch for supplying a high-level voltage, and By turning off the fourth switch when the number circuit is inactive and turning on the fifth switch, the effect of further improving the reproducibility of the identification number and the resistance to aging can be obtained. Can be
(24) The input terminal and the output terminal of the first inverter circuit are short-circuited by the first switch, and a plurality of unit elements provided with the input terminal and the second switch of the first inverter circuit are connected via the second switch. An identification element sequence is formed in a tandem form, an output terminal of the first inverter circuit corresponding to the last stage of the identification element sequence is connected to an input terminal of an amplifier circuit including a second inverter circuit, and a clock is counted. A decoder for decoding the count output of the binary counter is provided in correspondence with the first switch and the second switch of each of the first inverter circuits in the identification element sequence, and the identification element sequence is generated in accordance with the count output of the binary counter. The first switch is sequentially turned on from the first stage circuit, and the second switch is turned off complementarily with the first switch, and the third switch includes the third inverter circuit. By incorporating an identification number circuit for generating an identification number by obtaining a plurality of pieces of identification information corresponding to each first inverter circuit of the identification element row based on the output signal of the amplifier circuit, individual circuits can be simplified while simplifying the circuit. An effect is obtained that the semiconductor chip can be identified.
(25) The input terminal and the output terminal of the first inverter circuit are short-circuited by the first switch, and a plurality of unit elements each having the second switch provided at the input terminal of the first inverter circuit are connected via the second switch. And an output terminal of the first inverter circuit corresponding to the last stage of the identification element sequence is connected to an input terminal of an amplifier circuit including a second inverter circuit. A shift register having shift bits corresponding to the first switch and the second switch of each first inverter circuit in the element row is provided, and the identification element row is sequentially shifted from the first-stage circuit to the first element in correspondence with the shift operation of the shift register. The switches are sequentially turned on, the second switch is turned off complementarily with the first switch, and the output signal of the amplifying circuit including the third inverter circuit outputs the signal. A built-in identification number circuit that obtains a plurality of pieces of identification information corresponding to each first inverter circuit in a separate element row and generates an identification number enables identification of individual semiconductor integrated chips while simplifying the circuit. Is obtained.
(26) A first switch for selectively short-circuiting an input terminal and an output terminal of the first inverter circuit, and a second inverter circuit having an output terminal of the first inverter circuit connected to the input terminal are provided, and an output signal thereof is provided. By providing a plurality of identification elements which are amplified by an amplifier circuit in response to the received signals, an identification number circuit for generating an identification number based on an output signal from each identification element when the first switch is turned on is built in, An advantage is obtained that individual semiconductor integrated circuit devices can be identified with a simple configuration.
(27) The input terminal and the output terminal of the first inverter circuit are short-circuited by the first switch, and a plurality of unit elements provided with the second switch at the input terminal of the first inverter circuit are connected via the second switch. To form an identification element sequence in a cascade, connecting an output terminal of the first inverter circuit corresponding to the last stage of the identification element sequence to an input terminal of an amplifier circuit including a second inverter circuit, and Decoders for decoding the count output of the binary counter for counting are provided corresponding to the first switch and the second switch of each of the first inverter circuits of the identification element sequence, and the identification element sequence is corresponding to the count output of the binary counter. The first switch is sequentially turned on from the first stage circuit, and the second switch is turned off complementarily with the first switch to include the third inverter circuit. By incorporating an identification number circuit that generates a plurality of identification numbers by obtaining a plurality of pieces of identification information corresponding to each of the first inverter circuits of the identification element row based on the output signal of the amplifier circuit, individual circuits can be simplified while simplifying the circuit. This makes it possible to identify the semiconductor integrated circuit device.
(28) The input terminal and the output terminal of the first inverter circuit are short-circuited by the first switch, and a plurality of unit elements provided with the input terminal and the second switch of the first inverter circuit are connected via the second switch. Forming an identification element sequence in a tandem form, connecting an output terminal of the first inverter circuit corresponding to the last stage of the identification element sequence to an input terminal of an amplifier circuit including a second inverter circuit, A shift register having shift bits corresponding to the first switch and the second switch of each first inverter circuit in the column is provided. In response to the shift operation of the shift register, the identification element columns are sequentially arranged in the first switch from the first stage circuit. Are sequentially turned on, the second switch is turned off complementarily with the first switch, and the identification is performed based on the output signal of the amplifier circuit including the third inverter circuit. By incorporating an identification number circuit for generating identification numbers by obtaining a plurality of identification information corresponding to each of the first inverter circuits in the element row, it is possible to identify individual semiconductor integrated circuit devices while simplifying the circuit. Is obtained.
(29) In addition to the above, a test circuit conforming to the JTAG standard is further provided, and the identification number generated by the identification number circuit is output via an interface conforming to the JTAG standard, whereby the test circuit The effect of simplification of the circuit can be obtained by diversion.
(30) In addition to the above, the identification number circuit including the unit element, the first switch, and the second switch performs circuit design and circuit layout using soft IP technology, thereby reducing design cost. Is obtained.
(31) The input terminal and the output terminal of the first inverter circuit are short-circuited by the first switch, and a plurality of unit elements each having the second switch provided at the input terminal of the first inverter circuit are connected via the second switch. And an output terminal of the first inverter circuit corresponding to the last stage of the identification element sequence is connected to an input terminal of an amplifier circuit including a second inverter circuit. A shift register having shift bits corresponding to the first switch and the second switch of each first inverter circuit in the element row is provided, and the identification element row is sequentially shifted from the first-stage circuit to the first element in correspondence with the shift operation of the shift register. The switches are sequentially turned on, the second switch is turned off complementarily with the first switch, and the output signal of the amplifying circuit including the third inverter circuit outputs the signal. A semiconductor integrated circuit is obtained by performing a circuit design and a circuit layout using soft IP technology on an identification number circuit that obtains a plurality of pieces of identification information corresponding to each first inverter circuit in another element row and generates an identification number. The effect that the manufacturing cost of the device can be reduced is obtained.
Although the invention made by the inventor has been specifically described based on the embodiments, the invention of the present application is not limited to the embodiments, and it is needless to say that various modifications can be made without departing from the gist of the invention. Nor. For example, a plurality of identification elements having the same form, which are formed in the process of manufacturing a semiconductor integrated circuit device, include a resistance element having the same resistance value in the semiconductor integrated circuit device when the signal is read out electrically. A plurality of capacitors having a capacitance value may be formed, and process variations of the resistance value and the capacitance value may be extracted in the form of current or voltage and used as an identification number.
In addition to the lead width or pitch width of the semiconductor integrated circuit device, a plurality of straight lines having the same length or width are printed or stamped on the surface of a semiconductor package or the like, and variations in the width or pitch width are used. Various embodiments can be adopted.
The resistance element exemplified above can be implemented without requiring a relatively complicated manufacturing process as in the CMOS configuration of the embodiment. Examples of the resistance element include a polysilicon resistance formed by a semiconductor integrated circuit technology and a so-called diffusion resistance formed by introducing a conductivity type determining impurity into single crystal silicon by a known ion implantation method. A semiconductor resistance and a metal resistance composed of a metal layer of the same quality as the metal wiring layer can be considered. Among these resistors, the diffused resistor is suitable for obtaining specific information according to the characteristic variation in that it is easy to set an appropriate resistance value and the change in resistance value with time is relatively small. .
The specific information corresponding to the resistance variation includes, for example, a resistance-voltage conversion in which a predetermined bias current is applied to two resistance elements to be compared at each time and a voltage difference generated between the two resistances at that time is determined. It can be formed by a technique of comparing and judging, or by a technique of forming a resistance bridge by a plurality of resistance elements and determining the output of the resistance bridge. The characteristic information corresponding to the resistance element can also be formed by a technique that uses the resistance element as a resistance-current conversion element and compares and determines the converted current, in addition to the above-described technique. Furthermore, by making the resistance element a part of the oscillation frequency determination element of the oscillation circuit or the delay time determination element of the delay circuit, it is possible to use the characteristic variation of the resistance element as frequency information or delay time information.
In the case where the resistance element is used as a load element for the signal input MOSFET constituting the inverter, the information corresponding to the characteristic variation reflects both the characteristic variation of the resistance element and the characteristic variation of the signal input MOSFET. .
The specific information corresponding to the resistance variation does not necessarily need to be formed only in the semiconductor integrated circuit device. If necessary, the semiconductor integrated circuit device is configured so that it can be appropriately shifted to the specific information forming mode. Under the mode, a plurality of resistance elements in the semiconductor integrated circuit device are set in the semiconductor integrated circuit device. It is also possible to switchly connect to an existing external terminal such as a signal input / output terminal. In this case, the specific information corresponding to the characteristic variation of the resistance element is formed by a circuit device outside the semiconductor integrated circuit device coupled to the external terminal. In this case, an increase in the number of circuit elements in the semiconductor integrated circuit device can be suppressed, and the number of external terminals can be suppressed by using existing terminals of the semiconductor integrated circuit device.
The leakage current of a plurality of circuits having the same configuration or the leakage current of a circuit element such as a MOSFET is empirically recognized as maintaining the characteristic variation permanently. The leak current level can be detected by current-voltage conversion and voltage comparison, similarly to the variation in the characteristics of the resistance element. The circuit that forms the leak current may be a circuit having the same configuration as described above, or may be a MOSFET in which the gate and the source are connected.
As a preferable leak current source for specific information, a signal output buffer circuit connected to a signal output external terminal or a signal input / output external terminal of the semiconductor integrated circuit device can be cited. This type of signal output buffer has a circuit element such as a MOSFET which constitutes the comparatively large size, often generates a relatively large leak current, and its measurement is relatively easy. This is because existing external terminals can be used as they are.
The withstand voltage characteristic of an element such as an input protection diode in the semiconductor integrated circuit device connected to the external signal input terminal of the semiconductor integrated circuit device can also be a source of the above-described specific information corresponding to the micro-variation. Even when a plurality of external terminals of a semiconductor integrated circuit device constitute a bus line having a relatively small number of bits in an electronic system, the number of external terminals can be significantly increased by a brute force comparison method as described above. Thus, it is possible to form information that can be appropriately identified.
A capacitance such as a drain junction capacitance of a MOS transistor in a semiconductor integrated circuit device coupled to an external terminal of the semiconductor integrated circuit device has a microscopic variation. Therefore, it can also be a source of the specific information as described above corresponding to the variation.
The information retention time in the dynamic memory also shows micro-variation. In this case, even if a special configuration is not added to the dynamic memory, that is, even if a configuration for forming unique identification information is not set, a plurality of memory addresses in a specific plurality of memory addresses among a plurality of memory addresses are set. It is possible to measure the information retention time of the memory cell and use the result of the measurement as specific information.
When a plurality of semiconductor chips are provided on a common substrate such as a multi-chip module, a unique identification circuit is set for each semiconductor chip, and unique identification information from each semiconductor chip is transmitted through the common substrate. It is also possible to take it out. When the number of terminals required on the common substrate for reading the unique identification information of each semiconductor chip is limited, each semiconductor chip has a chip selection control circuit and a parallel-serial conversion circuit for the unique identification information. May be set. At this time, the identification information unique to each semiconductor chip is serialized by the parallel-serial conversion circuit in the selected state of the chip, output from each semiconductor chip, and read out via the common substrate. In the case where a dedicated program chip in the sense as shown in FIG. 33 is provided, the dedicated program chip may be configured to be compatible with a plurality of different types of semiconductor chips on a common substrate.
Industrial applicability
The present invention relates to a method of identifying a semiconductor integrated circuit device or a semiconductor chip, and a method of identifying a semiconductor integrated circuit device or a semiconductor chip by assigning unique identification information to the semiconductor integrated circuit device or the semiconductor chip. The present invention can be widely used for a device manufacturing method, a semiconductor integrated circuit device, and a semiconductor chip.
[Brief description of the drawings]
FIG. 1 is a basic circuit diagram showing an embodiment of an identification number generating circuit according to the present invention,
FIG. 2 is a basic circuit diagram showing another embodiment of the identification number generating circuit according to the present invention,
FIG. 3 is a basic circuit diagram showing another embodiment of the identification number generating circuit according to the present invention,
FIG. 4 is an explanatory diagram of the operation of the identification number generating circuit of FIG. 3,
FIG. 5 is a basic circuit diagram showing another embodiment of the identification number generating circuit according to the present invention,
FIG. 6 is an equivalent circuit diagram for explaining the embodiment of FIG. 5;
FIG. 7 is a circuit diagram showing a specific embodiment corresponding to the embodiment of FIG.
FIG. 8 is a timing chart for explaining the operation of the embodiment of FIG. 7;
FIG. 9 is an explanatory diagram of the operation of the embodiment circuit of FIG.
FIG. 10 is a modification showing an embodiment of a unit circuit composed of a CMOS inverter circuit and a switch MOSFET, which is the core of the identification number generation circuit according to the present invention,
FIG. 11 is a modified example showing another embodiment of a unit circuit composed of a CMOS inverter circuit and a switch MOSFET, which is the core of the identification number generating circuit according to the present invention,
FIG. 12 is a modified example showing another embodiment of a unit circuit composed of a CMOS inverter circuit and a switch MOSFET, which is the core of the identification number generating circuit according to the present invention,
FIG. 13 is a modification showing another embodiment of a unit circuit composed of a CMOS inverter circuit and a switch MOSFET, which is the core of the identification number generation circuit according to the present invention,
FIG. 14 is a modified example showing another embodiment of a unit circuit composed of a CMOS inverter circuit and a switch MOSFET, which is the core of the identification number generating circuit according to the present invention,
FIG. 15 is a modification showing another embodiment of a unit circuit composed of a CMOS inverter circuit and a switch MOSFET, which is the core of the identification number generation circuit according to the present invention,
FIG. 16 is a circuit diagram showing an embodiment of a CMOS inverter circuit used in the identification number generating circuit according to the present invention,
FIG. 17 is a circuit diagram showing another embodiment of the identification number generating circuit according to the present invention,
FIG. 18 is a waveform diagram for explaining the operation of the embodiment circuit shown in FIG. 17;
FIG. 19 is a block diagram showing another embodiment of the identification number generating circuit according to the present invention,
FIG. 20 is a circuit diagram showing another embodiment of the identification number generating circuit according to the present invention,
FIG. 21 is a schematic block diagram showing one embodiment of a semiconductor integrated circuit device according to the present invention;
FIG. 22 is an element layout diagram showing one embodiment of the semiconductor integrated circuit device according to the present invention,
FIG. 23 is an equivalent circuit diagram corresponding to FIG. 22;
FIG. 24 is a block diagram showing an embodiment when the present invention is applied to a dynamic RAM,
FIG. 25 is a schematic configuration diagram showing one embodiment of a semiconductor integrated circuit device using the identification number generation circuit according to the present invention;
FIG. 26 is an explanatory diagram for explaining an identification number identification algorithm according to the present invention;
FIG. 27 is an explanatory diagram for explaining an identification algorithm of an identification number according to the present invention;
FIG. 28 is a configuration diagram showing one embodiment of a method of registering a collation algorithm in the identification system of the semiconductor integrated circuit device according to the present invention;
FIG. 29 is a block diagram showing one embodiment of a collation algorithm collation method in a semiconductor integrated circuit device identification system according to the present invention;
FIG. 30 is an explanatory view showing an example of the comparison method of FIG. 29,
FIG. 31 is an explanatory diagram showing an example of a comparison method using the order of the logical threshold value of the CMOS inverter circuit.
FIG. 32 is an explanatory diagram showing an example of a comparison method using the order of the logical threshold value of the CMOS inverter circuit.
FIG. 33 is a block diagram showing one embodiment of a semiconductor integrated circuit device to which the present invention is applied.
FIG. 34 is a block diagram showing one embodiment of a multichip module to which the present invention is applied;
FIG. 35 is a block diagram showing one embodiment of the program dedicated chip of FIG. 34;
FIG. 36 is a configuration diagram for explaining a manufacturing process of an embodiment of a semiconductor integrated circuit device equipped with an identification number generation circuit according to the present application;
FIG. 37 is a configuration diagram for explaining a manufacturing process of an embodiment when assembling a semiconductor integrated circuit device equipped with the identification number generation circuit according to the present application on a circuit mounting board,
FIG. 38 is a configuration diagram for explaining a manufacturing process of another embodiment of the semiconductor integrated circuit device equipped with the identification number generating circuit according to the present application,
FIG. 39 is a block diagram showing an example of an application-specific LSI provided with an identification number generating circuit according to the present invention;
FIG. 40 is a circuit diagram showing an embodiment in which the variation of the logical threshold value of the CMOS inverter according to the present invention is applied to a random number generator.
FIG. 41 is a configuration diagram for explaining an example of use of the chip identification number generation circuit according to the present invention for the purpose of reducing fraudulent acts and various troubles in the electronic component procurement market between companies;
FIG. 42 is a schematic plan view showing another embodiment of the semiconductor integrated circuit device according to the present invention,
FIG. 43 is a basic circuit diagram showing another embodiment of the identification number generating circuit according to the present invention,
FIG. 44 is a circuit diagram showing another embodiment of the identification number generating circuit according to the present invention,
FIG. 45 is a specific circuit diagram showing one embodiment of the identification number generating circuit according to the present invention;
FIG. 46 is a specific circuit diagram showing still another embodiment of the identification number generating circuit according to the present invention;
FIG. 47 is a timing chart for explaining the operation of the embodiment circuit of FIG. 46;
FIG. 48 is a circuit diagram showing another embodiment of the unit circuit used in the embodiment of FIG. 46,
FIG. 49 is a circuit diagram showing still another embodiment of the identification number generating circuit according to the present invention;
FIG. 50 is a circuit diagram showing still another embodiment of the identification number generating circuit according to the present invention;
FIG. 51 is a circuit layout diagram showing one embodiment of a semiconductor integrated circuit device or a semiconductor chip to which the present invention is applied;
FIG. 52 is a block diagram showing a standard embodiment of the I / O cell.
FIG. 53 is a circuit layout diagram showing one embodiment of an I / O cell provided in a semiconductor integrated circuit device or a semiconductor chip according to the present invention;
FIG. 54 is a circuit diagram showing one embodiment of an output buffer circuit provided in a semiconductor integrated circuit device or a semiconductor chip according to the present invention;
FIG. 55 is a circuit diagram showing another embodiment of the output buffer circuit provided in the semiconductor integrated circuit device or the semiconductor chip according to the present invention;
FIG. 56 is a schematic configuration diagram showing one embodiment of a semiconductor integrated circuit device according to the present invention;
FIG. 57 is a block diagram showing one embodiment of a basic JTAG cell of the semiconductor integrated circuit device according to the present invention;
FIG. 58 is a block diagram for explaining an embodiment of a serial output operation of an identification number utilizing a shift operation of a boundary scan register of a semiconductor integrated circuit device according to the present invention;
FIG. 59 is a block diagram for explaining another embodiment of the serial number output operation using the shift operation of the boundary scan register of the semiconductor integrated circuit device according to the present invention,
FIG. 60 is a configuration diagram for explaining another embodiment of the serial number output operation using the shift operation of the boundary scan register of the semiconductor integrated circuit device according to the present invention;
FIG. 61 is a configuration diagram for explaining another embodiment of the serial number output operation of the identification number utilizing the shift operation of the boundary scan register of the semiconductor integrated circuit device according to the present invention;
FIG. 62 is a circuit diagram showing still another embodiment of the identification number generating circuit according to the present invention;
FIG. 63 is an explanatory diagram of an identification number according to the present invention;
FIG. 64 is an explanatory diagram of an identification number according to the present invention;
FIG. 65 is a flowchart for explaining an embodiment of a high-speed identification number collation (search) algorithm for identification numbers generated by the identification number generation circuit according to the present invention;
FIG. 66 is a block diagram corresponding to the embodiment of FIG. 65,
FIG. 67 is a flowchart showing one embodiment of a circuit design method for a semiconductor chip incorporating the identification number generation circuit according to the present invention;
FIG. 68 is a flowchart showing one embodiment of an LSI design method incorporating an identification number generating circuit according to the present invention;
FIG. 69 is a flowchart showing one embodiment of a method of manufacturing a semiconductor integrated circuit device using a semiconductor chip having a built-in identification number generating circuit according to the present invention.
FIG. 70 is a flowchart showing one embodiment of an assembling process of a semiconductor integrated circuit device using a semiconductor chip on which an identification number generating circuit according to the present invention is mounted;
FIG. 71 is a block diagram showing an embodiment of a method for reducing the number of bits of the identification number generating circuit according to the present invention,
FIG. 72 is a configuration diagram showing one embodiment of a method for reducing the number of bits of the identification number generation circuit according to the present invention;
FIG. 73 is a configuration diagram for explaining an inspection method using an identification number generation circuit mounted on a semiconductor integrated circuit device according to the present invention;
FIG. 74 is a configuration diagram for explaining an inspection method using an identification number generation circuit mounted on a semiconductor integrated circuit device according to the present invention;
FIG. 75 is a configuration diagram for explaining a method of managing the correlation of characteristic data of each semiconductor chip in each inspection process using an identification number generation circuit mounted on a semiconductor integrated circuit device according to the present invention;
FIG. 76 is a configuration diagram for explaining a method of automatically managing a wafer in a previous process using an identification number generation circuit mounted on a semiconductor integrated circuit device according to the present invention,
FIG. 77 is a configuration diagram for explaining a method of storing and retrieving an identification number of an identification number generation circuit mounted on a semiconductor integrated circuit device according to the present invention;
FIG. 78 is a configuration diagram for explaining another example of a method of storing and retrieving the identification number of the identification number generation circuit mounted on the semiconductor integrated circuit device according to the present invention;
FIG. 79 is a block diagram showing one embodiment of a method for repairing a semiconductor integrated circuit device using an identification number generating circuit according to the present invention;
FIG. 80 is a layout diagram showing one embodiment of a semiconductor integrated circuit device equipped with an identification number generating circuit according to the present invention;
FIG. 81 is a partially enlarged layout diagram of the layout diagram of FIG. 80;
FIG. 82 is a layout diagram showing another embodiment of the semiconductor integrated circuit device equipped with the identification number generating circuit according to the present invention,
FIG. 83 is a circuit diagram corresponding to the layout of FIG. 81,
FIG. 84 is a configuration diagram showing still another embodiment of the semiconductor integrated circuit device equipped with the identification number generation circuit according to the present invention;
FIG. 85 is a partial plan pattern diagram of the semiconductor integrated circuit device constituting the embodiment of FIG. 84;
FIG. 86 is another partial plan pattern diagram of the semiconductor integrated circuit device constituting the embodiment of FIG. 84;
FIG. 87 is a circuit diagram showing one embodiment of a semiconductor integrated circuit device equipped with an identification number generating circuit according to the present invention.

Claims (75)

A plurality of identification elements formed with the same form and formed with the same manufacturing process are attached to the semiconductor integrated circuit device,
A semiconductor integrated circuit that forms information reflecting the magnitude relationship between the physical quantities of the plurality of identification elements, which is provided in correspondence with the mutual variation in the physical quantities of the plurality of identification elements, and adds the information reflecting the magnitude relationship to the semiconductor integrated circuit. A method for identifying a semiconductor integrated circuit device, wherein the method is set as unique identification information of the circuit device. In claim 1,
The method for identifying a semiconductor integrated circuit device, wherein the plurality of identification elements are set in the semiconductor integrated circuit device. In claim 2,
The method for identifying a semiconductor integrated circuit device, wherein the unique identification information further includes first identification information having a value set in the manufacturing process. In claim 2,
The method for identifying a semiconductor integrated circuit device, wherein the unique identification information includes order information indicating a magnitude order of physical quantities of the plurality of identification elements. In claim 3,
The identification method of a semiconductor integrated circuit device, wherein the plurality of identification elements each include a logic circuit, and the magnitude relationship of the physical quantities is a magnitude relationship of electrical parameters of the plurality of logic circuits. In claim 4,
Wherein the plurality of logic circuits output output voltages equal to respective threshold voltages to respective outputs by electrically coupling respective inputs and outputs as the electric parameters. A method for identifying an integrated circuit device. In claim 6,
The method for identifying a semiconductor integrated circuit device, wherein the plurality of logic circuits include an inverter circuit. In claim 7,
The method for identifying a semiconductor integrated circuit device, wherein the identification element comprises a CMOS inverter circuit including an N-channel MOSFET and a P-channel MOSFET. In claim 5,
The method for identifying a semiconductor integrated circuit device, wherein the plurality of logic circuits include an inverter circuit. In claim 9,
The method for identifying a semiconductor integrated circuit device, wherein the identification element comprises a CMOS inverter circuit including an N-channel MOSFET and a P-channel MOSFET. In claim 5,
A method for identifying a semiconductor integrated circuit device, characterized in that application of an operating voltage is restricted to the logic circuit when the operation of determining the magnitude relationship of the electrical parameter as the physical quantity is not performed. In claim 1,
The method for identifying a semiconductor integrated circuit device, wherein the unique identification information includes order information indicating a magnitude order of physical quantities of the plurality of identification elements. In claim 12,
The identification method of a semiconductor integrated circuit device, wherein the plurality of identification elements each include a logic circuit, and the magnitude relationship of the physical quantities is a magnitude relationship of electrical parameters of the plurality of logic circuits. In claim 13,
A method for identifying a semiconductor integrated circuit device, characterized in that application of an operating voltage is restricted to the logic circuit when the operation of determining the magnitude relationship of the electrical parameter as the physical quantity is not performed. In claim 13,
Wherein the plurality of logic circuits output output voltages equal to respective threshold voltages to respective outputs by electrically coupling respective inputs and outputs as the electric parameters. A method for identifying an integrated circuit device. In claim 15,
The method for identifying a semiconductor integrated circuit device, wherein the plurality of logic circuits include an inverter circuit. In claim 16,
The method for identifying a semiconductor integrated circuit device, wherein the identification element comprises a CMOS inverter circuit including an N-channel MOSFET and a P-channel MOSFET. In claim 13,
The method for identifying a semiconductor integrated circuit device, wherein the plurality of logic circuits include an inverter circuit. In claim 18,
The method for identifying a semiconductor integrated circuit device, wherein the identification element comprises a CMOS inverter circuit including an N-channel MOSFET and a P-channel MOSFET. In claim 1,
The identification method of a semiconductor integrated circuit device, wherein the plurality of identification elements each include a logic circuit, and the magnitude relationship of the physical quantities is a magnitude relationship of electrical parameters of the plurality of logic circuits. In claim 20,
A method for identifying a semiconductor integrated circuit device, characterized in that application of an operating voltage is restricted to the logic circuit when the operation of determining the magnitude relationship of the electrical parameter as the physical quantity is not performed. In claim 20,
Wherein the plurality of logic circuits output output voltages equal to respective threshold voltages to respective outputs by electrically coupling respective inputs and outputs as the electric parameters. A method for identifying an integrated circuit device. In claim 22,
The method for identifying a semiconductor integrated circuit device, wherein the plurality of logic circuits include an inverter circuit. In claim 23,
The method for identifying a semiconductor integrated circuit device, wherein the identification element comprises a CMOS inverter circuit including an N-channel MOSFET and a P-channel MOSFET. In claim 20,
The method for identifying a semiconductor integrated circuit device, wherein the plurality of logic circuits include an inverter circuit. In claim 25,
The method for identifying a semiconductor integrated circuit device, wherein the identification element comprises a CMOS inverter circuit including an N-channel MOSFET and a P-channel MOSFET. A method of manufacturing a semiconductor integrated circuit device, which enables reference of manufacturing information specific to the semiconductor integrated circuit device by measuring the semiconductor integrated circuit device,
The semiconductor integrated circuit device has a plurality of identification elements formed in the same form and in the same manufacturing process,
The measurement of the semiconductor integrated circuit device at one stage in the manufacturing process of the semiconductor integrated circuit device allows the mutual identification of the plurality of identification elements to be performed in response to the mutual variation in the physical quantities of the plurality of identification elements. Forming first information that reflects the magnitude relationship of the physical quantities,
An information holding device outside the semiconductor integrated circuit device, using the first information and the second information including management information set in the manufacture of the semiconductor integrated circuit device that provided the information as unique information of the semiconductor integrated circuit device. Will be held in
Thereby, the third information in the information holding device is corresponded from the third information which is the same type of information as the first information obtained by measuring the semiconductor integrated circuit device at a time different from the one time. A method of manufacturing the semiconductor integrated circuit device, wherein the first information is queried, and the second information is queried from the first information queried based on the third information. Forming a semiconductor integrated circuit device constituting a first chip, the semiconductor integrated circuit device having a plurality of identification elements formed in the same form and having the same manufacturing process; ,
Obtaining unique identification information from the plurality of identification elements in the semiconductor integrated circuit device constituting the first chip;
Writing a plurality of unique identification information from the semiconductor integrated circuit devices constituting the plurality of first chips and operation modification information for the semiconductor integrated circuit device that has provided the respective unique identification information to the second chip; ,
A step of integrally assembling the first chip and the second chip,
The assembled second chip is configured to output the operation modification information to the first chip based on unique identification information obtained from the first chip integrally assembled with the second chip. A method for manufacturing a semiconductor integrated circuit device. In claim 28,
The semiconductor integrated circuit device forms, as the unique identification information, information including information reflecting the magnitude relationship between the physical quantities of the plurality of identification elements, which is caused by mutual variation in the physical quantities of the plurality of identification elements. A method of manufacturing a semiconductor integrated circuit device. In claim 29,
The information reflecting the magnitude relationship of the physical quantities of the plurality of identification elements is based on comparison information in which the physical quantities of a plurality of identification elements are compared with the physical quantities of the individual identification elements. A method for manufacturing a semiconductor integrated circuit device. In claim 29,
The method of manufacturing a semiconductor integrated circuit device, wherein the information reflecting the magnitude relationship between the physical quantities of the plurality of identification elements is rank information corresponding to the magnitude permutation of the physical quantities of the plurality of identification elements. In claim 28,
The first chip is a memory having a redundant circuit,
The method of manufacturing a semiconductor integrated circuit device, wherein the second chip stores a defect address of the first chip as the operation modification information. In claim 28,
Performing a further test in a state where the first chip and the second chip are assembled;
A step of removing the second chip and integrating the semiconductor integrated circuit device constituting the first chip into another plurality of semiconductor integrated circuit devices when a failure occurs in the test in the assembled state. A method for manufacturing a semiconductor integrated circuit device, comprising: In claim 33,
The method of manufacturing a semiconductor integrated circuit device, wherein the first chip and the second chip are integrally sealed after the selection in the assembled state. In claim 34,
The method for manufacturing a semiconductor integrated circuit device, wherein the first chip and the second chip are assembled on a common mounting substrate. Having a plurality of identification elements formed as the same form with the same manufacturing process,
A semiconductor integrated circuit device having unique identification information determined by the plurality of identification elements,
A semiconductor integrated circuit characterized in that the unique identification information has a state corresponding to a magnitude relationship between mutual physical quantities of the plurality of identification elements due to characteristic variations of the plurality of identification elements. apparatus. In claim 36,
The semiconductor integrated circuit device, wherein the unique identification information includes a plurality of pieces of comparison information in which a physical quantity of each identification element is compared with a plurality of identification elements. In claim 37,
The unique identification information includes a plurality of pieces of comparison information corresponding to each of the plurality of identification elements,
Each of the plurality of pieces of comparison information is characterized by comprising information of a plurality of bits in which the magnitudes of mutual physical quantities of the corresponding specific identification element and the plurality of identification elements corresponding thereto are compared. Semiconductor integrated circuit device. In claim 38,
Wherein each of the plurality of pieces of comparison information is data-converted to information obtained from a direct comparison between a physical quantity of the specific identification element and a physical quantity of a plurality of identification elements compared thereto. Integrated circuit device. In claim 38,
A semiconductor integrated circuit device, wherein each of the plurality of pieces of comparison information is composed of information whose bit number has been compressed. In claim 40,
The semiconductor integrated circuit device according to claim 1, wherein the order information includes a smaller number of bits than the number of comparisons between the specific identification element and a plurality of identification elements corresponding thereto. In claim 37,
The semiconductor integrated circuit device, wherein the order information includes a plurality of order information corresponding to each of the plurality of identification elements. In claim 36,
2. The semiconductor integrated circuit device according to claim 1, wherein the unique identification information includes order information reflecting the order of the magnitude of the physical quantity of the plurality of identification elements. In claim 43,
The semiconductor integrated circuit device according to claim 1, wherein the order information includes a smaller number of bits than the number of comparisons between the specific identification element and a plurality of identification elements corresponding thereto. In claim 36,
The semiconductor integrated circuit device, wherein the unique identification information further includes first identification information having a value set in the manufacturing process. In claim 36,
The semiconductor integrated circuit device, wherein each of the identification elements comprises a logic circuit, and the magnitude relation of the physical quantities is a magnitude relation of electric parameters of a plurality of logic circuits. In claim 46,
The semiconductor integrated circuit device, wherein the plurality of logic circuits include an inverter circuit. In claim 46,
A semiconductor integrated circuit device, wherein the plurality of logic circuits output output voltages equal to respective threshold voltages to respective outputs by electrically coupling respective inputs and outputs. In claim 48,
The semiconductor integrated circuit device, wherein the plurality of logic circuits include an inverter circuit. In claim 49,
The identification element includes a CMOS inverter circuit composed of an N-channel MOSFET and a P-channel MOSFET that forms an output voltage corresponding to variation in each output terminal when an input voltage is applied to each input terminal. A semiconductor integrated circuit device characterized by the following. In claim 50,
A semiconductor integrated circuit device, wherein the CMOS inverter circuit forms the output voltage by connecting an input terminal and an output terminal thereof. In claim 51,
A voltage comparison circuit;
A first switch provided for each of the plurality of CMOS inverter circuits and transmitting an output voltage of the corresponding CMOS inverter circuit to one input terminal of the voltage comparison circuit; and another input terminal of the voltage comparison circuit A second switch to tell the
A first switch and a second switch corresponding to the plurality of CMOS inverter circuits, each of which compares the output voltage of the plurality of CMOS inverter circuits with the output voltage of another of the plurality of CMOS inverter circuits by the voltage comparison circuit; A control circuit for controlling the switch,
A semiconductor integrated circuit device further comprising: In claim 52,
A semiconductor integrated circuit device, wherein the switch is a switch configured from a MOSFET. In claim 51,
First to third switches provided corresponding to each of the plurality of CMOS inverter circuits;
A control circuit for controlling the first to third switches,
The first switch is provided between an input terminal and an output terminal of a corresponding CMOS inverter circuit,
The second switch is provided between a common first circuit node and an input terminal of a corresponding CMOS inverter circuit,
The third switch is provided between an output terminal of a corresponding CMOS inverter circuit and a common second circuit node,
The control circuit includes a pair of the two CMOS inverter circuits, the input terminal and the output terminal of the one CMOS inverter circuit being connected to each other, and the output voltage from the one CMOS inverter circuit is output from the one CMOS inverter circuit. And the output voltage of the one CMOS inverter circuit is supplied to the input terminal of the other CMOS inverter circuit via the first circuit node, and the output voltage of the other CMOS inverter circuit is supplied to the second circuit node from the other CMOS inverter circuit. The first to third switches are controlled so as to provide an output signal as a result of determining the potential of the output voltage of the one CMOS inverter circuit using the logic threshold voltage of the other CMOS inverter circuit as a reference voltage. A semiconductor integrated circuit device. In claim 54,
A semiconductor integrated circuit device, wherein the switch is a switch configured from a MOSFET. In claim 54,
A semiconductor integrated circuit device wherein the CMOS inverter circuit and the first to third switches use elements constituting a CMOS gate array. In claim 56,
A semiconductor integrated circuit device, wherein the switch is a switch configured from a MOSFET. In claim 54,
The semiconductor integrated circuit device, wherein the plurality of CMOS inverter circuits are configured to limit the application of an operating voltage when the physical quantity voltage determination operation is not performed. In claim 58,
A semiconductor integrated circuit device, wherein the switch is a switch configured from a MOSFET. A first inverter circuit;
A first switch provided between an input terminal and an output terminal of the first inverter circuit;
A second inverter circuit having an input terminal connected to an output terminal of the first inverter circuit,
A plurality of identification elements including an amplifier circuit that receives an output signal of an output terminal of the second inverter circuit;
A semiconductor chip comprising an identification number circuit for generating identification number information based on an output signal of the amplifier circuit when the first switches of the plurality of identification elements are on. In claim 60,
The inverter circuit includes a CMOS inverter circuit,
The semiconductor chip further includes a voltage forming circuit that forms a voltage to be applied to an input terminal of the first inverter circuit when the first switch is in an off state,
The voltage forming circuit forms a voltage at a level that avoids inversion due to aging of the output signal based on the level of the output signal of the amplifier circuit when the first switch is on. A semiconductor chip characterized by the above-mentioned. In claim 61,
The semiconductor chip includes a signal path for setting the voltage of the voltage generation circuit via the first and second inverter circuits,
If the output signal of the second inverter circuit when the first switch is in the ON state is higher than the logical threshold value, the voltage generation circuit generates a low-level output voltage corresponding to the logic threshold value; A latch circuit set to form a high level when the output signal of the second inverter circuit is at a low level with respect to the logical threshold value when the first switch is on. Characteristic semiconductor chip. In claim 62,
A semiconductor chip, wherein the latch circuit is set on an output path of the amplifier circuit. In claim 60,
The first inverter circuit and the second inverter circuit are composed of CMOS inverter circuits,
A second switch is provided between the first inverter circuit and the second inverter circuit;
Each of the input terminals of the CMOS inverter circuits constituting the first inverter circuit, the second inverter circuit, and the amplifier circuit is provided with a second switch for applying a high-level potential,
A third switch is provided between the first inverter circuit and the second inverter circuit;
When the identification number circuit is inactive, the first switch is turned off, the second switch is turned on, and the third switch is turned off. Set the terminal to the high-level potential,
A semiconductor chip characterized in that when the identification number circuit is operating, the first switch and the third switch are turned on and the second switch is turned off. A first inverter circuit and a second inverter circuit;
A first switch provided between an input terminal and an output terminal of each of the first inverter circuit and the second inverter circuit;
A second switch provided between an output terminal of the first inverter circuit and an input terminal of the second inverter circuit;
A plurality of identification elements including an amplifier circuit including a third inverter circuit in which an output terminal of the second inverter circuit is connected to an input terminal;
The output of the amplifier circuit including the third inverter circuit when the first switch of the first inverter circuit is turned on, the first switch of the second inverter circuit is turned off, and the second switch is turned on. First identification information is obtained by a signal,
Identification in which the first switch of the second inverter circuit is turned on and the output signal of the amplifier circuit including the third inverter circuit when the second switch is turned off obtains second identification information. A semiconductor chip having a built-in identification number circuit for generating a number. In claim 65,
The first inverter circuit and the second inverter circuit form a circuit row, and a plurality of circuit rows are provided in a form in which the first inverter circuit and the second inverter circuit are arranged correspondingly,
A common switch control signal is supplied to a corresponding first switch of the plurality of circuit rows, and an output signal of the second inverter circuit of the plurality of circuit rows is a third switch for selecting a desired circuit row in the plurality of circuit rows. A semiconductor chip, which is supplied to an input terminal of the third inverter circuit forming the amplification circuit via an input terminal. In claim 66,
Input terminals of the first inverter circuit and the second inverter circuit are provided with a fourth switch for interrupting an input signal and a fifth switch for supplying a high-level voltage,
A semiconductor chip wherein the fourth switch is turned off and the fifth switch is turned on when the identification number circuit is not operating. A plurality of unit elements including a first inverter circuit, a first switch for short-circuiting an input terminal and an output terminal of the first inverter circuit, and a second switch provided at an input terminal of the first inverter circuit, An identification element sequence formed in a tandem form via a second switch;
An amplifier circuit including a second inverter circuit in which an output terminal of the first inverter circuit corresponding to the last stage of the identification element sequence is connected to an input terminal;
A binary counter for counting clocks,
A decoder provided for receiving the count output of the binary counter and corresponding to the first switch and the second switch of each first inverter circuit of the identification element sequence;
In response to the count output of the binary counter, the identification element is sequentially turned on from the first stage circuit, the second switch is turned off complementarily with the first switch, and the output signal of the amplifier circuit including the third inverter circuit is output. A semiconductor chip having a built-in identification number circuit for generating an identification number by obtaining a plurality of pieces of identification information corresponding to each of the first inverter circuits of the identification element sequence. A plurality of unit elements including a first inverter circuit, a first switch for short-circuiting an input terminal and an output terminal of the first inverter circuit, and a second switch provided at an input terminal of the first inverter circuit, An identification element sequence formed in a tandem form via a second switch;
An amplifier circuit including a second inverter circuit in which an output terminal of the first inverter circuit corresponding to the last stage of the identification element sequence is connected to an input terminal;
A shift register that receives a clock and has shift bits corresponding to the first switch and the second switch of each first inverter circuit of the identification element sequence;
Corresponding to the shift operation of the shift register, the identification elements are sequentially turned on from the first circuit to the first switch, and the second switch is turned off complementarily to the first switch to include the third inverter circuit. A semiconductor chip having a built-in identification number circuit for generating an identification number by obtaining a plurality of pieces of identification information corresponding to each of the first inverter circuits in the identification element row based on an output signal of the amplifier circuit. A first inverter circuit, a first switch for short-circuiting an input terminal and an output terminal of the first inverter circuit,
A plurality of identification elements including a second inverter circuit having an input terminal connected to an output terminal of the first inverter circuit, and an amplifier circuit for amplifying a signal at an output terminal of the second inverter circuit;
A semiconductor integrated circuit device comprising an identification number circuit for generating an identification number based on an output signal of the amplifier circuit when the first switches of the plurality of identification elements are on. A plurality of unit elements including a first inverter circuit, a first switch for short-circuiting the input terminal and the output terminal of the first inverter circuit, and a second switch provided at an input terminal of the first inverter circuit are provided by the first inverter circuit. A sequence of identification elements arranged in tandem via two switches;
An amplifier circuit including a second inverter circuit in which an output terminal of the first inverter circuit corresponding to the last stage of the identification element sequence is connected to an input terminal;
A binary counter for counting clocks,
A decoder provided for receiving the count output of the binary counter and corresponding to the first switch and the second switch of each first inverter circuit of the identification element sequence;
In response to the count output of the binary counter, the identification elements are sequentially turned on from the first stage to the first switch, and the second switch is turned off complementarily to the first switch to include the third inverter circuit. A semiconductor integrated circuit device having a built-in identification number circuit for generating an identification number so as to obtain a plurality of pieces of identification information corresponding to each of the first inverter circuits in the identification element row based on an output signal of the amplifier circuit; . A plurality of unit elements including a first inverter circuit, a first switch for short-circuiting an input terminal and an output terminal of the first inverter circuit, and a second switch provided at an input terminal of the first inverter circuit, An identification element sequence formed in a tandem form via a second switch;
An amplifier circuit including a second inverter circuit in which an output terminal of the first inverter circuit corresponding to the last stage of the identification element sequence is connected to an input terminal;
A shift register that receives a clock and has shift bits corresponding to the first switch and the second switch of each first inverter circuit of the identification element sequence;
In response to the shift operation of the shift register, the identification element includes the third inverter circuit in which the first switch is turned on sequentially and the second switch is turned off complementarily with the first switch in order from the first stage circuit. A semiconductor integrated circuit having a built-in identification number circuit for generating an identification number for obtaining a plurality of identification information corresponding to each of the first inverter circuits of the identification element row based on an output signal of the amplifier circuit. Circuit device. In claim 72,
Further equipped with a test circuit adapted to the JTAG project,
A semiconductor integrated circuit device which outputs an identification number generated by the identification number circuit through an interface conforming to the JTAG standard. In claim 72,
A semiconductor integrated circuit device, wherein a circuit design and a circuit layout of the identification number circuit including the unit element, the first switch, and the second switch are performed using soft IP technology. A plurality of unit elements including a first inverter circuit, a first switch for short-circuiting an input terminal and an output terminal of the first inverter circuit, and a second switch provided at an input terminal of the first inverter circuit, An identification element sequence formed in a tandem form via a second switch;
An amplifier circuit including a second inverter circuit in which an output terminal of the first inverter circuit corresponding to the last stage of the identification element sequence is connected to an input terminal;
A shift register that receives a clock and has shift bits corresponding to the first switch and the second switch of each first inverter circuit of the identification element sequence;
In response to the shift operation of the shift register, the identification element includes the third inverter circuit in which the first switch is turned on sequentially and the second switch is turned off complementarily with the first switch in order from the first stage circuit. An identification number circuit for generating an identification number for obtaining a plurality of identification information corresponding to each of the first inverter circuits of the identification element row based on an output signal of the amplifier circuit has a circuit design and circuit layout using soft IP technology. And a method for manufacturing a semiconductor integrated circuit device.

Images