JP5013387B2 - Integrated circuit device identification method, integrated circuit device manufacturing method, integrated circuit device, semiconductor chip, and mount - Google Patents

Description

構成図が示されている。この実施例では、本体ＬＳＩをＤＲＡＭとＳＲＡＭが混載された大規模システムＬＳＩとし、プログラム専用チップはレーザ切断メタルフューズの使用を前提としている。以下、図３６図を用いて製造工程の流れを説明する。
▲１▼ 本体ＬＳＩをプローブ試験テスタにより試験する。ＤＲＡＭやＳＲＡＭの不良メモリセル救済情報、内部電源回路トリミング設定値、ディレイ回路設定値などと一緒に、ＬＳＩ内の識別番号をホストコンピュータに転送する。ホストコンピュータは、送られた情報やその他の製造管理情報などと連結しデータベースに格納する。
▲２▼ 本体ＬＳＩウエハをダイシングする。
▲３▼ 本体ＬＳＩのみ、マルチチップモジュール基板に仮実装する。本図では、本体ＬＳＩは１つであるが複数であることもある。
▲４▼ 選別試験テスタにより本体ＬＳＩから識別番号を読み出し、ホストコンピュータに送る。ホストコンピュータは、識別番号から本体ＬＳＩを認識し、個々の本体ＬＳＩに必要な情報をテスタに返す。必要な情報とは、上記の不良メモリセル救済情報や、本体ＬＳ１識別情報などホストコンピュータによりデータベースで管理されていたものである。これを本体ＬＳＩレジスタ情報と呼ぶ。選別試験テスタは、本体ＬＳＩレジスタ情報を、例えば不良メモリセル救済情報であれば、本体ＬＳＩ内の救済回路の救済アドレスレジスタに格納し、内部電源回路設トリミング定値であれば内部回路内のトリミング値設定レジスタに格納する。
選別試験テスタは、本体ＬＳＩレジスタ情報設定後、プローブ試験ではできないような高速動作試験などを行う。さらにここで新たに不良になったものについては、その不良情報をホストコンピュータに転送する。ホストコンピュータは、送られた不良情報とで採取した情報を合わせ再救済や調整が可能であるか解析し、再びデータベースに格納する。
▲５▼ プログラム専用チップに、本体ＬＳＩに必要なレジスタ情報をプログラムする。さらに必要であれば、製造管理情報や、顧客情報、暗号、機能情報などのプログラムを行う。プログラム専用チップは、１チップに複数の本体ＬＳＩの情報を格納できる。例えば、１００個の本体ＬＳＩ分の容量があるとすると、レーザ切断装置は、ホストコンピュータから１００個の本体ＬＳＩ分の識別番号とレジスタ情報を受け取り、受け取った情報をもとに、１００個のプログラム専用チップに全て同じ１００本体ＬＳＩ分のレジスタ情報をプログラムする。
ここで、プログラム専用チップのフューズ切断時間を見積もってみる。例えば、１個の本体ＬＳＩ当たりのプログラムビット数が１０００ビット、１個のプログラム専用チップに１００本体ＬＳ１分格納（登録）できるとすると、１つのプログラム専用チップは１０万本（１０００×１００）のヒューズを搭載する。最新のレーザ切断装置の能力は、毎秒５０００パルス以上であるので、約２０秒で１０万本すなわち１個のプログラム専用チップの切断が可能である。１００チップでは、２０００秒（３３分）である。また、プログラム専用チップの面積は、１つのフューズの大きさを１５平方マイクロンとすると、フューズ部だけで１．５平方ミリメートル、周辺回路やパッドを含めると約３平方ミリメートルである。
▲６▼ レーザ切断不良チップを除去するため、プローブ検査を行う。なお本工程の前に、チップを保護する保護膜を付ける工程を付加することもある。検査データパターンは、ホストコンピュータから受け取る。ここで、レーザ切断不良チップが発生することもあるので、前記工程▲５▼でプログラムされるチップ数は、１００個よりも多めとする。この数は歩留の実績によって調整する。ここで、プログラム専用チップが本体ＬＳＩより少なく不足した場合、余つた本体ＬＳＩは回収され別のグループに混成される。逆に、プログラム専用チップが余つた場合は廃棄する。いずれにしても損害になるが、貴重な本体ＬＳＩを廃棄するよりは経済的である。
▲７▼ プログラム専用チップをダイシングする。ダイシングされたチップは、工程▲６▼において同一のプログラムがされた１００個と余裕分がピックアップされ、本体ＬＳＩに対応するグループ（ロット）にまとめられる。
▲８▼ プログラム専用チップをマルチチップモジュールパッケージに実装する。この時、前記工程▲４▼と▲６▼で対応付けられたグループが組み合わされなければならない。しかし、個々の本体ＬＳＩとプログラム専用チップを一対一で対応させる必要がないので、従来の組立工程と比べ大幅な工程の変更は必要ない。なお、本実施例では、本組立工程では後の分離

しもこの方法に限定するものではない。
▲９▼ 完成したマルチチップモジュールが最終選別試験される。プログラム専用チツプには、上記実施例では、１００チップ分の救済情報が収められて（登録されて）いる。ボード上の本体ＬＳＩが立ち上がる際、本体ＬＳＩとプログラム専用チップの間でデータ交換が行われる。具体的には、本体ＬＳＩから識別番号がプログラム専用チップに送られ、プログラム専用チップは、送られた識別番号と登録された識別番号を比較し、モジュールに実装された本体ＬＳＩを認識し、救済情報など必要なレジスタ情報を本体ＬＳＩに送る。本体ＬＳＩは、送られたレジスタ情報をもとに内部の初期設定を行う。その後、最終試験が行われる。含格したものは、次の封止工程に送られ、不合格のものは、分離工程に送られると同時に、不良情報がホストコンピュータに送られ、再生可能であるか解析される。

る。

れる。

ＳＩから識別番号が読み出され、それに対応する過去のプロープ試験情報、選別試験情報、最終選別試験情報などがホストコンピュータから取り出される。また図示してしないが、この新たな再生可能品について、非再生品と同様にプログラム専用チップが作成され同様の工程を進行する。プログラム専用チップとして、電気的にプログラム可能な素子によるものに置き換えることもできる。この場合、工程数が削減できる。
第３７図には、本願に係る識別番号発生回路を搭載した半導体集積回路装置を回路実装ボードに組み立てる場合の一実施例の製造工程▲１▼ない

▲１▼ 本体ＬＳＩをプローブ試験テスタにより試験する。ＤＲＡＭやＳＲＡＭの不良メモリセル救済情報、内部電源回路トリミング設定値、ディレイ回路設定値などと一緒に、ＬＳＩ内の識別番号をホストコンピュータに転送する。ホストコンピュータは、送られた情報やその他の製造管理情報などを連携しデータベースに格納する。
▲２▼ 本体ＬＳＩウエハをダイシングする。
▲３▼ 本体ＬＳＩをパッケージに組み立てる。
▲４▼ 第３６図の工程▲４▼と同じ。
▲５▼ 第３６図の工程▲５▼と同じ。
▲６▼ プログラム専用チップをダイシングする。ダイシングされたチップは、第３６図の実施例と同様に、本体ＬＳＩに対応するグループ（ロット）にまとめられる。
▲７▼ 第３６図の工程▲７▼と同じ。
▲８▼ 本体ＬＳＩとプログラム専用チップを回路実装ボードに実装する。この時、前記工程▲４▼と▲６▼とで対応付けられたグループが組み合わされなければならない。しかし、個々の本体ＬＳＩとプログラム専用チップを一対一で対応させる必要がないので、従来の組立工程と比べ大幅な工程の変更は必要ない。
▲９▼ 完成したボードが実装試験される。ボード上の本体ＬＳＩが立ち上がる際、本体ＬＳＩとプログラム専用チップの間でデータ交換が行われる。本体ＬＳＩまたはプログラム専用チップおよびボード実装にともなう不具合が確認されたものは、分離工程に送られると同時に、不良情報がホストコンピュータに送られ、再生可能であるか解析される。

れる。

る。今回のレジスタ情報は、前回のレジスタ情報に実装試験結果が加えられたものである。

たプログラム専用チップとともに１つの実装ボードに実装され、以降同様の工程を進行する。

なお、ここに示した実施例は、一実施例にすぎず、適用される製品や既存の生産ラインの形態により変化する。
第３８図には、本願に係る識別番号発生回路を搭載した半導体集積回

▲１▼ 本体ＬＳＩをプローブ試験テスタにより試験する。ＤＲＡＭやＳＲＡＭの不良メモリセル救済情報、内部電源回路トリミング設定値、ディレイ回路設定値などと一緒に、ＬＳＩ内の識別番号をホストコンピュータに転送する。ホストコンピュータは、送られた情報やその他の製造管理情報などを連携しデータベースに格納する。
▲２▼ 本体ＬＳＩウエハをダイシングし、救済可能チップを選別する。
▲３▼ 本体ＬＳＩをベビーボードに仮組み立てする。
▲４▼ 組み立て不良などをチェック後に、エージングを行う。このとき、ベビーボード上のチップからは識別番号を読み出し、ホストコンピュータからは個々のチップに対応した救済データを取り出、ベビーボード上のチップに格納させる。
▲５▼ テスタによる選別を行う。
▲６▼ ベビーボードから本体ＬＳＩを分離する。
▲７▼ 本体ＬＳＩを出荷する。
▲８▼ 顧客にて本体ＬＳＩと同時にプログラムデバイスを回路実装ボードに実装する。
▲９▼ 本体ＬＳＩから識別番号を取り出す。

上記実装された本体ＬＳＩに対応したデータを受け取り、上記プログラムデバイスに転送されてデータを格納する。通信回線を用いずに例えばＣＤＲＯＭのような電子メディアを使って配布してもよい。

以上の各実施例の半導体集積回路装置の製造方法においては、
（１） 本体ＬＳＩとプログラム専用チップの組み合わせは、プログラム専用チップに登録される本体ＬＳＩ数であるため、一対一の管理が不要となり、生産性が向上するとともに既存の生産設備の変更が少なくて済む。
（２） プログラム専用チップにレーザ切断フューズが使用できる。メタルフューズの他の電気的プログラミング可能な素子に対しての長所は、標準ＣＭＯＳプロセスに対して変更が小規模、本体ＬＳ１の仕様に合わせた設計変更が容易であり、プロセスの世代に依存しないことなどである。標準プロセスからの変更点は、最終配線層形成とパッシベーション工程である。
（３） 本体ＬＳＩレジスタは、ラッチ回路でよいので面積が小さく、本体ＬＳＩのチップサイズ低減になる。
（４） 本体ＬＳＩにチップ識別番号発生回路を搭載すれば、本体チップにプログラマブル素子プロセスを追加する必要がない。
（５） プログラム専用チップの置き換え（リペア）ができる。モジュールやポードに実装後に本体ＬＳＩに修正や問題が発生した時、プログラム内容を変更したチップを交換することで対応できる。
（６） ホストコンピュータを中心とした情報の交換を、ネットワークを利用して実現することで離れた場所の製造工場を使用することができ、経済的な生産活動が可能となる。
第４０図は、ＣＭＯＳインバータの論理しきい値のバラツキを乱数発生器に応用した実施例である。より具体的な実施例として、第３９図のような特定用途向けＬＳＩを用いて説明する。このＬＳＩは、玩具用ロボットの制御のためである。現在、市販されている玩具用ロボットは、特に愛玩用飼育ロボットなどは工場出荷時点では、画一的な性格を持っている。しかし、それを実際の生物や動物に似せるために、例えばオスかメスという性別、気性、運動能力いった先天的あるいは遺伝的な特徴を持たせることで、それを保有する購入者に対し、さらに生き物としての強い感情を抱かさせることができる。
第４０図では、先天的な特徴を、プログラムなしでＬＳＩが製造された時に専用ＬＳＩに持たせるための最も単純な回路である。これは、２進数で４ビットの乱数を出力するもので、各ビットの出力値は個々のＬＳＩごとにランダムに発生する，例えば、Ｄ０はオスかメスを決定する。Ｄ１は気性を、Ｄ２とＤ３は飼い主に対する依存度を４段階で決定する。なお、Ｄ０とＤ１、Ｄ２とＤ３に２種類の回路方式を示しているが、基本的に２つのＣＭＯＳインバータの論理しきい値の違いを取り出すことは変わらない。
このような先天的は個性をロボットに持たせることは、他の方法でも可能ではある。例えば、制御プログラムの中身のパラメータを個々に変更することで可能ではある。しかし、それは製造メーカーによりプログラム、つまり人間によって作られたものであるという感覚が否めない。本実施例で示した方法によると、個々の個性は製造したメーカーにもコントロールできないという、いわば「神の摂理」のようなものが感じられて商品としての価値が高まる。
第４１図は、企業間の電子部品調達市場における不正行為や様々なトラブルを軽減することを目的とした、本願発明に係るチップ識別番号発生回路の利用例の他の構成図が示されている。
工場から出荷される半導体ＬＳＩには、前記のようなチップ識別番号発生回路が組み込まれている。工場すなわちメーカは、出荷品全てのチップ識別番号を採取する。チップ識別番号は、ランダムであるので管理上都合の良いＬＳＩ管理番号と対応させる。さらに各種の管理情報、例えば生産ライン名や製造日などと関連付ける。
第４１図の▲１▼のように顧客Ａに直接納入する場合、製品を梱包したユニット（箱など）番号や顧客番号などの帳票データなどの情報をデータベースの管理情報に追加する。品物を受け取つた顧客Ａは、受け入れ検査時にチップ識別番号を全ＬＳＩまたは抜き取つたＬＳＩから読み出す。次に顧客Ａは、例えばインターネツトなどのネットワークを通じメーカのデータベースにアクセスする。データベースから、入荷したユニツトに含まれるＬＳＩのチップ識別番号を取り出し、入荷したＬＳＩから読み出した識別番号と比較する。識別番号どうしが一致すれば、製品の納入が正しいことが確認できる。この手法は汎用品でも顧客カスタム品でも可能であるが、特にカスタム品の場合有効である。
第４１図において、仲介業者（卸業者）が介入する場合を想定してみる。工場出荷は、上記と同じである。受け取った１次卸業者は、通常梱包を開梱しないが、ユニット番号をメーカのサーバに照会すると同時に、次の納品先情報などを登録する。さらに２次、３次の卸業者も同様にする。最終顧客は、前記▲１▼と同様に入荷したＬＳＩの識別番号をＬＳＩから読み出し、メーカのデータベースに照会する。以上のシステムを構築することで次のような効果が期待できる
（１）納入品の取り違えが防止できる。
（２）仲介業者による中古品の入れ替えなどの不正行為を防止できる。
（３）返品による不良品および中古品の再販を防止できる。
（４）流通ルートの確認ができる。
第４２図には、この発明に係る半導体集積回路装置の他の一実施例の模試的平面図が示されている。同図は、半導体装置の樹脂封止体の上部を除去した状態の模式的平面図であり、ＭＣＰ（Ｍｕｌｔｉ Ｃｈｉｐ Ｐａｃｋａｇｅ）型と呼称される半導体装置に適用される。この実施例のＭＣＰ型半導体装置においては、２つの半導体チップを積層して１つのパッケージに組み込んだものである。このうち半導体集積回路装置１０はベースチップとされて第３３図、第３４図等の本体ＬＳＩとされる。そして、その上に搭載された半導体チップ２０が前記プログラム専用チップとされる。この実施例のＱＦＰ型半導体装置３０Ａは、２つの半導体チップ（本体ＬＳＩ１０，フログラム専用チップ）を上下に積層し、この２つの半導体チップを１つの樹脂封止体１７で封止した構成になっている。
本体ＬＳＩ１０及びプログラム専用チップ２０は異なる平面サイズ（外形寸法）で形成され、夫々の平面形状は方形状で形成されている。本実施形態において、本体ＬＳＩ１０の平面形状は例えば４．０５［ｍｍ］×４．１５［ｍｍ］の長方形で形成され、プログラム専用チップ２０の平面形状は例えば１．９９［ｍｍ］×１．２３［ｍｍ］の長方形で形成されている。
本体ＬＳＩ１０及びプログラム専用チップ２０は、例えば、単結晶シリコンからなる半導体基板と、この半導体基板の回路形成面上において絶縁層、配線層の夫々を複数段積み重ねた多層配線層と、この多層配線層を覆うようにして形成された表面保護膜（最終保護膜）とを有する構成となっている。
本体ＬＳＩ１０の互いに対向する回路形成面（一主面）１０Ａ及び裏面（他の主面）のうちの回路形成面１０Ａには、複数のボンディングパッド１１が形成されている。この複数のボンディングパッド１１は、本体ＬＳＩ１０の多層配線層のうちの最上層の配線層に形成されている。最上層の配線層はその上層に形成された表面保護膜で被覆され、この表面保護膜にはボンディングパッド１１の表面を露出するボンディング開口が形成されている。
プログラム専用チップ２０の互いに対向する回路形成面（一主面）２０Ａ及び裏面（他の主面）のうちの回路形成面２０Ａには、複数のボンディングパッド２１が形成されている。この複数のボンディングパッド２１は、プログラム専用チップ２０の多層配線層のうちの最上層の配線層に形成されている。最上層の配線層はその上層に形成された表面保護膜で被覆され、この表面保護膜にはボンディングパッド２１の表面を露出するボンディング開口が形成されている。
本体ＬＳＩ１０のボンディングパッド１１及びプログラム専用チップ２０のボンディングパッド２１の平面形状は、例えば６５［μｍ］×６５［μｍ］の正方形で形成されている。
本体ＬＳＩ１０の複数のボンディングパッド１１は、本体ＬＳＩ１０の４つの辺（互いに対向する２つの長辺（１０Ａ１，１０Ａ２）及び互いに対向する２つの短辺（１０Ａ３，１０Ａ４））に沿って配列されている。プログラム専用チップ２０の複数のボンディングパッド２１は、ＥＥＰＲＯＭ用チップ２０の４つの辺（互いに対向する２つの短辺（２０Ａ１，２０Ａ２）及び互いに対向する２つの長辺（２０Ａ３，２０Ａ４））に沿って配列されている。
プログラム専用チップ２０は、プログラム専用チップ２０の他の主面である裏面が本体ＬＳＩ１０の回路形成面１０Ａと向かい合う状態で本体ＬＳＩ１０の回路形成面１０Ａ上に配置され、接着層１５を介在して本体ＬＳＩ１０の回路形成面１０Ａに接着固定されている。本実施形態において、接着層１５としては例えばポリイミド系の接着用樹脂フィルムを用いている。
本体ＬＳＩ１０は、その裏面がダイパッドと向かい合う状態で、接着層を介在してダイパッドに接着固定されている。ダイパッドには４本の吊りリード６が一体化され、これらのダイパッド５及び４本の吊りリード６で支持体が構成されている。
樹脂封止体１７の平面形状は方形状で形成されている。本実施形態において、樹脂封止体１７の平面形状は例えば１０［ｍｍ］×１０［ｍｍ］の正方形で形成されている。樹脂封止体１７は、低応力化を図る目的として、例えばフェノール硬化剤、シリコーンゴム及びフィラー等が添加されたエポキシ系の樹脂で形成されている。この樹脂封止体１７の形成においては、大量生産に好適なトランスファモールド法が用いられている。トランスファモールド法は、ポット、ランナー、流入ゲート及びキャビティ等を備えた成形金型を使用し、ポットからランナー及び流入ゲートを通してキャビティの内部に樹脂を注入して樹脂封止体を形成する方法である。
本体ＬＳＩ１０の周囲には、樹脂封止体１７の各辺に沿って配列された複数のリード２が配置されている。複数のリード２の夫々は、内部リード部（インナーリード）及びこの内部リード部と一体に形成された外部リード部（アウターリード）を有する構成となっている。各リード２の内部リード部は樹脂封止体１７の内部に位置し、外部リード部は樹脂封止体１７の外部に位置する。即ち、複数のリード２は、樹脂封止体１７の内外に亘って延在している。各リード２の外部リード部は、面実装型リード形状の１つである例えばガルウィング型リード形状に折り曲げ成形されている。
この実施例では、本体ＬＳＩ１０には、前記のようにＣＭＯＳインバータ回路の論理しきい値の大小関係で生成される識別番号発生回路を備えている。このようなＣＭＯＳインバータ回路を用いた場合には、本体ＬＳＩに動作電圧を供給し、識別番号発生回路を動作させるような制御信号の入力が必要である。そのために、簡単な構成ではあるが特別な電源供給装置と信号読み出し装置が必要になる。
半導体集積回路装置が流通経路にあるとき、その識別番号を知りたいて時がしばしば生じ、その環境のもとでは動作電圧の供給ができない場合も考えられる。本願の発明思想は、半導体集積回路装置の製造工程の過程で同一の形態からなる複数の識別要素のプロセスバラツキに対応した物理量の大小関係を判定するものである。半導体集積回路装置では、複数のリードを有し、そのリード幅ｄは一律になるようにプレス等により形成される。
しかしながら、複数のリードの幅ｄ１，ｄ２等はプロセスバラツキが生じるものとなる。そこで、複数のリードのリード幅ｄ１、ｄ２等を光学装置で測定し、その大小比較を行うことにより、前記ＣＭＯＳインバータ回路の論理しきい値と同様にプロセスバラツキを利用した識別番号生成に利用するものである。この構成では、測定装置によりリードのリード幅を複数個測定し、その大小関係を判定することで前記同様な半導体集積回路装置に固有の識別番号を判定することができる。
つまり、半導体集積回路装置の出荷前に前記のように１６本のリードを決めておいて、そのリードの幅、あるいはリード間のピッチ等を測定し、その位置情報と大小関係をデータベース化して保持させる。リード幅ピッチを測定する場合、リード２がパッケージ１７から突出する部分で行うことが望ましい。この測定は、光学装置により単時間で行うことができるから出荷時の識別番号の判定にはさほど時間を要しない。
ＣＭＯＳ回路を搭載しない半導体集積回路装置にも利用できるし、ＣＭＯＳ回路の半導体集積回路装置では、前記ＣＭＯＳインバータ回路の電気的な識別番号と組み合わせて使用するものであってもよい。このような２通りの物理量のバラツキを総合的に判断して識別番号の判定をより確実にすることができる。
第４３図には、この発明に係る識別番号発生回路の他の一実施例の基本的回路図が示されている。前記実施例では、第７図に代表される回路により、複数のＣＭＯＳインバータ回路のバラツキの論理しきい値の順番を識別番号とするものであった。これに対して、この実施例では、２つのＣＭＯＳインバータ回路ＩＮＶ１とＩＮＶ２の論理しきい値の比較結果を識別番号の１ビットにするものである。この考えは、前記第４０図の実施例でも利用されている。
この実施例では、２つのＣＭＯＳインバータ回路ＩＮＶ１とＩＮＶ２の論理しきい値の比較は、次のようにして行われる。インバータ回路ＩＮＶ１の入力端子と出力端子との間には、短絡用のＮチャンネル型ＭＯＳＦＥＴＱ２が設けられる。特に制限されないが、このＣＭＯＳインバータ回路ＩＮＶ１の入力端子と電源電圧ＶＤＤとの間には、Ｐチャンネル型ＭＯＳＦＥＴＱ１が設けられる。これらのＭＯＳＦＥＴＱ１とＱ２のゲートには、識別番号回路イネーブル信号ＥＮが供給される。
上記インバータ回路ＩＮＶ１の出力端子は、上記インバータ回路ＩＮＶ２の入力端子に接続される。このインバータ回路ＩＮＶ２の出力信号は、同様なＣＭＯＳインバータ回路ＩＮＶ３ないしＩＮＶ５の縦列回路からなる増幅回路により２値化されて出力端子ＯＵＴから識別番号出力が形成される。
識別番号回路イネーブル信号ＥＮがロウレベルとき、回路は非活性状態であり、ＭＯＳＦＥＴＱ１がオン状態となりＣＭＯＳインバータ回路ＩＮＶ１の入力端子には電源電圧ＶＤＤに対応したハイレベルが供給される。このとき、ＭＯＳＦＥＴＱ２はオフ状態にされ、インバータ回路ＩＮＶ１の出力信号はロウレベルにされ、以下、インバータ回路列ＩＮＶ２〜ＩＮＶ５により、ハイレベル、ロウレベル…のように順次に反転信号が伝達される。
ＣＭＯＳインバータ回路を構成するＭＯＳＦＥＴは、そのゲートバイアス電圧の印加状態によっては、その特性が不所望に変化してしまう可能性を持つ。Ｐチャンネル型ＭＯＳＦＥＴとＮチャンネル型ＭＯＳＦＥＴとでは、第１９図に対する説明で紹介し、また次の第４４図でも説明するようなＮＢＴＩ現象による影響もあり、Ｐチャンネル型ＭＯＳＦＥＴの方が比較的大きな特性変動を生ずる可能性が高い。
第４３図の識別番号回路の非活性状態時オン状態となるプルアップ動作のＭＯＳＦＥＴＱ１は、初段ＣＭＯＳインバータ回路の貫通電流防止の作用と共に、かかる初段ＣＭＯＳインバータ回路におけるＰチャンネル型ＭＯＳＦＥＴのゲート電位をそのソース電位すなわち電源電位レベルの高電位に維持させることによって、かかるＰチャンネル型ＭＯＳＦＥＴの特性変動を充分に抑える作用を持つ。
識別番号回路が活性化されるとき、つまり識別番号を生成するときには、上記信号ＥＮがハイレベルにされる。これにより、ＣＭＯＳインバータ回路ＩＮＶ１は入力と出力とがＭＯＳＦＥＴＱ２により短絡させられて、その論理しきい値電圧に対応した電圧を生成する。ＣＭＯＳインバータ回路ＩＮＶ１の論理しきい値に対応した電圧は、ＣＭＯＳインバータ回路ＩＮＶ２の入力端子に供給される。ＣＭＯＳインバータ回路ＩＮＶ２は、自身の論理しきい値電圧と上記ＣＭＯＳインバータ回路ＩＮＶ１の論理しきい値に対応した電圧とを比較する。
上記インバータ回路ＩＮＶ１の論理しきい値がインバータ回路ＩＮＶ２のそれより低い時、その出力電位は、インバータ回路ＩＮＶ２の論理しきい値電圧より高くなる。つづく、インバータ回路ＩＮＶ３、ＩＮＶ３、ＩＮＶ５によって上記インバータ回路ＩＮＶ２の出力信号は増幅され、ノードＮ５の電位はＶＳＳ近くになる。上記とは逆にインバータ回路ＩＮＶ１の論理しきい値がインバータ回路ＩＮＶ２のそれより高い時、その出力電位は、インバータ回路ＩＮＶ２の論理しきい値電圧より低くなる。つづく、インバータ回路ＩＮＶ３、ＩＮＶ３、ＩＮＶ５によつて上記インバータ回路ＩＮＶ２の出力信号は増幅され、ノードＮ５の電位はＶＤＤ近くになる。
第４４図には、この発明に係る識別番号発生回路の他の一実施例の回路図が示されている。同図においては、動作に特徴があるので、それを説明するために動作状態１と動作状態２に対応した２つの回路が合わせて示されている。
前記第４３図で説明した実施例のように、２つのＣＭＯＳインバータ回路ＩＮＶ１，ＩＮＶ２の論理しきい値差により識別情報を得るものでは、その差が小さい時でも出力信号の再現性を保証することが重要である。特にＰチャンネル型ＭＯＳＦＥＴのしきい値電圧（ＣＭＯＳインバータ回路の論理しきい値ではない）は、近年のデバイスで顕著になつたＮＢＴＩという現象により変動することを考慮することが必要である。つまり、ＮＢＴＩという現象により上記の２つのＣＭＯＳインバータ回路のうち、一方のＣＭＯＳインバータ回路のＰチャンネル型ＭＯＳＦＥＴのしきい値電圧が変動して、かかるＣＭＯＳインバータ回路の論理しきい値も影響を受けて、上記２つのＣＭＯＳインバータ回路の論理しきい値差が逆転したのでは、それより生成される識別情報の信頼性が低下するという問題が生じる。
この実施例では、かかる識別番号の再現性の保証と、経時変化に対する耐性を高めるためにラッチと帰還経路を加えたものである。つまり、前記のような増幅回路を構成するインバータ回路ＩＮＶ５の出力信号は、スイッチＳＷ１を介してラッチ回路を構成する入力側のＣＭＯＳインバータ回路ＩＮＶ６の入力に伝えられる。このインバータ回路ＩＮＶ６の出力信号はインバータ回路ＩＮＶ７の入力に伝えられ、かかるインバータ回路ＩＮＶ７の出力信号がスイッチＳＷ２を通して上記インバータ回路ＩＮＶ６の入力に帰還される。また、上記インバータ回路ＩＮＶ７の出力信号は、スイッチＳＷ３を介して前記インバータ回路ＩＮＶ１の入力に帰還される。
第４４図の動作状態１は、識別情報を生成する動作が示されており、スイッチＳＷ０がオン状態となってＣＭＯＳインバータ回路ＩＶＮ１の入力と出力とを短絡して論理しきい値電圧に対応した電圧を出力ノードＮ１に生成する。前記のように上記ＣＭＯＳインバータ回路ＩＮＶ１の論理しきい値に対応された電圧がＣＭＯＳインバータ回路ＩＮＶ２に入力されることにより、ＣＭＯＳインバータ回路ＩＮＶ２の出力ノードＮ２には、上記論理しきい値電圧の差に対応した電圧が得られ、増幅回路を構成するＣＭＯＳインバータ回路ＩＮＶ３〜ＩＮＶ５により増幅される。
インバータ回路ＩＮＶ１の論理しきい値がインバータ回路ＩＮＶ２のそれより低い時、ノードＮ２の電位は、ＩＮＶ２の論理しきい値電圧より高くなる。つづく、インバータ回路ＩＮＶ３、ＩＮＶ４、ＩＮＶ５によつてＩＮＶ２の電位と論理しきい値の差は増幅され、ノードＮ５の電位はＶＳＳ近くになる。この時、ラッチ回路のスイッチＳＷ１はオン状態に、スイッチＳＷ２はオフ状態となり、上記オン状態のスイッチＳＷ１を介して増幅信号が伝えられて、インバータ回路ＩＮＶ６の入力ノードＮ６、インバータ回路ＩＮＶ６の出力ノードＮ７、インバータ回路ＩＮＶ７の出力ノードＮ８の電位は、それぞれＶＳＳ、ＶＤＤ，ＶＳＳとなる。
第４４図の動作状態２は、フィードバック動作が示されており、ラッチ回路のスイッチＳＷ１はオフ状態に、スイッチＳＷ２はオン状態となり上記状態が保持される。スイッチＳＷ０がオフ状態にスイッチＳＷ３がオン状態となり、ノードＮ８の保持電圧がＣＭＯＳインバータ回路ＩＶＮ１の入力にフィードバックされる。
これにより、インバータ回路ＩＮＶ１のゲート入力は、ノードＮ８すなわちＶＳＳ電位となる。また、ＩＮＶ２のゲート入力は、ＶＤＤとなる。つまり、インバータ回路ＩＮＶ１のＰチャンネル型ＭＯＳＦＥＴのゲート電位はＶＳＳである。これは、当該Ｐチャンネル型ＭＯＳＦＥＴにとって、ＮＢＴＩを加速させる条件であり、この状態を長く保持すると当該ＭＯＳＦＥＴのしきい値（論理しきい値ではない）電圧は徐々に高くなる傾向となる。必ずしも高くなる確証はないが、少なくとも低くなる条件ではない。インバータ回路ＩＮＶ１のＰチャンネル型ＭＯＳＦＥＴのしきい値が高くなるように変動すると、Ｎチャンネル型ＭＯＳＦＥＴとの関係で相対的にインバータ回路ＩＮＶ１の論理しきい値電圧は低くなる。
一方、インバータ回路ＩＮＶ２のＰチャンネル型ＭＯＳＦＥＴにとつてみると、ゲート電位はＶＤＤであり、これはＮＢＴＩの加速が起こりにくい条件であるため、インバータ回路ＩＮＶ２の論理しきい値電圧の変化は比較的小さい。すなわち、動作状態２が継続されことによってインバータ回路ＩＮＶ１の論理しきい値は低く変動し、インバータ回路ＩＮＶ２のそれを維持するため、相対的にもとのしきいい値の差が拡大されることになる。これにより、論理しきい値の差が小さい場合でも、再現性の低い識別ビットの再現性が上がり、経時変化に対し耐性の高い識別番号発生回路が実現できる。
なお、インバータ回路ＩＮＶ１の論理しきい値がインバータ回路ＩＮＶ２のそれより高い時、ノードＮ２の電位は、ＩＮＶ２の論理しきい値電圧より低くなる。したがって、フィードバック動作においては、ノードＮ８は増幅されてＶＤＤ電位となる。また、ＩＮＶ２のゲート入力は、ＶＳＳとなる。つまり、インバータ回路ＩＮＶ２のＰチャンネル型ＭＯＳＦＥＴのゲート電位はＶＳＳである。これは、当該Ｐチャンネル型ＭＯＳＦＥＴにとって、ＮＢＴＩを加速させる条件であり、前記同様にこの状態を長く保持すると当該ＭＯＳＦＥＴのしきい値（論理しきい値ではない）電圧は徐々に高くなる傾向となる。必ずしも高くなる確証はないが、少なくとも低くなる条件ではない。インバータ回路ＩＮＶ２のＰチャンネル型ＭＯＳＦＥＴのしきい値が高くなるように変動すると、Ｎチャンネル型ＭＯＳＦＥＴとの関係で相対的にインバータ回路ＩＮＶ２の論理しきい値電圧は低くなる。
一方、インバータ回路ＩＮＶ１のＰチャンネル型ＭＯＳＦＥＴにとつてみると、ゲート電位はＶＤＤであり、これはＮＢＴＩの加速が起こりにくい条件であるため、インバータ回路ＩＮＶ１の論理しきい値電圧の変化は比較的小さい。すなわち、動作状態２が継続されことによってインバータ回路ＩＮＶ２の論理しきい値は低く変動し、インバータ回路ＩＮＶ１のそれを維持するため、相対的にもとのしきいい値の差が拡大されることになる。これにより、論理しきい値の差が小さい場合でも、再現性の低い識別ビットの再現性が上がり、経時変化に対し耐性の高い識別番号発生回路が実現できる。
第４４図において、動作状態２が誤った状態にされてしまうことを防ぐ上で、半導体集積回路装置の電源投入毎のような起動時には、半導体集積回路装置における電源リセット回路もしくはイニシャライズ回路のような回路によって先ず第１動作状態が開始され、その後第２動作状態に移行される。これによって、インバータ回路ＩＮＶ６、ＩＮＶ７それ自体の電源起動特性にかかわらずに、適切なフィードバック動作が可能となる。
第４５図には、この発明に係る識別番号発生回路の一実施例の具体的回路図が示されている。この実施例では、前記スイッチＳＷ０〜ＳＷ３としてＮチャンネル型ＭＯＳＦＥＴとＰチャンネル型ＭＯＳＦＥＴとが並列接続されてなるＣＭＯＳスイッチが用いられる。また、インバータ回路ＩＮＶ２と増幅回路を構成する各インバータ回路ＩＮＶ３〜ＩＮＶ５の各入力端子には、ＣＭＯＳスイッチと電源電圧ＶＤＤにプルアップするＰチャンネル型ＭＯＳＦＥＴが設けられる。
そして、フィードバック制御信号ＦＢは、ラッチ回路のスイッチＳＷ１〜ＳＷ３の制御の他に、インバータ回路ＩＮＶ１の入力と出力とを短絡させるスイッチＳＷ０をスイッチ制御にも用いられる。つまり、上記フィードバック信号ＦＢの反転信号を形成するインバータ回路ＩＮＶ１０の出力信号は、前記のようなＣＭＯＳスイッチＳＷ１〜ＳＷ３の制御のための他に、ナンドゲート回路Ｇ１の一方の入力に供給される。このナンドゲート回路Ｇ１の他方の入力には、前記信号ＥＮが供給されており、ナンドゲート回路Ｇ１の出力信号と、インバータ回路ＩＮＶ９で形成された反転信号とによってスイッチＳＷ０の制御を行う。
この実施例回路では、かかる識別番号回路が搭載された半導体集積回路装置又は半導体チップに電源電圧が供給された状態で、信号ＥＮがロウレベルなら、Ｐチャンネル型ＭＯＳＦＥＴＱ１１〜Ｑ１５がオン状態となり、各ＣＭＯＳインバータ回路の入力端子に電源電圧ＶＤＤのようなハイレベルを供給する。このとき、信号ＥＮのロウレベルと、インバータ回路ＩＮＶ８による反転信号のハイレベルにより、各ＣＭＯＳインバータ回路ＩＮＶ２ないしＩＮＶ５の入力端子に設けられたスイッチがオフ状態になっており、各インバータ回路間の縦列接続が切断されているので、入力端子の電圧レベルは、上記ＭＯＳＦＥＴＱ１１〜Ｑ１５のオン状態に対応したハイレベルにされる。
このことは、半導体集積回路装置や半導体チップに電源供給が行われた状態で、識別番号を取り出さない状態でのＣＭＯＳインバータ回路を構成するＰチャンネル型ＭＯＳＦＥＴのしきい値電圧（ＣＭＯＳインバータ回路の論理しきい値ではない）がＮＢＴＩという現象により変動することを防止する上で有益である。
上記信号ＥＮをロウレベルからハイレベルに変化させると、インバータ回路ＩＮＶ１〜ＩＮＶ５を縦列形態に接続させるスイッチがオン状態となり、ゲート回路Ｇ１の出力信号がロウレベルとなってスイッチＳＷ０をオン状態にさせる。これにより、ＣＭＯＳインバータ回路ＩＮＶ１の論理しきい値電圧と、インバータ回路ＩＮＶ２の論理しきい値電圧との差電圧を増幅した信号がインバータ回路ＩＮＶ５の出力から得られる。信号ＦＢがロウレベルのとき、スイッチＳＷ０がオン状態となっており、かかるインバータ回路ＩＮＶ５の出力信号がラッチ回路を構成するインバータ回路ＩＮＶ６，ＩＮＶ７に取り込まれる。
上記の状態で信号ＦＢをロウレベルからハイレベルに変化させると、ラッチ回路ではスイッチＳＷ１がオフ状態になり、スイッチＳＷ２とＳＷ３がオン状態となり上記取り込んだ識別情報を保持し、かつそれに対応した信号をスイッチＳＷ３を通してインバータ回路ＩＮＶ１の入力に帰還させて、インバータ回路ＩＮＶ１〜ＩＮＶ５の入力電圧を設定して前記のようにＮＢＴＩを逆に利用した識別番号の保証ないし安定化を図るようにする。このとき、信号ＦＢのハイレベルによりナンドゲート回路Ｇ１の出力信号がハイレベルに戻り、上記インバータ回路ＩＮＶ１の入力と出力とを短絡させていたスイッチＳＷ０をオフ状態にする。
増幅回路を構成するインバータ回路ＩＮＶ４、ＩＮＶ５等は、その入力電圧が論理しきい値電圧との差電圧が大きいので、前記のようにＮＢＴＩの影響を実質的に受けることはないと考えられる。しかしながら、インバータ回路ＩＮＶ２、ＩＮＶ３等と同じ回路構成とすることにより、半導体集基板上に回路を形成する上で同じ回路セルを用いることができるので後述するソフトＩＰ技術を利用する上で有益となる。
第４６図には、この発明に係る識別番号発生回路の更に他の一実施例の具体的回路図が示されている。この実施例は、前記第４４図等に示したような１ビット別識別番号発生回路を拡張したものである。本実施例は、少ない回路素子により８ビットの識別番号を生成する回路に向けられている。
この実施例では、回路図中の全てのＣＭＯＳインバータ回路の定数およびレイアウト形状は同一である。つまり、単位回路（セル）は、ＣＭＯＳインバータ回路と、その入力端子に設けられたＣＭＯＳスイッチと、その入力端子と出力端子とを短絡するＣＭＯＳスイッチとから構成される。上記入力端子に設けられたＣＭＯＳスイッチにより各単位回路が縦列形態に接続される。同図には４個の単位回路が縦列形態に接続される。４つの単位回路のうち初段回路には、上記ＣＭＯＳスイッチを介して電源電圧が供給される。
上記のような縦列回路が２つ並列に設けられ、対応する位置に配置されたＣＭＯＳインバータ回路の２つのＣＭＯＳスイッチには、選択信号Ｘ０及びその反転信号Ｘ０／〜Ｘ３及びその反転信号Ｘ３／が共通に供給される。これにより、上記単位回路は縦列接続されてなる信号伝達方向と、それと直交する方向にマトリックス状態に配置される。
上記２つの縦列回路の終段回路の出力端子には、スイッチが設けられて、いずれかの縦列回路を選択する選択信号Ｙ０，Ｙ０／及びＹ１，Ｙ１／が供給される。そして、前記のような増幅回路を構成するインバータ回路ＩＮＶ４とＩＮＶ５が設けられて出力端子ＯＵＴから識別番誤出力が出力される。上記インバータ回路ＩＮＶ４の入力には、前記のようなＮＢＴＩ対策のために信号ＰＯＮにより制御されてインバータ回路ＩＮＶ４の入力端子に電源電圧を供給するＰチャンネル型ＭＯＳＦＥＴが設けられる。
第４７図には、前記第４６図の実施例回路の動作を説明するためのタイミング図が示されている。
１）パワーオン信号ＰＯＮがロウレベルの時、選択信号は、Ｘ０〜Ｘ３はロウレベル、その反転信号Ｘ０／〜Ｘ３／はハイレベルであり、Ｙ０とＹ１はロウレベルであり、その反転信号Ｙ０／とＹ１／はハイレベルである。ＣＭＯＳインバータの出力はそれぞれ、ＩＮＶ００、２０及びＩＮＶ０１、ＩＮＶ２１とＩＮＶ４がロウレベル、ＩＮＶ１０、ＩＮＶ３０及びＩＮＶ１１、ＩＮＶ３１及びＩＮＶ５がハイレベルである。
２）パワーオン信号ＰＯＮがハイレベルに遷移すると、選択信号Ｘ０はハイレベル、Ｘ０／はロウレベル、Ｙ０はハイレベル、Ｙ０／はロウレベルとなる。インバータ回路ＩＮＶ００とＩＮＶ０１の入力は、電源電圧ＶＤＤから切断され、それぞれの入力と出力が選択信号Ｘ０のハイレベル、Ｘ０／のロウレベルよりオン状態にされるＣＭＯＳスイッチにより短絡され、インバータ回路ＩＮＶ００とＩＮＶ０１の出力電圧は、論理しきい値に対応した電圧となる。
インバータ回路ＩＮＶ００の論理しきい値ＶＬＴ（ＩＮＶ００）とその次段のインバータ回路ＩＮＶ１０の論理しきい値ＶＬＴ（ＩＮＶ１０）の関係が、ＶＬＴ（ＩＮＶ００）＞ＶＬＴ（ＩＮＶ１０）であれば、インバータ回路ＩＮＶ１０の出力電圧は、インバータ回路ＩＮＶ１０の持つ反転増幅作用により、ＶＳＳ電位側すなわちロウレベル側に大きく振幅する。逆に、ＶＬＴ（ＩＮＶ００）＜ＶＬＴ（ＩＮＶ１０）であれば、ＶＤＤ電位側すなわちハイレベル側に大きく振幅する。インバータ回路ＩＮＶ１０、ＩＮＶ１１の出力振幅は、次段のインバータ回路ＩＮＶ２０〜ＩＮＶ３０、ＩＮＶ２１〜ＩＮＶ３１でさらに増幅される。
インバータ回路ＩＮＶ３０の出力は、選択信号Ｙ０，Ｙ０／で選択されたＣＭＯＳスイッチを通り、さらに２段のＣＭＯＳインバータ回路ＩＮＶ４とＩＮＶ５からなる増幅回路を通り、出力端子ＯＵＴに出力される。結局、ＶＬＴ（ＩＮＶ００）＞ＶＬＴ（ＩＮＶ１０）であれば、出力端子ＯＵＴにはロウレベルが出力され、ＶＬＴ（ＩＮＶ００）＜ＶＬＴ（ＩＮＶ１０）であれば、出力端子ＯＵＴにはハイレベルが出力される。
３）次に選択信号が遷移し、Ｘ０がロウレベル（Ｘ０／がハイレベル）に、Ｘ１がハイレベル（Ｘ０／がロウレベル）になる。インバータ回路ＩＮＶ１０とＩＮＶ１１の入力は、Ｘ１のハイレベル（Ｘ０／のロウレベル）により入力端子に設けられたＣＭＯＳスイッチがオフ状態となって前段インバータ回路ＩＮＶ００とＩＮＶ０１の出力から切断され、それぞれの入力と出力がＣＭＯＳスイッチにより短絡され、インバータ回路ＩＮＶ１０とＩＮＶ１１の出力は、論理しきい値となる。インバータ回路ＩＮＶ１０の論理しきい値ＶＬＴ（ＩＮＶ１０）とその次段のインバータ回路ＩＮＶ１１の論理しきい値ＶＬＴ（ＩＮＶ１１）の関係が、ＶＬＴ（ＩＮＶ１０）＞ＶＬＴ（ＩＮＶ２０）であれば、インバータ回路ＩＮＶ２０の出力電圧は、インバータ回路ＩＮＶ２０の持つ反転増幅作用により、ＶＳＳ電位側すなわちロウレベル側に大きく振幅する。逆に、ＶＬＴ（ＩＮＶ１０）＜ＶＬＴ（ＩＮＶ２０）であれば、インバータ回路ＩＮＶ２０の出力電圧は、インバータ回路ＩＮＶ２０の持つ反転増幅作用により、ＶＤＤ電位側すなわちハイレベル側に大きく振幅する。
上記インバータ回路ＩＮＶ２０、ＩＮＶ２１の出力振幅のそれぞれは、次段のインバータ回路ＩＮＶ３０、ＩＮＶ３１でさらに増幅される。上記インバータ回路ＩＮＶ３０の出力は、選択信号Ｙ０、Ｙ０／で選択されたＣＭＯＳスイッチを通り、さらに２段のＣＭＯＳインバータ回路ＩＮＶ４とＩＮＶ５を通り、出力端子ＯＵＴに出力される。
結局、ＶＬＴ（ＩＮＶ１０）＞ＶＬＴ（ＩＮＶ２０）であれば、出力端子ＯＵＴにハイレベルが出力され、ＶＬＴ（ＩＮＶ１０）＜ＶＬＴ（ＩＮＶ２０）であれば、出力端子ＯＵＴにはロウレベルが出力される。ここで、ＣＭＯＳインバータ回路の論理しきい値の前後の大小関係と、出力端子ＯＵＴの値の対応が、上記２）と３）のケースで逆転している。これは上記ＣＭＯＳスイッチにより接続されるインバータ回路の数、つまりは論理しきい値電圧差を増幅するＣＭＯＳインバータ回路の段数が異なることによるものである。
４）次に選択信号が遷移し、Ｘ１がロウレベル（Ｘ１／がハイレベル）、Ｘ２がハイレベル（Ｘ２／がロウレベル）になる。インバータ回路ＩＮＶ２０とＩＮＶ２１の入力は、前記同様にＣＭＯＳスイッチのオフ状態により前段のインバータ回路ＩＮＶ１０とＩＮＶ１１の出力から切断され、それぞれの入力と出力がＣＭＯＳスイッチにより短絡され、インバータ回路ＩＮＶ２０とＩＮＶ２１の出力は、論理しきい値となる。
以降の動作は、上記２）に準ずる。
５）次に選択信号が遷移し、Ｘがロウレベル（Ｘ２／がハイレベル）、Ｘ３がハイレベル（Ｘ３／がロウレベル）になる。インバータ回路ＩＮＶ３０とＩＮＶ３１の入力は、前記同様にＣＭＯＳスイッチがオフ状態となり、前段のインバータ回路ＩＮＶ２０とＩＮＶ２１の出力から切断され、それぞれの入力と出力がＣＭＯＳスイッチにり短絡され、インバータ回路ＩＮＶ３０とＩＮＶ３１の出力は論理しきい値となる。インバータ回路ＩＮＶ３０の論理しきい値ＶＬＴ（ＩＮＶ３０）とその次段のインバータ回路ＩＮＶ４の論理しきい値ＶＬＴ（ＩＮＶ４）の関係が、ＶＬＴ（ＩＮＶ３０）＞ＶＬＴ（ＩＮＶ４）であれば、インバータ回路ＩＮＶ４の出力電圧は、インバータ回路ＩＮＶ５の持つ反転増幅作用により、ＶＳＳ電位側すなわちロウレベル側に大きく振幅する。逆に、ＶＬＴ（ＩＮＶ３０）＜ＶＬＴ（ＩＮＶ４）であれば、ＶＤＤ電位側すなわちハイレベル側に大きく振幅する。
結局、ＶＬＴ（ＩＮＶ３０）＞ＶＬＴ（ＩＮＶ４）であれば、出力端子ＯＵＴにはハイレベル出力され、ＶＬＴ（ＩＮＶ３０）＜ＶＬＴ（ＩＮＶ４）であれば、出力端子ＯＵＴにはロウレベル出力される。
６）次以降の遷移においては、選択信号Ｙ０がロウレベル（Ｙ０／がハイレベル）で、Ｙ１がハイレベル（Ｙ１／がロウレベル）となり、上記２）〜５）に準ずる動作が行われる。これにより、４×２＝８ビットからなる識別番号出力が行われる。
この実施例では、識別番号を生成するインバータ回路と増幅回路を兼ねているいることと、読み出し動作により識別番号がシリアルに出力されるという特徴を持つ。これにより、回路の簡素化が可能となり、１つの端子からシリアルに識別番号を出力させる場合に適している。
第４８図には、前記図４６の実施例に用いられる単位回路の他の一実施例の回路図が示されている。この実施例は、前記のようなＮＢＴＩ対策が行われるいる。つまり、インバータ回路の入力端子には、前記のようなインバータ回路を縦列接続するためのＣＭＯＳスイッチの他、識別番号回路が非活性状態のときに入力端子を前段回路から切り離すためのＣＭＯＳスイッチが追加される。そして、入力端には入力端子に電源電圧を供給するためのＰチャンネル型ＭＯＳＦＥＴが設けられる。
この実施例の単位回路では、パワーオン信号ＰＯＮがロウレベルのとき、つまり電源電圧が供給されて、識別番号発生回路から識別番号を読み出さない時に、かかる信号ＰＯＮをロウレベルとして、各インバータ回路の入力端子を前記のような選択信号Ｘ０，Ｘ０／等とは無関係に前段回路から切り離して、Ｐチャンネル型ＭＯＳＦＥＴにより電源電圧ＶＤＤを供給するものである。
第４９図には、この発明に係る識別番号発生回路の更に他の一実施例の回路図が示されている。この実施例は、前記第４６図に示した単位回路を１列に縦列接続し、バイナリカウンタとデコーダを用いて選択信号を形成するものである。つまり、バイナリカウンタによりカウントアップクロックを計数し、その計数出力を各単位回路に対応して設けられたデコーダに供給し、前記初段回路から順に選択信号Ｘ０（Ｘ０／）ないしＸｎ（Ｘｎ／）を生成する。
第５０図には、この発明に係る識別番号発生回路の更に他の一実施例の回路図が示されている。この実施例は、前記第４６図に示した単位回路を１列に縦列接続し、シフトレジスタを用いて選択信号を形成するものである。つまり、各単位回路に対応してシフトレジスタ（１段分）を設けて前記選択信号を順次にシフトして初段の単位回路から順に前記のような選択動作を行わせるようにするものである。
第４９図及び第５０図のいずれの実施例でも破線で囲んだものを一つの単位回路とすることで、設計や拡張、実装が容易になる。特に第５０図の実施例回路においては、識別番号のビット数を拡張する場合、単位回路の縦列接続線、シフトクロック及びリセットからなる３種類の信号線を連結するだけでよいので、チップ実装に関して自由度が高いため、後述するようなソフトＩＰに好適である。
第５１図には、この発明が適用される半導体集積回路装置又は半導体チップの一実施例の回路レイアウト図が示されている。同図は、一般的なシステムＬＳＩチップを模したものであり、チップ周辺部には、通常Ｉ／Ｏセル（入出力回路）が設けられ、内蔵回路はシステムＬＳＩの機能に応じた回路が複数個設けられる。
第５２図には、上記Ｉ／Ｏセルの標準的な一実施例のブロック図が示されおり、出力バッファ回路、入力バッファ回路及びこれらに対応して設けられるボンディングパッド（ＰＡＤ）から構成される。上記出力バッファ回路と入力バッファ回路は、入出力制御信号により制御されて入力動作又は出力動作が行われる。
第５３図には、この発明に係る半導体集積回路装置又は半導体チップに設けられるＩ／Ｏセルの一実施例の回路レイアウト図が示されている。この実施例では、出力ＭＯＳＦＥＴを駆動するための出力プリバッファ回路が設けられる。前記第５２図の出力バッファ回路は、上記出力プリバッファ回路と出力ＭＯＳＦＥＴにより構成される。
ワイヤボンディングのためにボンディングＰＡＤは、比較的大きな占有面積を持って形成される。これに適合するように出力ＭＯＳＦＥＴ及び出力プリバッファ回路及び入力バッファ回路がレイアウトされる。これにより、ボンディングパッドのピッチに対応してＩ／Ｏセルを効率よく配置させることができる。
このようにＩ／Ｏセルは、比較的大きな占有面積を持つようにされるので、出力プリバッファ回路又は出力ＭＯＳＦＥＴの一部に斜線を付したように前記実施例に示したような１ビット識別番号発生回路を嵌め込むようにすることができる。
第５４図には、この発明に係る半導体集積回路装置又は半導体チップに設けられる出力バッファ回路の一実施例の回路図が示されている。この実施例では、出力バッファ回路に前記１ビット識別番号発生回路が付け加えられる。
この実施例では、識別番号回路イネーブル信号が活性化した時（その時、正規の出力イネーブルは非活性）、正規出力バッファ回路に並列に設けられたバッファから１ビットの識別番号を出力する。このバッファは、駆動能力が小さくてもよいから正規回路の出力ＭＯＳＦＥＴに比べて小さいサイズのＭＯＳＦＥＴで足りる。この構成においては、識別番号を出力するための特別な出力端子が不要となり、半導体集積回路装置又は半導体チップに設けられた多数の入出力端子又入出力パッドを利用して多ビットからなる識別番号を取り出すようにすることができる。
第５５図には、この発明に係る半導体集積回路装置又は半導体チップに設けられる出力バッファ回路の他の一実施例の回路図が示されている。この実施例でも、出力バッファ回路に前記１ビット識別番号発生回路が付け加えられる。この実施例では、正規出力バッファ回路を利用して識別番号が出力される。つまり、出力プリバッファ回路にゲート回路を追加して正規出力と識別番号とを選択的に出力させるようにするものである。識別番号回路イネーブル信号は、ＬＳＩの専用ピンから生成されてもよいし、特別のＤＦＴ機能によって生成されてもよい。このことは、前記第５４図の実施例でも同様である。
近年、ロジックＬＳＩにおいてＪＴＡＧ（Ｊｏｉｎｔ Ｔｅｓｔ Ａｃｔｉｏｎ Ｇｒｏｕｐ）の採用が広がっている。ＪＴＡＧ規格の中にも、ＬＳＩの識別番号を登録し、読み出すＩＤＣＯＤＥという機能がある。しかし、ビット数が３２ビットと少なく、しかも各ビットがデバイス及び製造メーカーなどを識別するようビット構成が細かく規定されているため、個々のチップの識別番号として使うことはできない。
第５６図には、この発明に係る半導体集積回路装置の一実施例の概略構成図が示されている。この実施例ではＪＴＡＧのインターフェイスを利用して識別番号の出力を行うように工夫されている。
ＪＴＡＧ対応デバイス（半導体集積回路装置）には、半導体集積回路装置本来の機能を行うための内蔵ロジックの他に、バウンダリスキャンレジスタ、インストラクションレジスタ、オプションレジスタ及びバイバスレジスタと、これらを制御するＴＡＰコントローラによって構成されるテストロジックが内蔵される。
テストロジックに対する命令やテストデータ、テスト結果のデータなどの入出力を行うシリアルインターフェイスは、ＴＡＰ（Ｔｓｅｔ Ａｃｃｅｓｓ Ｐｏｒｔ）と呼ばれ、５本の信号線を持っている。この信号線を外部のホストコンピュータ等で制御することによりＪＴＡＧテストが実施される。
第５７図には、この発明に係る半導体集積回路装置の基本的にＪＴＡＧセルの一実施例のブロック図が示されている。この実施例では、ＪＴＡＧのバウンダリスキャンレジスタを構成するセルに１ビット識別番号発生回路が組み込まれる。ＪＴＡＧセルは、前記第５１図等のＩ／Ｏセルに組み込まれることもあれば、内蔵ロジックに組み込まれることもある。
バウンダリスキャンレジスタのセルに、内蔵ロジックからの信号と１ビット識別番号発生回路で生成した識別情報とを切り替えて入力させる回路を付加することより、バウンダリスキャンレジスタのシフト動作を利用したシリアル出力を行うようにすることができる。
第５８図には、この発明に係る半導体集積回路装置のバウンダリスキャンレジスタのシフト動作を利用した識別番号のシリアル出力動作の一実施例を説明するための構成図が示されている。
この実施例では、ＬＳＩを３つ（Ａ〜Ｃ）、それぞれのＪＡＴＧセル（バウンダリ・スキャン・レジスタ）が７個、７個、９個とし、各セル中にデータの流れを示すためにデータの番号の数字が付されている。そして、同図には、代表としてＬＳＩ−Ｂに搭載された識別番号発生回路（ＩＤ−ＲＯＭ）からの識別番号を読み出す動作の例が示されている。
状態１は、初期状態でありＪＴＡＧでの動作状態が示されている。
状態２は、例えばＪＴＡＧのプライベート命令により、ＬＳＩ−ＢのＴＤＯが、ＪＴＡＧセルから切り離され、代わって識別番号発生回路ＩＤ−ＲＯＭに接続される。
状態３では、ＪＴＡＧのシフト命令により、識別番号発生回路ＩＤ−ＲＯＭがシフト動作を行って識別番号が、逐次ＴＤＯから出力される。同図においては３ビットの識別番号情報（Ｉ、ＩＩ、ＩＩＩ）が送り出された状態を示している。なお、各ＬＳＩ内のＪＴＡＧセルは、通常と同じく右へシフトしてＬＳＩ−Ｃを通してＬＳＩ−Ｂの識別番号が出力されることになる。
この識別番号を取り出した後は、図示しないけれどもプライベート命令モードから通常自動モードに戻り、ＴＤＯがＪＴＡＧセルに接続され

するが、必要ならその後に通常モードでシフトを繰返すことでセル情報

第５９図は、この発明に係る半導体集積回路装置のバウンダリスキャンレジスタのシフト動作を利用した識別番号のシリアル出力動作の他の一実施例を説明するための構成図が示されている。前記第５８図の実施例と異なるのは、状態３において、ＬＳＩ−ＣのＪＴＡＧセルのみがシフトしていることである。これにより、前記第５９図の実施例において

かたかもＩＤ−ＲＯＭ情報がＬＳＩ−ＢとＬＳＯ−ＣのＪＴＡＧセル情報の間に挿入された結果とすることができる。
第５９図は、この発明に係る半導体集積回路装置のバウンダリスキャンレジスタのシフト動作を利用した識別番号のシリアル出力動作の他の一実施例を説明するための構成図が示されている。この実施例の識別番号発生回路（ＩＤ−ＲＯＭ）は、前記第５７図に示した識別番号発生回路に対応している。
状態１は初期状態である。
状態２では、例えばＪＴＡＧのプライベート命令により、１ビット識別番号発生回路の情報をＬＳＩ−ＢのＪＴＡＧセルに転送する。この時

よって置き換えられるので破壊される。
状態３では、ＪＴＡＧのシフト命令により、ＩＤ−ＲＯＭの識別番号が、逐次ＬＳＩ−ＢのＴＤＯから出力される。
第６１図は、この発明に係る半導体集積回路装置のバウンダリスキャンレジスタのシフト動作を利用した識別番号のシリアル出力動作の他の一実施例を説明するための構成図が示されている。この実施例においては、識別番号専用のシフトレジスタ（ＩＤレジスタ・セル）が組み込まれたものである。
状態１は初期状態である。
状態２では、例えばＪＴＡＧのプライベート命令により、ＬＳＩ−ＢのＴＤＯは、ＪＴＡＧセルから切り離され、別番号専用のシフトレジスタの先頭に接続される。また、識別番号専用のシフトレジスタの最後尾は、ＬＳＩ−ＢのＪＴＡＧセルの先頭が接続される。この時同時に、識別番号専用のシフトレジスタには識別番号がセットされる。
状態３では、ＪＴＡＧのシフト命令により、ＩＤ−ＲＯＭの識別番号が、逐次ＬＳＩ−ＢのＴＤＯから出力される。同時に、ＬＳＩ−ＡのＪＴＡＧセル情報が、ＬＳＩ−ＢのＪＴＡＧセル情報と識別番号専用のシフトレジスタにシフトインされる。
図示しないけれどもさらにシフトをつづけ、ＬＳＩ−Ｂの全ての有効なＪＴＡＧセル情報がシフトアウトされた後、初期状態に戻す。
第６２図には、この発明に係る識別番号発生回路の更に他の一実施例の回路図が示されている。この実施例は、前記のようなＣＭＯＳインバータ回路ＩＮＶ１とＩＮＶ２の論理しきい値電圧差を増幅回路で増幅した識別情報を、ナンドゲート回路からなるラッチ回路に保持させる。つまり、第１書き込み信号ＷＲＩＴＥ１のハイレベルより、上記インバータ回路ＩＮＶ１とＩＮＶ２の論理しきい値電圧差に対応した２値の識別情報をラッチに入力する。
次に、上記第１書き込み信号ＷＲＩＴＥ１をロウレベルにして、上記２値の識別情報をラッチ回路に保持させるとともに、上記インバータ回路ＩＮＶ１、ＩＮＶ２及び増幅回路からなるインバータ回路列には、入力段のインバータ回路ＩＮＶ１の入力にプルアップＭＯＳＦＥＴで形成されたハイレベルを供給する。
次に、第２書き込み信号ＷＲＩＴＥ２と高電圧ＶＰＰとを用いて上記ラッチ回路の保持情報を、例えばヒューズ（ＦＵＳＥや、ＥＥＰＲＯＭ等からなる）不揮発性のプログラマブルデバイスに書き込む。そして、識別番号を必要とするときには、信号ＲＤによりプログラマブルデバイスをアクセスして上記書き込まれた識別番号をリードデータとして出力させる。
この構成は、上記第１書き込み信号ＷＲＩＴＥ１でのインバータ回路ＩＮＶ１とＩＮＶ２の論理しきい値電圧差に対応した識別情報が別の不揮発性回路に記録されるので、前記のようなＮＢＴＩの影響を受けることなく、識別ビットの再現性を維持し、経時変化に対しも耐性の高い識別番号発生回路を得ることができる。
以上の実施例のようにＣＭＯＳインバータ回路の論理しきい値のバラツキを用いた識別番号発生回路では、各素子のしきい値の大きさの順番を識別情報の源としている。
第６３図及び第６４図に４つの識別番号の例が示されている。第６３図は、それらのしきい値の順位をグラフ化したものであり、第６４図において、被識別番号の素子（ＣＭＯＳインバータ回路）は、１６個の素子の中で最も順位が高く、素子１０は最も順位が低い。これは、素子１の論理しきい値が最も高く、素子１０の論理しきい値が最も低いことを意味している。さて、この素子１と素子１０に注目すると、素子１に最も順位が近い素子は素子５であり、素子１０に最も順位が近いものは素子９である。
本願発明に係る識別番号発生回路では、ＣＭＯＳインバータ回路の論理しきい値のバラツキ方を順位化しているので、例えば素子１と素子５の間にどれくらいの論理しきい値電圧の差が存在するかは不明である。同様に素子１０と素子９の間についても不明である。また、それらの差が極めて僅かである場合、試験条件などで素子１と素子５順位が入れ替わる可能性がある。しかし、素子１と素子１０が入れ替わる可能性は極めて低いものと考えられる。それは、第６３図のグラフからも理解することが容易である。
照合時に取得される被識別番号というのは、過去において少なくとも１回以上取得され、データベースに格納されており、被識別番号と非常に類似した形で存在しているはずでる。類似とは、前述のように、本願発明の識別番号発生回路において、経時変化等の影響を受けて完全に識別番号が再現されない場合を考慮したものである。このように一部にＣＭＯＳインバータ回路間でのバラツキ方を順位が入れ替わっても上述のように、第６４図の例では、少なくとも素子１と素子１０の順位に関しては、過去に取得された識別番号も最新の被識別番号もその大小関係は変化していないことが容易に推定できる。
第６５図には、この発明に係る識別番号発生回路で生成された識別番号の高速識別番号照合（検索）アルゴリズムの一実施例を説明するためのフローチャート図が示されている。第６６図には、それに対応した構成図が示されている。
▲１▼被識別番号を読み込みステップでは、”０”と”１”からなる前記１ビット識別番号発生回路においてそれぞれから生成された連続データである。
▲２▼順位解析ステップでは、上記データを順位を表わす数字に変換する。つまり、前記第６４図のような１ビット識別番号発生回路の順位が数字に変換される。
▲３▼最大最小素子抽出ステップでは、順位を解析して、最大順位の素子と最小順位の素子の番号を抽出し記録しておく。
▲４▼において管理台帳から、登録済みの識別番号を一つ取り出す。
▲５▼において、上記の登録済み識別番号の中の、上記で記録した最大と最小の素子番号にあたる素子番号の順位を取り出す。例えば、前記第６４図の例では、識別番号１は最大が１、最小が１０であるが、１と１０という数を比較すると大小の関係が逆転している。これは、順位がバラツキなどによる変動をはるかに越えた現象であるため、被識別番号を識別番号１は異なるチップから採取されたものと容易に推定できる。よって、識別番号１は、不適合と判定され、その後の詳細な照合検査を省略する。
上記において適合と判定されたものは、▲６▼と▲７▼におて詳細検査を行う。基本的に、前記実施例と同様であるため割愛する。最も類似性の高い識別番号を一致候補とする。なお、▲５▼において、順位の大小比較では確率的に適合と、不適合の発生する割合は５割づつであるから、詳細検査が省略される効果もほぼ５割である。
そこで、この実施例では、１組の大小比較であるが、これを２組とすることで、上記効果をさらに２倍にすることが期待できる。ただし、これを増やすと、大小比較の処理自身が増大し効果を押し下げる可能性もあるので、識別番号の桁数や、識別番号の総母数との兼ね合いで選択することが望ましい。
第６７図には、この発明に係る識別番号発生回路を組み込んだ半導体チップの回路設計方法の一実施例のフローチャート図が示されている。この実施例のような回路設計ソフトウェアをデザイン企業や製造専門企業に提供する。あるいは、同一機能をＥＤＡベンダのツールに組み込むようにするものである。
（１）メニューをプルダウンして選択する。
（２）メニューデータが生成される。２回目以後は、このメニューデータを指定するだけで所望のＩＰを選択できる。
（３）メニューデータを分析し、違反などを検出する。
（４）メニューデータに従い、必要な情報を、ローカルデータベースから取り出す。ローカルデータベースにない最新の情報は、インターネット等のネットワークを介し、製造専門会社のデータベース等から取得する。
（５）データベースから収集した情報をもとにに、ソフトＩＰに必要なデータを生成処理を行う。
（６）ソフトＩＰが生成可能か判断する。不可能であれば、ハードＩＰ設計を選択する。
第６８図には、この発明に係る識別番号発生回路を内蔵したＬＳＩ設計方法の一実施例のフローチャート図が示されている。この実施例では、特に制限されないが、特定用途向けＬＳＩ（ＡＳＩＣ）の設計フローに向けられている。
論理合成ツールは、前記第６７図に示した設計フローでのソフトＩＰ生成の判断結果により、真理値表やＲＴＬ記述、状態遷移図などからゲートレベルの論理回路（ネットリスト）を生成する。また、図示していないが、多くの場合、ＲＴＬなどは、ＶＨＤＬやＶｅｒｉｌｏｇ ＨＤＬ等の機能記述言語をもとに生成される。論理合成の際必要とされるのは、セルライブラリ情報であり、これにはトランジスタレベルの接続情報や、ディレー情報、レイアウト情報などが含まれている。また、通常ＲＴＬなどには、制約情報と呼ばれるタイミング誤差許容値やレイアウト配置間隔、最大信号配線長などの情報が付加されている。ＤＦＴツールはゲートレベルの論理回路にＬＳＩの検査に有効な診断論理を付加し、自動配置配線ツールによって最終的なレイアウトデータを作成する。
セルライブラリに登録されているセルの種類は、インバータやＮＡＮＤ（ナンド）、フリップフロップなどの最も基本的な回路構成要素が主なものである。一般にセルライブラリのデータ、例えばレイアウト情報などは人手により作成される。しかし、規模が大きい物や、例えばメモリのように基本的な機能は変わらないがその構成がわずかづつ異なる物については、自動セル生成ツールやラムコンパイラなどが用いられることがある。
ここで、本願発明でいうハードＩＰとソフトＩＰについて簡単に説明する。現在、半導体産業において、特に特定用途向けＬＳＩ設計製造においては、顧客（例えばゲーム機や自動車メーカなど）から受けた仕様をもとに、設計から製造までを１つの企業で行う総合企業形態と、設計だけを専業とするいわゆるＬＳＩデザイン企業と、製造を専業とするいわゆるファンドリ企業によって分業化される形態に分類される。
また、最近では分業化の流れに乗り、ＩＰを供給する企業（ＩＰベンダ）やそれらの流通市場や、標準化支援団体などが生まれている。ＩＰはＬＳＩの設計効率を向上する上でも重要な存在となってきており、総合企業においても無視できないものとなっている。
ＩＰには、大きくハードＩＰとソフトＩＰと呼ばれるものがある。両者の違いを、ＬＳＩデザイン企業とファンドリ企業による分業形態を対象した場合を比較してみる。ＬＳＩデザイン企業（ファブレス企業）は、顧客の仕様をもとに第６８図のＶＨＤＬやＶｅｒｉｌｏｇ ＨＤＬ等の機能記述言語を用いたデータや、真理値表やＲＴＬ記述、状態遷移図などのデータ、制約情報などを作成する。ただし、顧客自身が、これらのデータまで作成しＬＳＩデザイン企業に渡す場合もある。
次にＬＳＩデザイン企業は、冒頭で述べた論理合成ツールを使用してネットリストを作成する。論理合成の際に、用いられる回路素子は、セルライブラリに登録されているものに限られる。それらは、製品を製造する製造専門会社が認定したものであり、一般に製造会社が自ら提供するのは、先に述べたインバータ回路やＮＡＮＤゲート回路のような基本的なものである。
ただし実際には、製造専門会社も、自社の競争力をたかめるため、より複雑なものを提供している。しかし、製造専門会社だけで、例えばＰＬＬやＳＲＡＭ、演算回路など複雑で高機能な回路を準備することは困難であるため、それらを設計し供給するＩＰベンダが多く登場する。ＩＰの中でもＰＬＬなどは、回路自身が複雑で、かつ使用するプロセスに特性が大きく依存するため、ＩＰベンダは一般的にハードＩＰという形で供給する。ハードＩＰは、簡単にいうとセルライブラリに、ＩＰベンダが設計したセルレイアウトが登録されるものである。それ故、ハードＩＰベンダはハードＩＰを供給する場合に、製造専門会社はもちろん、そのプロセス世代毎にもＩＰを変更し、製造会社の認定を受け、さらに各ＬＳＩデザイン企業の持つセルライブラリに登録してもらわなければならない。
一方、ソフトＩＰの場合、ＩＰベンダは、先のＶＨＤＬやＶｅｒｉｌｏｇ ＨＤＬ等の機能記述言語を用いたデータや、真理値表やＲＴＬ記述、状態遷移図などのデータ、制約情報などを、ＬＳＩデザイン企業やファンドリ企業、あるいはその上の顧客に供給するのみである。そのため現在、特定用途向けＬＳＩの市場では、ソフトＩＰの普及が先行しており今後もその優位性は変わらないと考えられる。また、ラムコンパイラもあくまでセルライブラリの部品の作成を自動化するものであり、ハードＩＰの範疇に含まれる。
上記のように、ハードＩＰによる供給形態は、ＩＰの流通や普及の点で劣り、さらにハードＩＰを供給する側にもプロセス毎の設計変更などの負担などの短所がある。対して、この実施例の識別番号発生回路、特に第４９図や第５０図に示したような回路は、その心臓部でさえインバータとパストランジスタのみであり、むろんその他は標準的な論理素子で構成されているためソフトＩＰ化が比較的容易である。例えば、セルライブラリにＣＭＯＳインバータ回路（当然ある）とＣＭＯＳスイッチ（パストランジスタ）が既に登録されていれば、ＲＴＬ記述のみでＩＰを設計企業に供給できる。仮にパストランジスタが標準で登録されていない場合、新たにパストランジスタのみを登録する必要があるが、その規模は極めて小さい。
また、自動配置配線処理は配置や配線の結果が不規則でることが弱点として上げられるが、例えば、２つの識別用インバータが極端に離れた位置に配置されることも起こり得る。すると、回路図の信号Ｐと信号ＰＰの配線長が長くなり、周辺からの雑音の影響を受けやすくなる。これを低減するために、配置配線処理において、配置や信号線長の制限を与えることが有効である。また、この部分だけを、セルライブラリに登録された標準セルを組み合わせて新たなセルとして登録することも有効である。むしろカウンタやデコーダなどは、自動配置配線などで作成した方が効率的である。
近年、ＬＳＩにＩＤ番号や各種の固有情報（以降、これを一般情報と呼ぶ）などを組み込む応用例が増えている。例えば、製品の製造ライン番号や、製造週番号、製品のグレード、製造管理情報であったりする。これらは、一般にレーザフューズやＥＰＲＯＭなどを用いてＩＤ番号をプログラムしている。このプログラムにおいて、当然レーザプログラムのミスはあってはならないし、しかも、レーザフューズ方式は、ほとんどウェハ状態で加工されるが、レーザ工程以降の工程で変化してもならない。その情報が、生命・財産にかかわる内容のものであればなおさら重要である。
しかし、プログラム後ダイシングされチップがひとつひとつばらばらな状態では、レーザプログラム時に書き込まれた一般情報は読み出すことはできても、それが正しいかどうかを確認することは、非常に困難であるという重要な問題がある。その対策として次のようなものが考えられる。一つには、パリティビット付加し、データの変動を検出するものである。パリティ検査のための機能は、チップに内蔵してもよいが、測定器において判定してもよい。
しかし、厳密な意味で、チップに書き込まれているデータを確認したことにはならない。
他の一つは、読み出した情報の信頼性を確保するため、何らかの方法で読み出した一般情報を記録する仕掛けを作り、情報の重複を確認する方法である。この方法では、最悪重複したチップを全て不良品扱いとすることで製品の事故は防ぐことができる。しかし、現実には複数のチップの読み出し情報が重複した場合、どれが正しいものであるか確認は困難であり、チップの管理及び処置が複雑となる。
つまり、先に上げた問題の本質的な解決方法は、いったんばらばらにされたチップを識別し、そのチップの正しい情報を知り得て、それと比較することであると考えられる。
そこで、チップに固有の識別番号を付け加え、その情報を元に正しい番号をデータベース等から得るという発想も考えられるが、それ自体を同じレーザフューズで書き込んでも、それはいたちごっこになるだけである。
一方、情報論（例えば、情報論：瀧康夫著、岩波新書刊）によれば、符号間の距離（例えばハミング距離）が大きければ、それらに雑音が乗っても、元の情報の変化の検出とさらに修復も可能であるということが周知（例えば、誤り訂正符合とその応用：映像情報メディア学会編、オーム社刊）である。ここでは符合とは、レーザフューズで書き込んだ情報であり、雑音とはその一部が変化したことに相当する。
つまり、上記固有情報に、符号間の距離の大きなチップ固有識別番号を加えることで、全体の情報の一部が多少変化しても、他の識別番号すなわちチップと十分区別できるようになる。そこで、本願発明に係る識別番号発生回路の利用が有効となるものである。
第６９図には、この発明に係る識別番号発生回路内蔵の半導体チップを用いた半導体集積回路装置の製造方法の一実施例のフローチャート図が示されている。
一般情報とチップに符号間の距離の大きな固有の識別番号を合わせた情報（以降、これを管理情報と呼ぶ）を指示されたウェハ上のレーザフューズにプログラムする。固有識別番号は、内蔵の識別番号発生回路で生成されたものが用いられる。
一般情報と固有識別番号は、管理情報として、データベース上に保存され管理される。管理情報は、例えば一般情報＋チップの識別番号から構成される。
半導体集積回路装置又はＩＣカードの組み立て後の検査工程では、管理情報を読み出してデータベースを参照し同一の管理情報があるか確認する。同一の管理情報がデータベース内に存在すれば、レーザによるプログラムは正しいと判定される。同一の管理情報がデータベース内に見付からない時は、最も類似した管理情報を抽出する。次に、読み出した情報と抽出した管理情報のそれぞれの一般情報どうしを比較する。
この読み出しの際、一般情報の部分については、例えば電源電圧条件を変えるなど複数の条件で読み出し、固有識別番号については１回のみ読み出すことで、短時間にデータの書き込みが十分安定しているか確認することができる。なお、試験中は高速にデータベース上の管理情報との照合を行う必要がある。例えば、検査が始まる前に予め参照される管理情報のデータを試験装置に付随するワークステーション等に格納しておいてもよい。
上記の方法によって、プログラム情報の迅速で正確な確認が出来るようになる。しかも、固有識別番号の書き込みをレーザフューズ等で逐一行うと、加工時間とチップ面積の増加をもたらす可能性があるが、本願発明に係るＣＭＯＳインバータ回路論理しきい値のバラツキを用いたチップ識別番号発生回路を用いることで、簡単にしかも自動的に固有識別番号を得ることができる。
つまり、レーザプログラムに先立つ、プローブ検査等で取得されたチップ識別番号および、ロットやウェハ等の情報を、管理情報データベースに登録する。指示されたウェハ上のチップに対応する管理情報をレーザフューズへ書き込むというものである。
第７０図には、この発明に係る識別番号発生回路を搭載した半導体チップを用いた半導体集積回路装置の組み立て工程（いわゆる後工程）の一実施例のフローチャート図が示されている。
（１）プローブ検査では、識別番号発生回路によるＩＤ番号、ロット名、ウェハ番号、チップ番号等をデータベースに登録する。
（２）登録時に既に登録されたＩＤ番号に類似した新たなＩＤ番号が発生した場合、何らかの警告を発しチップを処置する。
（３）組み立て試験以降の工程では、既にチップはダイシング工程にてバラバラに分かれているため、識別番号発生回路によるＩＤ番号と、工程番号、当該工程ロット名をデータベースに登録する。
（４）本願に係る識別番号発生回路によって取得できるＩＤ番号は、組み立て工程の機械的、熱的ストレスやバーイン工程の電気的ストレス等で変動する可能性があるため、最新検査工程で取得されたＩＤ番号をデータベースに格納する。
（５）後工程内のチップ追跡の必要がない場合、最終出荷選別工程でのみ識別番号発生回路によるＩＤ番号を取得しデータベースに登録する。
（６）各試験工程で、不良になったチップの既取得ＩＤ番号情報は、削除するか印を付けて以降の検索処理時間を軽減する。
（７）マーキング工程では、製品を製造したラインを示す記号や番号、製造した時期を示す年番号や週番号が刻印されることがある。個別サンプルの識別を行う上で、これらの刻印は検索のための情報となる。そこで、出荷選別２では、識別番号発生回路によるＩＤ番号とこららの刻印情報をデータベースに登録する。共通の刻印情報を持つチップでは、識別番号発生回路によるＩＤ番号は全て独立である必要があるが、異なる刻印情報を持つチップでは、識別番号発生回路によるＩＤ番号に同一あるいは類似しても構わない。すなわち、各チップに搭載する識別番号発生回路によるＩＤ番号の識別能力を抑えることが可能で、識別番号発生回路の規模および識別番号のビット数を削減できる。
（８）各工程毎の識別番号発生回路によるＩＤ番号の登録時に、ＩＤ番号をもとにロットの混入・混合を検出し、何らかの警告を発する。
この実施例では、全ての工程とデータベース間がオンラインで直結しているが、現実には立地条件により通信回線による接続が困難である場合や、通信速度が遅い、バッチ処理が介在するなどの理由でリアルタイム性に欠けるような状況が発生する。そのような場合、いったんローカルなデータベースに蓄える。さらに、即時性が必要でない場合、記憶媒体に保存し、データベースまで輸送するか、現物と一緒に、次工程に搬送する。
各工程の試験装置や処理計算機などの制約などによって、データベースに集められるデータの形式が異なる場合がある。そのような場合、データフォーマットのを変換する処理を、データベース登録直前に挿入すればよい。
第７１図と第７２図には、この発明に係る識別番号発生回路のビット数を減少させる方法の一実施例の構成図が示されている。第７１図には、識別番号発生回路のビット数を低減させる登録方法、第７２図には、その照合方法が示されている。
世の中に半導体集積回路装置等の製品が出荷されユーザで使用中に不良となった場合に、返品され不良原因調査を行う場合にも本願発明に係る識別番号発生回路が有効に機能する。この場合には、出荷時に識別番号を管理するデータベースへ登録し、もし不良で製品が戻ってきた場合にその製造過程のデータを調査する。このときに、不良品がどの管理番号の製品であるかを照合する必要がある。製品の出荷数が多ければ、以下のような状況が発生する。
識別番号の識別可能数は識別番号発生回路のビット数に依存しておりビット数が多ければ識別の確度は向上するが、それだけ識別対象データ数は多くなる。製品の識別を行う上で、識別対象数が多くなれば、比較照合するためにデータベース上の多くのデータを読み出し、かつ照合演算を実行する必要がある。そこで、比較照合処理の時間やシステムへの負荷を軽減するために、第７１図のように識別番号グループを示す情報を別途定義する。これにより第７２図のように照合データ数の範囲を、少なくすることができる。
このような識別番号のビット数を低減させるための識別番号グループは、一般的なロット、マークと呼ばれている情報が使用される。この情報と識別番号との組み合わせで製品がユニークに管理できるように管理することができる。また、出荷後の製品を管理するだけのデータベースにおいては、不良となったチップの情報を削除し管理コストを削減する。の識別グループでデータベース上の膨大なデータの中から照合対象を減らし、処理時間、システム負荷を減らすことができる。
第７３図と第７４図には、この発明に係る半導体集積回路装置に搭載された識別番号発生回路を利用した検査方法を説明するための構成図が示されている。第７３図は、識別番号取得工程が示され、第７４図は、検査工程が示されている。
第７３図に示した製造過程の終了に近い段階で、識別番号発生回路はその機能が利用できるため、何回かの検査工程の前に識別番号取得工程を設け、まず最初に、製品の識別番号と管理番号・品種などの後の工程で必要となるデータをデータベースへ登録する。ただし、識別番号発生に関する最低限の動作が可能なデバイスに限られる。
第７４図に示した以降の各検査工程では、まず製品の識別番号を読み出し、データベース上の識別番号と照合し管理番号を取得する。この管理番号から品種や検査仕様のデータを一意に決定し、検査装置へ転送する。検査装置は個々の製品毎に与えられた検査仕様で検査を行うことができる。この構成の利点は、各検査工程では、品種や検査仕様あるいはその他の付随データを最初の識別番号取得工程のみでデータベースに与えれば、その後の各検査工程あるいは製造工程において与える必要がないため生産の効率を上げることができる。
第７５図には、この発明に係る半導体集積回路装置に搭載された識別番号発生回路を利用し各検査工程で半導体チップ毎の特性データの相関を管理する方法を説明するための構成図が示されている。
半導体製造における各検査工程で得られる特性データ（測定値）は、各工程で得られるが、その特性データの変化を分析することがある。これらの特性データを管理するために識別番号を使用しチップ毎に各工程毎の特性データをデータベースに格納する。この時、データベースの識別番号も、最新の工程で得られた識別番号で更新することで回路の動作変化による識別番号の変化をデータベースに取り込む。
従来は、プローブ検査と完成品検査との相関は、ロット単位に複数チップをグループとして相関を取るしかなかった。今回は各チップ毎に各工程間の特性データ変化の相関を取ることができるため分析の精度を上げることができる。
第７６図には、この発明に係る半導体集積回路装置に搭載された識別番号発生回路を利用し前工程でウェハを自動で管理する方法を説明するための構成図が示されている。
ＴＥＧ上にウェハを識別するための識別番号発生回路を設け、最初の配線工程で、その機能が完成する場合に、個々のウェハをその識別番号で管理することができる。これによりウェハに管理用のタグを付けることが不要であるし、ウェハの製造工程を管理するシステムへの情報入力も不要になる。
識別番号発生回路の機能が有効となり、かつ、それ以降の各工程でそのウェハが処理される製造装置・検査装置に識別番号読み取り機構が付いていれば、読み取った識別番号でデータベースにアクセスすることで、自動でそのウェハの情報を装置に設定することが可能である。また、そのウェハを処理したときの製造条件や検査データをデータベースへ自動で格納することもできる。
識別番号読み取り機構は、パソコンから制御可能な電源と識別番号発生回路を機能させるための信号生成とその出力（識別番号）を読み取れるボードとソフトウエアで構成できる。ＴＥＧと信号の入出力するためのプローブも必要である。
第７７図には、この発明に係る半導体集積回路装置に搭載された識別番号発生回路の識別番号の格納・検索方法を説明するための構成図が示されている。
この実施例では、識別番号の上位Ｎビットを取り出しインデックスとしてデータベース上のテーブルフィールドに格納・管理する方式を採ることにより検索スピードの向上、システムへの負荷低減が行える。比較対象の識別番号とデータベース内の識別番号群との比較方法で、比較対象の識別番号の上位ビットをまず抽出し、この値をデータベース上のインデックス値と一致する条件でテーブルを検索する。次に、ここで得られた識別番号群に対して１件づつ識別番号距離を求めて最小のものを一致識別番号と判定する。これにより、テーブル上の全件の識別番号を比較することなく該当データを見つけ出すことが可能である。
第７８図には、この発明に係る半導体集積回路装置に搭載された識別番号発生回路の識別番号の格納・検索方法の他の例を説明するための構成図が示されている。
識別番号の検索範囲を限定してデータベースの識別番号群と比較する方式を採用することにより検索スピードの向上、システムへの負荷低減が行える。比較対象の識別番号とデータベース内の識別番号群との比較方法で、比較対象の識別番号に対して揺らぎによる許容範囲の上限・下限をデータベース検索条件としてテーブルを検索する。次に、ここで得られた識別番号群に対して１件づつ識別番号距離を求めて最小のものを一致識別番号と判定する。これにより、テーブル上の全件の識別番号を比較することなく該当データを見つけ出すことが可能である。１回目の許容範囲の上限・下限で該当せずにデータが検索できなかった場合は、上限・下限を緩めて再度検索処理を行っていく。
第７９図には、この発明に係る識別番号発生回路を利用した半導体集積回路装置の救済方法の一実施例の構成図が示されている。
▲１▼本体チップのプローブ検査が実施される。この検査によりＤＲＡＭ等の救済データを識別番号発生回路から取り出した識別番号とともにホストコンピュータに送る。
▲２▼ダイシングして完全動作品と救済可能品のみを取り出す。
▲３▼救済データ専用ＥＥＰＲＯＭのプローブ試験を実施する。
▲４▼正常動作品をダイシングし、ストックして置く。
▲５▼本体ＬＳＩと救済データ専用ＥＥＰＲＯＭを同一モジュールに実装する。
▲６▼実装済モジュールの本体ＬＳＩの識別番号を読み出し、対応する救済データを救済データ専用ＥＥＰＲＯＭに書き込む。
▲７▼選別試験を行う。
▲８▼良品ＬＳＩは出荷し、不良ＬＳＩのうち再度救済可能なものはステップ前記▲６▼に戻り、対応する救済データを救済データ専用ＥＥＰＲＯＭに書き込む。
これにより、半導体集積回路装置の救済が簡単にしかも合理的に行うようにすることができる。
なお、半導体集積回路装置の救済の他にも上記識別番号を利用した検査コストの低減が可能である。半ウェハ上に半導体チップが形成された時点で行われるプローブ試験において、例えば、フラッシュメモリのような半導体チップでは、同じ回路機能で動作電圧が３．０Ｖ、２．５Ｖ及び１．８Ｖのように異なるものを別品種として製造するものがある。
このとき、１．８Ｖに対応した電圧設定によりテストを実施し、正しくメモリ動作が行われるか否かの判定が行われる。この判定により良品とされた半導体チップには、その識別番号に１．８Ｖ動作確認の電圧情報が記録される。動作確認の情報は、半導体チップそれ自体に不揮発的に書き込み保持される。そのために、半導体チップ内には、フラッシュメモリからなるような管理メモリが設定される。
上記１．８Ｖで不良となったチップについては、２．５Ｖに電圧設定してメモリ動作が行われるか否かの判定が行われる。この判定により良品とされた半導体チップには、その識別番号に２．５Ｖ動作確認の電圧情報が記録される。そして、上記２．５Ｖで不良となったチップについては、２．５Ｖに電圧設定してメモリ動作が行われるか否かの判定が行われる。この判定により良品とされた半導体チップには、その識別番号に３．０Ｖ動作確認の電圧情報が記録される。この３．０Ｖで不良となったチップは不良チップとして廃棄される。
この実施例においては、例えば上記１．８Ｖで動作するものとされた半導体チップについて、２．５Ｖや３．０Ｖでの動作試験を行うことなく、２．５Ｖや３．０Ｖでの動作が可能なものとして扱われる。同様に、上記２．５Ｖで動作するものとされた半導体チップについて、３．０Ｖでの動作試験を行うことなく３．０Ｖでの動作が可能なものとして扱われる。このため、１．８Ｖで動作するものとされた半導体チップを２．５Ｖや３．０Ｖでの動作させたときに不良となる可能性を持つが、その確率は小さいと考えられるので逐一各電圧での動作を行うことよりもそれを省略してテスト時間の短縮化を図った方が全体としての製造のコストの低減が可能になる。
そして、フラッシュメモリ単体として組み立てるとき、あるいはマイクロプロセッサ等と組み合わせて１つの半導体集積回路装置として組み立てられるとき、上記識別番号からホストコンピュータに記憶された動作電圧情報を得て、適合するものが組み合わられる。このとき、２．５Ｖで動作する半導体集積回路装置は、前記１．８Ｖの動作確認のチップも用いることができ、３．０Ｖで動作する半導体集積回路装置は、前記１．８Ｖと２．５Ｖで動作するチップも用いることができる。
第８０図は、この発明に係る識別番号発生回路を備えた半導体集積回路装置の更に他の実施例のレイアウト図であり、第８１図は第８０図の部分拡大レイアウト図である。 第８０図の半導体集積回路装置は、多くの一般的な半導体集積回路装置と同様に、それを構成する半導体チップのほぼ中央に内蔵回路ないし内部回路が配置され、その周辺に外部との信号の授受のための複数の入出力セル（Ｉ／Ｏセル）が配置された構成を採る。
半導体チップの周辺部の４つの角は、一般的な半導体集積回路装置と同様に、Ｉ／Ｏセルが配置されていない空領域となっている。この実施例ではかかる空領域を利用し、その１つに、識別番号発生回路ＣＲＮＣが設けられている。
識別番号発生回路ＣＲＮＣは、半導体チップ上に延長形成される信号及び電源配線層によって内蔵回路と結合される。
後で説明するように、信号及び電源配線は、切断される場合が有る。かかる切断の便宜の上では、かかる信号及び電源配線層は、その数が少ない方が望ましい。そこで実施例では、識別番号発生回路と内蔵回路のインターフェースのための配線は、該識別番号発生回路のための電源配線（ＶＤＤ、ＶＳＳ）と、リセット信号（ＲＥＳ）、クロック信号（ＣＬＫ）、識別番号出力信号（ＯＵＴ）のための３つの信号配線とからなるような少ない数の配線から構成される。第８１図の部分拡大図では、比較的太い線によって電源配線ＶＤＤ、ＶＳＳを表示し、比較的細い線によってリセット信号、クロック信号識別番号出力信号のための信号配線を表示している。図から明らかなように、信号配線は、実質的に電源配線ＶＤＤ，ＶＳＳによって囲まれた状態を持って延長されている。 識別番号発生回路ＣＲＮＣは、上記リセット信号、クロック信号の元で、前記実施例のような総当たり方式を持っての識別番号発生が可能なように構成される。識別番号発生回路ＣＲＮＣの周囲の空領域上には、第８１図のように、かかる回路ＣＲＮＣのリセット信号（ＲＥＳ）、クロック信号（ＣＬＫ）、識別番号出力信号（ＯＵＴ）電源端子ＶＤＤ、ＶＳＳにつながる電極パッドＲＥＳ、ＣＬＫ、ＯＵＴ、ＶＤＤ、ＶＳＳが設けられている。それら電極パッドは、モールドレジンなどのパッケージ部材によって半導体チップをパッケージして構成されたような半導体集積回路装置の外部端子とされるものでなく、プローブニードルと称されるようなコンタクタに適合可能なように、半導体チップ上に構成される。
図示の識別番号発生回路ＣＲＮＣからの識別番号情報は、半導体集積回路装置の電源線、内蔵回路，Ｉ／Ｏセルなどの径路が動作可能であるなら、Ｉ／Ｏセルを介する正常径路を通って外部への読み出しが可能にされる。
ここで、識別番号情報は、製品の来歴調査を含めての多くの必要性に応えられることが望ましい。識別番号情報は、場合によっては、動作不能となった半導体集積回路装置からも得られることが望まれる。
半導体集積回路装置が、不都合なことに、電源電流の異常増大、他の種々要因にによって正常動作しなくなっている場合には、モールドレジンのようなパケージ部材が除去され、半導体チップが露出され、識別番号発生回路ＣＲＮＣと内蔵回路との間の電源及び信号配線層がレーザ切断装置のような装置によって切断除去される。これによって識別番号発生回路ＣＲＮＣは、上記電極パッドのみに接続された状態にされる。言い換えると、該回路ＣＲＮＣは、半導体集積回路装置の内部配線ショート、内部素子破壊等から自由にされ、それ自体独立的に動作可能にされる。そこで、この状態で、上記電極パッドにコンタクタが接触され、かかるコンタクタを介して、識別番号情報の取得が可能となる。
半導体集積回路装置が、半導体チップ上に応力緩和の狙いを持つような絶縁層及び再配置配線のような配線層を介してバンプ電極からなるような複数の外部端子を設けるところのチップ・サイズ・パッケージないしはチップ・スケール・パッケージと称されるようなパッケージ形態を取る場合も、同様に識別番号情報を得ることができる。この場合、通常の外部端子を介して識別番号情報を得ることが困難なときには、バンプ電極、絶縁層の除去によって上記と同じ電極パッド、及び切断すべき配線部分の露出が行われ、配線切断除去の後に、上記電極パッドを介しての識別番号情報の読み出しが行われる。
第８２図は、この発明に係る識別番号発生回路を備えた半導体集積回路装置の他の実施例の構成図であり、第８３図はその回路図である。
この実施例の半導体集積回路装置は、ＭＯＳＦＥＴ等を構成する半導体領域を固定的パターンとしておき、配線により所望の機能の回路を構成するようにする、いわゆるマスタースライス方式のものとされる。半導体集積回路装置を成す半導体チップ上に設定されるＩ／Ｏセルの内、遊休Ｉ／Ｏセル、すなわち該半導体集積回路装置の機能の上からは使用されないＩ／Ｏセルは、識別番号発生回路を構成するものとされる。
１つのＩ／Ｏセルは、図示のように、比較的小さい面積の出力制御回路のための領域、比較的大きい面積の出力ＭＯＳＦＥＴのための領域（出力ＭＯＳ）、及び入出力パッド電極（Ｉ／ＯＰＡＤ）を配置するための領域からなり、その全体は図示のように長方形の平面パターンを成している。
上記出力制御回路のための領域は、比較的小さい面積とされるが、所望の出力制御回路、入力回路を構成可能なように、比較的多数のゲート回路、インバータ回路及びＭＯＳＦＥＴのようなサブ要素を持つ。出力ＭＯＳＦＥＴのための領域は、１つもしくは２つのｐチャンネル型ＭＯＳＦＥＴと１つもしくは２つのＮチャンネル型ＭＯＳＦＥＴとからなるような比較的少ない数のＭＯＳＦＥＴしか持たないが、高い外部負荷駆動能力の点で比較的大きい面積とされる。
上記識別番号発生回路は、遊休Ｉ／Ｏセルにおける出力制御回路のための領域におけるサブ要素によって構成される。上記識別番号発生回路は、かかる出力制御回路のための領域における比較的多数のサブ要素によって、かかる領域に構成可能となる。
第８３図に図示のＰチャンネル型ＭＯＳＦＥＴ及びＮチャンネル型ＭＯＳＦＥＴ、インバータ回路、ＮＡＮＤ回路及びＮＯＲ回路は、全体として、識別番号発生回路の出力を外部に出力させるためのトライステート出力バッファ回路を構成している。かかる出力バッファ回路において、インバータ回路、ＮＡＮＤ回路及びＮＯＲ回路は、出力制御回路のための領域におけるサブ要素によって構成され、出力ＭＯＳＦＥＴは出力ＭＯＳＦＥＴのための領域におけるＭＯＳＦＥＴによって構成される。
上記遊休Ｉ／Ｏセルにおけるトライステート出力バッファ回路の出力は、同セルに設けられる入出力パッド電極（Ｉ／ＯＰＡＤ）に結合される。言い換えると、図示の入出力パッド電極は、識別番号情報専用の出力電極とされる。
上記入出力パッド電極は、半導体集積回路装置における、通常はＮＣ（Ｎｏｎ Ｃｏｎｎｅｃｔｉｏｎ）ピンと称されるような半導体集積回路装置の空ピンないしは空き端子に、結合される。
この実施例によれば、図中に識別番号回路イネーブルと標記されているイネーブル信号がハイレベルのような有意レベルにされることによって、識別番号発生回路及びトライステート出力バッファ回路が動作状態にされる。識別番号発生回路の動作のために、図中に、出力クロックと標記されている連続クロック信号が供給される。かかる連続クロック信号に応答して入出力パッド電極に准じに識別番号情報が供給される。
第８４図は、この発明に係る識別番号発生回路を備えた半導体集積回路装置の他の実施例の構成図である。この実施例は、近年のような大規模な半導体集積回路装置に有っては、消費電流の増大や動作速度の高速化に対応するような電源強化の点から、遊休Ｉ／Ｏセルが有っても、そのセル領域を電源強化のために転用する、と言うことが考慮されている。
第８４図のレイアウト図では、３つのＩ／Ｏセルが例示されている。かかる３つのＩ／Ｏセルの内、図面の上の方のＩ／Ｏセルは遊休Ｉ／Ｏセルとされ、図面の下の方の他のＩ／Ｏセルは、半導体集積回路装置動作のために動作利用される正規Ｉ／Ｏセルとされる。
遊休Ｉ／Ｏセルにおいて、その入出力パッド電極用の領域には電源パッド電極、すなわち電源等に転用されたパッド電極が設けられている。電源パッド電極は、複数のＩ／Ｏセル、ないしは内蔵回路のための図示しない電源配線層に結合されている。なお、遊休Ｉ／Ｏセル上の電源配線層は、通常、多層配線構造を採る配線層の内のメタルからなるような上層配線層からなると理解されたい。
遊休Ｉ／Ｏセルにおいて、上記第８１図の出力制御回路のための領域と対応する部分には、多層配線層における下層側の配線層による配線によって、上記第８１図の例と同等に、出力クロック信号、識別番号回路イネーブル信号を受け、識別番号出力を形成するところの識別番号発生回路が構成されている。
上記識別番号発生回路と内蔵回路との間の出力クロック信号、識別番号回路イネーブル信号及び識別番号出力のための配線層は、後で説明する配線切断及び端子形成が容易なように、それぞれの一部が比較的上層の配線層を使用するようにされる。
識別番号発生回路の出力信号は、出力セルとして設定される正規Ｉ／Ｏセルの入力側に設けられた出力選択回路の供給される。
これによって、出力セルとして設定される正規Ｉ／Ｏセルは、半導体集積回路装置の通常動作においては、内蔵回路から出力選択回路を介して供給される正規出力データをその入出力パッド電極に出力する。
かかる正規Ｉ／Ｏセルは、識別番号情報を出力すべきときには、識別番号発生回路から出力選択回路を介して供給される識別番号情報をその入出力パッド電極に出力する。
第８５図は、識別番号発生回路の電源端子ＶＤＤ及びグランド端子と称されるような基準電位端子ＶＳＳと、複数のＩ／Ｏセル上を延長されるような電源配線層及び基準電位配線層との結合パターンを示している。上記のＩ／Ｏセル上を延長する電源配線層ＶＤＤ及び基準電位配線層ＶＳＳが電源系強化の意図の元で比較的広い幅を持つようにされる。この実施例では、第８５図のように、比較的幅広の電源配線層に対し細い幅の分岐配線層が設けられ、かかる細い幅の分岐配線層が、識別番号発生回路のための電源配線ＶＤＤ−Ｖと結合される。基準電位配線層と識別番号発生回路の基準電位配線ＶＳＳ−Ｖとの結合も同様にな構成とされる。この構成は、識別番号発生回路と電源配線層及び基準電位配線層との間の次に説明するような分離を用意にする。
電源配線層−基準電位配線層間の短絡等の異常にかかわらずに、識別番号発生回路から識別番号情報を得る必要が生じたときには、第８６図のように、かかる回路の電源端子ＶＤＤ、基準電位端子ＶＳＳにつながる細幅分岐配線層が、レーザ切断技術やフォーカスド・イオン・ビーム（ＦＩＢ）技術のような技術によって切断される。これと共に、識別番号発生回路と内蔵回路との間の前述のような信号線も同様に切断される。
ついで、絶縁膜形成、それに対する開口形成、及び導電層の選択形成がＦＩＢ技術のような公知の技術によって行われる。これによって、識別番号発生回路の電源端子ＶＤＤ、基準電位端子ＶＳＳには、第８６図のように新たな導電層からなる導電気領域が設定される。同時に、上述の信号線に対しても新たな導電層が設定される。
プローブ針と称されるようなコンタクタがそれら導電層に接触され、識別番号発生回路が動作され、識別番号情報が得られることとなる。
第８７図は、この発明に係る識別番号発生回路を備えた半導体集積回路装置の他の実施例の回路図である。
この実施例では、半導体集積回路装置に構成された識別番号発生回路に対して、図示のような２つのダイオード接続のＭＯＳＦＥＴＱ１、Ｑ２、識別番号回路用電源パッド、識別番号専用出力パッド、識別番号専用クロックパッド、及び識別番号専用イネーブルパッドが設けられている。
半導体集積回路装置が正常動作可能である場合には、識別番号発生回路は、半導体集積回路装置の正規電源端子ＶＤＤ、正規電源配線及びダイオード接続ＭＯＳＦＥＴＱ１を介して動作電圧が与えられ、かつ図示しない内蔵回路からのクロック信号、識別番号イネーブル信号に応答して、内蔵回路に識別番号情報を出力する。
正規電源端子ＶＤＤ及びそれにつながる電源配線と、正規基準電位端子ＶＳＳ及びそれにつながる基準電位配線との間の短絡異常などによって、正規端子ＶＤＤ・ＶＳＳ−を介して識別番号発生回路に電源供給ができない場合には、図示の各種パッドを介して必要な電圧、信号がかかる回路に加えられ、かかる回路が動作される。ダイオード接続のＭＯＳＦＥＴＱ１は、識別番号回路用電源パッド及びＭＯＳＦＥＴＱ２を介して該回路に加えられる電源電圧に対して自動的にオフ状態となるようなスイッチ動作をする。これによって正規電源系の異常にかかわらずに識別番号発生回路に給電をすることができる。
上記の各実施例から得られる作用効果は、下記の通りである。
（１） 半導体集積回路装置の製造工程の過程で同一の形態からなる複数の識別要素を形成し、そのプロセスバラツキに対応した複数の識別要素の相互の物理量の大小関係を判定して、半導体集積回路装置の固有の識別情報として用いることにより、簡単な構成で個々の半導体集積回路装置の識別を可能にすることができるという効果が得られる。
（２） 上記に加えて、上記固有の識別情報を上記製造時に識別要素に割り当てられた第１識別情報と、上記判定により得られた上記複数の識別要素の物理量を大小関係の順位情報とを用いることにより、個々の半導体集積回路装置の識別のための情報量を少なくできるから、識別情報を記憶する記憶回路を簡単にできるとともにその判定時間も短縮化できるという効果が得られる。
（３） 上記に加えて、上記識別要素をＮチャンネル型ＭＯＳＦＥＴとＰチャンネル型ＭＯＳＦＥＴからなるＣＭＯＳインバータ回路の入力端子と出力端子とを接続し、その論理しきい値を大小比較を行う物理量とすることにより、ＣＭＯＳ回路等の基本的なデジタル回路で構成できるから格別な製造プロセスの追加なく適用可能な半導体集積回路装置の範囲を広くできるという効果が得られる。
（４） 上記に加えて、上記ＣＭＯＳインバータ回路に対して、物理量としての論理しきい値電圧判定時にのみ動作電圧を印加するようにすることにより、素子特性の劣化の影響を軽減できるので安定的で信頼性の高い識別結果を得ることができるという効果が得られる。
（５） 半導体集積回路装置の製造工程の過程で同一の形態からなる複数の識別要素を形成し、そのプロセスバラツキに対応した物理量を判定し、上記複数の識別要素の相互の物理量の大小関係に基づいて固有の識別情報を生成して製造履歴と附帯させて記憶し、かかる半導体集積回路装置について不良が発生したときに、上記固有の識別情報を基に上記記憶された製造履歴を読み出し不良解析を行って、必要に応じて上記製造工程にフィードバックさせることにより、合理的な製造システムの構築を行うようにすることができるという効果が得られる。
（６） 第１チップを構成する半導体集積回路装置の製造工程の過程で同一の形態からなる複数の識別要素を形成し、そのプロセスバラツキに対応した相互の物理量の大小関係に基づいてかかる第１チップの固有の識別情報を生成し、上記第１チップを構成する半導体集積回路装置の複数に対して、それぞれの電気的特性に応じて複数の動作修飾情報を形成し、上記個々の第１チップの識別情報に対応させて第２チップに書き込み、上記第１チップと第２チップとを組み立てて第１チップの識別情報を基に上記動作修飾情報を第１チップに向けて出力させることにより、マルチチップ構成の半導体集積回路装置を煩雑なチップ管理を行うことなく効率よく製造することができるという効果が得られる。
（７） 上記に加えて、上記第１チップで冗長回路を持つメモリを構成し、上記第２チップを不良アドレスを記障するものとすることにより、簡単な構成で製造歩留りを高くしたメモリ装置を得ることができるという効果が得られる。
（８） 上記に加えて、上記第１チップと第２チップが組み立てられた状態で更に試験を行って不良が発生した場合に、上記第２チップを取り外して、上記第１チップを構成する半導体集積回路装置の別の複数の半導体集積回路装置の纏められる工程に戻すことにより、製造歩留りを改善することができるという効果が得られる。
（９） 上記に加えて、上記第１チップと第２チップとを上記組み立てられた状態での選別の後に一体的に封止することにより、製造歩留りの改善を行ないつつ、半導体集積回路装置の小型化を実現できるという効果が得られる。
（１０） 上記に加えて、上記第１チップと第２チップとを共通の実装基板上に組み立てるようにすることにより、第２チップの取り外しが簡単となって、上記不良が発生した場合の再利用を効果的に行うようにすることができるという効果が得られる。
（１１） 半導体集積回路装置の製造工程の過程で同一の形態として形成された複数の識別要素のプロセスバラツキに対応した相互の物理量の大小関係に基づいて固有の識別情報を持たせることにより、簡単な構成で個々の半導体集積回路装置の識別情報を組み込むことができるという効果が得られる。
（１２） 上記に加えて、上記固有の識別情報を上記製造時に識別要素に割り当てられた第１識別情報と、上記複数の識別要素の物理量を大小関係の順位情報とすることにより、個々の半導体集積回路装置の識別のための情報量を少なくできるから、それを記憶する記憶回路を簡素化できるとともにその判定動作の高速化もできるという効果が得られる。
（１３） 上記に加えて、識別要素をＮチャンネル型ＭＯＳＦＥＴとＰチャンネル型ＭＯＳＦＥＴからなるＣＭＯＳインバータ回路の入力端子と出力端子とを接続し、その論理しきい値を大小判定の物理量として利用することにより、ＣＭＯＳ回路等の基本的なデジタル回路で構成できるから格別な製造プロセスの追加なく適用可能な半導体集積回路装置の範囲を広くできるという効果が得られる。
（１４） 上記に加えて、ＣＭＯＳインバータ回路の入力端子と出力端子とを接続し、その論理しきい値を大小判定を行う回路として、複数のＣＭＯＳインバータ回路の各々にスイッチを設け、２個ずつの組み合わせで総当たりで共通の電圧比較回路に上記論理しきい値電圧を供給して判定することにより、簡単な構成で高い識別能力を実現できるという効果が得られる。
（１５） 上記に加えて、複数のＣＭＯＳインバータ回路の各々に対応して、その入力端子と出力端子とを接続する第１スイッチと、共通の第１回路ノードと入力端子とのを接続する第２スイッチと、出力端子と共通の第２回路ノードとを接続する第３スイッチとを設けて、かかる第１ないし第３スイッチの組み合わせにより、複数のインバータ回路間において２つのＣＭＯＳインバータ回路を１組として総当たりで、一方のＣＭＯＳインバータ回路の入力端子と出力端子とを接続して上記第１の回路ノードに得られて電圧を他方のＣＭＯＳインバータ回路の入力端子に供給して、かかる他方のＣＭＯＳインバータ回路の論理しきい値電圧を参照電圧として電圧比較の出力信号を上記第２の回路ノードに得るようにすることにより、簡単な構成での識別番号の生成を行うようにすることができるという効果が得られる。
（１６） 上記に加えて、上記ＣＭＯＳインバータ回路と第１スイッチないし第３スイッチをＣＭＯＳゲートアレイを構成する素子を用いることにより、配線設計のみにより識別番号発生回路を得ることができるという効果が得られる。
（１７） 上記に加えて、上記ＣＭＯＳインバータ回路に上記物理量としての電圧判定時にのみ動作電圧を供給することにより、素子特性の劣化の影響を軽減できるので安定的で信頼性の高い識別番号を得ることができるという効果が得られる。
（１８） 第１インバータ回路の入力端子と出力端子とを選択的に短絡させる第１スイッチと、上記第１インバータ回路の出力端子が入力端子に接続された第２インバータ回路を設け、その出力信号を受けて増幅回路で増幅してなる識別要素の複数個を設け、上記第１スイッチがオン状態のときの各識別要素からの出力信号により識別番号を生成する識別番号回路を内蔵させることにより、簡単な構成で個々の半導体集チップの識別を可能にすることができるという効果が得られる。
（１９） 上記に加えて、上記インバータ回路をＣＭＯＳインバータ回路とし、上記第１スイッチがオン状態のときの第２インバータ回路の出力信号がその論理しきい値に対してハイレベル側なら上記増幅回路の出力信号を受けてロウレベルを形成し、上記第１スイッチがオン状態のときの第２インバータ回路の出力信号がその論理しきい値に対してロウレベル側なら上記増幅回路の出力信号を受けてハイレベルを形成し、上記第１スイッチがオフ状態にされるフィードバック動作のときに上記第１インバータ回路の入力端子に帰還させるラッチ回路を更に設けることにより、識別番号の再現性と経時変化に対する耐性を高めることができるという効果が得られる。
（２０） 上記に加えて、上記増幅回路を複数個のＣＭＯＳインバータ回路の縦列接続回路とし、上記第１インバータ回路、第２インバータ回路及び増幅回路を構成する各ＣＭＯＳインバータ回路の入力端子のそれぞれにハイレベル側の電圧を与える第３スイッチを設け、上記第１インバータ回路ないし上記増幅回路を構成する各インバータ回路列のそれぞれの相互接続点に第３スイッチを設け、上記識別番号回路が非動作状態のときは上記第２スイッチをオン状態にし、上記第３スイッチをオフ状態にし、上記第１スイッチをオン状態にされた識別情報の増幅時及び上記フィードバック動作時には上記第２スイッチをオフ状態にし、上記第３スイッチをオン状態にすることにより、識別番号の再現性と経時変化に対する耐性をいっそ高めることができるという効果が得られる。
（２１） 第１インバータ回路及び第２インバータ回路のそれぞれの入力端子と出力端子とを短絡させる第１スイッチを設け、上記第１インバータ回路の出力端子を第２インバータ回路の入力端子に接続させる第２スイッチを設け、上記第２インバータ回路の出力端子が入力端子に接続されてなる第３インバータ回路を含んだ増幅回路とを含む複数個の識別要素を用い、上記第１インバータ回路の第１スイッチをオン状態にし、第２インバータ回路の第１スイッチをオフ状態にし、上記第２スイッチをオン状態にしたたときの上記第３インバータ回路を含む上記増幅回路の出力信号により第１識別情報を得て、上記第２インバータ回路の第１スイッチをオン状態にして上記第２スイッチをオフ状態にしたときの上記第３インバータ回路を含む上記増幅回路の出力信号により第２識別情報を得るように識別番号を生成する識別番号回路を内蔵させることにより、回路の簡素化を図りつつ、個々の半導体集チップの識別を可能にすることができるという効果が得られる。
（２２） 上記に加えて、上記第１インバータ回路、第２インバータ回路からなる回路列を上記第１インバータ回路及び第２インバータ回路が対応して並ぶように複数回路列を設け、上記複数回路列の対応する第１スイッチには同じスイッチ制御信号が共通に供給し、複数回路列の上記第２インバータ回路の出力信号のいずれか１つを第３スイッチにより選択して上記増幅回路の初段回路を構成する第３インバータ回路の入力端子に接続することにより、多数の識別情報を効率的に得るようにすることができるという効果が得られる。
（２３） 上記に加えて、上記第１インバータ回路及び第２インバータ回路の入力端子には、入力信号を切断する第４スイッチと、ハイレベル側の電圧を供給する第５スイッチを設け、上記識別番号回路が非動作状態のときは上記第４スイッチをオフ状態にし、上記第５スイッチをオン状態にすることにより、識別番号の再現性と経時変化に対する耐性をいっそ高めることができるという効果が得られる。
（２４） 第１インバータ回路の入力端子と出力端子とを第１スイッチで短絡させ、上記第１インバータ回路の入力端子第２スイッチを設けてなる単位要素の複数個を上記第２スイッチを介して縦列形態にして識別要素列を構成し、上記識別要素列の最終段に対応された上記第１インバータ回路の出力端子を第２インバータ回路を含んだ増幅回路の入力端子に接続し、クロックを計数するバイナリカウンタの計数出力をデコードするデコーダを上記識別要素列の各第１インバータ回路の第１スイッチ及び第２スイッチに対応して設け、上記バイナリカウンタの計数出力に対応して上記識別要素列を初段回路から順に上記第１スイッチを順次オン状態に、第２スイッチは第１スイッチと相補的にオフ状態にして上記第３インバータ回路を含む上記増幅回路の出力信号により上記識別要素列の各第１インバータ回路に対応した複数の識別情報を得て識別番号を生成する識別番号回路を内蔵させることにより、回路の簡素化を図りつつ、個々の半導体集チップの識別を可能にすることができるという効果が得られる。
（２５） 第１インバータ回路の入力端子と出力端子とを第１スイッチで短絡させ、上記第１インバータ回路の入力端子に第２スイッチを設けてなる単位要素の複数個を上記第２スイッチを介して縦列形態にして識別要素列を構成し、上記識別要素列の最終段に対応された上記第１インバータ回路の出力端子を第２インバータ回路を含んだ増幅回路の入力端子に接続し、上記識別要素列の各第１インバータ回路の第１スイッチ及び第２スイッチに対応したシフトビットを有するシフトレジスタを設け、上記シフトレジスタのシフト動作に対応し、上記識別要素列を初段回路から順に上記第１スイッチを順次オン状態に、第２スイッチは第１スイッチと相補的にオフ状態にして上記第３インバータ回路を含む上記増幅回路の出力信号により上記識別要素列の各第１インバータ回路に対応した複数の識別情報を得て識別番号を生成する識別番号回路を内蔵させることにより、回路の簡素化を図りつつ、個々の半導体集チップの識別を可能にすることができるという効果が得られる。
（２６） 第１インバータ回路の入力端子と出力端子とを選択的に短絡させる第１スイッチと、上記第１インバータ回路の出力端子が入力端子に接続された第２インバータ回路を設け、その出力信号を受けて増幅回路で増幅してなる識別要素の複数個を設け、上記第１スイッチがオン状態のときの各識別要素からの出力信号により識別番号を生成する識別番号回路を内蔵させることにより、簡単な構成で個々の半導体集積回路装置の識別を可能にすることができるという効果が得られる。
（２７） 第１インバータ回路の入力端子と出力端子とを第１スイッチで短絡させ、上記第１インバータ回路の入力端子に第２スイッチを設けてなる単位要素の複数個を上記第２スイッチを介して縦列形態にして識別要素列を構成し、上記識別要素列の最終段に対応された上記第１インバータ回路の出力端子を第２インバータ回路を含んだ増幅回路の入力端子に接続し、クロックを計数するバイナリカウンタの計数出力をデコードするデコーダを上記識別要素列の各第１インバータ回路の第１スイッチ及び第２スイッチに対応して設け、上記バイナリカウンタの計数出力に対応して上記識別要素列を初段回路から順に上記第１スイッチを順次オン状態に、第２スイッチは第１スイッチと相補的にオフ状態にして上記第３インバータ回路を含む上記増幅回路の出力信号により上記識別要素列の各第１インバータ回路に対応した複数の識別情報を得て識別番号を生成する識別番号回路を内蔵させることにより、回路の簡素化を図りつつ、個々の半導体集積回路装置の識別を可能にすることができるという効果が得られる。
（２８） 第１インバータ回路の入力端子と出力端子とを第１スイッチで短絡させ、上記第１インバータ回路の入力端子第２スイッチを設けてなる単位要素の複数個を上記第２スイッチを介して縦列形態にして識別要素列を構成し、上記識別要素列の最終段に対応された上記第１インバータ回路の出力端子を第２インバータ回路を含んだ増幅回路の入力端子に接続し、上記識別要素列の各第１インバータ回路の第１スイッチ及び第２スイッチに対応したシフトビットを有するシフトレジスタを設け、上記シフトレジスタのシフト動作に対応し、上記識別要素列を初段回路から順に上記第１スイッチを順次オン状態に、第２スイッチは第１スイッチと相補的にオフ状態にして上記第３インバータ回路を含む上記増幅回路の出力信号により上記識別要素列の各第１インバータ回路に対応した複数の識別情報を得て識別番号を生成する識別番号回路を内蔵させることにより、回路の簡素化を図りつつ、個々の半導体集積回路装置の識別を可能にすることができるという効果が得られる。
（２９） 上記に加えて、ＪＴＡＧ規格に適合されたテスト回路を更に備え、上記識別番号回路で生成された識別番号を上記ＪＴＡＧ規格に適合されたインターフェイスを介して出力させることにより、テスト回路の流用によって回路の簡素化が可能になるという効果が得られる。
（３０） 上記に加えて、上記単位要素、第１スイッチ及び第２スイッチを含んだ識別番号回路は、ソフトＩＰ技術を用いて回路設計及び回路レイアウトを行うようにすることにより、設計コストの低減が可能になるという効果が得られる。
（３１） 第１インバータ回路の入力端子と出力端子とを第１スイッチで短絡させ、上記第１インバータ回路の入力端子に第２スイッチを設けてなる単位要素の複数個を上記第２スイッチを介して縦列形態にして識別要素列を構成し、上記識別要素列の最終段に対応された上記第１インバータ回路の出力端子を第２インバータ回路を含んだ増幅回路の入力端子に接続し、上記識別要素列の各第１インバータ回路の第１スイッチ及び第２スイッチに対応したシフトビットを有するシフトレジスタを設け、上記シフトレジスタのシフト動作に対応し、上記識別要素列を初段回路から順に上記第１スイッチを順次オン状態に、第２スイッチは第１スイッチと相補的にオフ状態にして上記第３インバータ回路を含む上記増幅回路の出力信号により上記識別要素列の各第１インバータ回路に対応した複数の識別情報を得て識別番号を生成する識別番号回路をソフトＩＰ技術を用いて回路設計及び回路レイアウトが行うようにすることにより、半導体集積回路装置の製造コストの低減が可能になるという効果が得られる。
以上本発明者よりなされた発明を実施例に基づき具体的に説明したが、本願発明は前記実施例に限定されるものではなく、その要旨を逸脱しない範囲で種々変更可能であることはいうまでもない。例えば、半導体集積回路装置の製造工程の過程で形成される同一の形態からなる複数の識別要素は、電気的に信号を読み出すものでは半導体集積回路装置に同じ抵抗値になるような抵抗素子や同じ容量値になるようなキャパシタを複数個成形し、その抵抗値や容量値のプロセスバラツキを電流又は電圧の形態で取り出して、識別番号として利用するものであってもよい。
また、半導体集積回路装置のリードの幅あるいはピッチ幅の他に、半導体パッケージ等の表面に同じ長さ又は幅にされた複数の直線を印刷又は刻印し、その幅又はピッチの幅のバラツキを利用するもの等種々の実施形態をとることができる。
上記に例示の抵抗素子は、実施例のＣＭＯＳ構成のような比較的複雑な製造プロセスを要さないでも実施できる。抵抗素子としては、半導体集積回路技術によって構成されるポリシリコン抵抗や、単結晶シリコンに導電型決定不純物を周知のイオンインプランテーション法のような方法によって導入することによって構成するいわゆる拡散抵抗のような半導体抵抗や、金属配線層と同質の金属層からなる金属抵抗を検討することができる。それら抵抗の中では、拡散抵抗は、適切な抵抗値に設定することが容易である点、抵抗値の経時変化が比較的小さい点から、特性バラツキに応じた特定情報を得るために好適である。
抵抗バラツキに対応する特定情報は、例えば、所定のバイアス電流をその時々に対比すべき２つの抵抗素子に流し、その時に２つの抵抗に発生する電圧差を判別して行くような抵抗−電圧変換及び比較判定の技術によって形成することや、複数の抵抗素子によって抵抗ブリッジを構成し、その抵抗ブリッジの出力を判別する技術によって形成することが可能である。抵抗素子に対応する特性情報は、また、上のような技術以外に、抵抗素子を抵抗−電流変換素子として利用し、変換された電流を比較判定する技術によって形成することも可能である。更には、抵抗素子を発振回路の発振周波数決定素子や遅延回路の遅延時間決定素子の一部とすることによって、抵抗素子の特性バラツキを周波数情報や遅延時間情報として利用することも可能である。
抵抗素子を、インバータを構成する信号入力ＭＯＳＦＥＴに対する負荷素子とするような場合には、特性バラツキに応ずる情報は、抵抗素子の特性バラツキと信号入力ＭＯＳＦＥＴの特性バラツキとの両方を反映したものとなる。
抵抗バラツキに対応する特定情報は、必ずしも半導体集積回路装置内のみで形成する必要は無い。必要ならば、半導体集積回路装置を、適宜に特定情報形成モードに移行可能な構成にしておき、そのモードの元で、半導体集積回路装置内の複数の抵抗素子を、半導体集積回路装置に設定されている信号入出力端子のような既存の外部端子にスイッチ的に切換え結合に結合させることもできる。この場合には、抵抗素子の特性バラツキに対応する特定情報は、かかる外部端子に結合する半導体集積回路装置外の回路装置によって形成される。この場合には半導体集積回路装置内の回路素子数の増大を抑制することが出来、また半導体集積回路装置の既存の端子の利用によって、その外部端子数の抑制を図ることもできる。
複数の同じ構成の回路相互、あるいはＭＯＳＦＥＴのような回路素子のリーク電流も特性バラツキを恒久的に維持するものとして経験的に把握される。リーク電流レベルは、抵抗素子の特性バラツキと同様に、電流電圧変換と電圧比較によって検出可能である。リーク電流を形成するものは、上のように互いに同じ構成の回路であっても良いし、ゲート・ソース間が接続されたようなＭＯＳＦＥＴであっても良い。
特定情報のためのリーク電流源の好適なものとしては、半導体集積回路装置の信号出力外部端子もしくは信号入出力外部端子につながる信号出力バッファ回路を掲げることができる。かかる種の信号出力バッファは、それを構成するＭＯＳＦＥＴのような回路素子が比較的大きいサイズとされ、比較的大きいリーク電流を形成することが少なくなく、その測定が比較的容易であるからであり、また既存の外部端子をそのまま利用できるからである。
半導体集積回路装置の外部信号入力端子につながる半導体集積回路装置内の入力保護ダイオードのような素子の耐圧特性も、ミクロ的なバラツキに対応する前述のような特定情報の源とすることができる。半導体集積回路装置の複数の外部端子が、電子システムにおける比較的少ないビット数のバスラインを構成する場合であっても、前述の実施定のような総当り比較の手法によって、著しく多数のものに対して適切に識別可能な情報を形成することが可能である。
半導体集積回路装置の外部端子に結合される半導体集積回路装置内のＭＯＳトランジスタのドレイン接合容量のような容量は、ミクロ的なバラツキを持つ。よってそれもまたバラツキに対応する前述のような特定情報の源とすることができる。
ダイナミック型メモリにおける情報保持時間もミクロ的なバラツキを示す。この場合、ダイナミック型メモリに、特別の構成を付加しないでも、すなわち、固有の識別情報形成のための構成を設定しなくても、複数のメモリアドレスの内の特定の複数のメモリアドレスにおける複数のメモリセルの情報保持時間を計測し、その計測結果に基づいて特定情報とすることが可能である。
マルチチップモジュールのように共通基板に、複数の半導体チップが設けられる場合、個々の半導体チップに固有の識別回路を設定しておき、個々の半導体チップからの固有の識別情報を共通の基板を介して取り出せるようにすることも可能である。個々の半導体チップの固有の識別情報を読み出すために共通基板に必要となる端子の数に制約が有るときには、それぞれの半導体チップにチップ選択制御回路とともに固有の識別情報のための並列−直列変換回路を設定しても良い。この時には、各半導体チップにおける固有の識別情報は、そのチップの選択状態において、並列−直列変換回路によって直列化された上で、各半導体チップから出力され、共通基板を介して読み出される。第３３図のような意味でのプログラム専用チップが設けられる場合には、かかるプログラム専用チップは、共通基板上の異なった種類の複数の半導体チップに対応可能なように構成されても良い。
産業上の利用可能性
この発明は、半導体集積回路装置又は半導体チップに固有の識別情報を割り当てて、個々の半導体集積回路装置又は半導体チップの識別を行うようにした半導体集積回路装置又は半導体チップの識別方法と半導体集積回路装置の製造方法、半導体集積回路装置及び半導体チップに広く利用することができる。
【図面の簡単な説明】
第１図は、この発明に係る識別番号発生回路の一実施例を示す基本的回路図であり、
第２図は、この発明に係る識別番号発生回路の他の一実施例を示す基本的回路図であり、
第３図は、この発明に係る識別番号発生回路の他の一実施例を示す基本的回路図であり、
第４図は、前記第３図の識別番号発生回路の動作の説明図であり、
第５図は、この発明に係る識別番号発生回路の他の一実施例を示す基本的回路図であり、
第６図は、前記第５図の実施例回路を説明するための等価回路図であり、
第７図は、前記第５図の実施例に対応した具体的一実施例を示す回路図であり、
第８図は、前記第７図の実施例回路の動作を説明するためのタイミングチャート図であり、
第９図は、前記第７図の実施例回路の動作の説明図であり、
第１０図は この発明に係る識別番号発生回路の核になるＣＭＯＳインバータ回路とスイッチＭＯＳＦＥＴからなる単位回路の一実施例を示す変形例であり、
第１１図は、この発明に係る識別番号発生回路の核になるＣＭＯＳインバータ回路とスイッチＭＯＳＦＥＴからなる単位回路の他の一実施例を示す変形例であり、
第１２図は、この発明に係る識別番号発生回路の核になるＣＭＯＳインバータ回路とスイッチＭＯＳＦＥＴからなる単位回路の他の一実施例を示す変形例であり、
第１３図は、この発明に係る識別番号発生回路の核になるＣＭＯＳインバータ回路とスイッチＭＯＳＦＥＴからなる単位回路の他の一実施例を示す変形例であり、
第１４図は、この発明に係る識別番号発生回路の核になるＣＭＯＳインバータ回路とスイッチＭＯＳＦＥＴからなる単位回路の他の一実施例を示す変形例であり、
第１５図は、この発明に係る識別番号発生回路の核になるＣＭＯＳインバータ回路とスイッチＭＯＳＦＥＴからなる単位回路の他の一実施例を示す変形例であり、
第１６図は、この発明に係る識別番号発生回路に用いられるＣＭＯＳインバータ回路の一実施例を示す回路図であり、
第１７図は、この発明に係る識別番号発生回路の他の一実施例を示す回路図であり、
第１８図は、前記第１７図に示した実施例回路の動作を説明するための波形図であり、
第１９図は、この発明に係る識別番号発生回路の他の一実施例を示すブロック図であり、
第２０図は、この発明に係る識別番号発生回路の他の一実施例を示す回路図であり、
第２１図は、この発明に係る半導体集積回路装置の一実施例を示す概略ブロック図であり、
第２２図は、この発明に係る半導体集積回路装置の一実施例を示す素子レイアウト図であり、
第２３図は、前記第２２図に対応した等価回路図であり、
第２４図は、この発明をダイナミック型ＲＡＭに適用した場合の一実施例を示すブロック図であり、
第２５図は、この発明に係る識別番号発生回路を用いた半導体集積回路装置の一実施例を示す概略構成図であり、
第２６図は、この発明に係る識別番号の識別アルゴリズムを説明する説明図であり、
第２７図は、この発明に係る識別番号の識別アルゴリズムを説明する説明図であり、
第２８図は、この発明に係る半導体集積回路装置の識別システムにおける照合アルゴリズムの登録方法の一実施例を示す構成図であり、
第２９図は、この発明に係る半導体集積回路装置の識別システムにおける照合アルゴリズムの照合方法の一実施例を示す構成図であり、
第３０図は、前記第２９図の比較方法の一例を示す説明図であり、
第３１図は、ＣＭＯＳインバータ回路の論理しきい値の順位を用いた場合の比較方法の一例を示す説明図であり、
第３２図は、ＣＭＯＳインバータ回路の論理しきい値の順位を用いた場合の比較方法の一例を示す説明図であり、
第３３図は、この発明が適用される半導体集積回路装置の一実施例を示す構成図であり、
第３４図は、この発明が適用されるマルチチップモジュールの一実施例を示すブロック図であり、
第３５図は、前記図３４のプログラム専用チップの一実施例を示すブロック図であり、
第３６図は、本願に係る識別番号発生回路を搭載した半導体集積回路装置の一実施例の製造工程を説明するための構成図であり、
第３７図は、本願に係る識別番号発生回路を搭載した半導体集積回路装置を回路実装ボードに組み立てる場合の一実施例の製造工程を説明するための構成図であり、
第３８図は、本願に係る識別番号発生回路を搭載した半導体集積回路装置の他の一実施例の製造工程を説明するための構成図であり、
第３９図は、この発明に係る識別番号発生回路が設けられる特定用途向けＬＳＩの一例を示すブロック図であり、
第４０図は、この発明に係るＣＭＯＳインバータの論理しきい値のバラツキを乱数発生器に応用した実施例を示す回路図であり、
第４１図は、企業間の電子部品調達市場における不正行為や様々なトラブルを軽減することを目的とした、本願発明に係るチップ識別番号発生回路の利用例を説明するための構成図であり、
第４２図は、この発明に係る半導体集積回路装置の他の一実施例を示す模試的平面図であり、
第４３図は、この発明に係る識別番号発生回路の他の一実施例を示す基本的回路図であり、
第４４図は、この発明に係る識別番号発生回路の他の一実施例を示す回路図であり、
第４５図は、この発明に係る識別番号発生回路の一実施例を示す具体的回路図であり、
第４６図は、この発明に係る識別番号発生回路の更に他の一実施例を示す具体的回路図であり、
第４７図は、前記第４６図の実施例回路の動作を説明するためのタイミング図であり、
第４８図は、前記図４６の実施例に用いられる単位回路の他の一実施例を示す回路図であり、
第４９図は、この発明に係る識別番号発生回路の更に他の一実施例を示す回路図であり、
第５０図は、この発明に係る識別番号発生回路の更に他の一実施例を示す回路図であり、
第５１図は、この発明が適用される半導体集積回路装置又は半導体チップの一実施例を示す回路レイアウト図であり、
第５２図は、上記Ｉ／Ｏセルの標準的な一実施例を示すブロック図であり、
第５３図は、この発明に係る半導体集積回路装置又は半導体チップに設けられるＩ／Ｏセルの一実施例を示す回路レイアウト図であり、
第５４図は、この発明に係る半導体集積回路装置又は半導体チップに設けられる出力バッファ回路の一実施例を示す回路図であり、
第５５図は、この発明に係る半導体集積回路装置又は半導体チップに設けられる出力バッファ回路の他の一実施例を示す回路図であり、
第５６図は、この発明に係る半導体集積回路装置の一実施例を示す概略構成図であり、
第５７図は、この発明に係る半導体集積回路装置の基本的なＪＴＡＧセルの一実施例を示すブロック図であり、
第５８図は、この発明に係る半導体集積回路装置のバウンダリスキャンレジスタのシフト動作を利用した識別番号のシリアル出力動作の一実施例を説明するための構成図であり、
第５９図は、この発明に係る半導体集積回路装置のバウンダリスキャンレジスタのシフト動作を利用した識別番号のシリアル出力動作の他の一実施例を説明するための構成図であり、
第６０図は、この発明に係る半導体集積回路装置のバウンダリスキャンレジスタのシフト動作を利用した識別番号のシリアル出力動作の他の一実施例を説明するための構成図であり、
第６１図は、この発明に係る半導体集積回路装置のバウンダリスキャンレジスタのシフト動作を利用した識別番号のシリアル出力動作の他の一実施例を説明するための構成図であり、
第６２図は、この発明に係る識別番号発生回路の更に他の一実施例を示す回路図であり、
第６３図は、この発明に係る識別番号の説明図であり、
第６４図は、この発明に係る識別番号の説明図であり、
第６５図は、この発明に係る識別番号発生回路で生成された識別番号の高速識別番号照合（検索）アルゴリズムの一実施例を説明するためのフローチャート図であり、
第６６図は、第６５図の実施例に対応した構成図であり、
第６７図は、この発明に係る識別番号発生回路を組み込んだ半導体チップの回路設計方法の一実施例を示すフローチャート図であり、
第６８図は、この発明に係る識別番号発生回路を内蔵したＬＳＩ設計方法の一実施例を示すフローチャート図であり、
第６９図は、この発明に係る識別番号発生回路内蔵の半導体チップを用いた半導体集積回路装置の製造方法の一実施例のフローチャート図が示されている。
第７０図は、この発明に係る識別番号発生回路を搭載した半導体チップを用いた半導体集積回路装置の組み立て工程の一実施例を示すフローチャート図であり、
第７１図は、この発明に係る識別番号発生回路のビット数を減少させる方法の一実施例を示す構成図であり、
第７２図は、この発明に係る識別番号発生回路のビット数を減少させる方法の一実施例を示す構成図であり、
第７３図は、この発明に係る半導体集積回路装置に搭載された識別番号発生回路を利用した検査方法を説明するための構成図であり、
第７４図は、この発明に係る半導体集積回路装置に搭載された識別番号発生回路を利用した検査方法を説明するための構成図であり、
第７５図は、この発明に係る半導体集積回路装置に搭載された識別番号発生回路を利用し各検査工程で半導体チップ毎の特性データの相関を管理する方法を説明するための構成図であり、
第７６図は、この発明に係る半導体集積回路装置に搭載された識別番号発生回路を利用し前工程でウェハを自動で管理する方法を説明するための構成図であり、
第７７図は、この発明に係る半導体集積回路装置に搭載された識別番号発生回路の識別番号の格納・検索方法を説明するための構成図であり、
第７８図は、この発明に係る半導体集積回路装置に搭載された識別番号発生回路の識別番号の格納・検索方法の他の例を説明するための構成図であり、
第７９図は、この発明に係る識別番号発生回路を利用した半導体集積回路装置の救済方法の一実施例を示す構成図であり、
第８０図は、この発明に係る識別番号発生回路を搭載した半導体集積回路装置の一実施例を示すレイアウト図であり、
第８１図は，第８０図のレイアウト図の部分拡大レイアウト図であり、
第８２図は、この発明に係る識別番号発生回路を搭載した半導体集積回路装置の他の一実施例を示すレイアウト図であり、
第８３図は、第８１図のレイアウトに対応する回路図であり、
第８４図は、この発明に係る識別番号発生回路を搭載した半導体集積回路装置の更に他の一実施例を示す構成図であり、
第８５図は、第８４図の実施例を構成する半導体集積回路装置の部分平面パターン図であり、
第８６図は、第８４図の実施例を構成する半導体集積回路装置の他の部分平面パターン図であり、
第８７図は、この発明に係る識別番号発生回路を搭載した半導体集積回路装置の一実施例を示す回路図である。Technical field
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device identification method, a semiconductor integrated circuit device manufacturing method, a semiconductor integrated circuit device, and a semiconductor chip, and mainly assigns identification information unique to the semiconductor integrated circuit device or the semiconductor chip. The present invention relates to a technique for identifying an apparatus or a semiconductor chip.
Background art
If the semiconductor integrated circuit device is given identification information unique to the semiconductor integrated circuit device, various desired utilization actions can be performed based on the identification information. If unique identification information can be set at a level such as one by one in a semiconductor integrated circuit device, the description will be made after the present inventor has made clear under the use of the unique identification information. New manufacturing methods and product management technologies can be provided.
If a failure occurs at a stage such as the actual use stage of a semiconductor integrated circuit device, if it is possible to obtain unique identification information from the semiconductor integrated circuit device, it is easy to pursue the factor that caused the failure. To do. For example, for a semiconductor manufacturer, information such as a manufacturing time, a manufacturing line, a manufacturing lot, an inspection history, design information, and the like can be grasped based on identification information unique to the semiconductor integrated circuit device. As a result, it becomes easy to pursue the cause of the failure and countermeasures are also facilitated.
Marking such as ink printing or laser marking applied to a package constituting a semiconductor integrated circuit device can be regarded as a kind of identification information. This type of marking is mainly based on the product type name of the semiconductor integrated circuit device, but it may include a code display of the manufacturing time such as year and week along with the product type name. However, in this type of marking display, depending on the small amount of information that can be displayed, each semiconductor integrated circuit device is manufactured in large quantities as an industrial product or manufactured over a long period of time. It is difficult to set unique identification information at the level.
It is possible to assume that a programmable element such as a fuse element is set for a semiconductor chip constituting a semiconductor integrated circuit device and unique identification information is given to the programmable element. However, such a conceivable technique is that if the original semiconductor integrated circuit device does not require a program element, a new manufacturing process is required for the programmable element. The manufacturing process is complicated and the price increases. If the semiconductor integrated circuit device originally has programmable elements, there is no complication of a new manufacturing process. Even in that case, it is necessary to add or change a manufacturing process for writing unique recognition information to the programmable element.
In a known technique called a silicon signature, a product type name and unique information are written in a semiconductor integrated circuit device in a form that can be electrically read out. However, in this type of technology, it is necessary to add or change a manufacturing process for writing the information as described above.
As a result of investigation after the present invention has been made, the present inventor is considered to be related to the present invention described later, as disclosed in JP-A-6-196435, JP-A-10-055939, and JP-A-11-214274. No. 7, JP-A-7-335509, and JP-A-7-050233. All of the inventions described in these publications are recognized as requiring a special manufacturing process in order to write identification information unique to each chip. However, these publications do not allow a description of a method for identifying a semiconductor integrated circuit device that does not require the addition or change of a special manufacturing process as in the present invention described later.
Accordingly, an object of the present invention is to provide a semiconductor integrated circuit device or a semiconductor chip and a method for identifying the semiconductor integrated circuit device or semiconductor chip that can identify individual semiconductor integrated circuit devices or semiconductor chips with a simple configuration. Another object of the present invention is to provide a semiconductor integrated circuit device capable of identifying individual semiconductor integrated circuit devices or semiconductor chips with high reliability. Another object of the present invention is to provide a rational method for manufacturing a semiconductor integrated circuit device. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
Disclosure of the invention
The outline of a typical invention among the inventions disclosed in the present application will be briefly described as follows. That is, a plurality of identification elements having the same form are formed in the course of the manufacturing process of the semiconductor integrated circuit device, and the semiconductor integrated circuit device is based on the mutual magnitude relationship of physical quantities corresponding to the process variation of the plurality of identification elements Alternatively, it is used as unique identification information of the semiconductor chip.
BEST MODE FOR CARRYING OUT THE INVENTION
In order to describe the present invention in more detail, it will be described with reference to the accompanying drawings.
FIG. 1 shows a basic circuit diagram of an embodiment of an identification number generating circuit according to the present invention. The CMOS inverter circuits INV1 to INV4 are configured to have the same characteristics within a practically controllable range in designing and manufacturing a semiconductor integrated circuit device. A specific configuration suitable for the present invention for making a plurality of inverters have the same characteristics will be better understood by referring to FIG. 22 and the description thereof. Therefore, techniques for obtaining the same characteristics will be schematically described below.
It will be understood that in a CMOS inverter circuit, its characteristics are generally determined by the relative conductance between the P-channel MOSFET and the N-channel MOSFET constituting the CMOS inverter circuit. From this point of view, it can be understood that CMOS inverters having the same characteristics can be formed by MOSFETs having the same ratio W / L of the channel width W and the channel length L but having different sizes. However, the influence on the electrical characteristics due to the manufacturing variation of the semiconductor integrated circuit device is different for elements of different sizes.
In the embodiment, each of the plurality of CMOS inverters INV1 to INV4 is preferably configured such that the elements constituting each of them, that is, the P-channel MOSFETs and the N-channel MOSFETs have the same structure and the same size. It is configured with. Needless to say, these elements are manufactured according to the characteristics of the semiconductor integrated circuit device in which the same elements are manufactured together under the same process. As a result, the plurality of CMOS inverters INV1 to INV4 are equally affected by manufacturing variations such as variations in processing dimensions in manufacturing the semiconductor integrated circuit device, thickness variations in various layers, impurity concentration variations, and the like.
The output voltage of the CMOS inverter circuit whose input and output are short-circuited as shown in FIG. 1 reaches the logical threshold voltage. If all the CMOS inverter circuits have completely the same electrical characteristics, the potentials of the short-circuit nodes of the four inverter circuits INV1 to INV4 are equal. However, this is an ideal state, and in an actual semiconductor element, there is a slight difference in characteristics, so that a difference occurs in the input / output short-circuit node potential, that is, the logic threshold voltage of each inverter circuit INV1 to INV4.
As a factor of variation in the logic threshold value of the CMOS inverter circuit, it may be considered that variation in MOS transistor characteristics is dominant. The causes of variations in MOS transistor characteristics include the gate width of the MOS transistor, the gate insulating film thickness, the conductivity determining impurity concentration and its distribution, and the like. These variations can be divided into macro parts and micro parts. The macro portion includes variations in gate width between a plurality of wafers in the same lot.
In the invention of the present application, a variation in a micro part is mainly used, and a variation between elements arranged at relatively close positions is used. This is because such microscopic variations are observed to occur randomly between elements that are relatively close to each other.
That is, the variation in the logic threshold value of the inverter circuits INV1 to INV4 in FIG. 1 is considered to be random. This variation in the logical threshold value is the basis of a solution means of “extracting variation in characteristic characteristics of a semiconductor element as unique identification information”, which is a problem to be solved by the present application. When a CMOS inverter circuit is used, the variation in the logic threshold can be regarded as the variation of the N-channel MOS transistor plus the variation of the P-channel MOS transistor, and the variation range is It is possible to effectively generate an identification number or identification information.
In the embodiment shown in FIG. 1, the order of the magnitudes of the logic threshold values of the four inverter circuits INV1 to INV4 is determined. That is, the voltage (corresponding to the logic threshold value) of the shorted input / output nodes of each of the CMOS inverter circuits INV1 to INV4 is selected by the switch and sequentially input to the analog / digital converter ADC, and the measurement is quantized. A value (digital signal) is stored in a register, and the magnitude is compared by a digital comparator or the like (not shown).
That is, the digitized logic threshold values of the four CMOS inverter circuits INV1 to INV4 stored in the register are compared by a comparator or the like, and are arranged in descending order. If a processor such as a CPU is mounted on the semiconductor integrated circuit device in which the identification number generation circuit is formed, it is possible to compare the size using software.
For example, digital values are stored corresponding to the numbers 1 to 4 assigned to the CMOS inverter circuits INV1 to INV4, and the rank is determined by, for example, 1-3-2-4 by comparing the magnitudes thereof. Identification information is generated based on −3-2-4.
FIG. 2 shows a basic circuit diagram of another embodiment of the identification number generating circuit according to the present invention. In this embodiment, an analog comparator COMP is used. In this embodiment, voltages corresponding to the logical threshold values of the CMOS inverter circuits INV1 to INV4 one by one are sequentially supplied by the switch and compared with the reference potential of the comparator COMP. The reference voltage is changed stepwise, the detection level when the comparison result of the comparator changes from the low level to the high level is stored in the register, and the magnitudes of the logical threshold values of the CMOS inverter circuits INV1 to INV4 are compared. It is a method. That is, it is considered that the logic threshold value is the smallest when the output signal of the comparator changes from the low level to the high level at the lowest reference voltage.
In the identification number generating circuit shown in FIG. 1 or FIG. 2, circuits such as a high resolution analog / digital converter ADC, comparator COMP, stepped voltage generator, etc., that is, a circuit not included in a digital circuit or a logic circuit. Is necessary.
FIG. 3 shows a basic circuit diagram of another embodiment of the identification number generating circuit according to the present invention. In this embodiment, consideration is given to facilitating implementation in the form of using a kind of cell that substantially constitutes a digital circuit or a logic circuit. In this embodiment, two logical threshold values of four CMOS inverter circuits INV1 to INV4 are combined and compared by a comparator COMP. Comparison of logic threshold values of these CMOS inverter circuits INV1 to INV4 is a round-robin (league battle) format.
FIG. 4 is an explanatory diagram of the operation of the identification number generation circuit of FIG. 3 and shows an example of the brute force comparison result. In FIGS. 4A and 4B, the switches Y1 to Y4 and the switches X1 to X4 are turned on one by one, which is a battle table, which is connected to the non-inverting input terminal (+) of the comparator COMP. From the short-circuit node potential (that is, the logic threshold voltage) of the CMOS inverter circuit selected by the switch (Y), the CMOS inverter circuit selected by the switch (X) connected to the inverting input terminal (−) of the comparator COMP If the result of subtracting the short-circuit node potential is plus (high level), a “+” symbol is entered in the figure, and if it is minus (low level), a “−” symbol is entered. Since “*” is a self match (no match), it is invalid.
Looking at FIG. 4 (A), Y1 has three “+” s, that is, all wins. Next, Y2 is 2, Y3 is 1, Y4 is 0 (all losses). That is, the order of the magnitude of the logic threshold value (VLT) of the CMOS inverter circuit can be determined by the number “+”, and therefore, the order is VLT1 (logic threshold value of INV1) −VLT2-VLT3-VLT4.
FIG. 4B shows another example. Here, it is assumed that there is a clear difference in the logic threshold value of each CMOS inverter circuit. In other words, in an actual game or the like, the draw or the number of wins may be the same. The draw is indicated by (=). If there is such a draw (=), Y1 and Y2 are in the same rank, and Y3 and Y4 are also in the same rank, so that the above rank is not given. In this embodiment, 16 comparisons (games) are performed. However, since the minimum number of round-robin games by n teams is n (n-1) / 2 times, it is actually 6 times. Good.
In the embodiment shown in FIG. 3, the comparator is composed of one comparator and two selection circuits, and the configuration is relatively simple compared to the embodiment shown in FIGS. Therefore, it may be difficult to form a semiconductor integrated circuit device such as a gate array or a logic ASIC.
FIG. 5 shows a basic circuit diagram of another embodiment of the identification number generating circuit according to the present invention. In this embodiment, a basic circuit constituted by only a CMOS logic circuit and a MOSFET switch is used without using any analog circuit as in the embodiments of FIGS.
The CMOS inverter circuits INV1 to 1NV4 shown in FIG. Each of the CMOS inverter circuits INV1 to INV4 is provided with four switches. Switches A (A1 to A4) and B (B1 to B4) open and close simultaneously in conjunction with each other. The switches C (C1 to C4) and D (D1 to D4) are also opened and closed in conjunction with each other.
FIG. 6 shows an equivalent circuit corresponding to the open / close state of the switch for explaining the embodiment circuit of FIG. In FIG. 5, the switches A1 and B1, C2, and D2 are closed (ON state). The input / output of the CMOS inverter circuit INV1 is short-circuited by the switch B1, and the short-circuit node voltage is supplied to the common node P by the switch A1. Further, the potential of the common node P is applied to the input of the CMOS inverter circuit INV2 by the switch C2, and the output of the CMOS inverter circuit INV2 is supplied to the common node PP by the switch D2. The amplifier circuits AMP1 and AMP2 are composed of CMOS inverter circuits having the same shape as INV1 to INV4.
In the equivalent circuit of FIG. 6, the input and output of the CMOS inverter circuit INV1 are short-circuited by the on switch B1, and the potential of the common node P becomes the logic threshold value of the CMOS inverter circuit INV1 by the on switch A1. The common node P is connected to the input of the CMOS inverter circuit INV2 by the on switch C2. If the CMOS inverter circuits INV1 and 1NV2 have completely the same electrical characteristics, the potential of the common node PP to which the output of the CMOS inverter circuit INV2 is connected is equal to that of the common node P. Similarly, the output node potentials of the amplifier circuits AMP1 and AMP2 are also equal. That is, the input and output of the four inverters are all equal to the logical threshold voltage of the CMOS inverter circuit INV1. However, this is an ideal state, and in an actual semiconductor element, there is a slight difference in characteristics, so that a difference occurs in the potential of each node.
For example, the relationship between the logic threshold value VLT1 of the CMOS inverter circuit INV1 and the logic threshold value VLT2 of the CMOS inverter circuit INV2 is:
When VLT1 <VLT2, the potential of the common node PP> the potential of the common node P. Conversely, when VLT1> VLT2, the potential of the common node PP <the potential of the common node P.
The CMOS inverter circuit is also a high-gain inverting amplifier. The gain changes at the operating point, and the maximum gain is obtained when the input potential is near the logic threshold value of the CMOS inverter circuit. In general, the inversion gain near the logic threshold value of a CMOS inverter circuit is several tens to one hundred times.
Therefore, the difference between the logic threshold values of the CMOS inverter circuits INV1 and INV2 in FIG. 6 is amplified by the subsequent CMOS inverter circuit INV2. That is, the logical threshold voltage generated in the preceding CMOS inverter circuit is compared in magnitude and amplified with the logical threshold voltage of the subsequent CMOS inverter circuit as the reference voltage.
Further, it is also amplified by the amplifier circuits AMP2 and AMP3, and the difference between the logic threshold values of the CMOS inverter circuits INV1 and INV2 is amplified several tens of thousands of times by the CMOS inverter circuit INV2 and the amplifier circuits AMP1 and AMP2. Finally, at the node Q, a CMOS power supply voltage amplitude signal can be obtained. That is, the magnitude comparison result (positive / negative sign) of the logical threshold values of the two CMOS inverter circuits INV1 and INV2 can be detected by the CMOS amplitude signal.
By changing the combination of opening and closing of the switch as shown in FIG. 6, all CMOS inverter circuits INV1 to INV4 can be easily compared, and the result as shown in FIG. 4 (A) can be obtained. it can. Thus, this embodiment circuit is suitable for comparison of the logic threshold value of the CMOS inverter circuit.
In other words, by using a combination of a CMOS inverter circuit and a switch, one CMOS inverter circuit is used as a generation source of a logical threshold voltage, or a determination circuit that determines a logical threshold voltage generated by another CMOS inverter circuit. Since it is used, no special comparator is required, and the circuit configuration can be greatly simplified. In addition, since all of the MOSFETs including the CMOS inverter circuit are configured by switching operation, there is no particular difficulty when mounted on a semiconductor integrated circuit device such as a gate array or a logic ASIC.
FIG. 7 shows a circuit diagram of a specific embodiment corresponding to the embodiment of FIG. The CMOS inverter circuits INV1 to INV4 and the amplifier circuits AMP1 and AMP2 are congruent CMOS inverter circuits. In this embodiment, an N-channel MOSFET is used as the switch. A binary counter (Decoder) and a decoder (Decoder) for generating control signals Y1 to Y4 and X1 to X4 of these switches are provided.
An example of the CMOS inverter circuit INV1 is as follows. A control signal X1 is supplied to the gates of the switch MOSFET that short-circuits the input and output of the CMOS inverter circuit INV1 and the switch MOSFET that connects the common node P and the input. A control signal Y1 is supplied to the gates of the switch MOSFET that connects the input of the CMOS inverter circuit INV1 and the common node P and the switch MOSFET that connects the output and the common node PP. Similarly, in the CMOS inverter circuits INV2 to INV4, control signals X2 to X4 and control signals Y2 to Y4 are supplied to the gates of the corresponding switch MOSFETs.
The binary counter is a 4-bit binary counter that is reset by the reset signal RES and counts the number of pulses by supplying the clock signal CLK. The control signals Y1 to Y4 are output by the decoder in response to the count output of the lower 2 bits. And the control signals X1 to X4 are formed by the decoder corresponding to the count output of the upper 2 bits.
FIG. 8 is a timing chart for explaining the operation of the embodiment circuit of FIG. The reset signal RES is for initializing the binary counter. Here, during reset (RES = “H”) and immediately after reset, the outputs of the binary counters are all “1”. Therefore, X4 and Y4 are active in the decoder output. The binary counter advances (+1) at the rising edge of the first clock CLK after the reset is released, and all become “0”. Therefore, as for the output of the decoder, the control signals X1 and Y1 are activated.
Thereafter, the output of the binary counter repeatedly advances (+1) at the rising timing of the clock signal CLK, and the decoder advances as shown in FIG. Of course, it goes without saying that the output of the binary counter returns to “0” again at the 17th rise of the clock signal CLK. However, in this embodiment, since necessary information can be extracted by 16 operations, the 17th and subsequent clock operations are not necessary.
After reset release, the count operation of the binary counter proceeds every time the clock signal CLK rises, and the information b1 to b16 appearing at the output node OUT each time is as shown in FIG. As described above, the difference in logic threshold value of the CMOS inverter circuit is amplified by the amplifier circuits AMP1 and AMP2, and when VLTQy−VLTQx> 0, the output terminal OUT outputs “H” (high level). When VLTQy−VLTQx <0, the output terminal OUT outputs “L” (low level).
Thus, the winning / losing result in the round-robin battle of the four CMOS inverter circuits INV1 to INV4 can be used as the identification signals b1 to b16 as they are. Of the four rounds of brute force b1 to b16 in the four CMOS inverter circuits INV1 to INV4, a self-matching one may be set in advance to a specific level of high level or low level as described later. When numbers 1 to 4 assigned to the four CMOS inverter circuits are replaced with 2-bit information and arranged in descending order, for example, it is arranged as 1-2-3-4, so that 2 × 4 = Identification information compressed to ½, such as 8 bits, can be obtained.
FIG. 10 shows a modification of an embodiment of a unit circuit composed of a CMOS inverter circuit and a switch MOSFET which are the core of the identification number generating circuit according to the present invention. In the circuit of FIG. 10, each of the four switch MOSFETs (A to D) of FIG. 5 is a CMOS pair type. That is, an N-channel MOSFET and a P-channel MOSFET are connected in parallel, and complementary signals X and X / are supplied to the gates.
When a CMOS switch is used in this way, the voltage signal transmitted through the switch MOSFET is not limited by the threshold voltage, so the power supply voltage or the ground potential of the circuit and the logic threshold voltage It is effective for a circuit that operates at a low voltage such that the voltage difference, or the difference voltage between the power supply voltage or the ground potential of the circuit and the voltage to be output to the common node PP is smaller than the threshold voltage of the switch MOSFET. .
FIG. 11 shows a modification of another embodiment of the unit circuit composed of the CMOS inverter circuit and the switch MOSFET which are the core of the identification number generating circuit according to the present invention. In the circuit of FIG. 11, the position of the N-channel switch MOSFET that supplies the input / output short-circuit potential of the CMOS inverter circuit to the common node P is changed. That is, the common node P is connected to the output side of the CMOS inverter circuit whose input and output are short-circuited.
FIG. 12 shows a modification of another embodiment of the unit circuit consisting of a CMOS inverter circuit and a switch MOSFET which are the core of the identification number generating circuit according to the present invention. In the circuit of FIG. 12, two P-channel MOSFETs connected in series are provided between the input of the CMOS inverter circuit and the power supply voltage terminal. Selection signals X and Y are supplied to the gates of these P-channel MOSFETs. In this embodiment, when the CMOS inverter circuit is not selected, that is, when both the selection signals X and Y are not activated, the P-channel MOSFET is turned on and the input of the CMOS inverter circuit is set to a high level such as the power supply voltage. This is fixed to prevent a through current in the CMOS inverter circuit. In other words, if the input of the CMOS inverter circuit is set in a floating state, an intermediate potential may be generated and a large through current may flow between the N-channel MOSFET and the P-channel MOSFET of the CMOS inverter circuit. belongs to.
FIG. 13 shows a modification of another embodiment of the unit circuit composed of the CMOS inverter circuit and the switch MOSFET which are the core of the identification number generating circuit according to the present invention. In the circuit of FIG. 13, the switch MOSFET is changed from the N-channel type MOSFET to the P-channel type MOSFET as in the above embodiment, and the input of the CMOS inverter circuit is fixed to the low level by the N-channel type MOSFET when inactive. is there. In this case, the selection signals applied to the gates of the N-channel MOSFETs are inverted signals X / and Y /.
FIG. 14 shows a modification of another embodiment of the unit circuit composed of the CMOS inverter circuit and the switch MOSFET which are the core of the identification number generating circuit according to the present invention. In the circuit of FIG. 14, in order to avoid the common node PP being undefined at the time of the above-mentioned self-match, that is, the output becomes “H”, “L” or unstable. Two N-channel MOSFETs connected in series are provided between the input and the ground potential of the circuit, and the input of the CMOS inverter circuit is fixed at a low level.
Selection signals X and Y are supplied to the gates of these N-channel MOSFETs. As a result, the selection signals X and Y are at a high level during a self-match, and the ground potential of the circuit is supplied to the input. The short-circuit switch provided between the input and output of the CMOS inverter circuit is composed of a series circuit of an N-channel MOSFET that receives a selection signal X and a P-channel MOSFET that receives a selection signal Y. As a result, the input and the output are not short-circuited during the self-match, and a high level corresponding to the fixed low level supplied to the input can be output. In the non-selected state, the input is fixed at a high level such as the power supply voltage as in the embodiment of FIG.
FIG. 15 shows a modification of still another embodiment of the unit circuit composed of the CMOS inverter circuit and the switch MOSFET which is the core of the identification number generating circuit according to the present invention. In the circuit of FIG. 15, in order to avoid the common node PP being undefined at the time of the above-mentioned self-match, that is, the output becomes “H”, “L” or unstable. The input is fixed at a high level. In order to avoid a short circuit between the input and the output in the self-match as in the above, the shorting switch is composed of a series circuit of an N channel type MOSFET and a P channel type MOSFET as in the embodiment of FIG.
The purpose and effect of avoiding indefinite level of the common node PP will be described in detail later. The modifications shown in FIGS. 10 to 15 may be implemented in combination. For example, the N-channel type switch MOSFET of FIG. 14 may be replaced with a CMOS pair type.
The embodiment shown in FIGS. 14 and 15 can be used to embed fixed information in the self-competition (*) portion of FIG. Originally the self-competition part is indefinite, strictly speaking, it was the result of comparing the logic threshold values of each CMOS inverter circuit and the amplifier circuit AMP. Therefore, even if the information in that part is ignored or diverted, it can be identified. There is no loss of ability. By fixing the added N-channel type MOSFET connected in series to the ground potential or the power supply voltage as shown in FIGS. 14 and 15, the inputs of the CMOS inverter circuits INV1 to INV4 are biased to the low level or high level side, The output of the battle part can be set arbitrarily.
In recent years, a semiconductor integrated circuit device technology in which a bare chip is mounted on a substrate called a build-up substrate has been developed, and it is becoming impossible to specify a product and a shipping time from the appearance. Therefore, the necessity to insert such a fixed number for specifying the product and shipping time is increased. In other words, in a system on a chip (SOC), which will be described later, what is mounted on the base chip, what kind of individual chips are combined, and what kind of chip is reversed. The management of single items is becoming more and more important, such as whether to combine them, and the assignment of the fixed number is useful.
FIG. 16 is a circuit diagram showing one embodiment of a CMOS inverter circuit used in the identification number generating circuit according to the present invention. In a CMOS inverter circuit, generally, a P-channel MOSFET and an N-channel MOSFET are provided in series between a power supply voltage and a circuit ground potential, and gates are connected in common as inputs, and drains connected in common are connected. Can be configured as output. The CMOS inverter circuits INV1 to INV4 and the amplifier circuits AMP1 and AMP2 of the embodiment can be configured by the two MOSFETs as described above.
On the other hand, in this embodiment, a CMOS inverter circuit is configured using two P-channel MOSFETs and two N-channel MOSFETs. The two N-channel MOSFETs are connected in parallel between the output terminal and the ground potential point of the circuit, and the two P-channel MOSFETs are connected in series between the power supply voltage and the output terminal.
In this configuration, the conductance on the N-channel MOSFET side is large, and the conductance on the P-channel MOSFET side is small. That is, the current flowing through the N-channel MOSFET is set by the small conductance (large on-resistance value) of the P-channel MOSFET. Apparently, a constant current can be made to flow through the N-channel MOSFET, so that the logic threshold voltage of the CMOS inverter circuit is controlled by the threshold voltages of the two N-channel MOSFETs. Become. Thereby, the logic threshold value of the CMOS inverter circuit can be made less susceptible to the influence of the power supply voltage fluctuation.
The configuration in which the P-channel type MOSFET is operated as a simple high resistance element and the threshold voltage of the N-channel type MOSFET dominantly affects the logic threshold is affected by the deterioration of element characteristics (NBTI) described later. There is also an advantage that it is difficult to receive.
As will be described later, when the identification number generating circuit is configured by a gate array, the element sizes of the N-channel MOSFET and the P-channel MOSFET are determined. It is possible to vary the element size ratio between the N-channel MOSFET and the P-channel MOSFET and set the logic threshold value accordingly.
FIG. 17 is a circuit diagram showing another embodiment of the identification number generating circuit according to the present invention. In this embodiment, a circuit for fixing a part of the identification number to an arbitrary number is shown in the function for generating a random identification number described so far. In the embodiment shown in FIG. 7, 24 types of identification numbers could be generated. The number of information bits is 16 bits including the self-match result. Briefly explaining the circuit of this embodiment, the output node (common node) P of the first stage CMOS inverter circuit shown in FIG. 6 is forcibly fixed to an arbitrary value. In this case, the order of the first stage and the second stage cannot be switched.
In this embodiment circuit, the output node corresponding to the CMOC inverter circuit INV1 from the embodiment circuit of FIG. 7 is fixed to "H" (= VDD) by the MOSFET Q11, and the output node corresponding to the CMOS inverter circuit INV2 is fixed by the MOSFET Q21. It is fixed to “L” (= VSS). Since the MOSFETs Q11 and Q21 forming the fixed levels “H” and “L” are not input to the common node P, the decode signals Y1 and Y2 are unnecessary. Therefore, the binary counter circuit is also composed of 3 bits, and the output signal of the decoder circuit is also formed as Y3 and Y4.
FIG. 18 is a waveform diagram for explaining the operation of the embodiment circuit shown in FIG. There are 4 choices in the first stage and 2 choices in the second stage, and a total of 8 outputs can be obtained. That is, the number of information bits is 8 bits. In this embodiment, “0”, “0”, “1”, and “1” are always output as the output signals b1 to b4. The remaining b5 to b8 are the result of variations in the logic threshold values of the CMOS inverter circuits Q3 and Q4. In this embodiment, only two types of fixed numbers and a maximum of two types of random identification numbers are generated.
In actual use, the fixed part and the random part can be combined in any size. The fixed part indicates a product code, and the random part can be applied to indicate a sample number. Further, several methods are conceivable as a method for inserting the fixed identification number into the information bit string. For example, there are a method of replacing the self-competition part described in FIG. 14 and FIG. 15 and a method of replacing one of the overlapping battles (comparison in which the first stage and the second stage are switched). When these circuits are actually realized, it becomes a problem not only a circuit that generates an identification number, but also which part bears the function in the entire registration and verification system. However, since the registration and verification functions in the entire system are likely to be realized mainly by computer software, advanced functions can be realized relatively easily.
FIG. 19 is a block diagram showing another embodiment of the identification number generating circuit according to the present invention. The logical threshold value judgment unit displayed substantially only in the block of FIG. 6 is operated by a relatively low and stabilized voltage V2 output from the power supply circuit shown in FIG. The
That is, a P-channel type MOSFET whose gate is steadily applied with the circuit ground potential operates as a load means, and operating current flows to four N-channel type MOSFETs connected in series acting as constant voltage elements. Is intended to flow. As a result, a constant voltage V1 corresponding to a constant voltage (threshold voltage) between the gate and source of the serial N-channel MOSFET is formed, and the constant voltage V1 is generated via the gate and source of the N-channel MOSFET. It is supplied as the operating voltage V2 of the threshold value determination unit. The voltage supplied to such a logic threshold voltage determination unit is made constant. As a result, the logic threshold values of the CMOS inverter circuits INV1 to INV4 and the like can reduce the influence of fluctuations in the power supply voltage VDD. As a result, a more stable logic threshold value determination operation can be expected.
In the present invention, it is not essential to make the operating voltage of the logic threshold value determination unit constant. That is, in the present invention, the absolute value of the logic threshold voltage of the plurality of CMOS inverter circuits is not used, but the identification number is set corresponding to the difference between the logic threshold voltages of the individual CMOS inverter circuits. Is. This is because the fluctuation of the power supply voltage affects the logic threshold voltage of each CMOS inverter circuit in the same manner, so that the magnitude relationship does not change significantly.
FIG. 19 (B) shows a specific circuit for preventing the MOSFET from changing with time. A MOS transistor may undesirably fluctuate due to electric field stress whose threshold voltage depends on electric field strength and temperature. In particular, a phenomenon called NBTI (Negative Bias Temperature Instability) is a phenomenon that appears remarkably in a P-channel MOSFET. As this defense measure, a method is often used in which the voltage applied to the gate of the PMOS is set to a high voltage during an unintended time. In this embodiment, the ground potential VSS of the circuit of the logic threshold value judgment unit is supplied by the N channel type MOSFET, and when the logic threshold value judgment operation is performed by the high level of the power supply control signal PON, the N channel type MOSFET is turned on. To supply the ground potential VSS of the circuit. At other times than the logical threshold determination operation, the power supply control signal PON is set to the low level to turn off the N-channel MOSFET and the P-channel MOSFET is turned on to supply the power supply voltage VDD to the ground potential side of the circuit. Supply. As will be described below, the gate voltage is fixed to the gate of the P-channel MOSFET so as to supply the power supply voltage VDD. As a result, in the P-channel type MOSFET, the gate, drain and source, and the substrate (channel) all have the same potential equal to the power supply voltage VDD, and the fluctuation of the logic threshold due to the aging of the MOSFET is suppressed as much as possible.
FIG. 20 is a circuit diagram showing another embodiment of the identification number generating circuit according to the present invention. In this embodiment circuit, a series circuit of P-channel MOSFETs is provided at the inputs of the CMOS inverter circuits INV1 to INV4 so as to suppress the fluctuation of the logic threshold value due to the aging of the MOSFET as much as possible. At the time of reset when the signal RES / is set to the low level, the inputs of the CMOS inverter circuits INV1 to INV4 are fixed to the power supply voltage.
That is, all the output signals of the NAND gate circuit receiving the count outputs B0 to B3 of the binary counter circuit are set to the high level (logic 1) by the low level (logic 0) of the signal RES /. As a result, the output signals Y1 to Y4 and X1 to X4 of the NOR gate circuit constituting the decoder circuit all become low level (logic 0), and are provided between the inputs of the CMOS inverter circuits INV1 to INV4 and the power supply voltage VDD. The P-channel type MOSFET in series is turned on and fixed to the power supply voltage. As a result, the power supply voltage VDD is supplied to the gates of the P-channel MOSFETs constituting the CMOS inverter circuits INV1 to INV4.
Further, in this embodiment, the inputs of the amplifier circuits AMP1 and AMP2 are also fixed to the power supply voltage VDD by the P-channel MOSFET which is turned on by the low level of the signal RES /, and is connected to the gate of the P-channel MOSFET constituting the amplifier circuit. Supply the voltage and voltage.
Alternatively, all the selection signals Y1 to Y4 may be turned on to fix the common input node P to the power supply voltage. In any case, it is possible to control the gate voltage of the P-channel MOSFETs constituting the CMOS inverter circuits INV1 to INV4 and the amplifier circuits AMP1 and AMP2 or to shut off all the power sources of the identification number generation circuit. That's fine. However, in the method of cutting off all the power supplies, it is necessary to consider that the element region in which the MOSFET constituting the identification number generation circuit is formed is electrically separated from other circuits. That is, it is not desirable from the viewpoint of deterioration of the element characteristics that a constant voltage is constantly applied to the substrate gate (channel) of the MOSFET even when the power is shut off.
On the other hand, if attention is paid to such NBTI, normal reliability assurance becomes a problem. In other words, by applying the means for avoiding the stress as described above, it becomes impossible to screen for process defects performed in the so-called burn-in process. There is no problem if the scale of this circuit is considered to be extremely small compared to the entire LSI, but an application that requires screening should be assumed. In this case, a mode for arbitrarily resetting or releasing the power supply in a burn-in process or the like is prepared.
Naturally, it is sufficiently considered that the identification number fluctuates due to the stress here. However, it is possible to collect the final identification number after the burn-in process and re-register it in the database, and the size of lots handled in the burn-in process is limited to several hundred to several thousand. The impact is small even with fluctuations.
FIG. 21 is a schematic block diagram showing one embodiment of a semiconductor integrated circuit device according to the present invention. This embodiment is directed to power control when the identification number generation circuit is mounted on a system LSI. This system LSI is an example using two different power sources, VDD1 and VDD2.
The identification number generation circuit receives power supply from VDD1 during operation. Here, the time of operation is the time during which an identification number read request is sent from the main body LSI circuit unit 1 and the identification number is sent out. In other states, power supply is cut off. A signal for controlling the supply of power is a power control signal and is input to the power control circuit. The power supply control circuit is composed of an N-channel MOSFET and a P-channel MOSFET with a power supply control signal connected to the gate. When the power control signal is at high level, the power supply of the identification number generation circuit is fixed at VSS, and the identification number output signal is fixed at low level. When the power control signal is at a low level, VDD1 is supplied to the identification number generation circuit. The circuits included in the identification number generation circuit section in the figure are, for example, the logic threshold value judgment circuit section, binary counter section and decoder section of the CMOS inverter circuit shown in FIG. Further, only the logic threshold value judgment circuit portion of the CMOS inverter circuit may be provided, and the binary counter portion and the decoder portion may be included in the main body LSI circuit portion 1.
FIG. 22 shows a layout diagram of elements of an embodiment suitable for the semiconductor integrated circuit device according to the present invention. The configuration shown in the figure is not particularly limited, but may be understood as a layout example suitable for a so-called master slice type semiconductor integrated circuit device. In the figure, for easy understanding, only a planar pattern of an active region constituting a MOS transistor is shown, and a wiring layer pattern such as a metal wiring layer is not shown. Even with such a planar pattern, the essence of the technology is due to the fact that the MOS transistor has a dominant influence on the circuit characteristics to be obtained and that the influence on the circuit characteristics to be obtained such as metal wiring is small. Will be better understood.
Although the basic device structure of the semiconductor integrated circuit device itself is not directly related to the present invention and will not be described in detail, it will be briefly described as follows.
That is, a semiconductor substrate made of N-type single crystal silicon is used, and an N-type well region and a P-type well region are formed on the surface of the semiconductor substrate by an impurity selective introduction technique. An opening for defining an active region is provided in a so-called field insulating film made of a silicon oxide film provided on the surface of the semiconductor substrate, and the heat of silicon is formed on the surface of the N-type well region and the P-type well region exposed in the opening. A gate insulating film is formed by an oxidation method or the like. A gate electrode layer made of a polycrystalline silicon layer is selected on the gate insulating film and the field insulating film. By introducing P-type impurities using the gate electrode layer and the field insulating film as substantial impurity introduction masks, P-type semiconductor regions constituting the source and drain regions of the P-channel MOS transistor are formed on the surface of the N-type well region. ing. Similarly, by introducing N-type impurities using the gate electrode layer and the field insulating film as substantial impurity introduction masks, N-type semiconductor regions constituting the source and drain regions of the N-channel MOS transistor are formed on the surface of the P-type well region. Is formed. With respect to such a basic device structure, a desired wiring layer is formed by a known wiring layer forming technique or insulating layer forming technique.
In FIG. 22, a relatively small substantially square pattern constitutes one active region. One unit region is composed of such a relatively small substantially square pattern and two elongated patterns parallel to each other, each of which means a gate electrode layer drawn so as to overlap therewith. For example, a relatively small rectangular pattern with symbols PP, B, and P arranged at the upper right end of the drawing and two elongated strips drawn so as to overlap with the symbols Y0 / and X0 / respectively. A unit area is configured by a pattern.
Accordingly, two MOS transistors are formed in one active region by two parallel gate electrode layers and source and drain semiconductor regions formed on the surface of the active region in a self-aligned manner with respect to the two gate electrode layers. Is formed.
In FIG. 22, a plurality of unit regions for N-channel MOS transistors and a plurality of unit regions for P-channel MOS transistors are arranged in a matrix as shown in the figure. In the four unit region columns (hereinafter referred to as first region columns) for the uppermost P-channel MOS transistor on the drawing, each unit region has the same planar dimension and the same extending direction. It is composed. The unit regions in the four unit region columns (hereinafter referred to as second region columns) for the N-channel MOS transistors located below the first column also have the same planar dimensions, the same extending direction, It is configured with The first region row and the second region row are for constituting an inverter as shown in FIG. 20 and a switch MOS transistor coupled thereto.
Similarly, the third region column and the fourth region column are for configuring the X decoder unit, and the fifth region column and the sixth region column are for configuring the Y decoder unit. .
The whole of the first region column to the sixth region column having four unit regions in FIG. 22 is also set as a basic repeating unit. That is, according to the circuit scale to be obtained, a plurality of basic repeating units in FIG. 22 are arranged adjacent to each other in the horizontal direction in FIG. According to this configuration, the first region column in different basic repeating units constitutes one column (also referred to as an entire region column) as a whole in the layout. Similarly, each column after the second column also has the entire region column. Constitute.
The layout of FIG. 22 and the repeated layout as described above are suitable examples for forming identification information of the present invention.
Instead of the layout of FIG. 22, a plurality of unit regions that should form the same region row are arranged with a relatively large distance from each other because they are arranged so as to sandwich element regions constituting other circuits. In such cases, the following difficulties arise. That is, a plurality of unit regions are strongly affected by macro variation of pattern dimensions or macro variation of pattern distortion based on variations in manufacturing conditions of semiconductor integrated circuit devices, and relatively large patterns. A difference in shape will occur.
The mechanical stress imparted to the semiconductor chip by mounting the semiconductor chip or the like is likely to differ depending on the part of the semiconductor chip, so that the plurality of unit regions may be relatively different from each other. Have sex. The increase in operating temperature caused by the supply current flowing through the circuit is not uniform among the plurality of unit regions. The thickness of the gate insulating film and the subtle concentration change of the introduced impurity also have a risk of becoming relatively large when the plurality of unit regions are relatively separated from each other.
In the case of the layout shown in FIG. 22, the plurality of unit areas in the same area row are arranged relatively close to each other and have the same size and the same direction. Less susceptible to typical pattern dimensions, pattern distortion, mechanical stress, operating temperature, film thickness, and impurity concentration.
The so-called phase shift mask technique is understood as an effective technique for miniaturizing circuit elements, wirings, and the like constituting a semiconductor integrated circuit device to a so-called submicron level. In such a phase shift mask technique, the pattern is asymmetrical or distorted due to a slight change in the phase difference of light when the photosensitive material layer used as a mask is exposed. May bring The layout as shown in FIG. 22 can sufficiently reduce the deviation in electrical characteristics between the plurality of unit regions even if there is such a pattern distortion.
In addition to the difference in configuration from the above viewpoint, the influence of the carrier mobility on the crystal orientation in the semiconductor cannot be neglected for the present invention using the microscopic characteristics as described above. In the case of the layout of FIG. 22, all of the plurality of gate electrode layers forming the first region column have the same direction and the same pattern, and similarly, all of the plurality of gate electrode layers forming the second region column also Since they are in the same direction and in the same pattern, the MOS transistors belonging to the first region column and the MOS transistors belonging to the second region column have the characteristic difference based on the crystal orientation described above. Absent.
As described above, in the layout and the manufacturing of the semiconductor integrated circuit device, the macro variation or characteristic deviation as described above is considered to be remarkably reduced in the layout of FIG. It will be understood that consideration has been given so that micro variation can be appropriately utilized.
When there is a need to further sufficiently eliminate the bias in the electrical characteristics of the MOS transistor obtained by the configuration of FIG. 22, the end effect of the entire arrangement constituted by a plurality of basic repeating units of FIG. 22 is eliminated. A dummy area can be set. The dummy area is configured to make the end of the entire array equivalent to the inside of the entire array in terms of layout, and has at least a plurality of unit areas at the ends of the basic repeating unit. Can do.
If this type of dummy region is not set, the processing shape of the end may be affected by the configuration of the outside of the end in the overall arrangement, and the semiconductor substrate and its In some cases, the end portion and other portions may be different in how a force that may affect element characteristics such as stress caused between the surface insulating film and the other portions is applied. They are also factors that cause bias in electrical characteristics. In the case of setting the dummy area as described above, the above-described factors that cause the deviation of the electrical characteristics are sufficiently eliminated.
The dummy region can be a region that is not used as a circuit, or can be configured to configure another circuit that does not require attention to bias in electrical characteristics.
FIG. 23 shows an equivalent circuit diagram corresponding to FIG. 22 and 23, the terminal names and the element numbers correspond to each other. However, the decoder section is not particularly limited because it is not particularly limited except that it is arranged below (or above) the CMOS logic threshold value detection circuit. When the basic repeating units as shown in FIG. 22 are arranged in parallel, the CMOS inverter circuit formed by the elements can match the shape and surrounding environment with the same adjacent circuit. In the layout methods other than the gate array method, the basic repeating unit may be laid out so that the CMOS inverter circuit portions are congruent similarly to this. When a circuit is configured using such a gate array, the variation in threshold voltage of the N-channel MOSFET can be logically reduced while reducing the influence of the power supply voltage variation as in the embodiment of FIG. It can be reflected dominantly in the threshold value.
FIG. 24 is a block diagram showing an embodiment in which the present invention is applied to a dynamic RAM (random access memory; hereinafter simply referred to as DRAM). In this embodiment, the binary counter section and the decoder section are omitted from the identification number generating circuit shown in FIG. Instead of the counter unit and the decoder unit, the row address signal and the column address signal of the DRAM in which the counter unit and the decoder unit are mounted are supplied as the signals X and Y formed by the decoder unit, so that the logic threshold of the CMOS inverter circuit is obtained. It is used directly as a selection signal for the value judgment circuit. An identification number reading mode is set for the DRAM, a start signal is generated by the circuit DFT, and the address signals X and Y for reading are supplied from the outside to replace the selection operation of the memory array. The identification number generated by the generation circuit is output through the input / output circuit and the DQ pin. In this case, since the input order of the address signals X and Y can be made arbitrarily, it is possible to specify and read out only the fixed information of the self-competition part. Alternatively, the input order of the address signals X and Y may be input as encryption so that only a specific signal can output a fixed signal or identification number corresponding to the self-match.
This configuration is similarly applied to other semiconductor memory devices such as other static RAMs and flash EPROMs, or semiconductor integrated circuit devices such as CPUs (microprocessors) having address terminals, in addition to DRAMs. be able to.
FIG. 25 shows a schematic block diagram of an embodiment of a semiconductor integrated circuit device using the identification number generating circuit according to the present invention. The original purpose of assigning an identification number to a semiconductor integrated circuit device is to assign a unique number to each LSI. The numbering method includes a method using a laser fuse, a flash memory, or the like, but requires a special process or a program process.
In this embodiment, the identification number generated by the identification number generation circuit of the present application in the wafer state is read by a tester and registered in association with various data at the workstation. After each LSI becomes a product and is mounted on an electronic device such as a personal computer PC, an identification number is read from the LSI. At this time, even if the read identification number is the same LSI, the operating environment and conditions may differ from those at the time of registration, and there is no guarantee that they will be completely matched. However, it can be presumed that the identification numbers are the same or not the same from the degree of discrepancy between the identification numbers.
A determination algorithm of the identification system in the present application will be described. As already described, the identification number in this embodiment is the order of the logical threshold values of a plurality of CMOS inverter circuits. A circuit having four CMOS inverter circuits as in the above embodiment is counted as one unit. For example, the order of the logical implied values (number of permutations) of four CMOS inverter circuits is ₄ P ₄ = 4! = 4 × 3 × 2 × 1 = 24. If there are two units here, and the logic threshold varies completely randomly, the probability that the two unit CMOS inverter circuits are in the same order is about 4.2% (= 1-23 / 24) It is.
When one unit is composed of 8 CMOS inverter circuits, the number of permutations is 8! = 40,320. When 50 units are collected, the probability that one set or more in the same order exists is about 3% (= 1− (40320 × 40319 ×... × 40271) / 40320. ⁵⁰ ).
In 16 CMOS inverter circuits per unit, the combination is 16! = 2.09E13. Thus, the 16 permutations are a tremendous number, and when the logic threshold value of the CMOS inverter circuit varies randomly, there is almost no thing with the same arrangement. In fact, when there are 1 million units, the probability that there are one or more sets in the same order is estimated to be at least 5% or less (the exact calculation is difficult due to the large number of digits and is roughly estimated). That is, it is roughly one set per 20 million units. From such calculation, it is considered that about 16 CMOS inverter circuits are required for one unit in order to complete a practical identification number. Therefore, hereinafter, a 1-unit 16 CMOS inverter circuit will be described as an example.
If 16 CMOS inverter circuits per unit are realized as shown in FIG. 7, the round robin comparison result is 256 including the self-match. In the future, one comparison result output will be referred to as one bit.
FIG. 26 is the simplest example in which the logic threshold values of the 16 CMOS inverter circuits are continuously arranged as VLTQ1>VLTQ2>...> VLTQ16.
FIG. 27 shows an example in which the logic threshold value of the CMOS inverter circuit is random. When the logic threshold of the second stage CMOS inverter circuit is higher than the first stage, it is “1”, when the logic threshold is lower, “0”, and the self-competition is undefined “*”. As can be seen from the two examples, the bit pattern of OUT in the circuits corresponding to FIGS. 26 and 27 changes to a peculiar pattern depending on the arrangement of the logic threshold values of the CMOS inverter circuit. That is, the simplest method is to directly use the bit pattern of the output OUT as the identification number. The number of bits of identification number information in this method, that is, the data amount is 256 bits.
The bit pattern is a so-called battle result table itself. On the other hand, the idea on which the present application is based is the order of the logical threshold values of a plurality of CMOS inverter circuits. If only the information in the order of size is extracted from the match result table, it is considered that the data amount of information to be handled can be reduced.
The lower and right sides of FIGS. 26 and 27 show the total number excluding the self-competitive portion of “1” or “0” in the vertical and horizontal directions, for example, FIG. 26 and FIG. Looking at the sum of “1” on the lower side of the figure, the order of the numbers and the logical threshold values correspond to each other. This is the same as a strong team with a lot of wins when compared to a league match of sports such as soccer or baseball. Speaking of the CMOS inverter circuit, the higher the logic threshold value, the more “1”.
Since the number of wins or the total number of “1” s is equivalent to the rank, the total number of “1” s can be used to represent the order of the logical threshold values of the CMOS inverter circuit. . Of course, even if the total number of “0” is used, the inclusion of “1” or “0” in the horizontal direction is basically the same. When this method is used, the data amount of information bits can be reduced. Each CMOS inverter circuit can have a rank that can be expressed by a number from 0 to 15, respectively, and therefore requires an information amount of 4 bits in binary. Since there are 16 CMOS inverter circuits, a total of 64 bits (= 4 × 16) is required. Compared to the previous comparison result (competition result) table, the data amount can be reduced to a quarter from 256 bits to 64 bits.
Here, the configuration uses 16 CMOS inverter circuits per unit, but this effect increases as the number of CMOS inverter circuits increases. For example, in the 1 unit 32 CMOS inverter circuit configuration, the comparison result table has 1024 bits, but the case where the rank is used is 160 bits (= 5 × 32), which is 1 / 6.5. In other words, the comparison result increases four times (= 1024/256), but the information using the rank is suppressed to 2.5 times (= 160/64). This has the advantage that the amount of data to be managed by the identification system is small and the processing time spent for verification can be shortened.
FIGS. 28 and 29 each show a configuration diagram of an embodiment of a collation algorithm in the identification system for a semiconductor integrated circuit device according to the present invention. Although the method using the comparison result information of the logic threshold value of the CMOS inverter circuit will be described here, the overall flow is the same in the method using the order of the magnitude of the logic threshold value.
FIG. 28 shows a registration method.
{Circle around (1)} The comparison result information of the logical threshold value of the 256-bit CMOS inverter circuit is read from the identification number generation circuit.
{Circle around (2)} It is registered in the identification number management ledger, and a management number is provided to associate it with a database storing information such as measurement data.
(3) Increase the number of registrations by one. Here, it is premised that the newly registered identification number does not always overlap with the registered one, but the procedure for confirming duplication with the registered one at the time of new registration and issuing some kind of warning It is also effective to add
FIG. 29 shows a collation method. This system is characterized by allowing the identification number to vary due to differences in environment and conditions at the time of registration and verification.
{Circle around (1)} The comparison result information of the logical threshold value of the 256-bit CMOS inverter circuit is read from the identification number generation circuit. This is called an identification number.
(2) The registration identification numbers are sequentially extracted from the management ledger.
(3) Compare the registered identification number with the identification number. The comparison method will be described later.
{Circle around (4)} Matching candidates having a small difference in the comparison result between the registered identification number and the identification number are selected as matching candidates. By repeating {circle over (2)} to {circle around (4)}, the smallest difference among all the registered identification numbers finally becomes the same most likely candidate.
FIG. 30 shows an explanatory diagram of an example of the comparison method of FIG. The identification number is obtained by extracting 24 bits which are a part of the comparison result output of the logic threshold value of the 256-bit CMOS inverter circuit. Identification numbers 1 to 5 are registered identification numbers. The shaded portion is a portion different from the bit of the identification number. The total number of mismatch bits is shown on the right end.
As described with reference to FIG. 8, since the “0” and “1” output patterns of the identification number generating circuit are unique to each unit, whether the identification number is output from the same unit or not. Judgment can be made by the proportion of the number of bits constituting the pattern. Although the identification number here is merely an example for explanation, the number of mismatching bits of the identification number 5 is 1, and other than that, the matching rate of the identification number 5 is clearly high from 5 to 17. Therefore, the identification number 5 can be the most likely candidate.
FIG. 31 and FIG. 32 are explanatory diagrams showing an example of a comparison method of identification numbers in the case where the logical threshold order of the CMOS inverter circuit is used. FIG. 31 is shown in the form of a list, and FIG. 32 is shown in the form of a graph. Here, in order to simplify the explanation, the order of the elements with identification numbers, that is, the arrangement of the logic threshold values of the CMOS inverter circuit is assumed to be in the same order as the element numbers. The identification number 1 is the same except that the element numbers 8 and 9 are interchanged. Compared to the identification number, the absolute value of the distance between the two ranks is 2. In the identification number 2, the rank is random, the total distance of the rank is 66, and the average is 4.13. The expected value of the total distance of this rank is theoretically 85, and the average is 5.3. Therefore, it can be said that there is a high possibility that the identification number 1 having a ranking distance sum of 2 and an average of 0.125 is extremely the same. In other words, in this method, in order to allow fluctuations in identification numbers due to differences in environment and conditions at the time of registration and verification, the total difference between the identification number and the registered identification number is the smallest candidate. To do.
In the identification number 3 in FIGS. 31 and 32, the rank of the element number 1 is shifted by 5 levels. The element numbers 2 to 6 are one stage, and the rest are zero. The rank distance inclusions and averages are 10 and 0.625, respectively. As long as this value is seen, it is a value that is sufficiently lower than the expected value, so there is a high possibility of being a candidate for matching. However, it is considered that the fact that the order of the element number 1 is shifted by 5 stages is a phenomenon that hardly occurs. In order to confirm the exact identity, including the case where the identification number is equal to or slightly larger than the identification number 3 here, the maximum difference in the order distance of each element is added to the determination element. Is effective. As a specific example of the determination criterion, “the rank distance of each element is 2 or less” is added to the standard “the total rank distance is 16 or less”. Actual judgment criteria differ depending on the characteristics of the identification number generation circuit and the applied system.
FIG. 31 and FIG. 32 illustrate the case where the number of elements for the identification number, ie, the number of CMOS inverter circuits is 16. There are cases where it is desired to increase the number of elements for the identification number for reasons such as satisfying higher identification ability. For this purpose, for example, a method of extending the configuration as shown in FIG. 20 is one of the simplest methods. The increase in the number of elements in the configuration of FIG. 20 is made possible by setting the CMOS inverter and switch MOSFET corresponding to the number, setting the number of counter bits corresponding to the number, and setting the decoder. As another method for increasing the number of elements, for example, a method of arranging a plurality of identification number generating circuits mainly composed of 16 CMOS inverters in the same semiconductor integrated circuit device can be adopted.
After the semiconductor integrated circuit device LSI is paid out from the previous process, a defect is detected by a probe inspection in a wafer state or a selection test in a state assembled in a package. In a logic LSI or the like in which a memory or a relatively large scale memory is embedded, a so-called redundancy repair technique is adopted in which a defective memory cell detected at the time of probe inspection is replaced with a spare memory cell. With recent miniaturization, high speed, and high performance of semiconductor processing technology, many product defects are detected in the final sorting process. In addition, the semiconductor integrated circuit device LSI has become large-scale, and the occurrence of a defect after such a manufacturing process causes an increase in cost and is a problem.
Thus, there is an increasing demand for relieving defects detected in the assembled product. For example, taking the memory unit as an example, the chips that are defective in the burn-in process or the like are collected, and the deteriorated bits included in the defective chips are relieved by the remaining spare memory cells.
When this re-rescue technique is specifically examined, the following two representative methods are conceivable for the rescue technique. In the first method, an independent number is assigned to each LSI, and relief information in the probe inspection process is managed for every memory chip. When re-relieving is performed, the chip number is extracted from the memory chip, the relieving information collected in the probe inspection process is extracted from the management computer, and unused memory cells are indexed and re-relieved based on this. The second method is a method of taking out the first relief information from the memory chip every time re-relief is performed. This uses a so-called address roll call technique.
In order to apply these re-rescue techniques, the following techniques are required. In the first method, it is necessary to assign an independent number to each memory chip. This can be realized by programming the identification number during the repair performed after the probe inspection. In both the first and second systems, it is necessary to incorporate an element that can be electrically programmed at the time of re-rescue. Devices that can be electrically programmed are currently a method of fusing polysilicon with current, a method of destroying an insulating film with a high electric field, a method using a FLASH memory, etc. Side effects such as device reliability and increased peripheral circuits are possible.
In any of the above methods, some kind of programming element is mounted in the main body LSI. The inventor of the present application examined a third method for dividing the two into separate chips from different angles. The feature of the third method is that a dedicated process suitable for the program can be applied to the program dedicated chip. This third method also has the following problems.
One is how to make the main body LSI correspond to the dedicated programming chip. Let us consider how to solve this problem using a multi-chip module as an example. In the case of a multichip module, both chips eventually become one semiconductor integrated circuit device on the module substrate. However, until each chip is assembled into a module, the combination must be strictly controlled. It is not easy to construct an LSI production line that realizes this. Therefore, a method is conceivable in which an identification number is assigned to the main body LSI, the identification number of the main body LSI is read out in a state of being mounted on the module substrate, and information corresponding to the main body LSI is programmed in a dedicated programming chip.
As a programming method, for example, when a technique of cutting with a laser irradiation apparatus is used, the laser irradiation cutting apparatus can cut the fuse of the chip in the wafer state, but it is difficult to cut the chip on the package or module. This is because the alignment of the fuse coordinates of the chip on the package or module and the laser beam is technically difficult, and even if possible, alignment is required for each chip and the throughput is extremely low. In the first place, how to read the identification information of the main body LSI before laser irradiation is also a problem. For this reason, the dedicated chip for programming is limited to the electrical program system in which the identification number of the main body LSI can be read and the program can be continuously executed on the same device.
Therefore, a realistic form of the third method is that “a main body LSI with an identification number and a dedicated program chip having an electrical programming element are mounted on a multichip module and programmed”. . However, the third method is also established under some restrictions, and is not necessarily the best in terms of cost and reliability, for example, in LSI production activities.
One of the limitations is that the use of multichip modules is a prerequisite. However, it is more impractical to take a method of combining two chips directly on a board without using a multichip module.
The second restriction is that a programming element used for a programming-dedicated chip must use an electrically programmable process such as polysilicon fuse, FLASH memory, and FRAM. All of these elements require a special process, the scale of peripheral circuits is large, and there is a problem in terms of reliability. There is a programming method that uses a laser-cut metal fuse as a method that has few of these problems and is relatively inexpensive, but as described above, it cannot be said to be compatible with the third method.
The third problem is the program (engraved) of the identification number of the main body LSI. This program also requires a laser fuse and an electrical program element. However, if a similar process is added to the main body LSI in spite of the fact that the program-dedicated chip is made into another chip, the merit of cost reduction of the main body LSI is reduced. Therefore, in order to solve these problems, an identification number generation circuit using variations in the logic threshold value of the CMOS inverter circuit is extremely useful.
FIG. 33 shows a block diagram of an embodiment of a semiconductor integrated circuit device to which the present invention is applied. First, a probe inspection of the main body LSI is performed. At this time, for example, if there is a defect in the memory unit mounted on the LSI, repair information for replacing the defective memory cell with a spare memory cell is created. In a general-purpose memory or the like, laser relief or the like is performed thereafter. In the semiconductor integrated circuit device of this embodiment, the main body LSI is diced and assembled as it is. Further, the defect information detected in the process such as aging and selection is added to the repair information at the time of probe inspection. The final remedy information is written in a dedicated programming chip. The main body LSI and the program dedicated chip are used in combination as a multichip module.
FIG. 34 is a block diagram showing an embodiment of the multichip module to which the present invention is applied. The main body LSI and the program dedicated chip transmit data to the serial in synchronization with the clock through the data exchange control circuit. That is, the identification number generated by the identification number generation circuit of the main body LSI is transmitted to the program dedicated chip through the data exchange control circuit.
In the program dedicated chip, a plurality of registration numbers (identification numbers) corresponding to one unit and defect repair information are held as programming data in a one-to-one correspondence. In the program dedicated chip, the identification number transmitted from the main body LSI via the data exchange control circuit is registered in the identification number register via the counter.
The verification circuit compares and compares the identification number with the registered identification number in the programming data. In this collation operation, the determination is performed in accordance with the algorithm shown in FIG. 30 to FIG. 31 while allowing the identification number to vary due to the difference in environment and conditions at the time of registration and collation. When the matching candidate number is detected, the register data in the programming data is read out to the data reading circuit. Then, relief information is transmitted from the program dedicated chip to the main body LSI via the data exchange control circuit, contrary to the identification number. This relief information is serial / parallel converted and held in the data register, and used for defect relief.
Since the program dedicated chip has defect relief information for a plurality of chips corresponding to one unit, one type of program dedicated chip is formed for a plurality of main body LSIs for one unit and used in combination. It is done. Therefore, it is not necessary to manufacture, manage, and assemble the main body LSI and the program dedicated chip in a one-to-one correspondence.
FIG. 35 shows a block diagram of an embodiment of a dedicated program chip. The program-dedicated chip is not particularly limited, but includes an identification number decoding circuit, a verification circuit, programming data and a data reading circuit, and the like. The registration identification number and register data are registered by selective cutting of the fuse by laser irradiation.
The matching circuit corresponds to the determination algorithm shown in FIG. 30 or FIG. 31, and detects the deviation by using the subtractor to compare the absolute value of the subtraction result with the upper limit value by the comparator 1. The comparator 2 compares the cumulative distances output from the accumulator with reference to the minimum cumulative distance that is sequentially replaced, and outputs one match candidate number from 1 to N together with the deviation detection signal by the determination circuit. Register data is selected by this match candidate number and transmitted to the data read circuit. The data read circuit has an ECC function (error correction function). This increases the reliability of the data.
FIG. 36 shows a semiconductor integrated circuit equipped with the identification number generating circuit according to the present application.

A block diagram is shown. In this embodiment, the main body LSI is a large-scale system LSI in which DRAM and SRAM are mixedly mounted, and the program dedicated chip is premised on the use of a laser cut metal fuse. The flow of the manufacturing process will be described below with reference to FIG.
(1) The main body LSI is tested with a probe test tester. The identification number in the LSI is transferred to the host computer together with the defective memory cell repair information of the DRAM or SRAM, the internal power supply circuit trimming setting value, the delay circuit setting value, and the like. The host computer concatenates the sent information and other manufacturing management information and stores it in the database.
(2) The main body LSI wafer is diced.
(3) Only the main body LSI is temporarily mounted on the multichip module substrate. In this figure, there is one main body LSI, but there may be a plurality of LSIs.
(4) The identification number is read from the main body LSI by the selection test tester and sent to the host computer. The host computer recognizes the main body LSI from the identification number and returns information necessary for each main body LSI to the tester. The necessary information is information managed by the host computer in the database, such as the defective memory cell relief information and the main body LS1 identification information. This is called main body LSI register information. The sorting test tester stores the main body LSI register information in, for example, the repair address register of the repair circuit in the main body LSI if it is defective memory cell repair information, and the trimming value in the internal circuit if the internal power supply circuit trimming fixed value Store in the setting register.
The screening tester performs a high-speed operation test that cannot be performed by the probe test after setting the main body LSI register information. Further, regarding the newly defective one here, the defect information is transferred to the host computer. The host computer combines the collected information with the sent defect information, analyzes whether it can be repaired and adjusted, and stores it again in the database.
(5) Program register information necessary for the main body LSI in a dedicated program chip. If necessary, programs such as manufacturing management information, customer information, encryption, and function information are executed. The program dedicated chip can store information on a plurality of main body LSIs in one chip. For example, if there is a capacity for 100 main LSIs, the laser cutting device receives an identification number and register information for 100 main LSIs from the host computer, and 100 programs based on the received information. The register information for the same 100 main body LSIs is programmed in all the dedicated chips.
Here, let us estimate the fuse cutting time of the dedicated program chip. For example, if the number of program bits per main body LSI is 1000 bits, and it can be stored (registered) for 100 main body LSs in one program dedicated chip, one program dedicated chip is 100,000 (1000 × 100). Mount a fuse. Since the latest laser cutting apparatus has a capacity of 5000 pulses or more per second, it can cut 100,000 chips, that is, one program dedicated chip in about 20 seconds. With 100 chips, it is 2000 seconds (33 minutes). The area of the dedicated program chip is 1.5 square millimeters when only one fuse portion is 15 square microns, and about 3 square millimeters when peripheral circuits and pads are included.
(6) Probe inspection is performed in order to remove laser-cutting defective chips. Note that a step of attaching a protective film for protecting the chip may be added before this step. The inspection data pattern is received from the host computer. Here, since a laser cutting defective chip may occur, the number of chips programmed in the step (5) is more than 100. This number is adjusted according to the actual yield. Here, if the number of dedicated program chips is less than the main LSI, the surplus main LSI is collected and mixed into another group. Conversely, if there are extra program-only chips, they are discarded. In any case, it is damaging, but it is more economical than discarding the valuable main body LSI.
(7) Dicing the program dedicated chip. As for the diced chips, 100 chips and the surplus portions that have been programmed in the same manner in step (6) are picked up and collected into a group (lot) corresponding to the main body LSI.
(8) Mount the program dedicated chip on the multichip module package. At this time, the groups associated in the steps (4) and (6) must be combined. However, since there is no need for one-to-one correspondence between the individual main body LSI and the dedicated program chip, no significant change in the process is required compared to the conventional assembly process. In this embodiment, the subsequent separation is performed in the assembly process.

However, it is not limited to this method.
(9) The final multi-chip module is subjected to a final screening test. In the above-described embodiment, the program-dedicated chip contains (registered) relief information for 100 chips. When the main body LSI on the board starts up, data is exchanged between the main body LSI and the program dedicated chip. Specifically, an identification number is sent from the main body LSI to the program dedicated chip, and the program dedicated chip compares the sent identification number with the registered identification number, recognizes the main body LSI mounted on the module, and relieves it. Necessary register information such as information is sent to the main body LSI. The main body LSI performs internal initialization based on the sent register information. Thereafter, a final test is performed. The inclusions are sent to the next sealing process, and the rejected ones are sent to the separation process. At the same time, the defect information is sent to the host computer to analyze whether it can be reproduced.

The

It is.

An identification number is read from the SI, and past probe test information, sorting test information, and final sorting test information corresponding to the identification number are fetched from the host computer. Although not shown, a dedicated program chip is created for this new reproducible product in the same manner as the non-reproducible product, and the same process proceeds. As a dedicated program chip, it can be replaced with an electrically programmable element. In this case, the number of processes can be reduced.
In FIG. 37, there is no manufacturing process {circle around (1)} of an embodiment in which a semiconductor integrated circuit device equipped with an identification number generating circuit according to the present application is assembled on a circuit mounting board.

(1) The main body LSI is tested with a probe test tester. The identification number in the LSI is transferred to the host computer together with the defective memory cell repair information of the DRAM or SRAM, the internal power supply circuit trimming setting value, the delay circuit setting value, and the like. The host computer stores the sent information and other manufacturing management information in a database in cooperation with each other.
(2) The main body LSI wafer is diced.
(3) Assemble the main body LSI into a package.
(4) Same as step (4) in FIG.
(5) Same as step (5) in FIG.
(6) Dicing the program dedicated chip. The diced chips are grouped into groups (lots) corresponding to the main body LSI as in the embodiment of FIG.
(7) Same as step (7) in FIG.
(8) Mount the main body LSI and program dedicated chip on the circuit mounting board. At this time, the groups associated in the steps (4) and (6) must be combined. However, since there is no need for one-to-one correspondence between the individual main body LSI and the dedicated program chip, no significant change in the process is required compared to the conventional assembly process.
(9) The completed board is tested for mounting. When the main body LSI on the board starts up, data is exchanged between the main body LSI and the program dedicated chip. The main body LSI or program-dedicated chip and those confirmed to be defective due to board mounting are sent to the separation process, and at the same time, the defect information is sent to the host computer to analyze whether it can be reproduced.

It is.

The This register information is obtained by adding the implementation test result to the previous register information.

Are mounted on one mounting board together with the program dedicated chip, and the same process proceeds thereafter.

In addition, the Example shown here is only one Example, and changes with the forms of the applied product and the existing production line.
FIG. 38 shows a semiconductor integrated circuit equipped with the identification number generating circuit according to the present application.

(1) The main body LSI is tested with a probe test tester. The identification number in the LSI is transferred to the host computer together with the defective memory cell repair information of the DRAM or SRAM, the internal power supply circuit trimming setting value, the delay circuit setting value, and the like. The host computer stores the sent information and other manufacturing management information in a database in cooperation with each other.
(2) The main body LSI wafer is diced to select a repairable chip.
(3) Temporarily assemble the main body LSI on the baby board.
(4) Aging is performed after checking for defective assembly. At this time, the identification number is read from the chip on the baby board, and relief data corresponding to each chip is extracted from the host computer and stored in the chip on the baby board.
(5) Select with a tester.
(6) Separate the main body LSI from the baby board.
(7) Ship the main LSI.
(8) The customer mounts the program device on the circuit mounting board simultaneously with the main body LSI.
(9) Take out the identification number from the main body LSI.

Data corresponding to the mounted main body LSI is received, transferred to the program device, and stored. You may distribute using electronic media like CDROM, for example, without using a communication line.

In the manufacturing method of the semiconductor integrated circuit device of each of the above embodiments,
(1) Since the combination of the main body LSI and the program-dedicated chip is the number of main body LSIs registered in the program-dedicated chip, one-to-one management becomes unnecessary, productivity is improved, and changes to existing production facilities are reduced. That's it.
(2) A laser cutting fuse can be used for a dedicated chip for programming. The advantages of the metal fuse over other electrically programmable elements are that the change is small compared to the standard CMOS process, the design can be easily changed to the specifications of the main unit LS1, and it does not depend on the process generation Etc. The changes from the standard process are the final wiring layer formation and the passivation process.
(3) Since the main body LSI register may be a latch circuit, the area is small and the chip size of the main body LSI is reduced.
(4) If a chip identification number generating circuit is mounted on the main body LSI, there is no need to add a programmable element process to the main body chip.
(5) Program-specific chips can be replaced (repaired). When corrections or problems occur in the main body LSI after being mounted on a module or a pod, it can be dealt with by replacing the chip whose program content has been changed.
(6) By exchanging information centered on the host computer using a network, it is possible to use a manufacturing plant at a remote location, and economical production activities are possible.
FIG. 40 shows an embodiment in which the variation of the logic threshold value of the CMOS inverter is applied to a random number generator. As a more specific embodiment, description will be made using an application specific LSI as shown in FIG. This LSI is for controlling a toy robot. Currently, commercially available toy robots, especially pet breeding robots, have a uniform character when shipped from the factory. However, in order to make it resemble an actual living organism or animal, for example, by providing innate or genetic characteristics such as gender, temperament, and motor ability of male or female, You can have a strong feeling as a creature.
FIG. 40 shows the simplest circuit for providing a dedicated LSI with innate features when an LSI is manufactured without a program. This outputs a 4-bit random number in binary, and the output value of each bit is randomly generated for each LSI. For example, D0 determines male or female. D1 determines the temper, and D2 and D3 determine the dependence on the owner in four stages. In addition, although two types of circuit systems are shown for D0 and D1, and D2 and D3, the difference between the logical threshold values of the two CMOS inverters is basically the same.
It is possible to give such an innate personality to the robot by other methods. For example, it is possible to change the parameters of the contents of the control program individually. However, there is a sense that it is a program created by a manufacturer, that is, a product made by a human. According to the method shown in this embodiment, the individuality can not be controlled by the manufacturer, so that it feels like “God's providence”, and the value as a product increases.
FIG. 41 shows another configuration diagram of an example of use of the chip identification number generation circuit according to the present invention for the purpose of reducing fraud and various troubles in the electronic parts procurement market between companies. .
A chip identification number generating circuit as described above is incorporated in a semiconductor LSI shipped from a factory. The factory, that is, the manufacturer collects the chip identification numbers of all the shipments. Since the chip identification number is random, it is associated with an LSI management number that is convenient for management. Furthermore, it associates with various management information, for example, production line name and manufacturing date.
In the case of direct delivery to the customer A as shown in (1) of FIG. 41, information such as form data such as a unit (box etc.) number packing the product and customer number is added to the management information of the database. The customer A who received the product reads the chip identification number from the entire LSI or the extracted LSI at the time of acceptance inspection. Next, the customer A accesses the manufacturer's database through a network such as the Internet. The chip identification number of the LSI included in the received unit is extracted from the database and compared with the identification number read from the received LSI. If the identification numbers match, it can be confirmed that the product is delivered correctly. This method can be used for general-purpose products or customer-custom products, but is particularly effective for custom products.
In FIG. 41, let us assume a case where an intermediary (wholesaler) intervenes. Factory shipment is the same as above. The received primary wholesaler does not normally open the package, but inquires the unit number to the manufacturer's server and registers the next delivery destination information and the like. The same applies to secondary and tertiary wholesalers. The end customer reads the identification number of the received LSI from the LSI in the same manner as in the above (1), and makes an inquiry to the manufacturer's database. The following effects can be expected by building the above system.
(1) It is possible to prevent delivery mistakes.
(2) It is possible to prevent illegal acts such as replacement of second-hand goods by an intermediary.
(3) Resale of defective and second-hand goods due to returns can be prevented.
(4) The distribution route can be confirmed.
FIG. 42 shows a schematic plan view of another embodiment of the semiconductor integrated circuit device according to the present invention. This figure is a schematic plan view showing a state where the upper part of the resin sealing body of the semiconductor device is removed. M ulti C hip P The present invention is applied to a semiconductor device referred to as an “package” type. In the MCP type semiconductor device of this embodiment, two semiconductor chips are stacked and incorporated in one package. Among these, the semiconductor integrated circuit device 10 is a base chip, which is a main body LSI as shown in FIGS. The semiconductor chip 20 mounted thereon is used as the program dedicated chip. The QFP type semiconductor device 30A of this embodiment has a configuration in which two semiconductor chips (main body LSI 10 and program dedicated chip) are stacked one above the other, and the two semiconductor chips are sealed with one resin sealing body 17. Yes.
The main body LSI 10 and the program dedicated chip 20 are formed in different planar sizes (outer dimensions), and each planar shape is formed in a square shape. In the present embodiment, the planar shape of the main body LSI 10 is, for example, a rectangle of 4.05 [mm] × 4.15 [mm], and the planar shape of the program dedicated chip 20 is, for example, 1.99 [mm] × 1.23. It is formed in a [mm] rectangle.
The main body LSI 10 and the program dedicated chip 20 include, for example, a semiconductor substrate made of single crystal silicon, a multilayer wiring layer in which a plurality of insulating layers and wiring layers are stacked on the circuit formation surface of the semiconductor substrate, and the multilayer wiring layer And a surface protective film (final protective film) formed so as to cover the surface.
A plurality of bonding pads 11 are formed on the circuit forming surface 10A among the circuit forming surface (one main surface) 10A and the back surface (other main surface) facing each other of the main body LSI 10. The plurality of bonding pads 11 are formed on the uppermost wiring layer of the multilayer wiring layers of the main body LSI 10. The uppermost wiring layer is covered with a surface protective film formed thereon, and a bonding opening that exposes the surface of the bonding pad 11 is formed in this surface protective film.
A plurality of bonding pads 21 are formed on the circuit forming surface 20A among the circuit forming surface (one main surface) 20A and the back surface (the other main surface) facing each other of the program dedicated chip 20. The plurality of bonding pads 21 are formed in the uppermost wiring layer of the multilayer wiring layers of the program dedicated chip 20. The uppermost wiring layer is covered with a surface protective film formed thereon, and a bonding opening that exposes the surface of the bonding pad 21 is formed in the surface protective film.
The planar shape of the bonding pad 11 of the main body LSI 10 and the bonding pad 21 of the program dedicated chip 20 is, for example, a square of 65 [μm] × 65 [μm].
The plurality of bonding pads 11 of the main body LSI 10 are arranged along four sides of the main body LSI 10 (two long sides (10A1, 10A2) facing each other and two short sides (10A3, 10A4) facing each other). . The plurality of bonding pads 21 of the program dedicated chip 20 are along four sides of the EEPROM chip 20 (two short sides (20A1, 20A2) facing each other and two long sides (20A3, 20A4) facing each other). It is arranged.
The program dedicated chip 20 is arranged on the circuit forming surface 10A of the main body LSI 10 with the back surface, which is the other main surface of the program dedicated chip 20, facing the circuit forming surface 10A of the main body LSI 10, and the main body with the adhesive layer 15 interposed therebetween. The LSI 10 is bonded and fixed to the circuit forming surface 10A. In the present embodiment, as the adhesive layer 15, for example, a polyimide-based adhesive resin film is used.
The main body LSI 10 is bonded and fixed to the die pad with an adhesive layer in a state where the back surface thereof faces the die pad. The four suspending leads 6 are integrated with the die pad, and the die pad 5 and the four suspending leads 6 constitute a support.
The planar shape of the resin sealing body 17 is a square shape. In this embodiment, the planar shape of the resin sealing body 17 is, for example, a square of 10 [mm] × 10 [mm]. For the purpose of reducing the stress, the resin sealing body 17 is formed of, for example, an epoxy resin to which a phenol curing agent, silicone rubber, filler, or the like is added. In forming the resin sealing body 17, a transfer mold method suitable for mass production is used. The transfer mold method is a method of forming a resin sealing body by using a molding die including a pot, a runner, an inflow gate, a cavity, and the like, and injecting resin from the pot into the cavity through the runner and the inflow gate. .
A plurality of leads 2 arranged along each side of the resin sealing body 17 are arranged around the main body LSI 10. Each of the plurality of leads 2 has an internal lead portion (inner lead) and an external lead portion (outer lead) formed integrally with the internal lead portion. The internal lead portion of each lead 2 is located inside the resin sealing body 17, and the external lead portion is located outside the resin sealing body 17. That is, the plurality of leads 2 extend across the resin sealing body 17. The external lead portion of each lead 2 is bent and formed into, for example, a gull wing type lead shape which is one of surface mount type lead shapes.
In this embodiment, the main body LSI 10 is provided with an identification number generating circuit that is generated based on the magnitude of the logical threshold value of the CMOS inverter circuit as described above. When such a CMOS inverter circuit is used, it is necessary to input a control signal for supplying an operating voltage to the main body LSI and operating the identification number generating circuit. For this purpose, a special power supply device and a signal readout device are required although they have a simple configuration.
When a semiconductor integrated circuit device is in a distribution channel, it often happens that the identification number is known, and the operating voltage cannot be supplied under the environment. The inventive idea of the present application is to determine the magnitude relationship between physical quantities corresponding to process variations of a plurality of identification elements having the same form during the manufacturing process of a semiconductor integrated circuit device. A semiconductor integrated circuit device has a plurality of leads, and the lead width d is formed by pressing or the like so as to be uniform.
However, process variations occur in the widths d1, d2, etc. of the leads. Therefore, the lead widths d1, d2, etc. of a plurality of leads are measured with an optical device, and the size comparison is performed to use for identification number generation using process variations as in the case of the logical threshold value of the CMOS inverter circuit. Is. In this configuration, a plurality of lead widths of the leads are measured by the measuring device, and an identification number unique to the same semiconductor integrated circuit device can be determined by determining the magnitude relationship.
In other words, 16 leads are determined as described above before shipment of the semiconductor integrated circuit device, the lead width or the pitch between the leads is measured, and the positional information and the magnitude relationship are stored in a database. Let When measuring the lead width pitch, it is desirable that the lead 2 is formed at a portion protruding from the package 17. Since this measurement can be performed by an optical device in a single time, it does not take much time to determine the identification number at the time of shipment.
It can also be used for a semiconductor integrated circuit device not equipped with a CMOS circuit. In a semiconductor integrated circuit device with a CMOS circuit, it may be used in combination with an electrical identification number of the CMOS inverter circuit. It is possible to make the determination of the identification number more reliable by comprehensively determining such variations in the two physical quantities.
FIG. 43 shows a basic circuit diagram of another embodiment of the identification number generating circuit according to the present invention. In the above embodiment, the order of the logical threshold values of the variations of the plurality of CMOS inverter circuits is used as the identification number by the circuit represented by FIG. On the other hand, in this embodiment, the comparison result of the logical threshold values of the two CMOS inverter circuits INV1 and INV2 is set to 1 bit of the identification number. This idea is also used in the embodiment of FIG.
In this embodiment, the logical threshold values of the two CMOS inverter circuits INV1 and INV2 are compared as follows. A short-circuiting N-channel MOSFET Q2 is provided between the input terminal and the output terminal of the inverter circuit INV1. Although not particularly limited, a P-channel MOSFET Q1 is provided between the input terminal of the CMOS inverter circuit INV1 and the power supply voltage VDD. An identification number circuit enable signal EN is supplied to the gates of these MOSFETs Q1 and Q2.
The output terminal of the inverter circuit INV1 is connected to the input terminal of the inverter circuit INV2. The output signal of the inverter circuit INV2 is binarized by an amplifier circuit composed of a cascade circuit of similar CMOS inverter circuits INV3 to INV5, and an identification number output is formed from the output terminal OUT.
When the identification number circuit enable signal EN is at a low level, the circuit is inactive, the MOSFET Q1 is turned on, and a high level corresponding to the power supply voltage VDD is supplied to the input terminal of the CMOS inverter circuit INV1. At this time, the MOSFET Q2 is turned off, and the output signal of the inverter circuit INV1 is set to the low level. Thereafter, the inverted signals are sequentially transmitted in the order of the high level, the low level,.
The MOSFET constituting the CMOS inverter circuit has a possibility that its characteristics may be changed undesirably depending on the application state of the gate bias voltage. P-channel MOSFETs and N-channel MOSFETs are relatively large in characteristics due to the influence of the NBTI phenomenon as introduced in the explanation for FIG. 19 and also explained in FIG. 44 below. There is a high probability of fluctuation.
The pull-up MOSFET Q1 which is turned on when the identification number circuit in the inactive state in FIG. 43 has the function of preventing the through current of the first-stage CMOS inverter circuit and the gate potential of the P-channel MOSFET in the first-stage CMOS inverter circuit. Maintaining the source potential, that is, the high potential of the power supply potential level, has an effect of sufficiently suppressing the characteristic variation of the P-channel MOSFET.
When the identification number circuit is activated, that is, when an identification number is generated, the signal EN is set to high level. As a result, the CMOS inverter circuit INV1 has its input and output short-circuited by the MOSFET Q2, and generates a voltage corresponding to the logical threshold voltage. A voltage corresponding to the logic threshold value of the CMOS inverter circuit INV1 is supplied to the input terminal of the CMOS inverter circuit INV2. The CMOS inverter circuit INV2 compares its own logical threshold voltage with a voltage corresponding to the logical threshold voltage of the CMOS inverter circuit INV1.
When the logic threshold value of the inverter circuit INV1 is lower than that of the inverter circuit INV2, its output potential becomes higher than the logic threshold voltage of the inverter circuit INV2. Subsequently, the output signal of the inverter circuit INV2 is amplified by the inverter circuits INV3, INV3, and INV5, and the potential of the node N5 becomes close to VSS. Contrary to the above, when the logic threshold value of the inverter circuit INV1 is higher than that of the inverter circuit INV2, its output potential becomes lower than the logic threshold voltage of the inverter circuit INV2. Subsequently, the output signal of the inverter circuit INV2 is amplified by the inverter circuits INV3, INV3, and INV5, and the potential of the node N5 becomes close to VDD.
FIG. 44 is a circuit diagram showing another embodiment of the identification number generating circuit according to the present invention. In the figure, since there is a characteristic in the operation, two circuits corresponding to the operation state 1 and the operation state 2 are shown together for explaining the operation.
As in the embodiment described with reference to FIG. 43, in the case where identification information is obtained by the logical threshold difference between the two CMOS inverter circuits INV1 and INV2, the reproducibility of the output signal is ensured even when the difference is small. is important. In particular, it is necessary to consider that the threshold voltage of the P-channel type MOSFET (not the logic threshold value of the CMOS inverter circuit) fluctuates due to a phenomenon called NBTI that has become prominent in recent devices. That is, the threshold voltage of the P-channel type MOSFET of one of the two CMOS inverter circuits changes due to the phenomenon of NBTI, and the logical threshold value of the CMOS inverter circuit is also affected. If the logical threshold difference between the two CMOS inverter circuits is reversed, there arises a problem that the reliability of the identification information generated thereby is lowered.
In this embodiment, a latch and a feedback path are added in order to guarantee the reproducibility of the identification number and to improve the resistance against changes with time. That is, the output signal of the inverter circuit INV5 constituting the amplifier circuit as described above is transmitted to the input of the CMOS inverter circuit INV6 on the input side constituting the latch circuit via the switch SW1. The output signal of the inverter circuit INV6 is transmitted to the input of the inverter circuit INV7, and the output signal of the inverter circuit INV7 is fed back to the input of the inverter circuit INV6 through the switch SW2. The output signal of the inverter circuit INV7 is fed back to the input of the inverter circuit INV1 through the switch SW3.
The operation state 1 in FIG. 44 shows the operation for generating the identification information. The switch SW0 is turned on, and the input and output of the CMOS inverter circuit IVN1 are short-circuited to correspond to the logical threshold voltage. A voltage is generated at the output node N1. As described above, the voltage corresponding to the logic threshold value of the CMOS inverter circuit INV1 is input to the CMOS inverter circuit INV2, so that the difference between the logic threshold voltages is applied to the output node N2 of the CMOS inverter circuit INV2. Is obtained and amplified by the CMOS inverter circuits INV3 to INV5 constituting the amplifier circuit.
When the logic threshold value of the inverter circuit INV1 is lower than that of the inverter circuit INV2, the potential of the node N2 becomes higher than the logic threshold voltage of INV2. Subsequently, the difference between the potential of INV2 and the logic threshold is amplified by the inverter circuits INV3, INV4, and INV5, and the potential of the node N5 becomes close to VSS. At this time, the switch SW1 of the latch circuit is turned on and the switch SW2 is turned off, and the amplified signal is transmitted through the switch SW1 in the on state, and the input node N6 of the inverter circuit INV6 and the output node of the inverter circuit INV6. N7 and the potential of the output node N8 of the inverter circuit INV7 are VSS, VDD, and VSS, respectively.
The operation state 2 in FIG. 44 shows a feedback operation, and the switch SW1 of the latch circuit is turned off, the switch SW2 is turned on, and the above state is maintained. The switch SW0 is turned off and the switch SW3 is turned on, and the held voltage at the node N8 is fed back to the input of the CMOS inverter circuit IVN1.
Thereby, the gate input of the inverter circuit INV1 becomes the node N8, that is, the VSS potential. Further, the gate input of INV2 is VDD. That is, the gate potential of the P-channel MOSFET of the inverter circuit INV1 is VSS. This is a condition for accelerating NBTI for the P-channel MOSFET. If this state is maintained for a long time, the threshold voltage (not the logic threshold voltage) of the MOSFET tends to gradually increase. There is no guarantee that it will always be high, but it is not a condition that will at least be low. When the threshold value of the P-channel MOSFET of the inverter circuit INV1 varies so as to increase, the logic threshold voltage of the inverter circuit INV1 relatively decreases in relation to the N-channel MOSFET.
On the other hand, in the case of the P-channel MOSFET of the inverter circuit INV2, the gate potential is VDD, which is a condition in which the acceleration of NBTI does not easily occur. Therefore, the change in the logical threshold voltage of the inverter circuit INV2 is relatively small. small. That is, as the operation state 2 is continued, the logic threshold value of the inverter circuit INV1 fluctuates low, and in order to maintain that of the inverter circuit INV2, the difference between the original threshold values is relatively enlarged. Become. As a result, even when the difference between the logical thresholds is small, the reproducibility of the identification bit having low reproducibility is improved, and an identification number generating circuit having high resistance against changes with time can be realized.
Note that when the logic threshold value of the inverter circuit INV1 is higher than that of the inverter circuit INV2, the potential of the node N2 becomes lower than the logic threshold voltage of INV2. Therefore, in the feedback operation, the node N8 is amplified to the VDD potential. Further, the gate input of INV2 is VSS. That is, the gate potential of the P-channel MOSFET of the inverter circuit INV2 is VSS. This is a condition for accelerating NBTI for the P-channel MOSFET, and if this state is kept long as described above, the threshold voltage (not the logic threshold) voltage of the MOSFET tends to gradually increase. . There is no guarantee that it will always be high, but it is not a condition that will at least be low. When the threshold value of the P-channel MOSFET of the inverter circuit INV2 varies so as to increase, the logic threshold voltage of the inverter circuit INV2 becomes relatively low in relation to the N-channel MOSFET.
On the other hand, in the case of the P-channel MOSFET of the inverter circuit INV1, the gate potential is VDD, which is a condition in which NBTI is unlikely to accelerate, so the change in the logical threshold voltage of the inverter circuit INV1 is relatively small. small. That is, as the operation state 2 continues, the logic threshold value of the inverter circuit INV2 fluctuates low, and in order to maintain that of the inverter circuit INV1, the difference between the original threshold values is relatively enlarged. Become. As a result, even when the difference between the logical thresholds is small, the reproducibility of the identification bit having low reproducibility is improved, and an identification number generating circuit having high resistance against changes with time can be realized.
In FIG. 44, in order to prevent the operation state 2 from being set to an incorrect state, when the semiconductor integrated circuit device is started up every time the power is turned on, a power supply reset circuit or an initialization circuit in the semiconductor integrated circuit device is used. The circuit first starts the first operating state and then transitions to the second operating state. As a result, an appropriate feedback operation can be performed regardless of the power supply start characteristics of the inverter circuits INV6 and INV7 themselves.
FIG. 45 shows a specific circuit diagram of an embodiment of the identification number generating circuit according to the present invention. In this embodiment, a CMOS switch in which an N-channel MOSFET and a P-channel MOSFET are connected in parallel is used as the switches SW0 to SW3. Also, a CMOS switch and a P-channel MOSFET that is pulled up to the power supply voltage VDD are provided at each input terminal of each of the inverter circuits INV3 to INV5 that constitute the amplifier circuit INV2 and the amplifier circuit.
The feedback control signal FB is used not only for control of the switches SW1 to SW3 of the latch circuit but also for switch control of the switch SW0 that short-circuits the input and output of the inverter circuit INV1. That is, the output signal of the inverter circuit INV10 that forms the inverted signal of the feedback signal FB is supplied to one input of the NAND gate circuit G1 in addition to the control of the CMOS switches SW1 to SW3 as described above. The signal EN is supplied to the other input of the NAND gate circuit G1, and the switch SW0 is controlled by the output signal of the NAND gate circuit G1 and the inverted signal formed by the inverter circuit INV9.
In the circuit of this embodiment, when the power supply voltage is supplied to the semiconductor integrated circuit device or semiconductor chip on which such an identification number circuit is mounted and the signal EN is at a low level, the P-channel MOSFETs Q11 to Q15 are turned on, and each CMOS A high level such as the power supply voltage VDD is supplied to the input terminal of the inverter circuit. At this time, the switches provided at the input terminals of the CMOS inverter circuits INV2 to INV5 are turned off by the low level of the signal EN and the high level of the inverted signal by the inverter circuit INV8, and the cascade connection between the inverter circuits Is disconnected, the voltage level of the input terminal is set to a high level corresponding to the ON state of the MOSFETs Q11 to Q15.
This is because the threshold voltage of the P-channel MOSFET (the logic of the CMOS inverter circuit) that constitutes the CMOS inverter circuit in a state where the identification number is not taken out when power is supplied to the semiconductor integrated circuit device or the semiconductor chip. This is useful for preventing fluctuations (not threshold values) due to the phenomenon of NBTI.
When the signal EN is changed from the low level to the high level, the switches that connect the inverter circuits INV1 to INV5 in the column form are turned on, and the output signal of the gate circuit G1 becomes the low level to turn on the switch SW0. As a result, a signal obtained by amplifying the difference voltage between the logic threshold voltage of the CMOS inverter circuit INV1 and the logic threshold voltage of the inverter circuit INV2 is obtained from the output of the inverter circuit INV5. When the signal FB is at a low level, the switch SW0 is in an on state, and the output signal of the inverter circuit INV5 is taken into the inverter circuits INV6 and INV7 that constitute the latch circuit.
When the signal FB is changed from the low level to the high level in the above state, in the latch circuit, the switch SW1 is turned off, the switches SW2 and SW3 are turned on, the above-described identification information is held, and a signal corresponding thereto is By feeding back to the input of the inverter circuit INV1 through the switch SW3, the input voltages of the inverter circuits INV1 to INV5 are set so that the identification number is guaranteed or stabilized by using NBTI in reverse as described above. At this time, the output signal of the NAND gate circuit G1 returns to the high level due to the high level of the signal FB, and the switch SW0 that has short-circuited the input and output of the inverter circuit INV1 is turned off.
It is considered that the inverter circuits INV4, INV5, etc. constituting the amplifier circuit are not substantially affected by NBTI as described above because the input voltage has a large difference voltage from the logic threshold voltage. However, by using the same circuit configuration as that of the inverter circuits INV2, INV3, etc., it is possible to use the same circuit cell for forming a circuit on a semiconductor collector substrate, which is beneficial in using the soft IP technology described later. .
FIG. 46 shows a specific circuit diagram of still another embodiment of the identification number generating circuit according to the present invention. This embodiment is an extension of the 1-bit identification number generating circuit as shown in FIG. 44 and the like. The present embodiment is directed to a circuit that generates an 8-bit identification number with a small number of circuit elements.
In this embodiment, the constants and layout shapes of all the CMOS inverter circuits in the circuit diagram are the same. That is, the unit circuit (cell) includes a CMOS inverter circuit, a CMOS switch provided at the input terminal, and a CMOS switch that short-circuits the input terminal and the output terminal. Each unit circuit is connected in a column form by a CMOS switch provided at the input terminal. In the figure, four unit circuits are connected in a column form. The power supply voltage is supplied to the first stage circuit among the four unit circuits via the CMOS switch.
Two CMOS circuits as described above are provided in parallel, and the two CMOS switches of the CMOS inverter circuit arranged at the corresponding positions receive the selection signal X0 and its inverted signal X0 / ˜X3 and its inverted signal X3 /. Commonly supplied. Thus, the unit circuits are arranged in a matrix state in a signal transmission direction in which the unit circuits are connected in cascade and in a direction orthogonal to the signal transmission direction.
A switch is provided at the output terminal of the final stage circuit of the two column circuits, and selection signals Y0, Y0 / and Y1, Y1 / for selecting one of the column circuits are supplied. Inverter circuits INV4 and INV5 constituting the amplifier circuit as described above are provided, and an identification number error output is output from the output terminal OUT. The input of the inverter circuit INV4 is provided with a P-channel MOSFET that is controlled by the signal PON and supplies a power supply voltage to the input terminal of the inverter circuit INV4 as a measure against NBTI as described above.
FIG. 47 is a timing chart for explaining the operation of the embodiment circuit of FIG.
1) When the power-on signal PON is at the low level, the selection signals X0 to X3 are at the low level, the inverted signals X0 / to X3 / are at the high level, Y0 and Y1 are at the low level, and the inverted signals Y0 / and Y1 / Is high level. The outputs of the CMOS inverter are INV00, 20 and INV01, INV21 and INV4 are at low level, INV10, INV30 and INV11, INV31 and INV5 are at high level, respectively.
2) When the power-on signal PON transits to a high level, the selection signal X0 is at a high level, X0 / is at a low level, Y0 is at a high level, and Y0 / is at a low level. The inputs of the inverter circuits INV00 and INV01 are disconnected from the power supply voltage VDD, and the respective inputs and outputs are short-circuited by the CMOS switch which is turned on from the high level of the selection signal X0 and the low level of X0 /, and the inverter circuits INV00 and INV01 Output voltage corresponds to the logical threshold.
If the relationship between the logical threshold value VLT (INV00) of the inverter circuit INV00 and the logical threshold value VLT (INV10) of the inverter circuit INV10 at the next stage is VLT (INV00)> VLT (INV10), the inverter circuit INV10 The output voltage greatly swings to the VSS potential side, that is, the low level side due to the inverting amplification action of the inverter circuit INV10. Conversely, if VLT (INV00) <VLT (INV10), the amplitude greatly increases toward the VDD potential, that is, the high level. The output amplitudes of the inverter circuits INV10 and INV11 are further amplified by the next-stage inverter circuits INV20 to INV30 and INV21 to INV31.
The output of the inverter circuit INV30 is output to the output terminal OUT through the CMOS switch selected by the selection signals Y0 and Y0 / and further through the amplifier circuit composed of the two-stage CMOS inverter circuits INV4 and INV5. After all, if VLT (INV00)> VLT (INV10), a low level is output to the output terminal OUT, and if VLT (INV00) <VLT (INV10), a high level is output to the output terminal OUT.
3) Next, the selection signal transitions, and X0 becomes low level (X0 / is high level) and X1 becomes high level (X0 / is low level). The inputs of the inverter circuits INV10 and INV11 are disconnected from the outputs of the preceding inverter circuits INV00 and INV01 when the CMOS switch provided at the input terminal is turned off by the high level of X1 (X0 / low level). The output is short-circuited by the CMOS switch, and the outputs of the inverter circuits INV10 and INV11 become the logic threshold value. If the relationship between the logic threshold value VLT (INV10) of the inverter circuit INV10 and the logic threshold value VLT (INV11) of the inverter circuit INV11 in the next stage is VLT (INV10)> VLT (INV20), the inverter circuit INV20 The output voltage greatly swings to the VSS potential side, that is, the low level side due to the inverting amplification action of the inverter circuit INV20. On the contrary, if VLT (INV10) <VLT (INV20), the output voltage of the inverter circuit INV20 greatly swings toward the VDD potential side, that is, the high level side due to the inverting amplification action of the inverter circuit INV20.
The output amplitudes of the inverter circuits INV20 and INV21 are further amplified by the inverter circuits INV30 and INV31 in the next stage. The output of the inverter circuit INV30 is output to the output terminal OUT through the CMOS switch selected by the selection signals Y0 and Y0 / and further through the two-stage CMOS inverter circuits INV4 and INV5.
In the end, if VLT (INV10)> VLT (INV20), a high level is output to the output terminal OUT, and if VLT (INV10) <VLT (INV20), a low level is output to the output terminal OUT. Here, the correspondence between the magnitude relationship before and after the logic threshold value of the CMOS inverter circuit and the value of the output terminal OUT is reversed in the cases 2) and 3). This is because the number of inverter circuits connected by the CMOS switch, that is, the number of stages of CMOS inverter circuits that amplify the logical threshold voltage difference is different.
4) Next, the selection signal transits, and X1 becomes low level (X1 / is high level) and X2 becomes high level (X2 / is low level). Similarly to the above, the inputs of the inverter circuits INV20 and INV21 are disconnected from the outputs of the previous inverter circuits INV10 and INV11 due to the off state of the CMOS switch, the respective inputs and outputs are short-circuited by the CMOS switch, and the outputs of the inverter circuits INV20 and INV21 Is a logical threshold.
Subsequent operations conform to 2) above.
5) Next, the selection signal transits, and X becomes a low level (X2 // is a high level) and X3 becomes a high level (X3 / is a low level). Similarly to the input of the inverter circuits INV30 and INV31, the CMOS switch is turned off, the outputs of the previous inverter circuits INV20 and INV21 are disconnected, the respective inputs and outputs are short-circuited by the CMOS switch, and the inverter circuits INV30 and INV31 are connected. Output becomes a logic threshold value. If the relationship between the logical threshold value VLT (INV30) of the inverter circuit INV30 and the logical threshold value VLT (INV4) of the inverter circuit INV4 in the next stage is VLT (INV30)> VLT (INV4), the inverter circuit INV4 The output voltage greatly swings to the VSS potential side, that is, the low level side due to the inverting amplification action of the inverter circuit INV5. Conversely, if VLT (INV30) <VLT (INV4), the amplitude greatly increases toward the VDD potential side, that is, the high level side.
Eventually, if VLT (INV30)> VLT (INV4), the output terminal OUT outputs a high level, and if VLT (INV30) <VLT (INV4), the output terminal OUT outputs a low level.
6) In the next and subsequent transitions, the selection signal Y0 is at the low level (Y0 / is the high level), Y1 is at the high level (Y1 / is the low level), and the operations according to the above 2) to 5) are performed. As a result, an identification number output of 4 × 2 = 8 bits is output.
This embodiment is characterized in that it serves as both an inverter circuit and an amplifier circuit for generating an identification number, and the identification number is serially output by a read operation. As a result, the circuit can be simplified, which is suitable for serially outputting an identification number from one terminal.
FIG. 48 shows a circuit diagram of another embodiment of the unit circuit used in the embodiment of FIG. In this embodiment, the above-described NBTI countermeasure is taken. In other words, the CMOS circuit for disconnecting the input terminal from the preceding circuit is added to the input terminal of the inverter circuit in addition to the CMOS switch for cascading the inverter circuits as described above when the identification number circuit is inactive. Is done. A P-channel MOSFET for supplying a power supply voltage to the input terminal is provided at the input end.
In the unit circuit of this embodiment, when the power-on signal PON is at low level, that is, when the power supply voltage is supplied and the identification number is not read from the identification number generation circuit, the signal PON is set to low level and the input terminal of each inverter circuit Is disconnected from the preceding circuit regardless of the selection signals X0, X0 /, etc., and the power supply voltage VDD is supplied by the P-channel MOSFET.
FIG. 49 is a circuit diagram showing still another embodiment of the identification number generating circuit according to the present invention. In this embodiment, the unit circuits shown in FIG. 46 are connected in tandem in one column, and a selection signal is formed by using a binary counter and a decoder. That is, the count-up clock is counted by the binary counter, the count output is supplied to the decoder provided corresponding to each unit circuit, and the selection signals X0 (X0 /) to Xn (Xn /) are sequentially supplied from the first stage circuit. Generate.
FIG. 50 is a circuit diagram showing still another embodiment of the identification number generating circuit according to the present invention. In this embodiment, the unit circuits shown in FIG. 46 are connected in series in one column, and a selection signal is formed using a shift register. That is, a shift register (for one stage) is provided corresponding to each unit circuit, and the selection signal is sequentially shifted so that the selection operation as described above is performed in order from the unit circuit of the first stage.
In any of the embodiments shown in FIG. 49 and FIG. 50, design, expansion, and mounting are facilitated by using one unit circuit surrounded by a broken line. In particular, in the embodiment circuit of FIG. 50, when the number of bits of the identification number is expanded, it is only necessary to connect three types of signal lines consisting of the column connection line, shift clock and reset of the unit circuit. Since the degree of freedom is high, it is suitable for soft IP as described later.
FIG. 51 is a circuit layout diagram showing one embodiment of a semiconductor integrated circuit device or a semiconductor chip to which the present invention is applied. This figure simulates a general system LSI chip. In the periphery of the chip, a normal I / O cell (input / output circuit) is provided, and the built-in circuit includes a plurality of circuits corresponding to the function of the system LSI. Are provided.
FIG. 52 shows a block diagram of a typical embodiment of the I / O cell, which is composed of an output buffer circuit, an input buffer circuit, and bonding pads (PADs) provided corresponding thereto. . The output buffer circuit and the input buffer circuit are controlled by an input / output control signal to perform an input operation or an output operation.
FIG. 53 shows a circuit layout diagram of an embodiment of an I / O cell provided in a semiconductor integrated circuit device or a semiconductor chip according to the present invention. In this embodiment, an output prebuffer circuit for driving the output MOSFET is provided. The output buffer circuit of FIG. 52 includes the output prebuffer circuit and an output MOSFET.
For wire bonding, the bonding PAD is formed with a relatively large occupation area. The output MOSFET, the output prebuffer circuit, and the input buffer circuit are laid out so as to conform to this. Thereby, I / O cells can be efficiently arranged in accordance with the pitch of the bonding pads.
As described above, since the I / O cell has a relatively large occupied area, 1-bit identification as shown in the above-described embodiment is shown by hatching a part of the output prebuffer circuit or the output MOSFET. A number generation circuit can be fitted.
FIG. 54 is a circuit diagram showing one embodiment of an output buffer circuit provided in the semiconductor integrated circuit device or the semiconductor chip according to the present invention. In this embodiment, the 1-bit identification number generating circuit is added to the output buffer circuit.
In this embodiment, when the identification number circuit enable signal is activated (the normal output enable is deactivated at that time), a 1-bit identification number is output from a buffer provided in parallel with the normal output buffer circuit. Since this buffer may have a small driving capability, a MOSFET having a size smaller than that of an output MOSFET of a regular circuit is sufficient. In this configuration, a special output terminal for outputting an identification number is not required, and an identification number consisting of multiple bits using a large number of input / output terminals or input / output pads provided on a semiconductor integrated circuit device or a semiconductor chip. Can be taken out.
FIG. 55 is a circuit diagram showing another embodiment of the output buffer circuit provided in the semiconductor integrated circuit device or the semiconductor chip according to the present invention. Also in this embodiment, the 1-bit identification number generating circuit is added to the output buffer circuit. In this embodiment, the identification number is output using a normal output buffer circuit. That is, a gate circuit is added to the output prebuffer circuit to selectively output a normal output and an identification number. The identification number circuit enable signal may be generated from a dedicated pin of the LSI or may be generated by a special DFT function. This also applies to the embodiment shown in FIG.
In recent years, the use of JTAG (Joint Test Action Group) in logic LSIs has spread. The JTAG standard also has a function called IDCODE that registers and reads LSI identification numbers. However, since the number of bits is as small as 32 bits and the bit configuration is finely defined so that each bit identifies a device, a manufacturer, etc., it cannot be used as an identification number of an individual chip.
FIG. 56 shows a schematic block diagram of an embodiment of a semiconductor integrated circuit device according to the present invention. In this embodiment, the identification number is output using the JTAG interface.
A JTAG-compatible device (semiconductor integrated circuit device) includes a boundary scan register, an instruction register, an option register, a bypass register, and a TAP controller that controls these in addition to the built-in logic for performing the original function of the semiconductor integrated circuit device. Built-in test logic.
A serial interface for inputting / outputting instructions to the test logic, test data, test result data, and the like is called TAP (Tset Access Port) and has five signal lines. The JTAG test is performed by controlling this signal line with an external host computer or the like.
FIG. 57 is a block diagram showing one embodiment of a JTAG cell basically of the semiconductor integrated circuit device according to the present invention. In this embodiment, a 1-bit identification number generation circuit is incorporated in a cell constituting a JTAG boundary scan register. The JTAG cell may be incorporated into the I / O cell shown in FIG. 51 or the like, or may be incorporated into the built-in logic.
By adding a circuit for switching and inputting the signal from the built-in logic and the identification information generated by the 1-bit identification number generation circuit to the cells of the boundary scan register, serial output using the shift operation of the boundary scan register is performed. Can be.
FIG. 58 is a block diagram for explaining an embodiment of the serial output operation of the identification number using the shift operation of the boundary scan register of the semiconductor integrated circuit device according to the present invention.
In this embodiment, there are three LSIs (A to C), and each of the JATG cells (boundary scan registers) is seven, seven, and nine. Numbers are attached. The figure shows an example of an operation of reading an identification number from an identification number generation circuit (ID-ROM) mounted on LSI-B as a representative.
State 1 is an initial state and shows an operation state in JTAG.
In the state 2, for example, the TDO of the LSI-B is disconnected from the JTAG cell by a JTAG private instruction, and connected to the identification number generation circuit ID-ROM instead.
In state 3, the identification number generation circuit ID-ROM performs a shift operation according to a JTAG shift instruction, and the identification numbers are sequentially output from the TDO. In the figure, a state in which 3-bit identification number information (I, II, III) is sent out is shown. The JTAG cell in each LSI is shifted to the right as usual, and the identification number of LSI-B is output through LSI-C.
After taking out this identification number, although not shown, the private instruction mode is returned to the normal automatic mode, and the TDO is connected to the JTAG cell.

However, cell information can be obtained by repeating the shift in normal mode after that if necessary.

FIG. 59 is a block diagram for explaining another embodiment of the serial output operation of the identification number using the shift operation of the boundary scan register of the semiconductor integrated circuit device according to the present invention. The difference from the embodiment of FIG. 58 is that in state 3, only the LSI-C JTAG cell is shifted. As a result, in the embodiment of FIG.

It can be assumed that ID-ROM information is inserted between LSI-B and LSO-C JTAG cell information.
FIG. 59 is a block diagram for explaining another embodiment of the serial output operation of the identification number using the shift operation of the boundary scan register of the semiconductor integrated circuit device according to the present invention. The identification number generation circuit (ID-ROM) of this embodiment corresponds to the identification number generation circuit shown in FIG.
State 1 is an initial state.
In state 2, for example, the information of the 1-bit identification number generation circuit is transferred to the LSI-B JTAG cell by a JTAG private instruction. At this time

Therefore, it is destroyed because it is replaced.
In state 3, the ID number of the ID-ROM is sequentially output from the TDO of LSI-B by a JTAG shift instruction.
FIG. 61 is a block diagram for explaining another embodiment of the serial output operation of the identification number using the shift operation of the boundary scan register of the semiconductor integrated circuit device according to the present invention. In this embodiment, a shift register (ID register cell) dedicated to the identification number is incorporated.
State 1 is an initial state.
In state 2, for example, the TDO of LSI-B is disconnected from the JTAG cell and connected to the head of a shift register dedicated to another number by a JTAG private instruction. Further, the head of the LSI-B JTAG cell is connected to the tail end of the shift register dedicated to the identification number. At the same time, the identification number is set in the shift register dedicated to the identification number.
In state 3, the ID number of the ID-ROM is sequentially output from the TDO of LSI-B by a JTAG shift instruction. At the same time, the LSI-A JTAG cell information is shifted into the LSI-B JTAG cell information and a shift register dedicated to the identification number.
Although not shown in the figure, the shift is continued, and after all the valid JTAG cell information of LSI-B is shifted out, the initial state is restored.
FIG. 62 shows a circuit diagram of still another embodiment of the identification number generating circuit according to the present invention. In this embodiment, identification information obtained by amplifying the logic threshold voltage difference between the CMOS inverter circuits INV1 and INV2 as described above is held in a latch circuit composed of a NAND gate circuit. That is, binary identification information corresponding to the logical threshold voltage difference between the inverter circuits INV1 and INV2 is input to the latch from the high level of the first write signal WRITE1.
Next, the first write signal WRITE1 is set to a low level so that the binary identification information is held in the latch circuit, and the inverter circuit array including the inverter circuits INV1, INV2 and the amplifier circuit includes an inverter circuit in the input stage. A high level formed by a pull-up MOSFET is supplied to the input of INV1.
Next, using the second write signal WRITE2 and the high voltage VPP, the information held in the latch circuit is written, for example, in a fuse (made of FUSE, EEPROM, etc.) nonvolatile programmable device. When the identification number is required, the programmable device is accessed by the signal RD and the written identification number is output as read data.
In this configuration, identification information corresponding to the logical threshold voltage difference between the inverter circuits INV1 and INV2 in the first write signal WRITE1 is recorded in another non-volatile circuit, and thus is affected by the NBTI as described above. Therefore, it is possible to obtain an identification number generation circuit that maintains the reproducibility of the identification bits and is highly resistant to changes over time.
In the identification number generation circuit using the variation of the logic threshold value of the CMOS inverter circuit as in the above embodiment, the order of the threshold value of each element is used as the source of identification information.
FIG. 63 and FIG. 64 show examples of four identification numbers. FIG. 63 is a graph showing the order of the threshold values. In FIG. 64, the identified numbered element (CMOS inverter circuit) has the highest order among the 16 elements. 10 is the lowest ranking. This means that the logic threshold value of element 1 is the highest and the logic threshold value of element 10 is the lowest. When attention is paid to the elements 1 and 10, the element closest to the element 1 is the element 5, and the element closest to the element 10 is the element 9.
In the identification number generation circuit according to the present invention, since the variation of the logic threshold value of the CMOS inverter circuit is ranked, for example, how much difference in the logic threshold voltage exists between the element 1 and the element 5 Is unknown. Similarly, it is unclear between the element 10 and the element 9. In addition, when the difference between them is extremely small, there is a possibility that the ranks of the element 1 and the element 5 are switched depending on test conditions. However, the possibility that the element 1 and the element 10 are interchanged is considered to be extremely low. It is easy to understand from the graph of FIG.
The identification number acquired at the time of collation is acquired at least once in the past and stored in the database, and should exist in a form very similar to the identification number. Similar to the above, the case where the identification number is not completely reproduced in the identification number generation circuit of the present invention due to the influence of the change with time or the like as described above is considered. As described above, even if the order of variations among CMOS inverter circuits is partially changed as described above, in the example of FIG. 64, at least the order of the element 1 and the element 10 is obtained in the past. In addition, it can be easily estimated that the size relationship of the latest identification number has not changed.
FIG. 65 is a flow chart for explaining one embodiment of a high-speed identification number collation (search) algorithm for the identification number generated by the identification number generation circuit according to the present invention. FIG. 66 shows a corresponding configuration diagram.
(1) In the step of reading the identification number, the 1-bit identification number generation circuit composed of “0” and “1” is continuous data generated from each.
(2) In the rank analysis step, the data is converted into a number representing the rank. That is, the rank of the 1-bit identification number generating circuit as shown in FIG. 64 is converted into a number.
(3) In the maximum / minimum element extraction step, the rank is analyzed, and the numbers of the maximum rank element and the minimum rank element are extracted and recorded.
In (4), one registered identification number is extracted from the management ledger.
In {circle over (5)}, the ranks of the element numbers corresponding to the maximum and minimum element numbers recorded above are extracted from the registered identification numbers. For example, in the example of FIG. 64, the identification number 1 has a maximum of 1 and a minimum of 10, but when the numbers 1 and 10 are compared, the magnitude relationship is reversed. This is a phenomenon in which the ranking far exceeds fluctuations due to variations and the like, so that the identification number can be easily estimated that identification number 1 is collected from a different chip. Therefore, it is determined that the identification number 1 is nonconforming, and the subsequent detailed verification check is omitted.
If it is determined to be suitable in the above, detailed inspection is performed in (6) and (7). Since it is basically the same as the above embodiment, it is omitted. The identification number with the highest similarity is set as a match candidate. In (5), since the ratio of the probability and the occurrence of non-conformity is 50% in the rank comparison, the effect of omitting the detailed inspection is almost 50%.
Thus, in this embodiment, one set of magnitude comparisons is made, but by making two sets, it can be expected that the above effect is further doubled. However, if this is increased, the size comparison process itself may increase and the effect may be reduced. Therefore, it is desirable to select the balance in consideration of the number of digits of the identification number and the total number of parameters of the identification number.
FIG. 67 is a flow chart showing one embodiment of a circuit design method for a semiconductor chip incorporating the identification number generating circuit according to the present invention. Circuit design software such as this embodiment is provided to design companies and manufacturing specialist companies. Alternatively, the same function is incorporated into an EDA vendor's tool.
(1) Pull down the menu and select it.
(2) Menu data is generated. After the second time, a desired IP can be selected simply by specifying this menu data.
(3) Analyze menu data and detect violations.
(4) Retrieve necessary information from the local database according to the menu data. The latest information that is not in the local database is obtained from a database of a manufacturing specialist company through a network such as the Internet.
(5) Based on information collected from the database, data necessary for the soft IP is generated.
(6) It is determined whether a soft IP can be generated. If not possible, choose a hard IP design.
FIG. 68 is a flowchart showing an embodiment of an LSI design method incorporating an identification number generating circuit according to the present invention. In this embodiment, although not particularly limited, it is directed to a design flow of an application specific LSI (ASIC).
The logic synthesis tool generates a gate-level logic circuit (net list) from the truth table, RTL description, state transition diagram, and the like based on the determination result of the soft IP generation in the design flow shown in FIG. Although not shown, in many cases, RTL or the like is generated based on a function description language such as VHDL or Verilog HDL. What is required for logic synthesis is cell library information, which includes transistor level connection information, delay information, layout information, and the like. In addition, information such as timing error tolerance, layout arrangement interval, and maximum signal wiring length called constraint information is added to normal RTL. The DFT tool adds diagnostic logic effective for LSI inspection to a gate level logic circuit, and creates final layout data by an automatic placement and routing tool.
The types of cells registered in the cell library are mainly the most basic circuit components such as an inverter, NAND (Nand), and flip-flop. In general, cell library data such as layout information is created manually. However, an automatic cell generation tool, a ram compiler, or the like may be used for a large-scale object or an object whose basic function does not change, such as a memory, but has a slightly different configuration.
Here, the hard IP and the soft IP in the present invention will be briefly described. Currently, in the semiconductor industry, especially in the LSI design and manufacture for specific applications, based on the specifications received from customers (for example, game consoles and automobile manufacturers), a comprehensive enterprise form that performs from design to manufacturing in one company, It is classified into a form divided by so-called LSI design companies specializing only in design and so-called foundry companies specializing in manufacturing.
In addition, recently, companies that take advantage of the division of labor (IP vendors), their distribution markets, standardization support organizations, etc. are born. IP has become an important factor in improving LSI design efficiency, and cannot be ignored even in a general company.
There are two types of IP called hard IP and soft IP. Compare the difference between the two cases when the division of labor between LSI design companies and foundry companies is targeted. LSI design companies (fabless companies) use functional description languages such as VHDL and Verilog HDL as shown in Fig. 68 based on customer specifications, data such as truth tables, RTL descriptions, state transition diagrams, and restrictions. Create information. However, there are cases in which the customer himself creates these data and passes them to an LSI design company.
Next, the LSI design company creates a netlist using the logic synthesis tool described at the beginning. In logic synthesis, the circuit elements used are limited to those registered in the cell library. They are certified by a manufacturing company that manufactures products, and the manufacturing companies generally provide the basics such as the inverter circuit and NAND gate circuit described above.
In practice, however, manufacturing specialists also offer more complex ones to increase their competitiveness. However, since it is difficult to prepare complex and high-performance circuits such as PLLs, SRAMs, and arithmetic circuits, for example, only by a manufacturing company, many IP vendors design and supply them. Among IPs, such as PLL, the circuit itself is complicated and the characteristics greatly depend on the process to be used. Therefore, IP vendors generally supply hard IP. The hard IP is simply a cell layout designed by an IP vendor registered in a cell library. Therefore, when supplying hard IP, hard IP vendors change their IP for each process generation, as well as manufacturing specialist companies, receive certification from the manufacturing company, and register with the cell library of each LSI design company. I have to get it.
On the other hand, in the case of soft IP, IP vendors use the above-mentioned function description languages such as VHDL and Verilog HDL, data such as truth tables, RTL descriptions, state transition diagrams, and constraint information as well as LSI design companies. Or just to the foundry company or customers above it. Therefore, in the market for LSIs for specific applications, the spread of soft IP is ahead, and its superiority will not change in the future. The ram compiler also automates the creation of cell library parts and is included in the category of hard IP.
As described above, the supply form using the hard IP is inferior in terms of the distribution and diffusion of the IP, and the hard IP supply side also has disadvantages such as a burden of design change for each process. On the other hand, the identification number generation circuit of this embodiment, particularly the circuit shown in FIGS. 49 and 50, is only an inverter and a pass transistor even at the heart of the circuit, and other circuits are standard logic elements. Since it is configured, soft IP implementation is relatively easy. For example, if a CMOS inverter circuit (of course) and a CMOS switch (pass transistor) are already registered in the cell library, an IP can be supplied to a design company with only an RTL description. If the pass transistor is not registered as a standard, it is necessary to newly register only the pass transistor, but the scale is extremely small.
In addition, the automatic placement and routing process has a weak point that the result of the placement and wiring is irregular. For example, two identification inverters may be arranged at extremely separated positions. Then, the wiring length of the signal P and the signal PP in the circuit diagram becomes long, and it becomes easy to be affected by noise from the periphery. In order to reduce this, it is effective to limit the arrangement and signal line length in the arrangement and wiring process. It is also effective to register only this part as a new cell by combining standard cells registered in the cell library. Rather, it is more efficient to create counters and decoders by automatic placement and routing.
In recent years, there are an increasing number of application examples in which an ID number and various kinds of unique information (hereinafter referred to as general information) are incorporated into an LSI. For example, it may be a product production line number, a production week number, a product grade, or production management information. These are generally programmed with an ID number using a laser fuse, EPROM or the like. In this program, of course, there should be no mistakes in the laser program, and the laser fuse method is almost processed in the wafer state, but it should not be changed in the processes after the laser process. It is even more important if the information is related to life and property.
However, if the chips are diced after programming and are separated one by one, the general information written at the time of laser programming can be read, but it is very difficult to check whether it is correct. There is. The following can be considered as countermeasures. One is to add a parity bit to detect data fluctuation. The function for parity check may be built in the chip or may be determined by a measuring instrument.
However, in a strict sense, the data written in the chip is not confirmed.
The other is a method of confirming duplication of information by creating a mechanism for recording general information read by some method in order to ensure the reliability of the read information. In this method, accidents of products can be prevented by treating all the worst duplicated chips as defective products. However, in reality, when read information of a plurality of chips overlaps, it is difficult to confirm which one is correct, and chip management and processing become complicated.
In other words, the essential solution to the above-mentioned problem is to identify a chip that has been separated once, know the correct information for that chip, and compare it with it.
Therefore, the idea of adding a unique identification number to the chip and obtaining the correct number from a database or the like based on the information can be considered, but even if it is written with the same laser fuse, it is only a mess.
On the other hand, according to information theory (for example, information theory: written by Yasuo Tsuji, published by Iwanami Shinsho), if the distance between codes (for example, Hamming distance) is large, the detection of changes in the original information even if there is noise on them Furthermore, it is well known that repair is possible (for example, error correction codes and their applications: edited by the Institute of Image Information Media, published by Ohm). Here, the sign is information written by the laser fuse, and the noise is equivalent to a part of the change.
That is, by adding a chip unique identification number having a large distance between codes to the unique information, even if a part of the entire information changes slightly, it can be sufficiently distinguished from other identification numbers, that is, chips. Therefore, it is effective to use the identification number generation circuit according to the present invention.
FIG. 69 is a flow chart showing one embodiment of a method of manufacturing a semiconductor integrated circuit device using a semiconductor chip with a built-in identification number generating circuit according to the present invention.
Information (hereinafter referred to as management information) in which general information and a unique identification number having a large distance between codes is combined with the chip is programmed into the laser fuse on the designated wafer. The unique identification number is generated by a built-in identification number generation circuit.
The general information and the unique identification number are stored and managed on the database as management information. The management information is composed of, for example, general information + chip identification number.
In the inspection process after assembling the semiconductor integrated circuit device or IC card, the management information is read out and the database is referenced to check whether there is the same management information. If the same management information exists in the database, it is determined that the laser program is correct. When the same management information is not found in the database, the most similar management information is extracted. Next, the general information of the read information and the extracted management information is compared.
At the time of reading, the general information part is read under a plurality of conditions such as changing the power supply voltage condition, and the unique identification number is read only once to check whether data writing is sufficiently stable in a short time. can do. During the test, it is necessary to collate with the management information on the database at high speed. For example, management information data that is referred to in advance before the inspection may be stored in a workstation or the like attached to the test apparatus.
By the above method, the program information can be confirmed quickly and accurately. Moreover, if the unique identification number is written one by one with a laser fuse or the like, the processing time and the chip area may be increased, but the chip identification number using variations in the CMOS inverter circuit logic threshold value according to the present invention By using the generation circuit, the unique identification number can be obtained easily and automatically.
That is, the chip identification number acquired by the probe inspection or the like and the information such as the lot and the wafer prior to the laser program are registered in the management information database. The management information corresponding to the instructed chip on the wafer is written into the laser fuse.
FIG. 70 is a flow chart showing one embodiment of an assembling process (so-called post process) of a semiconductor integrated circuit device using a semiconductor chip on which the identification number generating circuit according to the present invention is mounted.
(1) In the probe inspection, an ID number, a lot name, a wafer number, a chip number and the like by an identification number generation circuit are registered in a database.
(2) When a new ID number similar to the ID number already registered at the time of registration occurs, some warning is issued and the chip is treated.
(3) In the processes after the assembly test, since the chips are already separated in the dicing process, the ID number by the identification number generation circuit, the process number, and the process lot name are registered in the database.
(4) The ID number that can be acquired by the identification number generating circuit according to the present application may be changed by mechanical or thermal stress in the assembly process, electrical stress in the burn-in process, etc. Store the ID number in the database.
(5) When there is no need for chip tracking in the subsequent process, the ID number by the identification number generation circuit is acquired and registered in the database only in the final shipment selection process.
(6) In each test process, the acquired ID number information of the chip that has become defective is deleted or marked to reduce subsequent search processing time.
(7) In the marking process, a symbol or number indicating a line for manufacturing a product, and a year number or week number indicating a manufacturing time may be stamped. In identifying individual samples, these marks become information for search. Therefore, in the shipping selection 2, the ID number by the identification number generation circuit and these marking information are registered in the database. In chips having common marking information, the ID numbers generated by the identification number generation circuit need to be independent. However, chips having different marking information may be the same as or similar to the ID numbers generated by the identification number generation circuit. . That is, the identification number identification capability of the identification number generation circuit mounted on each chip can be suppressed, and the size of the identification number generation circuit and the number of bits of the identification number can be reduced.
(8) When an ID number is registered by an identification number generation circuit for each process, mixing / mixing of lots is detected based on the ID number, and some warning is issued.
In this embodiment, all processes and the database are directly connected online, but in reality, it is difficult to connect via a communication line due to location conditions, the communication speed is slow, batch processing is involved, etc. In such a situation, real-time performance is lacking. In such a case, it is temporarily stored in a local database. Furthermore, when immediacy is not necessary, it is stored in a storage medium and transported to a database or transported to the next process together with the actual product.
The format of data collected in the database may differ depending on the limitations of the test equipment and processing computer of each process. In such a case, a process for converting the data format may be inserted immediately before database registration.
FIGS. 71 and 72 are block diagrams showing an embodiment of a method for reducing the number of bits of the identification number generating circuit according to the present invention. FIG. 71 shows a registration method for reducing the number of bits of the identification number generation circuit, and FIG. 72 shows the verification method.
When a product such as a semiconductor integrated circuit device is shipped and becomes defective during use by a user, the identification number generation circuit according to the present invention functions effectively even when the product is returned and the cause of the failure is investigated. In this case, it is registered in a database that manages the identification number at the time of shipment, and if the product returns due to a defect, the data of the manufacturing process is investigated. At this time, it is necessary to check which control number the defective product is. If the number of products shipped is large, the following situation occurs.
The number of identification numbers that can be identified depends on the number of bits of the identification number generation circuit. If the number of bits is large, the accuracy of identification is improved, but the number of identification target data is increased accordingly. In identifying products, if the number of objects to be identified increases, it is necessary to read a large amount of data on a database and execute a collation operation for comparison and collation. Therefore, in order to reduce the time for the comparison process and the load on the system, information indicating the identification number group is separately defined as shown in FIG. As a result, the range of the number of collation data can be reduced as shown in FIG.
For the identification number group for reducing the number of bits of the identification number, information called general lots and marks is used. The combination of this information and the identification number can be managed so that the product can be managed uniquely. Further, in a database that only manages products after shipment, information on defective chips is deleted to reduce management costs. With this identification group, the number of verification targets can be reduced from the enormous amount of data on the database, and the processing time and system load can be reduced.
FIGS. 73 and 74 are block diagrams for explaining an inspection method using an identification number generation circuit mounted on a semiconductor integrated circuit device according to the present invention. FIG. 73 shows an identification number acquisition process, and FIG. 74 shows an inspection process.
At the stage near the end of the manufacturing process shown in FIG. 73, since the function of the identification number generation circuit can be used, an identification number acquisition step is provided before several inspection steps. Register the data required for the subsequent processes such as the number, control number, and product type in the database. However, the device is limited to a device that can perform a minimum operation regarding generation of an identification number.
In each subsequent inspection process shown in FIG. 74, first, the product identification number is read out and collated with the identification number on the database to obtain the management number. From this management number, the product type and inspection specification data are uniquely determined and transferred to the inspection apparatus. The inspection apparatus can inspect with the inspection specification given for each product. The advantage of this configuration is that in each inspection process, if the product type, inspection specification, or other accompanying data is given to the database only in the initial identification number acquisition process, it is not necessary to provide it in each subsequent inspection process or manufacturing process. Efficiency can be increased.
FIG. 75 is a block diagram for explaining a method for managing the correlation of characteristic data for each semiconductor chip in each inspection process using the identification number generating circuit mounted in the semiconductor integrated circuit device according to the present invention. Has been.
Characteristic data (measured values) obtained in each inspection process in semiconductor manufacturing is obtained in each process, but changes in the characteristic data may be analyzed. In order to manage these characteristic data, identification numbers are used, and characteristic data for each process is stored in a database for each chip. At this time, the identification number of the database is also updated with the identification number obtained in the latest process, and the change in the identification number due to the change in the operation of the circuit is taken into the database.
Conventionally, the correlation between the probe inspection and the finished product inspection has to be made by correlating a plurality of chips as a group for each lot. This time, it is possible to increase the accuracy of the analysis because it is possible to correlate the characteristic data changes between the processes for each chip.
FIG. 76 is a block diagram for explaining a method of automatically managing a wafer in a previous process using an identification number generating circuit mounted on a semiconductor integrated circuit device according to the present invention.
An identification number generating circuit for identifying a wafer is provided on the TEG. When the function is completed in the first wiring process, each wafer can be managed by the identification number. This eliminates the need to attach a management tag to the wafer, and eliminates the need to input information to a system that manages the wafer manufacturing process.
If the function of the identification number generation circuit is enabled and the manufacturing equipment / inspection equipment that processes the wafer in each subsequent process has an identification number reading mechanism, the database is accessed with the read identification number. Thus, it is possible to automatically set the wafer information in the apparatus. In addition, manufacturing conditions and inspection data when the wafer is processed can be automatically stored in a database.
The identification number reading mechanism can be configured by a board and software capable of reading a signal generation and an output (identification number) for causing a controllable power source and an identification number generation circuit to function from a personal computer. A probe for inputting / outputting signals to / from the TEG is also required.
FIG. 77 is a block diagram for explaining a method for storing / retrieving the identification number of the identification number generating circuit mounted on the semiconductor integrated circuit device according to the present invention.
In this embodiment, the search speed can be improved and the load on the system can be reduced by adopting a system in which the upper N bits of the identification number are taken out and stored in a table field on the database as an index. In a method of comparing the identification number to be compared with the identification number group in the database, first, the upper bits of the identification number to be compared are extracted, and the table is searched under a condition that matches this value with the index value on the database. Next, the identification number distance is obtained for each identification number group obtained here, and the smallest one is determined as the matching identification number. Thereby, it is possible to find out the corresponding data without comparing the identification numbers of all cases on the table.
FIG. 78 is a block diagram for explaining another example of the method for storing and retrieving the identification number of the identification number generating circuit mounted on the semiconductor integrated circuit device according to the present invention.
By adopting a method in which the search range of the identification number is limited and compared with the identification number group of the database, the search speed can be improved and the load on the system can be reduced. A table is searched using the comparison method of the identification number of the comparison target and the identification number group in the database, using the upper and lower limits of the allowable range due to fluctuation for the comparison target identification number as a database search condition. Next, the identification number distance is obtained for each identification number group obtained here, and the smallest one is determined as the matching identification number. Thereby, it is possible to find out the corresponding data without comparing the identification numbers of all cases on the table. If data cannot be retrieved because the upper limit / lower limit of the first allowable range is not met, the search process is performed again with the upper limit / lower limit relaxed.
FIG. 79 shows a block diagram of an embodiment of a semiconductor integrated circuit device relief method using the identification number generating circuit according to the present invention.
(1) Probe inspection of the main body chip is performed. By this inspection, relief data such as DRAM is sent to the host computer together with the identification number extracted from the identification number generation circuit.
(2) Dicing is performed to take out only a fully operational product and a repairable product.
(3) Conduct a probe test of EEPROM dedicated to relief data.
(4) Dice normal operation products and stock them.
(5) The main body LSI and the relief data dedicated EEPROM are mounted on the same module.
(6) The identification number of the main body LSI of the mounted module is read, and the corresponding relief data is written in the relief data dedicated EEPROM.
(7) Conduct a screening test.
(8) Non-defective LSIs are shipped, and defective LSIs that can be repaired again return to step (6), and the corresponding repair data is written in the repair data dedicated EEPROM.
As a result, the semiconductor integrated circuit device can be repaired easily and rationally.
In addition to the relief of the semiconductor integrated circuit device, the inspection cost using the identification number can be reduced. In a probe test performed when a semiconductor chip is formed on a half-wafer, for example, in a semiconductor chip such as a flash memory, the operation voltage is 3.0 V, 2.5 V, and 1.8 V with the same circuit function. Some produce different products as different varieties.
At this time, a test is performed with a voltage setting corresponding to 1.8 V to determine whether or not the memory operation is performed correctly. Voltage information for 1.8 V operation confirmation is recorded in the identification number of the semiconductor chip determined to be non-defective by this determination. The operation confirmation information is written and held in a nonvolatile manner in the semiconductor chip itself. Therefore, a management memory such as a flash memory is set in the semiconductor chip.
For a chip that becomes defective at 1.8V, the voltage is set to 2.5V to determine whether or not the memory operation is performed. Voltage information for 2.5 V operation confirmation is recorded in the identification number of the semiconductor chip determined to be good by this determination. And about the chip | tip which became defective at the said 2.5V, it is determined whether a memory operation | movement is performed by setting a voltage to 2.5V. The voltage information of 3.0V operation confirmation is recorded in the identification number of the semiconductor chip determined to be non-defective by this determination. A chip that becomes defective at 3.0V is discarded as a defective chip.
In this embodiment, for example, a semiconductor chip that operates at 1.8V can be operated at 2.5V or 3.0V without performing an operation test at 2.5V or 3.0V. It is treated as something. Similarly, a semiconductor chip that operates at 2.5V is treated as capable of operating at 3.0V without performing an operation test at 3.0V. For this reason, there is a possibility that a semiconductor chip that operates at 1.8V may become defective when operated at 2.5V or 3.0V, but the probability is small, so each voltage It is possible to reduce the manufacturing cost as a whole by shortening the test time by omitting the operation of the above.
Then, when assembling as a single flash memory or as a single semiconductor integrated circuit device in combination with a microprocessor or the like, the operating voltage information stored in the host computer is obtained from the identification number, and the appropriate ones are combined. . At this time, the semiconductor integrated circuit device operating at 2.5V can also use the 1.8V operation check chip, and the semiconductor integrated circuit device operating at 3.0V can use the 1.8V and 2.5V. Chips that operate on can also be used.
FIG. 80 is a layout diagram showing still another embodiment of a semiconductor integrated circuit device having an identification number generating circuit according to the present invention. FIG. 81 is a partially enlarged layout diagram of FIG. The semiconductor integrated circuit device shown in FIG. 80, like many general semiconductor integrated circuit devices, has a built-in circuit or an internal circuit arranged almost at the center of a semiconductor chip constituting the semiconductor integrated circuit device, and a signal of an external signal in the periphery. A configuration is adopted in which a plurality of input / output cells (I / O cells) for transmission and reception are arranged.
The four corners of the peripheral portion of the semiconductor chip are empty areas where no I / O cells are arranged, as in a general semiconductor integrated circuit device. In this embodiment, such an empty area is used, and one of them is provided with an identification number generating circuit CRNC.
The identification number generation circuit CRNC is coupled to the built-in circuit by a signal and power supply wiring layer formed on the semiconductor chip.
As will be described later, the signal and power supply wiring may be disconnected. For the convenience of such cutting, it is desirable that the number of such signal and power supply wiring layers is small. Therefore, in the embodiment, the wiring for the interface between the identification number generation circuit and the built-in circuit includes the power supply wiring (VDD, VSS) for the identification number generation circuit, the reset signal (RES), the clock signal (CLK), the identification It is composed of a small number of wirings such as three signal wirings for the number output signal (OUT). In the partially enlarged view of FIG. 81, the power supply lines VDD and VSS are displayed by relatively thick lines, and the signal lines for the reset signal and the clock signal identification number output signal are displayed by relatively thin lines. As is apparent from the drawing, the signal wiring is extended with a state substantially surrounded by the power supply wirings VDD and VSS. The identification number generation circuit CRNC is configured to be able to generate an identification number with the brute force method as in the above-described embodiment based on the reset signal and the clock signal. As shown in FIG. 81, the reset signal (RES), clock signal (CLK), identification number output signal (OUT) of the identification number output circuit (NC) are supplied to the power supply terminals VDD and VSS on the empty area around the identification number generation circuit CRNC. Connected electrode pads RES, CLK, OUT, VDD, and VSS are provided. These electrode pads are not external terminals of a semiconductor integrated circuit device configured by packaging a semiconductor chip with a package member such as a mold resin, and can be adapted to a contactor called a probe needle. Thus, it is configured on a semiconductor chip.
The identification number information from the identification number generation circuit CRNC shown in the figure passes through the normal path via the I / O cell if the path of the power supply line, built-in circuit, I / O cell, etc. of the semiconductor integrated circuit device is operable. Reading to the outside is enabled.
Here, it is desirable that the identification number information can meet many needs including a product history survey. In some cases, it is desirable that the identification number information be obtained from a semiconductor integrated circuit device that has become inoperable.
Unfortunately, when the semiconductor integrated circuit device is not operating normally due to an abnormal increase in power supply current or other various factors, the package member such as a mold resin is removed, and the semiconductor chip is exposed. The power source and signal wiring layer between the identification number generation circuit CRNC and the built-in circuit are cut and removed by a device such as a laser cutting device. As a result, the identification number generation circuit CRNC is connected to only the electrode pad. In other words, the circuit CRNC is free from internal wiring short-circuits, internal element destruction, etc. of the semiconductor integrated circuit device, and can be operated independently. Therefore, in this state, the contactor is brought into contact with the electrode pad, and the identification number information can be acquired through the contactor.
A chip size in which a semiconductor integrated circuit device is provided with a plurality of external terminals such as bump electrodes through a wiring layer such as an insulating layer having a purpose of stress relaxation and a relocation wiring on a semiconductor chip. In the case of taking a package form called a package or a chip scale package, the identification number information can be obtained in the same manner. In this case, when it is difficult to obtain identification number information via a normal external terminal, the bump electrode and the insulating layer are removed to expose the same electrode pad as described above and the wiring portion to be cut. After that, the identification number information is read through the electrode pad.
FIG. 82 is a block diagram of another embodiment of a semiconductor integrated circuit device provided with an identification number generating circuit according to the present invention, and FIG. 83 is a circuit diagram thereof.
The semiconductor integrated circuit device of this embodiment is of a so-called master slice type in which a semiconductor region constituting a MOSFET or the like is set as a fixed pattern and a circuit having a desired function is constituted by wiring. Among the I / O cells set on the semiconductor chip constituting the semiconductor integrated circuit device, an idle I / O cell, that is, an I / O cell that is not used for the function of the semiconductor integrated circuit device is an identification number generating circuit. It is supposed to constitute.
As shown in the figure, one I / O cell includes a region for an output control circuit having a relatively small area, a region for an output MOSFET having a relatively large area (output MOS), and an input / output pad electrode (I / O). OPAD) is arranged, and the whole forms a rectangular plane pattern as shown in the figure.
The area for the output control circuit is a relatively small area, but a relatively large number of sub-elements such as a gate circuit, an inverter circuit, and a MOSFET so that a desired output control circuit and input circuit can be configured. have. The area for the output MOSFET has a relatively small number of MOSFETs, such as one or two p-channel MOSFETs and one or two N-channel MOSFETs, but has a high external load driving capability. The area is relatively large.
The identification number generation circuit is constituted by sub-elements in the area for the output control circuit in the idle I / O cell. The identification number generation circuit can be configured in such a region by a relatively large number of sub-elements in the region for the output control circuit.
The P-channel MOSFET and N-channel MOSFET, inverter circuit, NAND circuit, and NOR circuit shown in FIG. 83 constitute a tristate output buffer circuit for outputting the output of the identification number generation circuit to the outside as a whole. ing. In such an output buffer circuit, the inverter circuit, the NAND circuit, and the NOR circuit are configured by sub-elements in the region for the output control circuit, and the output MOSFET is configured by a MOSFET in the region for the output MOSFET.
The output of the tristate output buffer circuit in the idle I / O cell is coupled to an input / output pad electrode (I / OPAD) provided in the cell. In other words, the illustrated input / output pad electrode is an output electrode dedicated to identification number information.
The input / output pad electrode is coupled to a vacant pin or a vacant terminal of the semiconductor integrated circuit device, which is usually referred to as an NC (Non Connection) pin in the semiconductor integrated circuit device.
According to this embodiment, the identification number generation circuit and the tri-state output buffer circuit are put into an operation state by setting the enable signal, which is marked as identification number circuit enable in the figure, to a significant level such as high level. The For the operation of the identification number generating circuit, a continuous clock signal labeled as an output clock in the figure is supplied. In response to such a continuous clock signal, identification number information is supplied to the input / output pad electrodes.
FIG. 84 is a block diagram of another embodiment of a semiconductor integrated circuit device provided with an identification number generating circuit according to the present invention. In this embodiment, in a large-scale semiconductor integrated circuit device as in recent years, an idle I / O cell is present from the viewpoint of power supply enhancement corresponding to an increase in current consumption and an increase in operation speed. However, it is considered that the cell region is diverted for power supply enhancement.
In the layout diagram of FIG. 84, three I / O cells are illustrated. Of these three I / O cells, the upper I / O cell in the drawing is an idle I / O cell, and the other I / O cell in the lower portion of the drawing is used to operate the semiconductor integrated circuit device. The normal I / O cell is used for operation.
In the idle I / O cell, a power pad electrode, that is, a pad electrode diverted to a power source or the like is provided in the input / output pad electrode region. The power pad electrode is coupled to a plurality of I / O cells or a power wiring layer (not shown) for a built-in circuit. It should be understood that the power supply wiring layer on the idle I / O cell is usually composed of an upper wiring layer made of metal in a wiring layer having a multilayer wiring structure.
In the idle I / O cell, in the portion corresponding to the region for the output control circuit of FIG. 81, the output by the wiring layer on the lower layer side in the multilayer wiring layer is equivalent to the example of FIG. An identification number generation circuit is configured to receive the clock signal and the identification number circuit enable signal and form an identification number output.
The output clock signal, the identification number circuit enable signal, and the wiring layer for outputting the identification number between the identification number generation circuit and the built-in circuit are provided so as to facilitate wiring cutting and terminal formation, which will be described later. The part uses a relatively upper wiring layer.
The output signal of the identification number generation circuit is supplied to an output selection circuit provided on the input side of a normal I / O cell set as an output cell.
Thus, the normal I / O cell set as the output cell outputs the normal output data supplied from the built-in circuit via the output selection circuit to the input / output pad electrode in the normal operation of the semiconductor integrated circuit device. .
When the identification number information is to be output, the normal I / O cell outputs the identification number information supplied from the identification number generation circuit via the output selection circuit to the input / output pad electrode.
FIG. 85 shows a reference potential terminal VSS referred to as a power supply terminal VDD and a ground terminal of the identification number generation circuit, a power supply wiring layer and a reference potential wiring layer extended over a plurality of I / O cells, This shows the bonding pattern. The power supply wiring layer VDD and the reference potential wiring layer VSS extending on the I / O cell have a relatively wide width under the intention of strengthening the power supply system. In this embodiment, as shown in FIG. 85, a branch wiring layer having a narrow width is provided for a relatively wide power supply wiring layer, and this thin branch wiring layer is used as a power supply wiring VDD for an identification number generating circuit. Combined with -V. The coupling between the reference potential wiring layer and the reference potential wiring VSS-V of the identification number generation circuit is similarly configured. This configuration prepares the separation as described below between the identification number generation circuit and the power supply wiring layer and the reference potential wiring layer.
When it is necessary to obtain identification number information from the identification number generation circuit regardless of an abnormality such as a short circuit between the power supply wiring layer and the reference potential wiring layer, as shown in FIG. The narrow branch wiring layer connected to the terminal VSS is cut by a technique such as a laser cutting technique or a focused ion beam (FIB) technique. At the same time, the signal line as described above between the identification number generation circuit and the built-in circuit is similarly cut.
Next, formation of an insulating film, formation of an opening for the insulating film, and selective formation of a conductive layer are performed by a known technique such as the FIB technique. As a result, a conductive region made of a new conductive layer is set in the power supply terminal VDD and the reference potential terminal VSS of the identification number generating circuit as shown in FIG. At the same time, a new conductive layer is set for the above signal line.
A contactor such as a probe needle is brought into contact with these conductive layers, the identification number generating circuit is operated, and identification number information is obtained.
FIG. 87 is a circuit diagram of another embodiment of a semiconductor integrated circuit device provided with an identification number generating circuit according to the present invention.
In this embodiment, two diode-connected MOSFETs Q1 and Q2, an identification number circuit power pad, an identification number dedicated output pad, an identification number only, as shown in the figure, for an identification number generating circuit configured in a semiconductor integrated circuit device. A clock pad and an identification number dedicated enable pad are provided.
When the semiconductor integrated circuit device can operate normally, the identification number generation circuit is provided with an operating voltage via the normal power supply terminal VDD, the normal power supply wiring, and the diode connection MOSFET Q1 of the semiconductor integrated circuit device, and is not shown in the drawing. In response to the clock signal and identification number enable signal from the circuit, the identification number information is output to the built-in circuit.
When power cannot be supplied to the identification number generation circuit via the normal terminals VDD and VSS− due to a short circuit abnormality between the normal power supply terminal VDD and the power supply wiring connected thereto and the normal reference potential terminal VSS and the reference potential wiring connected thereto. First, necessary voltages and signals are applied to the circuit via the various pads shown in the figure, and the circuit is operated. The diode-connected MOSFET Q1 performs a switching operation so as to be automatically turned off with respect to the power supply voltage applied to the circuit via the power pad for the identification number circuit and the MOSFET Q2. As a result, power can be supplied to the identification number generation circuit regardless of the abnormality of the regular power supply system.
The operational effects obtained from the above embodiments are as follows.
(1) In the process of manufacturing a semiconductor integrated circuit device, a plurality of identification elements having the same form are formed, and the mutual relationship between the physical quantities of the plurality of identification elements corresponding to the process variation is determined. By using it as the identification information unique to the circuit device, it is possible to identify individual semiconductor integrated circuit devices with a simple configuration.
(2) In addition to the above, the first identification information assigned to the identification element at the time of manufacturing the unique identification information, and the magnitude information of the physical quantities of the plurality of identification elements obtained by the determination By using it, the amount of information for identifying each individual semiconductor integrated circuit device can be reduced, so that the memory circuit for storing the identification information can be simplified and the determination time can be shortened.
(3) In addition to the above, the identification element is connected to an input terminal and an output terminal of a CMOS inverter circuit composed of an N-channel MOSFET and a P-channel MOSFET, and the logical threshold value is a physical quantity for comparing the magnitudes. As a result, since it can be constituted by a basic digital circuit such as a CMOS circuit, the range of applicable semiconductor integrated circuit devices can be widened without adding a special manufacturing process.
(4) In addition to the above, the operation voltage is applied to the CMOS inverter circuit only when the logical threshold voltage as a physical quantity is determined, so that the influence of deterioration of element characteristics can be reduced and stable. Thus, it is possible to obtain a highly reliable identification result.
(5) A plurality of identification elements having the same form are formed in the process of manufacturing a semiconductor integrated circuit device, a physical quantity corresponding to the process variation is determined, and the magnitude relationship between the physical quantities of the plurality of identification elements is determined. Based on the unique identification information, the stored manufacturing history is read out when a defect occurs in the semiconductor integrated circuit device, and the unique identification information is generated and stored together with the manufacturing history. By performing the above and feeding back to the above manufacturing process as necessary, it is possible to obtain an effect that a rational manufacturing system can be constructed.
(6) A plurality of identification elements having the same form are formed in the course of the manufacturing process of the semiconductor integrated circuit device constituting the first chip, and the first relationship is based on the mutual relationship between the physical quantities corresponding to the process variation. A unique identification information of the chip is generated, and a plurality of pieces of operation modification information are formed for a plurality of semiconductor integrated circuit devices constituting the first chip in accordance with respective electric characteristics, and the individual first chips By writing to the second chip corresponding to the identification information of, and assembling the first chip and the second chip and outputting the operation modification information toward the first chip based on the identification information of the first chip, The advantage is that a multi-chip semiconductor integrated circuit device can be efficiently manufactured without complicated chip management.
(7) In addition to the above, a memory device having a redundant circuit in the first chip and a defective address in the second chip can be used to increase the manufacturing yield with a simple structure. The effect that can be obtained is obtained.
(8) In addition to the above, when a failure occurs after further testing in a state where the first chip and the second chip are assembled, the second chip is removed and the semiconductor constituting the first chip The manufacturing yield can be improved by returning to the step where the plurality of other semiconductor integrated circuit devices of the integrated circuit device are integrated.
(9) In addition to the above, the first chip and the second chip are integrally sealed after sorting in the assembled state, thereby improving the manufacturing yield and improving the semiconductor integrated circuit device. The effect that size reduction is realizable is acquired.
(10) In addition to the above, by assembling the first chip and the second chip on a common mounting substrate, the removal of the second chip is simplified, and the above-mentioned failure can be re-established. The effect that it can be used effectively is obtained.
(11) By providing unique identification information based on the magnitude relationship between physical quantities corresponding to process variations of a plurality of identification elements formed in the same form during the manufacturing process of the semiconductor integrated circuit device, With this configuration, the identification information of each semiconductor integrated circuit device can be incorporated.
(12) In addition to the above, the individual identification information is obtained by using the unique identification information as the first identification information assigned to the identification element at the time of manufacture and the physical quantities of the plurality of identification elements as the magnitude relation rank information. Since the amount of information for identifying the integrated circuit device can be reduced, it is possible to simplify the memory circuit for storing the information and to speed up the determination operation.
(13) In addition to the above, the identification element is connected to an input terminal and an output terminal of a CMOS inverter circuit composed of an N-channel type MOSFET and a P-channel type MOSFET, and the logical threshold value is used as a physical quantity for size determination. Thus, since it can be constituted by a basic digital circuit such as a CMOS circuit, an effect of widening the range of applicable semiconductor integrated circuit devices without adding a special manufacturing process can be obtained.
(14) In addition to the above, as a circuit for connecting the input terminal and the output terminal of the CMOS inverter circuit and determining the magnitude of the logical threshold value, a switch is provided in each of the plurality of CMOS inverter circuits, and two each In this combination, the logic threshold voltage is supplied to the brute force common voltage comparison circuit and the determination is made, whereby an effect of realizing a high discrimination capability with a simple configuration can be obtained.
(15) In addition to the above, corresponding to each of the plurality of CMOS inverter circuits, a first switch that connects the input terminal and the output terminal, and a first switch that connects the common first circuit node and the input terminal. Two switches and a third switch for connecting the output circuit and the common second circuit node are provided, and a combination of the first to third switches makes one set of two CMOS inverter circuits between a plurality of inverter circuits. As a brute force, the input terminal and the output terminal of one of the CMOS inverter circuits are connected to obtain the first circuit node, and the voltage is supplied to the input terminal of the other CMOS inverter circuit. By using the logical threshold voltage of the inverter circuit as a reference voltage, an output signal for voltage comparison is obtained at the second circuit node, thereby simplifying the configuration. This produces an effect that the identification number can be generated in
(16) In addition to the above, by using the elements constituting the CMOS gate array for the CMOS inverter circuit and the first switch to the third switch, it is possible to obtain an identification number generating circuit only by wiring design. It is done.
(17) In addition to the above, by supplying the operating voltage only to the CMOS inverter circuit at the time of voltage determination as the physical quantity, the influence of deterioration of element characteristics can be reduced, so that a stable and highly reliable identification number is obtained. The effect that it can be obtained.
(18) A first switch for selectively short-circuiting the input terminal and the output terminal of the first inverter circuit, and a second inverter circuit in which the output terminal of the first inverter circuit is connected to the input terminal are provided, and an output signal thereof By providing a plurality of identification elements that are amplified by an amplifier circuit and incorporating an identification number circuit that generates an identification number based on an output signal from each identification element when the first switch is on, An effect is obtained that it is possible to identify individual semiconductor collector chips with a simple configuration.
(19) In addition to the above, if the inverter circuit is a CMOS inverter circuit, and the output signal of the second inverter circuit when the first switch is in an ON state is the high level side with respect to the logic threshold value, the amplifier circuit When the output signal of the second inverter circuit when the first switch is on is at the low level side with respect to the logic threshold value, the output signal of the amplifier circuit is received and the high level is received. By providing a latch circuit that forms a level and feeds back to the input terminal of the first inverter circuit during the feedback operation in which the first switch is turned off, the reproducibility of the identification number and the resistance to changes with time are provided. The effect that it can raise is acquired.
(20) In addition to the above, the amplifier circuit is a cascade connection circuit of a plurality of CMOS inverter circuits, and each of the input terminals of the CMOS inverter circuits constituting the first inverter circuit, the second inverter circuit, and the amplifier circuit. A third switch for providing a high-level voltage is provided, and a third switch is provided at each interconnection point of each inverter circuit row constituting the first inverter circuit or the amplifier circuit, and the identification number circuit is in an inoperative state. At the time, the second switch is turned on, the third switch is turned off, the first switch is turned on, and the second switch is turned off at the time of amplification of the identification information and the feedback operation, By turning on the third switch, the reproducibility of the identification number and the resistance to changes over time can be further enhanced. The effect of being able to be obtained.
(21) A first switch for short-circuiting the input terminal and the output terminal of each of the first inverter circuit and the second inverter circuit is provided, and the output terminal of the first inverter circuit is connected to the input terminal of the second inverter circuit. A first switch of the first inverter circuit using a plurality of identification elements including a second inverter circuit and an amplifier circuit including a third inverter circuit in which an output terminal of the second inverter circuit is connected to an input terminal. Is turned on, the first switch of the second inverter circuit is turned off, and the first identification information is obtained from the output signal of the amplifier circuit including the third inverter circuit when the second switch is turned on. Including the third inverter circuit when the first switch of the second inverter circuit is turned on and the second switch is turned off. By incorporating an identification number circuit that generates an identification number so as to obtain second identification information from the output signal of the amplifier circuit, it is possible to identify individual semiconductor integrated chips while simplifying the circuit. The effect that it can be obtained.
(22) In addition to the above, a plurality of circuit rows are provided so that a circuit row composed of the first inverter circuit and the second inverter circuit is lined up correspondingly with the first inverter circuit and the second inverter circuit. The same switch control signal is commonly supplied to the corresponding first switch, and one of the output signals of the second inverter circuit in a plurality of circuit rows is selected by the third switch, and the first stage circuit of the amplifier circuit is selected. By connecting to the input terminal of the 3rd inverter circuit to comprise, the effect that many identification information can be obtained efficiently is acquired.
(23) In addition to the above, the input terminals of the first inverter circuit and the second inverter circuit are provided with a fourth switch for cutting off the input signal and a fifth switch for supplying a high-level side voltage. When the numbering circuit is in a non-operating state, the fourth switch is turned off and the fifth switch is turned on, so that the reproducibility of the identification number and the resistance to change with time can be further improved. It is done.
(24) The input terminal and the output terminal of the first inverter circuit are short-circuited by the first switch, and a plurality of unit elements provided with the input terminal second switch of the first inverter circuit are connected via the second switch. A discriminating element string is formed in a column form, and the output terminal of the first inverter circuit corresponding to the final stage of the discriminating element string is connected to the input terminal of the amplifier circuit including the second inverter circuit, and the clock is counted. A decoder for decoding the count output of the binary counter is provided corresponding to the first switch and the second switch of each first inverter circuit of the identification element sequence, and the identification element sequence is provided corresponding to the count output of the binary counter. The first switch is sequentially turned on in order from the first stage circuit, and the second switch is turned off complementarily with the first switch. By incorporating an identification number circuit that obtains a plurality of identification information corresponding to each first inverter circuit of the identification element sequence from the output signal of the amplifier circuit and generates an identification number, each circuit can be simplified while simplifying the circuit. There is an effect that the semiconductor collector chip can be identified.
(25) The input terminal and the output terminal of the first inverter circuit are short-circuited by the first switch, and a plurality of unit elements each provided with the second switch at the input terminal of the first inverter circuit are connected via the second switch. And forming an identification element string in a vertical form, and connecting the output terminal of the first inverter circuit corresponding to the final stage of the identification element string to the input terminal of the amplifier circuit including the second inverter circuit, A shift register having a shift bit corresponding to the first switch and the second switch of each first inverter circuit of the element row is provided, and the identification element row is arranged in order from the first stage circuit in correspondence with the shift operation of the shift register. The switches are sequentially turned on, and the second switch is turned off in a complementary manner with the first switch, and the above-mentioned information is output by the output signal of the amplifier circuit including the third inverter circuit. By incorporating a plurality of identification information corresponding to each first inverter circuit in another element row and generating an identification number, it is possible to identify individual semiconductor collector chips while simplifying the circuit. The effect that it can be made is obtained.
(26) A first switch for selectively short-circuiting the input terminal and the output terminal of the first inverter circuit, and a second inverter circuit in which the output terminal of the first inverter circuit is connected to the input terminal are provided, and its output signal By providing a plurality of identification elements that are amplified by an amplifier circuit and incorporating an identification number circuit that generates an identification number based on an output signal from each identification element when the first switch is on, There is an effect that it is possible to identify individual semiconductor integrated circuit devices with a simple configuration.
(27) The input terminal and the output terminal of the first inverter circuit are short-circuited by the first switch, and a plurality of unit elements each provided with the second switch at the input terminal of the first inverter circuit are connected via the second switch. In this way, an identification element string is formed in a column form, the output terminal of the first inverter circuit corresponding to the last stage of the identification element string is connected to the input terminal of the amplifier circuit including the second inverter circuit, and the clock is A decoder for decoding the count output of the binary counter for counting is provided corresponding to the first switch and the second switch of each first inverter circuit of the identification element sequence, and the identification element sequence corresponding to the count output of the binary counter In order from the first stage circuit, the first switch is sequentially turned on, and the second switch is turned off in a complementary manner with the first switch. By incorporating an identification number circuit that obtains a plurality of identification information corresponding to each first inverter circuit of the identification element sequence from the output signal of the amplifier circuit and generates an identification number, it is possible to simplify each circuit while simplifying the circuit. Thus, it is possible to identify the semiconductor integrated circuit device.
(28) The input terminal and the output terminal of the first inverter circuit are short-circuited by the first switch, and a plurality of unit elements provided with the input terminal second switch of the first inverter circuit are connected via the second switch. A discriminating element string is formed in a column form, and the output terminal of the first inverter circuit corresponding to the final stage of the discriminating element string is connected to the input terminal of an amplifier circuit including a second inverter circuit, and the identifying element A shift register having shift bits corresponding to the first switch and the second switch of each first inverter circuit in the column is provided, and the first switch is arranged in order from the first stage circuit in correspondence with the shift operation of the shift register. Are sequentially turned on, and the second switch is turned off in a complementary manner to the first switch, and the identification is made by the output signal of the amplifier circuit including the third inverter circuit. It is possible to identify individual semiconductor integrated circuit devices while simplifying the circuit by incorporating a plurality of identification information corresponding to each first inverter circuit in the element sequence and generating an identification number. The effect that it can be made is obtained.
(29) In addition to the above, a test circuit conforming to the JTAG standard is further provided, and the identification number generated by the identification number circuit is output via an interface conforming to the JTAG standard. The diversion makes it possible to simplify the circuit.
(30) In addition to the above, the identification number circuit including the unit element, the first switch, and the second switch reduces the design cost by performing the circuit design and circuit layout using the soft IP technology. Can be obtained.
(31) The input terminal and the output terminal of the first inverter circuit are short-circuited by the first switch, and a plurality of unit elements each provided with the second switch at the input terminal of the first inverter circuit are connected via the second switch. And forming an identification element string in a vertical form, and connecting the output terminal of the first inverter circuit corresponding to the final stage of the identification element string to the input terminal of the amplifier circuit including the second inverter circuit, A shift register having a shift bit corresponding to the first switch and the second switch of each first inverter circuit of the element row is provided, and the identification element row is arranged in order from the first stage circuit in correspondence with the shift operation of the shift register. The switches are sequentially turned on, and the second switch is turned off in a complementary manner with the first switch, and the above-mentioned information is output by the output signal of the amplifier circuit including the third inverter circuit. A semiconductor integrated circuit in which a circuit design and a circuit layout are performed by using a soft IP technology for an identification number circuit that obtains a plurality of identification information corresponding to each first inverter circuit in another element row and generates an identification number. The effect that the manufacturing cost of the apparatus can be reduced is obtained.
The invention made by the inventor has been specifically described based on the embodiments. However, the invention of the present application is not limited to the embodiments, and various modifications can be made without departing from the scope of the invention. Nor. For example, a plurality of identification elements having the same form formed in the course of the manufacturing process of a semiconductor integrated circuit device may be the same resistance element or the same resistance value as that of the semiconductor integrated circuit device when the signal is electrically read out. A plurality of capacitors having a capacitance value may be formed, and process variations of the resistance value and the capacitance value may be extracted in the form of current or voltage and used as an identification number.
In addition to the lead width or pitch width of a semiconductor integrated circuit device, a plurality of straight lines having the same length or width are printed or stamped on the surface of a semiconductor package or the like, and variations in the width or pitch width are used. Various embodiments can be taken.
The resistor element exemplified above can be implemented without requiring a relatively complicated manufacturing process as in the CMOS structure of the embodiment. Examples of the resistance element include a polysilicon resistor configured by a semiconductor integrated circuit technology and a so-called diffused resistor configured by introducing a conductivity determining impurity into a single crystal silicon by a method such as a well-known ion implantation method. Semiconductor resistance and metal resistance composed of the same metal layer as the metal wiring layer can be studied. Among these resistors, the diffused resistors are suitable for obtaining specific information according to the characteristic variation from the point that it is easy to set an appropriate resistance value and the change with time of the resistance value is relatively small. .
The specific information corresponding to the resistance variation is, for example, a resistance-voltage conversion in which a predetermined bias current is passed through two resistance elements to be compared from time to time, and a voltage difference generated between the two resistances is determined at that time. It can be formed by a technique for comparison and determination, or can be formed by a technique for configuring a resistance bridge by a plurality of resistance elements and discriminating the output of the resistance bridge. The characteristic information corresponding to the resistance element can also be formed by a technique in which the resistance element is used as a resistance-current conversion element and the converted current is compared and determined in addition to the above technique. Furthermore, by making the resistance element a part of the oscillation frequency determination element of the oscillation circuit or the delay time determination element of the delay circuit, the characteristic variation of the resistance element can be used as frequency information or delay time information.
When the resistance element is a load element for the signal input MOSFET constituting the inverter, the information corresponding to the characteristic variation reflects both the characteristic variation of the resistance element and the characteristic variation of the signal input MOSFET. .
The specific information corresponding to the resistance variation is not necessarily formed only in the semiconductor integrated circuit device. If necessary, the semiconductor integrated circuit device is configured so that it can appropriately shift to the specific information forming mode, and a plurality of resistance elements in the semiconductor integrated circuit device are set in the semiconductor integrated circuit device under the mode. It can also be switch-coupled to an existing external terminal such as a signal input / output terminal. In this case, the specific information corresponding to the characteristic variation of the resistance element is formed by a circuit device outside the semiconductor integrated circuit device coupled to the external terminal. In this case, an increase in the number of circuit elements in the semiconductor integrated circuit device can be suppressed, and the number of external terminals can be reduced by using existing terminals of the semiconductor integrated circuit device.
The leakage currents of a plurality of circuits having the same configuration or circuit elements such as MOSFETs are also empirically grasped as maintaining the characteristic variation permanently. The leak current level can be detected by current-voltage conversion and voltage comparison, similarly to the characteristic variation of the resistance element. What forms the leakage current may be circuits having the same configuration as described above, or may be a MOSFET in which the gate and the source are connected.
As a suitable leak current source for specific information, a signal output buffer circuit connected to a signal output external terminal or a signal input / output external terminal of a semiconductor integrated circuit device can be listed. This is because such a signal output buffer has a relatively large circuit element such as a MOSFET constituting the signal output buffer, often forms a relatively large leakage current, and is relatively easy to measure. This is because existing external terminals can be used as they are.
The withstand voltage characteristic of an element such as an input protection diode in the semiconductor integrated circuit device connected to the external signal input terminal of the semiconductor integrated circuit device can also be a source of specific information as described above corresponding to micro variations. Even when a plurality of external terminals of a semiconductor integrated circuit device constitute a bus line having a relatively small number of bits in an electronic system, the number of external terminals is significantly increased by the brute force comparison method as described above. It is possible to form information that can be appropriately identified.
The capacitance such as the drain junction capacitance of the MOS transistor in the semiconductor integrated circuit device coupled to the external terminal of the semiconductor integrated circuit device has a micro variation. Therefore, it can also be a source of the specific information as described above corresponding to the variation.
The information retention time in the dynamic memory also shows micro variations. In this case, even if a special configuration is not added to the dynamic memory, that is, a configuration for forming unique identification information is not set, a plurality of memory addresses in a plurality of specific memory addresses among a plurality of memory addresses are set. It is possible to measure the information holding time of the memory cell and use it as specific information based on the measurement result.
When multiple semiconductor chips are provided on a common substrate as in a multi-chip module, a unique identification circuit is set for each semiconductor chip, and unique identification information from each semiconductor chip is passed through the common substrate. It is also possible to be able to take it out. When there are restrictions on the number of terminals required for the common substrate for reading out the unique identification information of each semiconductor chip, a parallel-serial conversion circuit for unique identification information together with a chip selection control circuit for each semiconductor chip May be set. At this time, the unique identification information in each semiconductor chip is serialized by the parallel-serial conversion circuit in the selected state of the chip, output from each semiconductor chip, and read through the common substrate. When a program dedicated chip in the sense as shown in FIG. 33 is provided, the program dedicated chip may be configured to be compatible with a plurality of different types of semiconductor chips on a common substrate.
Industrial applicability
The present invention relates to a semiconductor integrated circuit device or semiconductor chip identification method and a semiconductor integrated circuit in which identification information unique to the semiconductor integrated circuit device or semiconductor chip is assigned to identify each semiconductor integrated circuit device or semiconductor chip. The present invention can be widely used in device manufacturing methods, semiconductor integrated circuit devices, and semiconductor chips.
[Brief description of the drawings]
FIG. 1 is a basic circuit diagram showing an embodiment of an identification number generating circuit according to the present invention.
FIG. 2 is a basic circuit diagram showing another embodiment of the identification number generating circuit according to the present invention.
FIG. 3 is a basic circuit diagram showing another embodiment of the identification number generating circuit according to the present invention.
FIG. 4 is an explanatory diagram of the operation of the identification number generation circuit of FIG. 3,
FIG. 5 is a basic circuit diagram showing another embodiment of the identification number generating circuit according to the present invention.
FIG. 6 is an equivalent circuit diagram for explaining the embodiment circuit of FIG.
FIG. 7 is a circuit diagram showing a specific embodiment corresponding to the embodiment of FIG.
FIG. 8 is a timing chart for explaining the operation of the embodiment circuit of FIG.
FIG. 9 is an explanatory view of the operation of the embodiment circuit of FIG.
FIG. 10 is a modification showing an embodiment of a unit circuit composed of a CMOS inverter circuit and a switch MOSFET which are the core of the identification number generation circuit according to the present invention.
FIG. 11 is a modification showing another embodiment of the unit circuit composed of the CMOS inverter circuit and the switch MOSFET which are the core of the identification number generating circuit according to the present invention,
FIG. 12 is a modification showing another embodiment of the unit circuit composed of the CMOS inverter circuit and the switch MOSFET which are the core of the identification number generating circuit according to the present invention,
FIG. 13 is a modification showing another embodiment of the unit circuit composed of the CMOS inverter circuit and the switch MOSFET which are the core of the identification number generating circuit according to the present invention,
FIG. 14 is a modification showing another embodiment of the unit circuit composed of the CMOS inverter circuit and the switch MOSFET which are the core of the identification number generating circuit according to the present invention,
FIG. 15 is a modification showing another embodiment of the unit circuit composed of a CMOS inverter circuit and a switch MOSFET which are the core of the identification number generating circuit according to the present invention,
FIG. 16 is a circuit diagram showing an embodiment of a CMOS inverter circuit used in the identification number generating circuit according to the present invention.
FIG. 17 is a circuit diagram showing another embodiment of the identification number generating circuit according to the present invention.
FIG. 18 is a waveform diagram for explaining the operation of the embodiment circuit shown in FIG.
FIG. 19 is a block diagram showing another embodiment of the identification number generating circuit according to the present invention.
FIG. 20 is a circuit diagram showing another embodiment of the identification number generating circuit according to the present invention.
FIG. 21 is a schematic block diagram showing one embodiment of a semiconductor integrated circuit device according to the present invention.
FIG. 22 is an element layout diagram showing one embodiment of a semiconductor integrated circuit device according to the present invention.
FIG. 23 is an equivalent circuit diagram corresponding to FIG.
FIG. 24 is a block diagram showing an embodiment when the present invention is applied to a dynamic RAM,
FIG. 25 is a schematic block diagram showing an embodiment of a semiconductor integrated circuit device using the identification number generating circuit according to the present invention,
FIG. 26 is an explanatory view for explaining an identification number identification algorithm according to the present invention.
FIG. 27 is an explanatory diagram for explaining an identification number identification algorithm according to the present invention,
FIG. 28 is a block diagram showing an embodiment of a collation algorithm registration method in the identification system for a semiconductor integrated circuit device according to the present invention;
FIG. 29 is a block diagram showing an embodiment of a collation algorithm collation method in the semiconductor integrated circuit device identification system according to the present invention;
FIG. 30 is an explanatory diagram showing an example of the comparison method of FIG. 29;
FIG. 31 is an explanatory diagram showing an example of a comparison method in the case of using the logic threshold level of the CMOS inverter circuit.
FIG. 32 is an explanatory view showing an example of a comparison method in the case of using the logic threshold level of the CMOS inverter circuit;
FIG. 33 is a block diagram showing an embodiment of a semiconductor integrated circuit device to which the present invention is applied.
FIG. 34 is a block diagram showing an embodiment of a multichip module to which the present invention is applied.
FIG. 35 is a block diagram showing an embodiment of the program dedicated chip of FIG.
FIG. 36 is a block diagram for explaining a manufacturing process of an embodiment of a semiconductor integrated circuit device on which the identification number generating circuit according to the present application is mounted;
FIG. 37 is a block diagram for explaining the manufacturing process of one embodiment when assembling a semiconductor integrated circuit device mounted with an identification number generating circuit according to the present application on a circuit mounting board;
FIG. 38 is a block diagram for explaining a manufacturing process of another embodiment of the semiconductor integrated circuit device on which the identification number generating circuit according to the present application is mounted;
FIG. 39 is a block diagram showing an example of an application specific LSI provided with an identification number generating circuit according to the present invention;
FIG. 40 is a circuit diagram showing an embodiment in which the variation in the logic threshold value of the CMOS inverter according to the present invention is applied to a random number generator;
FIG. 41 is a block diagram for explaining an example of use of a chip identification number generation circuit according to the present invention for the purpose of reducing fraud and various troubles in the electronic parts procurement market between companies.
FIG. 42 is a schematic plan view showing another embodiment of the semiconductor integrated circuit device according to the present invention.
FIG. 43 is a basic circuit diagram showing another embodiment of the identification number generating circuit according to the present invention.
FIG. 44 is a circuit diagram showing another embodiment of the identification number generating circuit according to the present invention.
FIG. 45 is a specific circuit diagram showing an embodiment of an identification number generating circuit according to the present invention.
FIG. 46 is a specific circuit diagram showing still another embodiment of the identification number generating circuit according to the present invention.
FIG. 47 is a timing chart for explaining the operation of the embodiment circuit of FIG.
FIG. 48 is a circuit diagram showing another embodiment of the unit circuit used in the embodiment of FIG.
FIG. 49 is a circuit diagram showing still another embodiment of the identification number generating circuit according to the present invention.
FIG. 50 is a circuit diagram showing still another embodiment of the identification number generating circuit according to the present invention.
FIG. 51 is a circuit layout diagram showing one embodiment of a semiconductor integrated circuit device or a semiconductor chip to which the present invention is applied;
FIG. 52 is a block diagram showing a typical embodiment of the I / O cell,
FIG. 53 is a circuit layout diagram showing one embodiment of an I / O cell provided in a semiconductor integrated circuit device or a semiconductor chip according to the present invention.
FIG. 54 is a circuit diagram showing one embodiment of an output buffer circuit provided in the semiconductor integrated circuit device or semiconductor chip according to the present invention;
FIG. 55 is a circuit diagram showing another embodiment of the output buffer circuit provided in the semiconductor integrated circuit device or semiconductor chip according to the present invention;
FIG. 56 is a schematic block diagram showing an embodiment of a semiconductor integrated circuit device according to the present invention.
FIG. 57 is a block diagram showing one embodiment of a basic JTAG cell of the semiconductor integrated circuit device according to the present invention.
FIG. 58 is a block diagram for explaining an embodiment of the serial output operation of the identification number using the shift operation of the boundary scan register of the semiconductor integrated circuit device according to the present invention,
FIG. 59 is a block diagram for explaining another embodiment of the serial output operation of the identification number using the shift operation of the boundary scan register of the semiconductor integrated circuit device according to the present invention.
FIG. 60 is a block diagram for explaining another embodiment of the serial output operation of the identification number using the shift operation of the boundary scan register of the semiconductor integrated circuit device according to the present invention.
FIG. 61 is a block diagram for explaining another embodiment of the serial output operation of the identification number using the shift operation of the boundary scan register of the semiconductor integrated circuit device according to the present invention,
FIG. 62 is a circuit diagram showing still another embodiment of the identification number generating circuit according to the present invention.
FIG. 63 is an explanatory diagram of an identification number according to the present invention,
FIG. 64 is an explanatory diagram of an identification number according to the present invention,
FIG. 65 is a flow chart for explaining one embodiment of a high-speed identification number collation (search) algorithm for the identification number generated by the identification number generation circuit according to the present invention;
FIG. 66 is a block diagram corresponding to the embodiment of FIG.
FIG. 67 is a flowchart showing one embodiment of a circuit design method for a semiconductor chip incorporating an identification number generation circuit according to the present invention;
FIG. 68 is a flowchart showing an embodiment of an LSI design method incorporating an identification number generation circuit according to the present invention;
FIG. 69 is a flowchart showing one embodiment of a method of manufacturing a semiconductor integrated circuit device using a semiconductor chip with a built-in identification number generation circuit according to the present invention.
FIG. 70 is a flow chart showing one embodiment of a process for assembling a semiconductor integrated circuit device using a semiconductor chip equipped with an identification number generating circuit according to the present invention.
FIG. 71 is a block diagram showing an embodiment of a method for reducing the number of bits of the identification number generating circuit according to the present invention,
FIG. 72 is a block diagram showing an embodiment of a method for reducing the number of bits of the identification number generating circuit according to the present invention,
FIG. 73 is a block diagram for explaining an inspection method using an identification number generation circuit mounted on a semiconductor integrated circuit device according to the present invention;
FIG. 74 is a block diagram for explaining an inspection method using an identification number generation circuit mounted on a semiconductor integrated circuit device according to the present invention;
FIG. 75 is a block diagram for explaining a method of managing the correlation of characteristic data for each semiconductor chip in each inspection process using the identification number generation circuit mounted in the semiconductor integrated circuit device according to the present invention;
FIG. 76 is a block diagram for explaining a method of automatically managing a wafer in a previous process using an identification number generation circuit mounted on a semiconductor integrated circuit device according to the present invention;
FIG. 77 is a block diagram for explaining a method for storing / retrieving the identification number of the identification number generating circuit mounted on the semiconductor integrated circuit device according to the present invention;
FIG. 78 is a block diagram for explaining another example of the method for storing and retrieving the identification number of the identification number generating circuit mounted on the semiconductor integrated circuit device according to the present invention;
FIG. 79 is a block diagram showing an embodiment of a semiconductor integrated circuit device relief method using the identification number generation circuit according to the present invention;
FIG. 80 is a layout diagram showing one embodiment of a semiconductor integrated circuit device equipped with an identification number generating circuit according to the present invention;
FIG. 81 is a partially enlarged layout diagram of the layout diagram of FIG.
FIG. 82 is a layout diagram showing another embodiment of a semiconductor integrated circuit device equipped with an identification number generating circuit according to the present invention,
FIG. 83 is a circuit diagram corresponding to the layout of FIG.
FIG. 84 is a block diagram showing still another embodiment of a semiconductor integrated circuit device equipped with an identification number generating circuit according to the present invention.
FIG. 85 is a partial plan pattern diagram of the semiconductor integrated circuit device constituting the embodiment of FIG.
FIG. 86 is another partial plane pattern diagram of the semiconductor integrated circuit device constituting the embodiment of FIG.
FIG. 87 is a circuit diagram showing one embodiment of a semiconductor integrated circuit device equipped with an identification number generating circuit according to the present invention.

Claims (57)

An identification information generation circuit including a plurality of identification elements formed in the same form in the semiconductor and manufactured through the same manufacturing process is attached to the integrated circuit device,
The identification information generation circuit performs a process of comparing information reflecting the physical quantity of each identification element in an operating state and generating one unique information based on the comparison result.
The information reflecting the physical quantity of the plurality of identification elements reflects the mutual variation of the physical quantity generated between the identification elements in the manufacturing process, and the result of mutual comparison of the information reflecting the physical quantity having the mutual variation An identification method for an integrated circuit device, wherein the one unique information generated based on the method is set as unique identification information for the integrated circuit device.   2. The integrated circuit device identification method according to claim 1, wherein the plurality of identification elements are set in the integrated circuit device.   N pieces of the plurality of identification elements are formed, and numbers 1 to N are assigned to the N pieces of identification elements, and the information reflecting the physical quantity read from each of the plurality of identification elements is large. 3. The integrated circuit device identification method according to claim 1, wherein the arrangement of the numbers when arranged in order or in ascending order is set as the identification information.   The plurality of identification elements are each composed of logic circuits formed in the same form, and each piece of information reflecting the physical quantity is an electrical characteristic of each logic circuit. The identification method of the integrated circuit device of description.   5. The integrated circuit according to claim 4, wherein each of the plurality of logic circuits has an input and an output electrically coupled, and outputs an output voltage equal to a threshold voltage to each output. Circuit device identification method.   6. The method for identifying an integrated circuit device according to claim 4, wherein each of the plurality of logic circuits comprises an inverter circuit.   7. The integrated circuit device identification method according to claim 6, wherein each of the identification elements comprises a CMOS inverter circuit composed of an N-channel MOSFET and a P-channel MOSFET.   8. The integrated circuit device according to claim 4, wherein application of an operating voltage is restricted to the logic circuit when the electrical characteristic comparison / determination operation is not performed. Identification method.   The unique identification information is stored in an information holding device together with management information related to the integrated circuit device in a manufacturing process of the integrated circuit device, and then the unique identification information is generated by operating the identification information generation circuit. 9. The integrated circuit device identification method according to claim 1, wherein the management information is searched using the generated identification information. A method of manufacturing an integrated circuit device, which enables inquiry of manufacturing information specific to the integrated circuit device, comprising:
The integrated circuit device has an identification information generation circuit including a plurality of identification elements formed in the same form on the semiconductor substrate and manufactured through the same manufacturing process.
One unique generation generated based on a result of mutual comparison of information reflecting physical quantities of the plurality of discriminating elements which are varied by operating the identification information generating circuit at one time of the manufacturing process of the integrated circuit device. Generating information as first information,
Management information related to the manufacture of the integrated circuit device is held in an information holding device outside the integrated circuit device in association with the first information,
The identification information generating circuit is operated at a time different from the one time, and one unique information generated based on the mutual comparison result of the information reflecting the physical quantities of the plurality of identification elements having a variation is obtained. It is possible to inquire about the management information held in the information holding device in association with the first information by using the fact that the second information is associated with the first information. A method of manufacturing an integrated circuit device, comprising: A plurality of unit regions each including a circuit that realizes a required function and a plurality of identification elements that have the same form and are manufactured through the same manufacturing process, each being a first chip when separated from each other Forming the unit region on a semiconductor substrate;
Obtaining unique identification information corresponding to each of the unit regions based on information reflecting the physical quantities of the plurality of identification elements for each of the plurality of unit regions;
Separating each of the plurality of unit regions to produce a plurality of the first chips;
Preparing a plurality of second chips in which operation modification information related to the integrated circuit formed on the first chip is written in association with the corresponding unique identification information;
Assembling each of the first chip and the second chip integrally,
In the integrally assembled body obtained in this way, the assembled second chip uses the operation modification information as the first chip based on the unique identification information obtained from the first chip assembled integrally therewith. A method for manufacturing an integrated circuit device, characterized in that the circuit is configured to output toward   The unique identification information is generated based on an intercomparison result of information reflecting physical quantities of the plurality of identification elements that are formed in the first chip and are mutually varied. Item 12. A method for manufacturing an integrated circuit device according to Item 11.   The information obtained by mutual comparison of the information reflecting the physical quantities of the plurality of identification elements is the physical quantities of the other plurality of identification elements for the information reflecting the physical quantities of the individual identification elements in the first chip. 13. The method of manufacturing an integrated circuit device according to claim 12, wherein the method is based on comparison information obtained by comparison with information reflecting the above.   The plurality of identification elements are formed N in the first chip, and the numbers of 1 to N are assigned to the N identification elements, and reflect the physical quantities of the plurality of identification elements. 14. The method of manufacturing an integrated circuit device according to claim 11, wherein the information is arrangement order information of the numbers when the information is arranged in order of increasing or decreasing order. The first chip is a memory having a redundant circuit,
15. The method of manufacturing an integrated circuit device according to claim 11, wherein the second chip stores a defective address of the first chip as the operation modification information. An integrated circuit device having unique identification information,
The integrated circuit device is formed with an identification information generation circuit including a plurality of identification elements formed in the semiconductor in the same form through the same manufacturing process.
The identification information generation circuit, when in an operating state, has one unique information based on a mutual comparison of information reflecting physical quantities of the plurality of identification elements having characteristic variations occurring between the plurality of identification elements during the manufacturing process. Which generates
An integrated circuit device, wherein the generated information is set as identification information of the integrated circuit device.   The unique identification information is composed of a plurality of pieces of contrast information obtained by comparing information reflecting the physical quantities of each identification element and information reflecting the physical quantities of other plurality of identification elements, respectively. The integrated circuit device according to claim 16. The unique identification information includes a plurality of pieces of contrast information corresponding to each of the plurality of identification elements,
Each of the plurality of pieces of contrast information is composed of a plurality of bits of information in which the magnitudes of information reflecting the mutual physical quantities of the corresponding specific identification elements and the plurality of identification elements contrasted with each other are compared. The integrated circuit device according to claim 17.   Each of the plurality of pieces of comparison information is data-converted with respect to information obtained from a direct comparison between information reflecting the physical quantity of the specific identification element and information reflecting the physical quantity of the plurality of identification elements to be compared with the information. The integrated circuit device according to claim 18, wherein   20. The integrated circuit device according to claim 18, wherein each of the plurality of pieces of contrast information includes information compressed in number of bits.   18. The integrated circuit device according to claim 17, wherein the comparison information includes a plurality of pieces of rank information corresponding to each of the plurality of identification elements.   17. The integrated circuit device according to claim 16, wherein the unique identification information includes rank information that reflects a rank order of physical quantities of the plurality of identification elements.   23. The integrated circuit device according to claim 20, wherein the comparison information is configured with a bit number smaller than the number of comparisons between the specific identification element and a plurality of identification elements corresponding to the specific identification element. . A plurality of identification elements that are manufactured in the same semiconductor as the same form through the same manufacturing process, and have different physical quantities due to variations that occur in the manufacturing process,
An identification information generation circuit that compares information reflecting each physical quantity of the plurality of identification elements with each other and generates identification information based on the mutual comparison results;
Means for controlling the operation / non-operation of the identification information generating circuit;
An integrated circuit device configured to include: An integrated circuit device in which a circuit for realizing a required function is formed,
The integrated circuit device includes a plurality of identification elements that are manufactured in the same semiconductor in the same form through the same manufacturing process and have different physical quantities due to variations generated in the manufacturing process, and the plurality of identifications A means for comparing information reflecting each physical quantity of the elements with each other and generating identification information based on the result of the mutual comparison;
An integrated circuit device configured to set unique information generated when the identification information generating circuit is operated as identification information unique to the integrated circuit device.   26. The integrated circuit device according to claim 25, wherein the identification information generating circuit is formed in a semiconductor substrate on which a circuit for realizing the required function is formed.   The identification elements are each composed of a logic circuit, and information generated based on the magnitude relationship of information reflecting the electrical characteristics of each of the logic circuits is set as the identification information as information reflecting the physical quantity. 27. The integrated circuit device according to claim 24.   28. The integrated circuit device according to claim 27, wherein each of the plurality of logic circuits has an input and an output electrically coupled to output an output voltage equal to a threshold voltage of the logic circuit.   29. The integrated circuit device according to claim 27, wherein the plurality of logic circuits are inverter circuits.   30. The integrated circuit device according to claim 27, wherein each of the plurality of identification elements includes a CMOS inverter circuit including an N-channel MOSFET and a P-channel MOSFET.   31. The integrated circuit device according to claim 30, wherein each of the CMOS inverter circuits constituting the identification element generates the output voltage by connecting an input terminal and an output terminal thereof. A plurality of identification elements that are manufactured in the same semiconductor in the form of the same CMOS inverter circuit through the same manufacturing process and have different electrical characteristics due to variations that occur in the manufacturing process;
A voltage comparison circuit;
A first switch is provided for each of the CMOS inverter circuits, and transmits the output voltage of the corresponding CMOS inverter circuit to one input terminal of the voltage comparison circuit, and to the other input terminal of the voltage comparison circuit. A second switch to communicate,
A control circuit for controlling the first switch and the second switch;
An integrated circuit device, further comprising: A plurality of identification elements manufactured in the same semiconductor in the form of the same CMOS inverter circuit through the same manufacturing process and having different electrical characteristics due to variations generated in the manufacturing process, and the plurality of identification elements And an identification information generating means connected to
The identification information generating means includes first to third switches provided corresponding to each of the plurality of CMOS inverter circuits, and a control circuit for controlling the first to third switches,
The first switch is provided between an input terminal and an output terminal of a corresponding CMOS inverter circuit,
The second switch is provided between the common first circuit node and the input terminal of the corresponding CMOS inverter circuit,
The third switch is provided between the output terminal of the corresponding CMOS inverter circuit and the common second circuit node,
In the plurality of CMOS inverter circuits, the control circuit forms a set of two CMOS inverter circuits, connects an input terminal and an output terminal of one of the CMOS inverter circuits, and outputs an output voltage from the one CMOS inverter circuit. And the output voltage of the one CMOS inverter circuit is supplied to the input terminal of the other CMOS inverter circuit through the first circuit node, and the other CMOS inverter circuit is supplied to the second circuit node. The first to third switches are controlled so as to give an output signal which is a result of determining the potential of the output voltage of the one CMOS inverter circuit using the logic threshold voltage of the other CMOS inverter circuit as a reference voltage. An integrated circuit device characterized by that.   34. The integrated circuit device according to claim 33, wherein the CMOS inverter circuit and the first to third switches use elements constituting a CMOS gate array.   34. The integrated circuit device according to claim 33, wherein the plurality of CMOS inverter circuits are configured to limit application of an operating voltage when the voltage determination operation as the physical quantity is not performed.   35. The integrated circuit device according to claim 32, wherein the switch is a switch composed of a MOSFET. A first inverter circuit; a first switch provided between an input terminal and an output terminal of the first inverter circuit; and a second inverter circuit having an input terminal connected to the output terminal of the first inverter circuit. And a plurality of identification elements including an amplifier circuit receiving an output signal of the output terminal of the second inverter circuit,
An identification number generation circuit for generating identification number information based on an output signal of the amplifier circuit when the first switch of the plurality of identification elements is in an ON state;
A semiconductor chip characterized in that it is built in. Each of the inverter circuits comprises a CMOS inverter circuit,
The semiconductor chip further includes a voltage generation circuit that generates a voltage to be applied to an input terminal of the first inverter circuit when the first switch is in an OFF state.
The voltage generation circuit generates a voltage at a level that avoids inversion due to a change with time of the output signal based on the level of the output signal of the amplifier circuit when the first switch is in an ON state. A semiconductor chip according to claim 37. The semiconductor chip includes a signal path for setting the voltage of the voltage generation circuit via the first and second inverter circuits.
The voltage generation circuit generates a low-level output voltage corresponding to an output signal of the second inverter circuit when the first switch is in an ON state when the output signal is at a high level with respect to the logic threshold value, and A latch circuit set to generate a high-level output voltage corresponding to the output signal of the second inverter circuit when the first switch is in the on-state when the output signal of the second inverter circuit is at a low level with respect to the logic threshold value; 40. The semiconductor chip according to claim 38, wherein: 40. The semiconductor chip according to claim 39, wherein the latch circuit is set in an output path of the amplifier circuit. The first inverter circuit and the second inverter circuit are CMOS inverter circuits,
Each of the input terminals of the first inverter circuit, the second inverter circuit, and the amplifier circuit is provided with a second switch that applies a high-level potential,
A third switch is provided between the first inverter circuit and the second inverter circuit,
When the identification number circuit is not in operation, the first switch is turned off, the second switch is turned on, and the third switch is turned off, whereby the inputs of the first and second inverter circuits are set. Set the terminal to the above high-level potential,
38. The semiconductor chip according to claim 37, wherein when the identification number circuit is in operation, the first switch and the third switch are turned on, and the second switch is turned off. A first inverter circuit; a second inverter circuit; a first switch provided between an input terminal and an output terminal of each of the first inverter circuit and the second inverter circuit; and an output terminal of the first inverter circuit. And a second switch provided between the first inverter circuit and the input terminal of the second inverter circuit, and an amplifier circuit including a third inverter circuit in which the output terminal of the second inverter circuit is connected to the input terminal With multiple elements,
The first identification information is obtained from the output signal of the amplifier circuit when the first switch of the first inverter circuit is turned on, the first switch of the second inverter circuit is turned off, and the second switch is turned on. Generating the second identification information from the output signal of the amplifier circuit when the first switch of the second inverter circuit is turned on and the second switch is turned off. A semiconductor chip incorporating a featured identification information generation circuit. The first inverter circuit and the second inverter circuit constitute a circuit row,
A plurality of circuit rows are configured in a form in which the first inverter circuit and the second inverter circuit are arranged correspondingly,
A common switch control signal is supplied to the corresponding first switch of the plurality of circuit rows,
The output signal of the second inverter circuit in the plurality of circuit arrays is supplied to the input terminal of the third inverter circuit constituting the amplifier circuit via the third switch for selecting a desired circuit array in the plurality of circuit arrays. 43. The semiconductor chip according to claim 42, wherein the semiconductor chip is formed. A fourth switch for controlling the supply and cut-off of the input signal connected to the input terminals of the first inverter circuit and the second inverter circuit and a fifth switch for controlling the supply and cut-off of the high-level voltage;
44. The semiconductor chip according to claim 43, wherein when the identification information generation circuit is inactive, the fourth switch is turned off and the fifth switch is turned on. A unit identification element comprising: a first inverter circuit; a first switch provided between an input terminal and an output terminal of the first inverter circuit; and a second switch provided at an input terminal of the first inverter circuit. A plurality of identification element rows formed in a column form through the second switch;
An amplifier circuit including a second inverter circuit in which an output terminal of the first inverter circuit corresponding to the final stage of the identification element row is connected to an input terminal;
A binary counter that counts the clock;
Receiving a count output of the binary counter, a decoder provided corresponding to the first switch and the second switch of each first inverter circuit of the identification element sequence,
Corresponding to the count output of the binary counter, the unit identification elements are sequentially turned on from the first stage circuit by sequentially controlling the first switch from the first stage circuit to the on state, and the second switch is complementary to the first switch. An identification number generation circuit for generating a plurality of identification information corresponding to each first inverter circuit of the identification element sequence in accordance with an output signal of the amplifier circuit and generating an identification number based on the plurality of identification information A semiconductor chip characterized by being built in. A plurality of unit elements including a first inverter circuit, a first switch provided between an input terminal and an output terminal of the first inverter circuit, and a second switch provided at the input terminal of the first inverter circuit Discriminating element rows, each of which is in the form of a column through the second switch,
An amplifier circuit including a second inverter circuit in which an output terminal of the first inverter circuit corresponding to the final stage of the identification element row is connected to an input terminal;
A shift register that receives a clock and has shift bits corresponding to the first switch and the second switch of each first inverter circuit of the identification element row,
Corresponding to the shift operation of the shift register, the first switch is sequentially turned on in order from the first stage circuit, and the second switch is turned off in a complementary manner to the first switch in accordance with the output signal of the amplifier circuit. A semiconductor chip comprising: a plurality of identification information corresponding to each first inverter circuit in the identification element sequence; and a built-in identification number generation circuit based on the plurality of identification information.   47. An integrated circuit device on which the semiconductor chip according to any one of claims 37 to 46 is mounted and identification information built in the semiconductor chip can be read in a mounted state.   47. A mounting body in which the semiconductor chip according to any one of claims 37 to 46 is mounted on a circuit board, wherein the mounting information enables reading of identification information built in the semiconductor chip in a mounted state. A test circuit adapted to the JTAG standard is further provided.
48. The integrated circuit device according to claim 47, wherein the identification number generated by the identification number generation circuit is output through an interface conforming to the JTAG standard. A plurality of integrated circuit layout units that realize a predetermined function are manufactured on a single semiconductor wafer through the same manufacturing process, and the semiconductor integrated circuit units corresponding to the layout units are separated into individual semiconductor integrated circuit chips. In a method for manufacturing an integrated circuit including a process,
In the design stage of the integrated circuit layout, an identification unit including a plurality of identification elements having the same circuit form is added to each of the integrated circuit layout units, and the integrated circuit and the identification are subjected to the same manufacturing process. Manufacturing a semiconductor wafer including a plurality of units of a semiconductor integrated circuit unit formed on the same semiconductor substrate;
A step of mutually comparing information reflecting physical quantities from each of the plurality of identification elements for each of the semiconductor integrated circuit units at one time of the manufacturing process of the integrated circuit, and generating identification information based on the mutual comparison; Including,
The physical quantity read from the plurality of identification elements reflects mutual variations occurring in the manufacturing process, and the generated identification information is used as identification information for each of the semiconductor integrated circuit units. Manufacturing method.   The integrated circuit layout unit further reflects a circuit that reads information reflecting a physical quantity of the identification element from each of the plurality of identification elements, a comparison circuit that compares the read information with each other, and a comparison result. 51. The method of manufacturing an integrated circuit device according to claim 50, further comprising: a circuit that generates identification information. A plurality of integrated circuit layout units that realize a predetermined function are manufactured on a single semiconductor wafer through the same manufacturing process, and the semiconductor integrated circuit units corresponding to the layout units are separated into individual semiconductor integrated circuit chips. In a method for manufacturing an integrated circuit including a process,
In the design stage of the integrated circuit layout, an identification unit including a plurality of identification elements having the same circuit form is added to the integrated circuit layout unit, and the integrated circuit and the identification unit are subjected to the same manufacturing process. Manufacturing a semiconductor wafer including a plurality of semiconductor integrated circuit units fabricated on the same semiconductor substrate;
Generating identification information reflecting physical quantities of the plurality of identification elements for each of the semiconductor integrated circuit units at one time of the manufacturing process of the integrated circuit,
The identification unit includes a first inverter circuit, a first switch connected between an input terminal and an output terminal of the first inverter circuit, and a second switch provided at the input terminal of the first inverter circuit. An identification element string in which a plurality of unit elements are arranged in a column through the second switch, and an output terminal of the first inverter circuit corresponding to the last stage of the identification element string is connected to an input terminal. An amplifier circuit including a second inverter circuit,
In the identification information generating step, the identification elements are sequentially turned on in order from the first stage circuit, the second switch is turned off in a complementary manner to the first switch, and the identification element is generated by an output signal of the amplifier circuit. A method for manufacturing an integrated circuit device, comprising: generating a plurality of identification information corresponding to each first inverter circuit in a column and generating an identification number based on the plurality of identification information. The identification unit further includes a shift register that receives a clock and has shift bits corresponding to the first switch and the second switch of each first inverter circuit of the identification element string,
53. The method of manufacturing an integrated circuit device according to claim 52, wherein the identification information generating step is executed in response to a shift operation of the shift register. A method of manufacturing an integrated circuit device including a semiconductor chip,
A plurality of identification elements each having the same circuit form, and setting means for obtaining a digital value based on variations in electrical characteristics resulting from manufacturing variations of the plurality of identification elements and setting the digital value as unique identification information; Are formed on a common semiconductor substrate,
The plurality of identification elements are formed on the semiconductor substrate by the same manufacturing process,
A method of manufacturing an integrated circuit device, wherein the semiconductor chip includes the plurality of identification elements and the setting means. A method of manufacturing an integrated circuit device including a semiconductor chip,
Formed on a common semiconductor substrate having a plurality of inverters and setting means for obtaining digital values based on variations in electrical characteristics resulting from manufacturing variations of the plurality of inverters and setting the digital values as unique identification information In particular, the plurality of identification elements are formed by the same manufacturing process,
The plurality of inverters are formed on the semiconductor substrate by the same manufacturing process, and each of the inverters has a P-channel transistor and an N-channel transistor in which the gates are connected and the drains are connected. Have
An integrated circuit device manufacturing method, wherein the semiconductor chip includes the plurality of inverters and the setting unit. An integrated circuit device having a semiconductor chip,
The semiconductor chip is
A plurality of identification elements manufactured through the same manufacturing process in the same circuit form,
Setting means for obtaining a digital value based on variation in electrical characteristics resulting from manufacturing variation of the plurality of identification elements and setting the digital value as unique identification information;
An integrated circuit device. An integrated circuit device having a semiconductor chip,
The semiconductor chip is
A plurality of inverters manufactured in the same manufacturing process,
Setting means for obtaining a digital value based on variations in electrical characteristics resulting from manufacturing variations of the plurality of inverters and setting the digital value as unique identification information;
Each of the plurality of inverters is an integrated circuit device having a P-channel transistor and an N-channel transistor having gates connected to each other and drains connected to each other.

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