JPS648880U - - Google Patents

Info

Publication number
JPS648880U
JPS648880U JP10346387U JP10346387U JPS648880U JP S648880 U JPS648880 U JP S648880U JP 10346387 U JP10346387 U JP 10346387U JP 10346387 U JP10346387 U JP 10346387U JP S648880 U JPS648880 U JP S648880U
Authority
JP
Japan
Prior art keywords
amplifier
agc
circuit
tuner
input signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10346387U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP10346387U priority Critical patent/JPS648880U/ja
Publication of JPS648880U publication Critical patent/JPS648880U/ja
Pending legal-status Critical Current

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  • Television Receiver Circuits (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案を実施したAGC回路の回路図
であり、第2図は本考案の他の実施例の回路図で
ある。第3図は本考案による効果を示す特性図で
ある。第4図は遅延型のAGC回路の構成例を示
すブロツク図、第5図は従来のAGC回路を示す
図である。第6図はIF・AGC特性図、第7図
はRF・AGC特性図である。 1……チユーナ、3……RF増幅器、7……I
F増幅器、10……AGC電圧生成回路、11…
…遅延回路、13……切換え回路。
FIG. 1 is a circuit diagram of an AGC circuit embodying the present invention, and FIG. 2 is a circuit diagram of another embodiment of the present invention. FIG. 3 is a characteristic diagram showing the effects of the present invention. FIG. 4 is a block diagram showing a configuration example of a delay type AGC circuit, and FIG. 5 is a diagram showing a conventional AGC circuit. FIG. 6 is an IF/AGC characteristic diagram, and FIG. 7 is an RF/AGC characteristic diagram. 1...Tuner, 3...RF amplifier, 7...I
F amplifier, 10...AGC voltage generation circuit, 11...
...Delay circuit, 13...Switching circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] テレビジヨンチユーナのRF増幅器と、前記チ
ユーナのIF出力を増幅するIF増幅器と、前記
IF増幅器を経たIF信号をもとにAGC電圧を
生成するAGC電圧生成回路と、前記RF増幅器
にAGCがかかり始める点のアンテナ入力信号レ
ベルが前記IF増幅器にAGCがかかり始める点
のアンテナ入力信号レベルよりも高い関係になる
ように前記AGC電圧を遅延させる遅延回路とを
有する遅延型のAGC回路において、前記遅延回
路の遅延量をチユーナの受信バンド又は受信チヤ
ンネルに応じて切換える手段を設けたことを特徴
とするAGC回路。
An RF amplifier of a television tuner, an IF amplifier that amplifies the IF output of the tuner, an AGC voltage generation circuit that generates an AGC voltage based on the IF signal that has passed through the IF amplifier, and an AGC applied to the RF amplifier. and a delay circuit that delays the AGC voltage so that the antenna input signal level at the starting point is higher than the antenna input signal level at the point at which AGC starts to be applied to the IF amplifier. An AGC circuit comprising means for switching the amount of delay in the circuit according to a reception band or a reception channel of a tuner.
JP10346387U 1987-07-06 1987-07-06 Pending JPS648880U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10346387U JPS648880U (en) 1987-07-06 1987-07-06

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10346387U JPS648880U (en) 1987-07-06 1987-07-06

Publications (1)

Publication Number Publication Date
JPS648880U true JPS648880U (en) 1989-01-18

Family

ID=31334319

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10346387U Pending JPS648880U (en) 1987-07-06 1987-07-06

Country Status (1)

Country Link
JP (1) JPS648880U (en)

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