JPS6488634A - Instruction decoder for computer - Google Patents

Instruction decoder for computer

Info

Publication number
JPS6488634A
JPS6488634A JP24717087A JP24717087A JPS6488634A JP S6488634 A JPS6488634 A JP S6488634A JP 24717087 A JP24717087 A JP 24717087A JP 24717087 A JP24717087 A JP 24717087A JP S6488634 A JPS6488634 A JP S6488634A
Authority
JP
Japan
Prior art keywords
address
decoder
instruction
program counter
counter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP24717087A
Other languages
Japanese (ja)
Inventor
Tatsuo Nishizawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP24717087A priority Critical patent/JPS6488634A/en
Publication of JPS6488634A publication Critical patent/JPS6488634A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To releave a programmer from a delayed jump which is the flaw of a pipeline processing which is essential for high-speed processing by adding a program counter and a decoder which is paired with the former. CONSTITUTION:The program counter 15 which a t all time represents the effective address of one instruction destination as well as the decoder 16 which is paired with the counter 15 is provided. Since the counter 15 always designates an address preceeding by one designated by a program counter 11, the decoder 16 decodes and executes an instruction always preceeding by one operational cycle. When the content in the address N of an instruction storing memory 12 is decoded as 'CALL M' in the decoder 16, an M is inputted to the program counter 11 in the succeeding execution cycle, and at the same time, a value N+1 is stored in a stack 14. Accordingly, the execution of an instruction in the address M can be enable in the cycle following the execution cycle for the address N. As a result, a delayed jump that is the flaw of pipeline processing can be prevented.
JP24717087A 1987-09-29 1987-09-29 Instruction decoder for computer Pending JPS6488634A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24717087A JPS6488634A (en) 1987-09-29 1987-09-29 Instruction decoder for computer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24717087A JPS6488634A (en) 1987-09-29 1987-09-29 Instruction decoder for computer

Publications (1)

Publication Number Publication Date
JPS6488634A true JPS6488634A (en) 1989-04-03

Family

ID=17159482

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24717087A Pending JPS6488634A (en) 1987-09-29 1987-09-29 Instruction decoder for computer

Country Status (1)

Country Link
JP (1) JPS6488634A (en)

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