JPS64866B2 - - Google Patents

Description

[Detailed Description of the Invention] (Field of Application) The present invention relates to a halftone expression method, and in particular, to a halftone expression method that performs halftone expression using a pixel pattern composed of a plurality of dots. .

(Prior Art) Conventional halftone expression methods include a systematic dither method and the like, and there is a method of expressing a wide halftone image by repeating a pixel pattern composed of a plurality of dots. For example, if we take a halftone expression method using a 2 x 2 matrix of the ternary dither method as an example, to express a wide halftone image, we can use a certain halftone expression matrix shown in Fig. 1 as shown in Fig. 2. This was done by repeating this.

In this case, the wide halftone image appears to be composed of repeating two vertical lines A and B shown in FIG. 2, and the halftone expression is not sufficiently clear. The drawback was that it was not carried out.

(Objective) An object of the present invention is to provide a halftone expression method that improves halftone expression in a device that expresses halftones by repeating a pixel pattern composed of a plurality of dots as described above. be.

(Overview) A feature of the present invention is that in a method of expressing halftones by configuring pixels with a plurality of dots, successive same halftone levels are alternately expressed in units of two lines.
The key point is that it is expressed by shifting the bits.

(Example) Hereinafter, an example in which the present invention is applied to a transfer type thermal recording device will be described.

In order for the recording section to output the halftone expressed by the 2x2 matrix of the ternary dither method, a minimum of two consecutive lines in the main scanning direction is required.
In order to express the entire image, the intermediate tones are expressed by repeatedly outputting these two lines as one unit in the sub-scanning direction.

In FIG. 3, a is a transmitted pattern signal, which is controlled by switch S1 in the main scanning direction.
Line buffer memory 1a alternately for each line,
1b. The switch S2 is connected to the other line buffer memory different from the line buffer memory selected by the switch S1, and reads out the pattern signal of the previous line at high speed.

Therefore, the read pattern signal b,
The timing with the pattern signal a input to the line buffer memories 1a and 1b is, for example, the fourth
as shown in the figure. That is, if one line of pattern signal a is sent over a period of time _T1 , the time _T2 during which one line of pattern signal a is read out is shorter than _T1 .

The pattern signal b read out at high speed in this manner is input to the circuit shown in FIG.

In FIG. 5, pattern signal b, which is a print signal in the main scanning direction, is sent bit by bit.
A first register 2 and a second register 3 each have a capacity for one line (one raster) in the main scanning direction.
is temporarily held. At this time, the pattern signal b input to the first register 2 passes through the 1-bit delay circuit 4, so the pattern signal b input to the first register 2 passes through the 1-bit delay circuit 4.
The pattern signal held at 3 is 1 in the main scanning direction.
The signal is shifted by a dot.

Reference numeral 5 denotes an odd-even line detection circuit that detects whether the pattern signal b for one line in the main scanning direction that is sent is an odd-numbered line signal or an even-numbered line signal. The odd-even line detection circuit 5 includes, for example,
It consists of a toggle flip-flop, and is triggered by a synchronization signal included in one line of pattern signal b. Therefore, the odd-even line detection circuit 5 alternately outputs high and low signals for each line, thereby causing the first
and second selection circuits 6 and 7 are controlled.

8 is an even latch circuit having a capacity for one line in the main scanning direction, and 9 is an odd latch circuit having the same capacity.

Now, suppose that an odd line pattern signal is input to the first and second registers 2 and 3.
The even latch circuit 8 holds the pattern signal of the previous line, and the odd latch circuit 9 holds the pattern signal of the line immediately before the previous line.
Further, the odd-even line detection circuit 5 outputs odd-numbered lines, and the first and second selection circuits 6 and 7 select the odd-numbered latch circuit 9.

In this state, the gate 10 is opened at an appropriate timing by a signal from a timing circuit (not shown), and the signal held in the second register is sent to the comparison circuit 11. On the other hand, the signal held in the odd latch circuit 9 selected by the first selection circuit 6 is sent to the comparison circuit 11. Then, the comparison circuit 9 compares the two.

When the comparison results in a match, a match signal is sent from the comparison circuit 11 to the third selection circuit 12. As a result, the selection circuit 12 selects the first register 2 that holds the pattern signal shifted by one bit. On the other hand, when there is a mismatch, the comparison circuit 11 outputs a mismatch signal, which causes the selection circuit 1
2 selects the second register 3. Note that the signal passing through the gate 10 is written into the second register 3 again.

Now, if a match signal is output from the comparison circuit 11, the third selection circuit 12 selects the first register 2, and the pattern signal held in the register 2, which is shifted by 1 bit, is output from the output circuit 13. , is sent to the second selection circuit 7. The output circuit 13 controls the drive circuit 14 based on the sent pattern signal. The drive circuit 14 is connected to the thermal head 15
is controlled in a well-known manner, for example by selectively heating the ink donor sheet 16. As a result, an image corresponding to the pattern signal is recorded on the recording paper 17.

On the other hand, the pattern signal from the first register 2 input to the second selection circuit 7 is written into the odd latch circuit 9 because the second selection circuit selects the odd latch circuit 9.

Next, the pattern signal b of the next even line
is input to the first and second registers 2 and 3, the odd-even line detection circuit 5 inverts and outputs an even line signal. As a result, the first and second selection circuits select the even latch circuit 8.

Subsequently, the gate 10 is opened at an appropriate timing, and the pattern signal held in the second register 3 and the pattern signal of the previous line held in the even latch circuit 8 are connected by a clock (not shown). , are compared by the comparison circuit 11. If they match, a match signal from the comparison circuit 11 selects the pattern signal held in the first register 2 that is shifted by one bit. On the other hand, if there is a mismatch, the second register 3 is selected.

Assuming that a match signal is now output from the comparator circuit 11, a pattern signal shifted by one bit is sent to the output circuit 13 and the even latch circuit 8 by the same operation as in the above case.

Therefore, the image recorded on the recording paper 17 by the pattern signal from the output circuit 13 is changed in the main scanning direction, for example, as shown in the third and fourth columns shown in FIG. The data is transferred with a 1-bit shift.

Next, the pattern signal b of the odd numbered line one after another
is input to the first registers 2, 3, and the odd latch circuit 9 holds a pattern signal that is shifted by 1 bit. A comparison with the pattern signal of the odd latch circuit 9 always results in a mismatch. Therefore, the third selection circuit 12
selects and outputs the pattern signal held in the second register 3, that is, the signal that is not shifted by one bit. This pattern signal is transmitted to the output circuit 13
The recording paper 1 is sent to the recording paper 1 by the thermal head 13.
7 is recorded.

This one line image is an image shifted by one bit from the pattern images in the third and fourth columns, as in the fifth column in FIG.

As described above, according to this embodiment, when the same halftone is spread over several lines or more, it is transferred with a one-bit shift every two lines. As is clear, the intermediate tone is expressed by one type of line pattern C. Therefore, good image quality with improved halftone expression can be obtained.

Further, according to this embodiment, since the heat generating portion of the thermal head changes every two lines, it is less susceptible to the heat storage effect of the heat generating resistor. Therefore, deterioration in image quality due to the heat storage effect can be reduced.

In the above embodiment, the capacity of the first and second registers has been described as one line, but this is not limited to one line, and may be smaller than one line. In this way, the same improvement as described above can be achieved even for uniform halftones with a width shorter than one line.

Furthermore, although the above embodiments have been explained using a transfer type thermal recording method as an example, the present invention is not limited thereto, and can be applied to a direct thermal recording method, an electrostatic recording method, an inkjet recording method, a laser recording method, an electric discharge recording method, etc. The present invention can be applied to any recording method that digitizes and handles the image signal, such as a destructive recording method.

(Effects) As is clear from the above description, according to the present invention, the following effects are achieved.

(1) Since halftones are expressed by one type of line pattern, good image quality with improved halftone expression can be obtained.

(2) Since the thermal head heat generating part changes every two lines, it is less susceptible to heat storage effects and can reduce the deterioration of image quality.

[Brief explanation of the drawing]

Figure 1 shows an example of a halftone pixel pattern expressed by a 2x2 matrix of the ternary dither method, and Figure 2 shows a conventional halftone pixel pattern expressed by the pixel pattern of Figure 1. FIG. 3 is a block diagram of a device that changes the write speed and read speed of pattern signals, FIG. 4 is a time chart of the signals in FIG. 3, and FIG. 5 is a block diagram of an embodiment of the present invention. , FIG. 6 is a diagram showing an example of halftones expressed by this embodiment. 2, 3...First and second registers, 4...1 bit delay circuit, 5...Odd-even line detection circuit, 6, 7, 1
2...First, second, and third selection circuits, 8, 9...Even and odd line circuits, 11...Comparison circuit.

Claims (1)

[Claims] 1. A first register into which a pattern signal is written, a second register into which a signal shifted by 1 bit from the pattern signal is written, and an odd latch circuit when the first and second registers are written to odd lines. a comparison circuit that compares the pattern signal stored in the first register with the pattern signal stored in the first register, and the pattern signal stored in the even latch circuit when the line is an even number;
a first selection circuit that selects the second register when the comparison result by the comparison circuit matches, and selects the first register when the comparison result does not match; and when the comparison result is an odd numbered line, the first selection circuit selects the second register; a second selection circuit that guides the selected pattern signal to the odd latch circuit and, when the line is an even line, leads the pattern signal to the even latch circuit; and a second selection circuit that receives the pattern signal selected by the first selection circuit. A halftone expression method characterized in that the same continuous halftone level is expressed by shifting one bit alternately in units of two lines.