JPS6486675A - Image reader - Google Patents

Abstract

PURPOSE:To perform density adjustment with the same width as that before the reduction of a bit by constituting a bit reduction circuit of a cut-off circuit which cuts off the least significant bit, a rounding circuit which carries one level if the least significant bit is '1' and cuts off if it is '0' and a switching means to select those circuits. CONSTITUTION:The bit reduction circuit 40 is constituted of two circuits: the cut-off circuit 41 which cuts off the least significant bit, and the rounding circuit 42 which outputs (the gradation of) a high-order bit after adding 1 when the least significant bit is '1', and outputs only the high-order bit when it is '0', and both circuits can be selected. In other words, in the bit reduction circuit 40, by switching those two circuits 41 and 42 by remarking the fact that a signal level is shifted by every one level before reduction as shown in dotted line (b) by reducing one bit by the rounding circuit 42 compared with a case where one bit is cut off by the cut-off circuit 41, it is possible to set the threshold value level of the binarization circuit at an interval of 1/2 of an on-going interval, therefore, fine adjustment for density can be performed, and recording picture quality can be improved.