JPS6486373A - Pointer signal generating circuit - Google Patents

Pointer signal generating circuit

Info

Publication number
JPS6486373A
JPS6486373A JP24244187A JP24244187A JPS6486373A JP S6486373 A JPS6486373 A JP S6486373A JP 24244187 A JP24244187 A JP 24244187A JP 24244187 A JP24244187 A JP 24244187A JP S6486373 A JPS6486373 A JP S6486373A
Authority
JP
Japan
Prior art keywords
signal
pointer
data
dropin
generating circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP24244187A
Other languages
Japanese (ja)
Inventor
Kunitaka Mori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP24244187A priority Critical patent/JPS6486373A/en
Publication of JPS6486373A publication Critical patent/JPS6486373A/en
Pending legal-status Critical Current

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  • Dc Digital Transmission (AREA)

Abstract

PURPOSE:To generate a pointer signal by discriminating the waveform and polarity appearing just after the reduction in the data amplitude likely to generate a dropin or regarded to be noise or dropin so as to decide more accurately that the error may be occurred. CONSTITUTION:Since a flip-flop 7 is reset by a signal (h) and set by a signal (g), no NRZI signal (j) (figure i) is disturbed by a dropin signal g-1 (figure g) corresponding to a noise signal shown in a-1 in figure (a). In case of a signal h-4 (figure h) corresponding to a noise signal shown in a-4 in the figure (a), however, inversion i-4 shown in the figure (i) is occurred and a data inversion 1-5 corresponding to a-5 shown in the figure (a) is no longer produced. In the digital data recovery circuit (a) as above, no error data is generated in a-1-a-3 shown in the figure (a), no pointer is generated in a pointer signal generating circuit B, and a dropin data is given in a-4 shown in the figure (a) and no correct data is to be reproduced. Thus, the pointer signal generating circuit B outputs a pointer signal.
JP24244187A 1987-09-29 1987-09-29 Pointer signal generating circuit Pending JPS6486373A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24244187A JPS6486373A (en) 1987-09-29 1987-09-29 Pointer signal generating circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24244187A JPS6486373A (en) 1987-09-29 1987-09-29 Pointer signal generating circuit

Publications (1)

Publication Number Publication Date
JPS6486373A true JPS6486373A (en) 1989-03-31

Family

ID=17089137

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24244187A Pending JPS6486373A (en) 1987-09-29 1987-09-29 Pointer signal generating circuit

Country Status (1)

Country Link
JP (1) JPS6486373A (en)

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